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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
3a8761c0 TL |
17 | |
18 | #include <linux/i2c-omap.h> | |
b86aeafc | 19 | #include <linux/power/smartreflex.h> |
4b25408f | 20 | #include <linux/platform_data/gpio-omap.h> |
55143438 | 21 | #include <linux/platform_data/hsmmc-omap.h> |
b86aeafc | 22 | |
45c3eb7d | 23 | #include <linux/omap-dma.h> |
79e3cb22 | 24 | #include "l3_3xxx.h" |
957988c7 | 25 | #include "l4_3xxx.h" |
2203747c AB |
26 | #include <linux/platform_data/asoc-ti-mcbsp.h> |
27 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
ce722d26 | 28 | #include <plat/dmtimer.h> |
7359154e | 29 | |
dbc04161 | 30 | #include "soc.h" |
2a296c8f | 31 | #include "omap_hwmod.h" |
43b40992 | 32 | #include "omap_hwmod_common_data.h" |
7359154e | 33 | #include "prm-regbits-34xx.h" |
6b667f88 | 34 | #include "cm-regbits-34xx.h" |
d5e7c864 | 35 | |
3a8761c0 | 36 | #include "i2c.h" |
ff2516fb | 37 | #include "wd_timer.h" |
3d82cbbb | 38 | #include "serial.h" |
7359154e PW |
39 | |
40 | /* | |
41 | * OMAP3xxx hardware module integration data | |
42 | * | |
844a3b63 | 43 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
44 | * TI hardware database or other technical documentation. Data that |
45 | * is driver-specific or driver-kernel integration-specific belongs | |
46 | * elsewhere. | |
47 | */ | |
48 | ||
13eeb0f3 TL |
49 | #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 |
50 | ||
844a3b63 PW |
51 | /* |
52 | * IP blocks | |
53 | */ | |
7359154e | 54 | |
844a3b63 | 55 | /* L3 */ |
4bb194dc | 56 | |
4a7cf90a | 57 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 58 | .name = "l3_main", |
43b40992 | 59 | .class = &l3_hwmod_class, |
2eb1875d | 60 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
61 | }; |
62 | ||
844a3b63 PW |
63 | /* L4 CORE */ |
64 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
65 | .name = "l4_core", | |
66 | .class = &l4_hwmod_class, | |
67 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 68 | }; |
7359154e | 69 | |
844a3b63 PW |
70 | /* L4 PER */ |
71 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
72 | .name = "l4_per", | |
73 | .class = &l4_hwmod_class, | |
74 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 75 | }; |
844a3b63 PW |
76 | |
77 | /* L4 WKUP */ | |
78 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
79 | .name = "l4_wkup", | |
80 | .class = &l4_hwmod_class, | |
81 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
82 | }; |
83 | ||
844a3b63 PW |
84 | /* L4 SEC */ |
85 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
86 | .name = "l4_sec", | |
87 | .class = &l4_hwmod_class, | |
88 | .flags = HWMOD_NO_IDLEST, | |
4a9efb62 PW |
89 | }; |
90 | ||
844a3b63 | 91 | /* MPU */ |
ee75d95c | 92 | |
844a3b63 PW |
93 | static struct omap_hwmod omap3xxx_mpu_hwmod = { |
94 | .name = "mpu", | |
95 | .class = &mpu_hwmod_class, | |
96 | .main_clk = "arm_fck", | |
b163605e PW |
97 | }; |
98 | ||
844a3b63 | 99 | /* IVA2 (IVA2) */ |
f42c5496 | 100 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
ed733619 TK |
101 | { .name = "logic", .rst_shift = 0, .st_shift = 8 }, |
102 | { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, | |
103 | { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, | |
f42c5496 PW |
104 | }; |
105 | ||
844a3b63 PW |
106 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
107 | .name = "iva", | |
108 | .class = &iva_hwmod_class, | |
f42c5496 PW |
109 | .clkdm_name = "iva2_clkdm", |
110 | .rst_lines = omap3xxx_iva_resets, | |
111 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
112 | .main_clk = "iva2_ck", | |
ed733619 TK |
113 | .prcm = { |
114 | .omap2 = { | |
115 | .module_offs = OMAP3430_IVA2_MOD, | |
116 | .prcm_reg_id = 1, | |
117 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
118 | .idlest_reg_id = 1, | |
119 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
d9d9cec0 | 120 | }, |
ed733619 | 121 | }, |
4a9efb62 PW |
122 | }; |
123 | ||
c7dad45f JH |
124 | /* |
125 | * 'debugss' class | |
126 | * debug and emulation sub system | |
127 | */ | |
128 | ||
129 | static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { | |
130 | .name = "debugss", | |
131 | }; | |
132 | ||
133 | /* debugss */ | |
134 | static struct omap_hwmod omap3xxx_debugss_hwmod = { | |
135 | .name = "debugss", | |
136 | .class = &omap3xxx_debugss_hwmod_class, | |
137 | .clkdm_name = "emu_clkdm", | |
138 | .main_clk = "emu_src_ck", | |
139 | .flags = HWMOD_NO_IDLEST, | |
140 | }; | |
141 | ||
844a3b63 | 142 | /* timer class */ |
844a3b63 PW |
143 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
144 | .rev_offs = 0x0000, | |
145 | .sysc_offs = 0x0010, | |
146 | .syss_offs = 0x0014, | |
725a8fe3 JH |
147 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
148 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
f3a13e72 JH |
149 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | |
150 | SYSS_HAS_RESET_STATUS), | |
844a3b63 | 151 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
10759e82 | 152 | .clockact = CLOCKACT_TEST_ICLK, |
844a3b63 | 153 | .sysc_fields = &omap_hwmod_sysc_type1, |
b163605e PW |
154 | }; |
155 | ||
844a3b63 PW |
156 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
157 | .name = "timer", | |
158 | .sysc = &omap3xxx_timer_sysc, | |
046465b7 KH |
159 | }; |
160 | ||
844a3b63 PW |
161 | /* secure timers dev attribute */ |
162 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
139486fa | 163 | .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, |
046465b7 KH |
164 | }; |
165 | ||
844a3b63 PW |
166 | /* always-on timers dev attribute */ |
167 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
168 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
169 | }; |
170 | ||
844a3b63 PW |
171 | /* pwm timers dev attribute */ |
172 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
173 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
174 | }; |
175 | ||
5c3e4ec4 JH |
176 | /* timers with DSP interrupt dev attribute */ |
177 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
178 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
179 | }; | |
180 | ||
181 | /* pwm timers with DSP interrupt dev attribute */ | |
182 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
183 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
184 | }; | |
185 | ||
844a3b63 PW |
186 | /* timer1 */ |
187 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
188 | .name = "timer1", | |
844a3b63 PW |
189 | .main_clk = "gpt1_fck", |
190 | .prcm = { | |
191 | .omap2 = { | |
192 | .prcm_reg_id = 1, | |
193 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
194 | .module_offs = WKUP_MOD, | |
195 | .idlest_reg_id = 1, | |
196 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
197 | }, | |
046465b7 | 198 | }, |
844a3b63 | 199 | .dev_attr = &capability_alwon_dev_attr, |
725a8fe3 | 200 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 201 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
202 | }; |
203 | ||
844a3b63 PW |
204 | /* timer2 */ |
205 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
206 | .name = "timer2", | |
844a3b63 PW |
207 | .main_clk = "gpt2_fck", |
208 | .prcm = { | |
209 | .omap2 = { | |
210 | .prcm_reg_id = 1, | |
211 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
212 | .module_offs = OMAP3430_PER_MOD, | |
213 | .idlest_reg_id = 1, | |
214 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
215 | }, | |
216 | }, | |
725a8fe3 | 217 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 218 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
219 | }; |
220 | ||
844a3b63 PW |
221 | /* timer3 */ |
222 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
223 | .name = "timer3", | |
844a3b63 PW |
224 | .main_clk = "gpt3_fck", |
225 | .prcm = { | |
226 | .omap2 = { | |
227 | .prcm_reg_id = 1, | |
228 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
229 | .module_offs = OMAP3430_PER_MOD, | |
230 | .idlest_reg_id = 1, | |
231 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
232 | }, | |
233 | }, | |
844a3b63 | 234 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 235 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
236 | }; |
237 | ||
844a3b63 PW |
238 | /* timer4 */ |
239 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
240 | .name = "timer4", | |
844a3b63 PW |
241 | .main_clk = "gpt4_fck", |
242 | .prcm = { | |
243 | .omap2 = { | |
244 | .prcm_reg_id = 1, | |
245 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
246 | .module_offs = OMAP3430_PER_MOD, | |
247 | .idlest_reg_id = 1, | |
248 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
249 | }, | |
250 | }, | |
844a3b63 | 251 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 252 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
046465b7 KH |
253 | }; |
254 | ||
844a3b63 PW |
255 | /* timer5 */ |
256 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
257 | .name = "timer5", | |
844a3b63 PW |
258 | .main_clk = "gpt5_fck", |
259 | .prcm = { | |
260 | .omap2 = { | |
261 | .prcm_reg_id = 1, | |
262 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
263 | .module_offs = OMAP3430_PER_MOD, | |
264 | .idlest_reg_id = 1, | |
265 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
266 | }, | |
4bf90f65 | 267 | }, |
5c3e4ec4 | 268 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 269 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 270 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4bf90f65 KM |
271 | }; |
272 | ||
844a3b63 PW |
273 | /* timer6 */ |
274 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
275 | .name = "timer6", | |
844a3b63 PW |
276 | .main_clk = "gpt6_fck", |
277 | .prcm = { | |
278 | .omap2 = { | |
279 | .prcm_reg_id = 1, | |
280 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
281 | .module_offs = OMAP3430_PER_MOD, | |
282 | .idlest_reg_id = 1, | |
283 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
284 | }, | |
285 | }, | |
5c3e4ec4 | 286 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 287 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 288 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4bf90f65 KM |
289 | }; |
290 | ||
844a3b63 PW |
291 | /* timer7 */ |
292 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
293 | .name = "timer7", | |
844a3b63 PW |
294 | .main_clk = "gpt7_fck", |
295 | .prcm = { | |
4fe20e97 | 296 | .omap2 = { |
844a3b63 PW |
297 | .prcm_reg_id = 1, |
298 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
299 | .module_offs = OMAP3430_PER_MOD, | |
300 | .idlest_reg_id = 1, | |
301 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
302 | }, | |
4fe20e97 | 303 | }, |
5c3e4ec4 | 304 | .dev_attr = &capability_dsp_dev_attr, |
844a3b63 | 305 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 306 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
307 | }; |
308 | ||
844a3b63 PW |
309 | /* timer8 */ |
310 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
311 | .name = "timer8", | |
844a3b63 PW |
312 | .main_clk = "gpt8_fck", |
313 | .prcm = { | |
4fe20e97 | 314 | .omap2 = { |
844a3b63 PW |
315 | .prcm_reg_id = 1, |
316 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
317 | .module_offs = OMAP3430_PER_MOD, | |
318 | .idlest_reg_id = 1, | |
319 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
320 | }, | |
4fe20e97 | 321 | }, |
5c3e4ec4 | 322 | .dev_attr = &capability_dsp_pwm_dev_attr, |
844a3b63 | 323 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 324 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
325 | }; |
326 | ||
844a3b63 PW |
327 | /* timer9 */ |
328 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
329 | .name = "timer9", | |
844a3b63 PW |
330 | .main_clk = "gpt9_fck", |
331 | .prcm = { | |
332 | .omap2 = { | |
333 | .prcm_reg_id = 1, | |
334 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
335 | .module_offs = OMAP3430_PER_MOD, | |
336 | .idlest_reg_id = 1, | |
337 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
338 | }, | |
4fe20e97 | 339 | }, |
844a3b63 PW |
340 | .dev_attr = &capability_pwm_dev_attr, |
341 | .class = &omap3xxx_timer_hwmod_class, | |
10759e82 | 342 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
343 | }; |
344 | ||
844a3b63 PW |
345 | /* timer10 */ |
346 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
347 | .name = "timer10", | |
844a3b63 PW |
348 | .main_clk = "gpt10_fck", |
349 | .prcm = { | |
4fe20e97 | 350 | .omap2 = { |
844a3b63 PW |
351 | .prcm_reg_id = 1, |
352 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
353 | .module_offs = CORE_MOD, | |
354 | .idlest_reg_id = 1, | |
355 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
356 | }, | |
4fe20e97 | 357 | }, |
844a3b63 | 358 | .dev_attr = &capability_pwm_dev_attr, |
725a8fe3 | 359 | .class = &omap3xxx_timer_hwmod_class, |
10759e82 | 360 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 RN |
361 | }; |
362 | ||
844a3b63 PW |
363 | /* timer11 */ |
364 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
365 | .name = "timer11", | |
844a3b63 PW |
366 | .main_clk = "gpt11_fck", |
367 | .prcm = { | |
368 | .omap2 = { | |
369 | .prcm_reg_id = 1, | |
370 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
371 | .module_offs = CORE_MOD, | |
372 | .idlest_reg_id = 1, | |
373 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
374 | }, | |
375 | }, | |
376 | .dev_attr = &capability_pwm_dev_attr, | |
377 | .class = &omap3xxx_timer_hwmod_class, | |
10759e82 | 378 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
d62bc78a NM |
379 | }; |
380 | ||
844a3b63 | 381 | /* timer12 */ |
d62bc78a | 382 | |
844a3b63 PW |
383 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
384 | .name = "timer12", | |
844a3b63 PW |
385 | .main_clk = "gpt12_fck", |
386 | .prcm = { | |
387 | .omap2 = { | |
388 | .prcm_reg_id = 1, | |
389 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
390 | .module_offs = WKUP_MOD, | |
391 | .idlest_reg_id = 1, | |
392 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
393 | }, | |
d3442726 | 394 | }, |
844a3b63 PW |
395 | .dev_attr = &capability_secure_dev_attr, |
396 | .class = &omap3xxx_timer_hwmod_class, | |
10759e82 | 397 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
d3442726 TG |
398 | }; |
399 | ||
844a3b63 PW |
400 | /* |
401 | * 'wd_timer' class | |
402 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
403 | * overflow condition | |
404 | */ | |
405 | ||
406 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
407 | .rev_offs = 0x0000, | |
408 | .sysc_offs = 0x0010, | |
409 | .syss_offs = 0x0014, | |
410 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
411 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
412 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
413 | SYSS_HAS_RESET_STATUS), | |
414 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
415 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
416 | }; |
417 | ||
844a3b63 PW |
418 | /* I2C common */ |
419 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
420 | .rev_offs = 0x00, | |
421 | .sysc_offs = 0x20, | |
422 | .syss_offs = 0x10, | |
423 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
424 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
425 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
426 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
427 | .clockact = CLOCKACT_TEST_ICLK, | |
428 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
429 | }; |
430 | ||
844a3b63 PW |
431 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
432 | .name = "wd_timer", | |
433 | .sysc = &omap3xxx_wd_timer_sysc, | |
414e4128 KH |
434 | .pre_shutdown = &omap2_wd_timer_disable, |
435 | .reset = &omap2_wd_timer_reset, | |
d3442726 TG |
436 | }; |
437 | ||
844a3b63 PW |
438 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
439 | .name = "wd_timer2", | |
440 | .class = &omap3xxx_wd_timer_hwmod_class, | |
441 | .main_clk = "wdt2_fck", | |
442 | .prcm = { | |
443 | .omap2 = { | |
444 | .prcm_reg_id = 1, | |
445 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
446 | .module_offs = WKUP_MOD, | |
447 | .idlest_reg_id = 1, | |
448 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
449 | }, | |
450 | }, | |
451 | /* | |
452 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
453 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
454 | */ | |
455 | .flags = HWMOD_SWSUP_SIDLE, | |
456 | }; | |
870ea2b8 | 457 | |
844a3b63 PW |
458 | /* UART1 */ |
459 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
460 | .name = "uart1", | |
844a3b63 | 461 | .main_clk = "uart1_fck", |
a2fc3661 | 462 | .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
463 | .prcm = { |
464 | .omap2 = { | |
465 | .module_offs = CORE_MOD, | |
466 | .prcm_reg_id = 1, | |
467 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
468 | .idlest_reg_id = 1, | |
469 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
470 | }, | |
870ea2b8 | 471 | }, |
844a3b63 | 472 | .class = &omap2_uart_class, |
870ea2b8 HH |
473 | }; |
474 | ||
844a3b63 PW |
475 | /* UART2 */ |
476 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
477 | .name = "uart2", | |
844a3b63 | 478 | .main_clk = "uart2_fck", |
a2fc3661 | 479 | .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
480 | .prcm = { |
481 | .omap2 = { | |
482 | .module_offs = CORE_MOD, | |
483 | .prcm_reg_id = 1, | |
484 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
485 | .idlest_reg_id = 1, | |
486 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
487 | }, | |
488 | }, | |
489 | .class = &omap2_uart_class, | |
870ea2b8 HH |
490 | }; |
491 | ||
844a3b63 PW |
492 | /* UART3 */ |
493 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
494 | .name = "uart3", | |
844a3b63 | 495 | .main_clk = "uart3_fck", |
7dedd346 | 496 | .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | |
a2fc3661 | 497 | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
498 | .prcm = { |
499 | .omap2 = { | |
500 | .module_offs = OMAP3430_PER_MOD, | |
501 | .prcm_reg_id = 1, | |
502 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
503 | .idlest_reg_id = 1, | |
504 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
505 | }, | |
273ff8c3 | 506 | }, |
844a3b63 | 507 | .class = &omap2_uart_class, |
273ff8c3 HH |
508 | }; |
509 | ||
844a3b63 | 510 | /* UART4 */ |
273ff8c3 | 511 | |
7359154e | 512 | |
844a3b63 PW |
513 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
514 | .name = "uart4", | |
844a3b63 | 515 | .main_clk = "uart4_fck", |
a2fc3661 | 516 | .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, |
844a3b63 PW |
517 | .prcm = { |
518 | .omap2 = { | |
519 | .module_offs = OMAP3430_PER_MOD, | |
520 | .prcm_reg_id = 1, | |
521 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
522 | .idlest_reg_id = 1, | |
523 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
524 | }, | |
525 | }, | |
526 | .class = &omap2_uart_class, | |
7359154e PW |
527 | }; |
528 | ||
43085705 | 529 | |
7359154e | 530 | |
82ee620d PW |
531 | /* |
532 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | |
533 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | |
534 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | |
535 | * should not be needed. The functional clock structure of the AM35xx | |
536 | * UART4 is extremely unclear and opaque; it is unclear what the role | |
537 | * of uart1/2_fck is for the UART4. Any clarification from either | |
538 | * empirical testing or the AM3505/3517 hardware designers would be | |
539 | * most welcome. | |
540 | */ | |
541 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | |
542 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | |
543 | }; | |
544 | ||
844a3b63 PW |
545 | static struct omap_hwmod am35xx_uart4_hwmod = { |
546 | .name = "uart4", | |
844a3b63 PW |
547 | .main_clk = "uart4_fck", |
548 | .prcm = { | |
549 | .omap2 = { | |
550 | .module_offs = CORE_MOD, | |
551 | .prcm_reg_id = 1, | |
bf765237 | 552 | .module_bit = AM35XX_EN_UART4_SHIFT, |
844a3b63 | 553 | .idlest_reg_id = 1, |
bf765237 | 554 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
844a3b63 PW |
555 | }, |
556 | }, | |
82ee620d PW |
557 | .opt_clks = am35xx_uart4_opt_clks, |
558 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | |
559 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
560 | .class = &omap2_uart_class, |
561 | }; | |
562 | ||
563 | static struct omap_hwmod_class i2c_class = { | |
564 | .name = "i2c", | |
565 | .sysc = &i2c_sysc, | |
566 | .rev = OMAP_I2C_IP_VERSION_1, | |
567 | .reset = &omap_i2c_reset, | |
568 | }; | |
569 | ||
570 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
571 | { .name = "dispc", .dma_req = 5 }, | |
572 | { .name = "dsi1", .dma_req = 74 }, | |
d9d9cec0 | 573 | { .dma_req = -1, }, |
43085705 PW |
574 | }; |
575 | ||
844a3b63 PW |
576 | /* dss */ |
577 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
578 | /* | |
579 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
580 | * driver does not use these clocks. | |
581 | */ | |
582 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
583 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
584 | /* required only on OMAP3430 */ | |
585 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
586 | }; |
587 | ||
844a3b63 PW |
588 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
589 | .name = "dss_core", | |
590 | .class = &omap2_dss_hwmod_class, | |
591 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
592 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
593 | .prcm = { | |
594 | .omap2 = { | |
595 | .prcm_reg_id = 1, | |
596 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
597 | .module_offs = OMAP3430_DSS_MOD, | |
598 | .idlest_reg_id = 1, | |
599 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
600 | }, | |
601 | }, | |
602 | .opt_clks = dss_opt_clks, | |
603 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
604 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
605 | }; | |
540064bf | 606 | |
844a3b63 PW |
607 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
608 | .name = "dss_core", | |
609 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
610 | .class = &omap2_dss_hwmod_class, | |
611 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
612 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
613 | .prcm = { | |
614 | .omap2 = { | |
615 | .prcm_reg_id = 1, | |
616 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
617 | .module_offs = OMAP3430_DSS_MOD, | |
618 | .idlest_reg_id = 1, | |
619 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
620 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
621 | }, | |
622 | }, | |
623 | .opt_clks = dss_opt_clks, | |
624 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
625 | }; |
626 | ||
540064bf | 627 | /* |
844a3b63 PW |
628 | * 'dispc' class |
629 | * display controller | |
540064bf KH |
630 | */ |
631 | ||
844a3b63 | 632 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
633 | .rev_offs = 0x0000, |
634 | .sysc_offs = 0x0010, | |
635 | .syss_offs = 0x0014, | |
844a3b63 PW |
636 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
637 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
638 | SYSC_HAS_ENAWAKEUP), | |
639 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
640 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 641 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
642 | }; |
643 | ||
844a3b63 PW |
644 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
645 | .name = "dispc", | |
646 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
647 | }; |
648 | ||
844a3b63 PW |
649 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
650 | .name = "dss_dispc", | |
651 | .class = &omap3_dispc_hwmod_class, | |
652 | .mpu_irqs = omap2_dispc_irqs, | |
653 | .main_clk = "dss1_alwon_fck", | |
654 | .prcm = { | |
655 | .omap2 = { | |
656 | .prcm_reg_id = 1, | |
657 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
658 | .module_offs = OMAP3430_DSS_MOD, | |
659 | }, | |
660 | }, | |
661 | .flags = HWMOD_NO_IDLEST, | |
d9d9cec0 | 662 | .dev_attr = &omap2_3_dss_dispc_dev_attr, |
6b667f88 VC |
663 | }; |
664 | ||
844a3b63 PW |
665 | /* |
666 | * 'dsi' class | |
667 | * display serial interface controller | |
668 | */ | |
4fe20e97 | 669 | |
b46211d6 SR |
670 | static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = { |
671 | .rev_offs = 0x0000, | |
672 | .sysc_offs = 0x0010, | |
673 | .syss_offs = 0x0014, | |
674 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
675 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
676 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
677 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
678 | .sysc_fields = &omap_hwmod_sysc_type1, | |
679 | }; | |
680 | ||
844a3b63 PW |
681 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
682 | .name = "dsi", | |
b46211d6 | 683 | .sysc = &omap3xxx_dsi_sysc, |
c345c8b0 TKD |
684 | }; |
685 | ||
844a3b63 PW |
686 | /* dss_dsi1 */ |
687 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
688 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
689 | }; |
690 | ||
844a3b63 PW |
691 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
692 | .name = "dss_dsi1", | |
693 | .class = &omap3xxx_dsi_hwmod_class, | |
844a3b63 PW |
694 | .main_clk = "dss1_alwon_fck", |
695 | .prcm = { | |
696 | .omap2 = { | |
697 | .prcm_reg_id = 1, | |
698 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
699 | .module_offs = OMAP3430_DSS_MOD, | |
700 | }, | |
ce722d26 | 701 | }, |
844a3b63 PW |
702 | .opt_clks = dss_dsi1_opt_clks, |
703 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
704 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
705 | }; |
706 | ||
844a3b63 PW |
707 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
708 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
709 | }; |
710 | ||
844a3b63 PW |
711 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
712 | .name = "dss_rfbi", | |
713 | .class = &omap2_rfbi_hwmod_class, | |
714 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
715 | .prcm = { |
716 | .omap2 = { | |
717 | .prcm_reg_id = 1, | |
844a3b63 PW |
718 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
719 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
720 | }, |
721 | }, | |
844a3b63 PW |
722 | .opt_clks = dss_rfbi_opt_clks, |
723 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
724 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
725 | }; |
726 | ||
844a3b63 PW |
727 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
728 | /* required only on OMAP3430 */ | |
729 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
730 | }; |
731 | ||
844a3b63 PW |
732 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
733 | .name = "dss_venc", | |
734 | .class = &omap2_venc_hwmod_class, | |
735 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
736 | .prcm = { |
737 | .omap2 = { | |
046465b7 | 738 | .prcm_reg_id = 1, |
844a3b63 PW |
739 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
740 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
741 | }, |
742 | }, | |
844a3b63 PW |
743 | .opt_clks = dss_venc_opt_clks, |
744 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
745 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
746 | }; |
747 | ||
844a3b63 PW |
748 | /* I2C1 */ |
749 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
750 | .fifo_depth = 8, /* bytes */ | |
972deb4f | 751 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
046465b7 KH |
752 | }; |
753 | ||
844a3b63 PW |
754 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
755 | .name = "i2c1", | |
756 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
844a3b63 | 757 | .main_clk = "i2c1_fck", |
046465b7 KH |
758 | .prcm = { |
759 | .omap2 = { | |
844a3b63 | 760 | .module_offs = CORE_MOD, |
046465b7 | 761 | .prcm_reg_id = 1, |
844a3b63 | 762 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 763 | .idlest_reg_id = 1, |
844a3b63 | 764 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
765 | }, |
766 | }, | |
844a3b63 PW |
767 | .class = &i2c_class, |
768 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
769 | }; |
770 | ||
844a3b63 PW |
771 | /* I2C2 */ |
772 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
773 | .fifo_depth = 8, /* bytes */ | |
972deb4f | 774 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
046465b7 KH |
775 | }; |
776 | ||
844a3b63 PW |
777 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
778 | .name = "i2c2", | |
779 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
844a3b63 | 780 | .main_clk = "i2c2_fck", |
046465b7 KH |
781 | .prcm = { |
782 | .omap2 = { | |
844a3b63 | 783 | .module_offs = CORE_MOD, |
046465b7 | 784 | .prcm_reg_id = 1, |
844a3b63 | 785 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 786 | .idlest_reg_id = 1, |
844a3b63 | 787 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
788 | }, |
789 | }, | |
844a3b63 PW |
790 | .class = &i2c_class, |
791 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
792 | }; |
793 | ||
844a3b63 PW |
794 | /* I2C3 */ |
795 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
796 | .fifo_depth = 64, /* bytes */ | |
972deb4f | 797 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, |
844a3b63 | 798 | }; |
046465b7 | 799 | |
046465b7 | 800 | |
046465b7 | 801 | |
844a3b63 PW |
802 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
803 | .name = "i2c3", | |
804 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
844a3b63 | 805 | .main_clk = "i2c3_fck", |
046465b7 KH |
806 | .prcm = { |
807 | .omap2 = { | |
844a3b63 | 808 | .module_offs = CORE_MOD, |
046465b7 | 809 | .prcm_reg_id = 1, |
844a3b63 | 810 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 811 | .idlest_reg_id = 1, |
844a3b63 | 812 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
813 | }, |
814 | }, | |
844a3b63 PW |
815 | .class = &i2c_class, |
816 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
817 | }; |
818 | ||
844a3b63 PW |
819 | /* |
820 | * 'gpio' class | |
821 | * general purpose io module | |
822 | */ | |
4fe20e97 | 823 | |
844a3b63 PW |
824 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
825 | .rev_offs = 0x0000, | |
826 | .sysc_offs = 0x0010, | |
827 | .syss_offs = 0x0014, | |
828 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
829 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
830 | SYSS_HAS_RESET_STATUS), | |
831 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
832 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
833 | }; |
834 | ||
844a3b63 PW |
835 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
836 | .name = "gpio", | |
837 | .sysc = &omap3xxx_gpio_sysc, | |
838 | .rev = 1, | |
4fe20e97 RN |
839 | }; |
840 | ||
844a3b63 PW |
841 | /* gpio_dev_attr */ |
842 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
843 | .bank_width = 32, | |
844 | .dbck_flag = true, | |
845 | }; | |
846 | ||
847 | /* gpio1 */ | |
848 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
849 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
850 | }; | |
851 | ||
852 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
853 | .name = "gpio1", | |
854 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
855 | .main_clk = "gpio1_ick", |
856 | .opt_clks = gpio1_opt_clks, | |
857 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
858 | .prcm = { |
859 | .omap2 = { | |
4fe20e97 | 860 | .prcm_reg_id = 1, |
844a3b63 PW |
861 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
862 | .module_offs = WKUP_MOD, | |
4fe20e97 | 863 | .idlest_reg_id = 1, |
844a3b63 | 864 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
865 | }, |
866 | }, | |
844a3b63 PW |
867 | .class = &omap3xxx_gpio_hwmod_class, |
868 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
869 | }; |
870 | ||
844a3b63 PW |
871 | /* gpio2 */ |
872 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
873 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
874 | }; |
875 | ||
844a3b63 PW |
876 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
877 | .name = "gpio2", | |
878 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
879 | .main_clk = "gpio2_ick", |
880 | .opt_clks = gpio2_opt_clks, | |
881 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
882 | .prcm = { |
883 | .omap2 = { | |
4fe20e97 | 884 | .prcm_reg_id = 1, |
844a3b63 | 885 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 886 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 887 | .idlest_reg_id = 1, |
844a3b63 | 888 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
889 | }, |
890 | }, | |
844a3b63 PW |
891 | .class = &omap3xxx_gpio_hwmod_class, |
892 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
893 | }; |
894 | ||
844a3b63 PW |
895 | /* gpio3 */ |
896 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
897 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
898 | }; |
899 | ||
844a3b63 PW |
900 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
901 | .name = "gpio3", | |
902 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
903 | .main_clk = "gpio3_ick", |
904 | .opt_clks = gpio3_opt_clks, | |
905 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
906 | .prcm = { |
907 | .omap2 = { | |
4fe20e97 | 908 | .prcm_reg_id = 1, |
844a3b63 | 909 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 910 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 911 | .idlest_reg_id = 1, |
844a3b63 | 912 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
913 | }, |
914 | }, | |
844a3b63 PW |
915 | .class = &omap3xxx_gpio_hwmod_class, |
916 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
917 | }; |
918 | ||
844a3b63 PW |
919 | /* gpio4 */ |
920 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
921 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
922 | }; |
923 | ||
844a3b63 PW |
924 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
925 | .name = "gpio4", | |
926 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
927 | .main_clk = "gpio4_ick", |
928 | .opt_clks = gpio4_opt_clks, | |
929 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
930 | .prcm = { |
931 | .omap2 = { | |
932 | .prcm_reg_id = 1, | |
844a3b63 | 933 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
934 | .module_offs = OMAP3430_PER_MOD, |
935 | .idlest_reg_id = 1, | |
844a3b63 | 936 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 937 | }, |
70034d38 | 938 | }, |
844a3b63 PW |
939 | .class = &omap3xxx_gpio_hwmod_class, |
940 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
941 | }; |
942 | ||
844a3b63 | 943 | /* gpio5 */ |
70034d38 | 944 | |
844a3b63 PW |
945 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
946 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
947 | }; |
948 | ||
844a3b63 PW |
949 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
950 | .name = "gpio5", | |
951 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
952 | .main_clk = "gpio5_ick", |
953 | .opt_clks = gpio5_opt_clks, | |
954 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
955 | .prcm = { |
956 | .omap2 = { | |
957 | .prcm_reg_id = 1, | |
844a3b63 PW |
958 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
959 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 960 | .idlest_reg_id = 1, |
844a3b63 | 961 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 962 | }, |
70034d38 | 963 | }, |
844a3b63 PW |
964 | .class = &omap3xxx_gpio_hwmod_class, |
965 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
966 | }; |
967 | ||
844a3b63 | 968 | /* gpio6 */ |
70034d38 | 969 | |
844a3b63 PW |
970 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
971 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
972 | }; |
973 | ||
844a3b63 PW |
974 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
975 | .name = "gpio6", | |
976 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
977 | .main_clk = "gpio6_ick", |
978 | .opt_clks = gpio6_opt_clks, | |
979 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
980 | .prcm = { |
981 | .omap2 = { | |
982 | .prcm_reg_id = 1, | |
844a3b63 PW |
983 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
984 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 985 | .idlest_reg_id = 1, |
844a3b63 | 986 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
987 | }, |
988 | }, | |
844a3b63 PW |
989 | .class = &omap3xxx_gpio_hwmod_class, |
990 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
991 | }; |
992 | ||
844a3b63 PW |
993 | /* dma attributes */ |
994 | static struct omap_dma_dev_attr dma_dev_attr = { | |
995 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
996 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
997 | .lch_count = 32, | |
ce722d26 TG |
998 | }; |
999 | ||
844a3b63 PW |
1000 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1001 | .rev_offs = 0x0000, | |
1002 | .sysc_offs = 0x002c, | |
1003 | .syss_offs = 0x0028, | |
1004 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1005 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1006 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1007 | SYSS_HAS_RESET_STATUS), | |
1008 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1009 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1010 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1011 | }; |
1012 | ||
844a3b63 PW |
1013 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1014 | .name = "dma", | |
1015 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1016 | }; |
1017 | ||
844a3b63 PW |
1018 | /* dma_system */ |
1019 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1020 | .name = "dma", | |
1021 | .class = &omap3xxx_dma_hwmod_class, | |
1022 | .mpu_irqs = omap2_dma_system_irqs, | |
1023 | .main_clk = "core_l3_ick", | |
1024 | .prcm = { | |
ce722d26 | 1025 | .omap2 = { |
844a3b63 PW |
1026 | .module_offs = CORE_MOD, |
1027 | .prcm_reg_id = 1, | |
1028 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1029 | .idlest_reg_id = 1, | |
1030 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1031 | }, |
1032 | }, | |
844a3b63 PW |
1033 | .dev_attr = &dma_dev_attr, |
1034 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1035 | }; |
1036 | ||
844a3b63 PW |
1037 | /* |
1038 | * 'mcbsp' class | |
1039 | * multi channel buffered serial port controller | |
1040 | */ | |
1041 | ||
1042 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1043 | .sysc_offs = 0x008c, | |
1044 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1045 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1046 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1047 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1048 | .clockact = 0x2, | |
70034d38 VC |
1049 | }; |
1050 | ||
844a3b63 PW |
1051 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1052 | .name = "mcbsp", | |
1053 | .sysc = &omap3xxx_mcbsp_sysc, | |
1054 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1055 | }; |
1056 | ||
7039154b PU |
1057 | /* McBSP functional clock mapping */ |
1058 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | |
1059 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1060 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | |
1061 | }; | |
1062 | ||
1063 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | |
1064 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1065 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | |
1066 | }; | |
1067 | ||
844a3b63 | 1068 | /* mcbsp1 */ |
6b667f88 | 1069 | |
844a3b63 PW |
1070 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1071 | .name = "mcbsp1", | |
1072 | .class = &omap3xxx_mcbsp_hwmod_class, | |
844a3b63 PW |
1073 | .main_clk = "mcbsp1_fck", |
1074 | .prcm = { | |
1075 | .omap2 = { | |
1076 | .prcm_reg_id = 1, | |
1077 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1078 | .module_offs = CORE_MOD, | |
1079 | .idlest_reg_id = 1, | |
1080 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1081 | }, | |
1082 | }, | |
7039154b PU |
1083 | .opt_clks = mcbsp15_opt_clks, |
1084 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1085 | }; |
1086 | ||
844a3b63 | 1087 | /* mcbsp2 */ |
70034d38 | 1088 | |
844a3b63 PW |
1089 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1090 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1091 | }; |
1092 | ||
844a3b63 PW |
1093 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1094 | .name = "mcbsp2", | |
1095 | .class = &omap3xxx_mcbsp_hwmod_class, | |
844a3b63 | 1096 | .main_clk = "mcbsp2_fck", |
70034d38 VC |
1097 | .prcm = { |
1098 | .omap2 = { | |
1099 | .prcm_reg_id = 1, | |
844a3b63 PW |
1100 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1101 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1102 | .idlest_reg_id = 1, |
844a3b63 | 1103 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1104 | }, |
1105 | }, | |
7039154b PU |
1106 | .opt_clks = mcbsp234_opt_clks, |
1107 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1108 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1109 | }; |
1110 | ||
844a3b63 | 1111 | /* mcbsp3 */ |
844a3b63 PW |
1112 | |
1113 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1114 | .sidetone = "mcbsp3_sidetone", | |
1115 | }; | |
1116 | ||
1117 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1118 | .name = "mcbsp3", | |
1119 | .class = &omap3xxx_mcbsp_hwmod_class, | |
844a3b63 | 1120 | .main_clk = "mcbsp3_fck", |
70034d38 VC |
1121 | .prcm = { |
1122 | .omap2 = { | |
1123 | .prcm_reg_id = 1, | |
844a3b63 PW |
1124 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1125 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1126 | .idlest_reg_id = 1, |
844a3b63 | 1127 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1128 | }, |
1129 | }, | |
7039154b PU |
1130 | .opt_clks = mcbsp234_opt_clks, |
1131 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1132 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1133 | }; |
1134 | ||
844a3b63 | 1135 | /* mcbsp4 */ |
844a3b63 | 1136 | |
844a3b63 PW |
1137 | |
1138 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1139 | .name = "mcbsp4", | |
1140 | .class = &omap3xxx_mcbsp_hwmod_class, | |
844a3b63 | 1141 | .main_clk = "mcbsp4_fck", |
70034d38 VC |
1142 | .prcm = { |
1143 | .omap2 = { | |
1144 | .prcm_reg_id = 1, | |
844a3b63 PW |
1145 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1146 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1147 | .idlest_reg_id = 1, |
844a3b63 | 1148 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1149 | }, |
1150 | }, | |
7039154b PU |
1151 | .opt_clks = mcbsp234_opt_clks, |
1152 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
046465b7 KH |
1153 | }; |
1154 | ||
844a3b63 | 1155 | /* mcbsp5 */ |
844a3b63 | 1156 | |
844a3b63 PW |
1157 | |
1158 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1159 | .name = "mcbsp5", | |
1160 | .class = &omap3xxx_mcbsp_hwmod_class, | |
844a3b63 | 1161 | .main_clk = "mcbsp5_fck", |
046465b7 KH |
1162 | .prcm = { |
1163 | .omap2 = { | |
046465b7 | 1164 | .prcm_reg_id = 1, |
844a3b63 PW |
1165 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1166 | .module_offs = CORE_MOD, | |
70034d38 | 1167 | .idlest_reg_id = 1, |
844a3b63 | 1168 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1169 | }, |
1170 | }, | |
7039154b PU |
1171 | .opt_clks = mcbsp15_opt_clks, |
1172 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1173 | }; |
1174 | ||
844a3b63 PW |
1175 | /* 'mcbsp sidetone' class */ |
1176 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1177 | .sysc_offs = 0x0010, | |
1178 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1179 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1180 | }; | |
046465b7 | 1181 | |
844a3b63 PW |
1182 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1183 | .name = "mcbsp_sidetone", | |
1184 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1185 | }; |
1186 | ||
844a3b63 | 1187 | /* mcbsp2_sidetone */ |
70034d38 | 1188 | |
844a3b63 PW |
1189 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1190 | .name = "mcbsp2_sidetone", | |
1191 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
3b80c9be PU |
1192 | .main_clk = "mcbsp2_ick", |
1193 | .flags = HWMOD_NO_IDLEST, | |
4bf90f65 KM |
1194 | }; |
1195 | ||
844a3b63 | 1196 | /* mcbsp3_sidetone */ |
4bf90f65 | 1197 | |
844a3b63 PW |
1198 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1199 | .name = "mcbsp3_sidetone", | |
1200 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
3b80c9be PU |
1201 | .main_clk = "mcbsp3_ick", |
1202 | .flags = HWMOD_NO_IDLEST, | |
4bf90f65 KM |
1203 | }; |
1204 | ||
844a3b63 PW |
1205 | /* SR common */ |
1206 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1207 | .clkact_shift = 20, | |
1208 | }; | |
4bf90f65 | 1209 | |
844a3b63 PW |
1210 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1211 | .sysc_offs = 0x24, | |
1212 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1213 | .clockact = CLOCKACT_TEST_ICLK, | |
1214 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1215 | }; |
1216 | ||
844a3b63 PW |
1217 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1218 | .name = "smartreflex", | |
1219 | .sysc = &omap34xx_sr_sysc, | |
1220 | .rev = 1, | |
e04d9e1e SG |
1221 | }; |
1222 | ||
844a3b63 PW |
1223 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1224 | .sidle_shift = 24, | |
1225 | .enwkup_shift = 26, | |
1226 | }; | |
e04d9e1e | 1227 | |
844a3b63 PW |
1228 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1229 | .sysc_offs = 0x38, | |
1230 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1231 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1232 | SYSC_NO_CACHE), | |
1233 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1234 | }; | |
1235 | ||
1236 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1237 | .name = "smartreflex", | |
1238 | .sysc = &omap36xx_sr_sysc, | |
1239 | .rev = 2, | |
1240 | }; | |
1241 | ||
1242 | /* SR1 */ | |
1243 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1244 | .sensor_voltdm_name = "mpu_iva", | |
1245 | }; | |
1246 | ||
844a3b63 PW |
1247 | |
1248 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1fcd3069 | 1249 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1250 | .class = &omap34xx_smartreflex_hwmod_class, |
1251 | .main_clk = "sr1_fck", | |
1252 | .prcm = { | |
e04d9e1e | 1253 | .omap2 = { |
844a3b63 PW |
1254 | .prcm_reg_id = 1, |
1255 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1256 | .module_offs = WKUP_MOD, | |
1257 | .idlest_reg_id = 1, | |
1258 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1259 | }, | |
e04d9e1e | 1260 | }, |
844a3b63 | 1261 | .dev_attr = &sr1_dev_attr, |
844a3b63 | 1262 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
e04d9e1e SG |
1263 | }; |
1264 | ||
844a3b63 | 1265 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1fcd3069 | 1266 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1267 | .class = &omap36xx_smartreflex_hwmod_class, |
1268 | .main_clk = "sr1_fck", | |
1269 | .prcm = { | |
e04d9e1e | 1270 | .omap2 = { |
844a3b63 PW |
1271 | .prcm_reg_id = 1, |
1272 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1273 | .module_offs = WKUP_MOD, | |
1274 | .idlest_reg_id = 1, | |
1275 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1276 | }, | |
e04d9e1e | 1277 | }, |
844a3b63 | 1278 | .dev_attr = &sr1_dev_attr, |
e04d9e1e SG |
1279 | }; |
1280 | ||
844a3b63 PW |
1281 | /* SR2 */ |
1282 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1283 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1284 | }; |
1285 | ||
844a3b63 PW |
1286 | |
1287 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1fcd3069 | 1288 | .name = "smartreflex_core", |
844a3b63 PW |
1289 | .class = &omap34xx_smartreflex_hwmod_class, |
1290 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1291 | .prcm = { |
1292 | .omap2 = { | |
1293 | .prcm_reg_id = 1, | |
844a3b63 PW |
1294 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1295 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1296 | .idlest_reg_id = 1, |
844a3b63 | 1297 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1298 | }, |
1299 | }, | |
844a3b63 | 1300 | .dev_attr = &sr2_dev_attr, |
844a3b63 | 1301 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
e04d9e1e SG |
1302 | }; |
1303 | ||
844a3b63 | 1304 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1fcd3069 | 1305 | .name = "smartreflex_core", |
844a3b63 PW |
1306 | .class = &omap36xx_smartreflex_hwmod_class, |
1307 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1308 | .prcm = { |
1309 | .omap2 = { | |
1310 | .prcm_reg_id = 1, | |
844a3b63 PW |
1311 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1312 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1313 | .idlest_reg_id = 1, |
844a3b63 | 1314 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1315 | }, |
1316 | }, | |
844a3b63 | 1317 | .dev_attr = &sr2_dev_attr, |
e04d9e1e SG |
1318 | }; |
1319 | ||
1ac6d46e | 1320 | /* |
844a3b63 PW |
1321 | * 'mailbox' class |
1322 | * mailbox module allowing communication between the on-chip processors | |
1323 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1324 | */ |
1325 | ||
844a3b63 PW |
1326 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1327 | .rev_offs = 0x000, | |
1328 | .sysc_offs = 0x010, | |
1329 | .syss_offs = 0x014, | |
1330 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1331 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1332 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1333 | .sysc_fields = &omap_hwmod_sysc_type1, |
1334 | }; | |
1335 | ||
844a3b63 PW |
1336 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1337 | .name = "mailbox", | |
1338 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1339 | }; |
1340 | ||
844a3b63 PW |
1341 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1342 | .name = "mailbox", | |
1343 | .class = &omap3xxx_mailbox_hwmod_class, | |
844a3b63 | 1344 | .main_clk = "mailboxes_ick", |
e04d9e1e SG |
1345 | .prcm = { |
1346 | .omap2 = { | |
1347 | .prcm_reg_id = 1, | |
844a3b63 PW |
1348 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1349 | .module_offs = CORE_MOD, | |
1350 | .idlest_reg_id = 1, | |
1351 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1352 | }, |
1353 | }, | |
e04d9e1e SG |
1354 | }; |
1355 | ||
1356 | /* | |
844a3b63 PW |
1357 | * 'mcspi' class |
1358 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1359 | * bus | |
e04d9e1e SG |
1360 | */ |
1361 | ||
844a3b63 PW |
1362 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1363 | .rev_offs = 0x0000, | |
1364 | .sysc_offs = 0x0010, | |
1365 | .syss_offs = 0x0014, | |
1366 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1367 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1368 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1369 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1370 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1371 | }; |
1372 | ||
844a3b63 PW |
1373 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1374 | .name = "mcspi", | |
1375 | .sysc = &omap34xx_mcspi_sysc, | |
1376 | .rev = OMAP3_MCSPI_REV, | |
affe360d AT |
1377 | }; |
1378 | ||
844a3b63 PW |
1379 | /* mcspi1 */ |
1380 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1381 | .num_chipselect = 4, | |
e04d9e1e SG |
1382 | }; |
1383 | ||
844a3b63 PW |
1384 | static struct omap_hwmod omap34xx_mcspi1 = { |
1385 | .name = "mcspi1", | |
844a3b63 PW |
1386 | .main_clk = "mcspi1_fck", |
1387 | .prcm = { | |
e04d9e1e | 1388 | .omap2 = { |
844a3b63 PW |
1389 | .module_offs = CORE_MOD, |
1390 | .prcm_reg_id = 1, | |
1391 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1392 | .idlest_reg_id = 1, | |
1393 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1394 | }, | |
e04d9e1e | 1395 | }, |
844a3b63 PW |
1396 | .class = &omap34xx_mcspi_class, |
1397 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1398 | }; |
1399 | ||
844a3b63 PW |
1400 | /* mcspi2 */ |
1401 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1402 | .num_chipselect = 2, | |
6c3d7e34 TV |
1403 | }; |
1404 | ||
844a3b63 PW |
1405 | static struct omap_hwmod omap34xx_mcspi2 = { |
1406 | .name = "mcspi2", | |
844a3b63 | 1407 | .main_clk = "mcspi2_fck", |
e04d9e1e SG |
1408 | .prcm = { |
1409 | .omap2 = { | |
844a3b63 | 1410 | .module_offs = CORE_MOD, |
e04d9e1e | 1411 | .prcm_reg_id = 1, |
844a3b63 PW |
1412 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1413 | .idlest_reg_id = 1, | |
1414 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1415 | }, |
1416 | }, | |
844a3b63 PW |
1417 | .class = &omap34xx_mcspi_class, |
1418 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1419 | }; |
1420 | ||
844a3b63 | 1421 | /* mcspi3 */ |
844a3b63 | 1422 | |
e04d9e1e | 1423 | |
844a3b63 PW |
1424 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1425 | .num_chipselect = 2, | |
6c3d7e34 TV |
1426 | }; |
1427 | ||
844a3b63 PW |
1428 | static struct omap_hwmod omap34xx_mcspi3 = { |
1429 | .name = "mcspi3", | |
844a3b63 | 1430 | .main_clk = "mcspi3_fck", |
e04d9e1e SG |
1431 | .prcm = { |
1432 | .omap2 = { | |
844a3b63 | 1433 | .module_offs = CORE_MOD, |
e04d9e1e | 1434 | .prcm_reg_id = 1, |
844a3b63 PW |
1435 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1436 | .idlest_reg_id = 1, | |
1437 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1438 | }, |
1439 | }, | |
844a3b63 PW |
1440 | .class = &omap34xx_mcspi_class, |
1441 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1442 | }; |
1443 | ||
844a3b63 | 1444 | /* mcspi4 */ |
e04d9e1e | 1445 | |
6c3d7e34 | 1446 | |
844a3b63 PW |
1447 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1448 | .num_chipselect = 1, | |
1449 | }; | |
1450 | ||
1451 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1452 | .name = "mcspi4", | |
844a3b63 | 1453 | .main_clk = "mcspi4_fck", |
e04d9e1e SG |
1454 | .prcm = { |
1455 | .omap2 = { | |
844a3b63 | 1456 | .module_offs = CORE_MOD, |
e04d9e1e | 1457 | .prcm_reg_id = 1, |
844a3b63 PW |
1458 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1459 | .idlest_reg_id = 1, | |
1460 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1461 | }, |
1462 | }, | |
844a3b63 PW |
1463 | .class = &omap34xx_mcspi_class, |
1464 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1465 | }; |
1466 | ||
844a3b63 PW |
1467 | /* usbhsotg */ |
1468 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1469 | .rev_offs = 0x0400, | |
1470 | .sysc_offs = 0x0404, | |
1471 | .syss_offs = 0x0408, | |
1472 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1473 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1474 | SYSC_HAS_AUTOIDLE), | |
1475 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1476 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1477 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1478 | }; | |
4fe20e97 | 1479 | |
844a3b63 PW |
1480 | static struct omap_hwmod_class usbotg_class = { |
1481 | .name = "usbotg", | |
1482 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1483 | }; |
1484 | ||
844a3b63 | 1485 | /* usb_otg_hs */ |
844a3b63 PW |
1486 | |
1487 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1488 | .name = "usb_otg_hs", | |
844a3b63 | 1489 | .main_clk = "hsotgusb_ick", |
4fe20e97 RN |
1490 | .prcm = { |
1491 | .omap2 = { | |
4fe20e97 | 1492 | .prcm_reg_id = 1, |
844a3b63 PW |
1493 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1494 | .module_offs = CORE_MOD, | |
4fe20e97 | 1495 | .idlest_reg_id = 1, |
844a3b63 | 1496 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
d9d9cec0 | 1497 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT, |
4fe20e97 RN |
1498 | }, |
1499 | }, | |
844a3b63 PW |
1500 | .class = &usbotg_class, |
1501 | ||
1502 | /* | |
1503 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1504 | * broken when autoidle is enabled | |
1505 | * workaround is to disable the autoidle bit at module level. | |
092bc089 GI |
1506 | * |
1507 | * Enabling the device in any other MIDLEMODE setting but force-idle | |
1508 | * causes core_pwrdm not enter idle states at least on OMAP3630. | |
1509 | * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY | |
1510 | * signal when MIDLEMODE is set to force-idle. | |
844a3b63 | 1511 | */ |
6a08b11a TL |
1512 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1513 | HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN, | |
4fe20e97 RN |
1514 | }; |
1515 | ||
844a3b63 | 1516 | /* usb_otg_hs */ |
4fe20e97 | 1517 | |
844a3b63 PW |
1518 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1519 | .name = "am35xx_usbotg", | |
844a3b63 PW |
1520 | }; |
1521 | ||
1522 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1523 | .name = "am35x_otg_hs", | |
89ea2583 | 1524 | .main_clk = "hsotgusb_fck", |
844a3b63 | 1525 | .class = &am35xx_usbotg_class, |
89ea2583 | 1526 | .flags = HWMOD_NO_IDLEST, |
4fe20e97 RN |
1527 | }; |
1528 | ||
844a3b63 PW |
1529 | /* MMC/SD/SDIO common */ |
1530 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1531 | .rev_offs = 0x1fc, | |
1532 | .sysc_offs = 0x10, | |
1533 | .syss_offs = 0x14, | |
1534 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1535 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1536 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1537 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1538 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1539 | }; | |
4fe20e97 | 1540 | |
844a3b63 PW |
1541 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1542 | .name = "mmc", | |
1543 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1544 | }; |
1545 | ||
844a3b63 PW |
1546 | /* MMC/SD/SDIO1 */ |
1547 | ||
4fe20e97 | 1548 | |
4fe20e97 | 1549 | |
844a3b63 PW |
1550 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1551 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1552 | }; | |
1553 | ||
55143438 | 1554 | static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
844a3b63 PW |
1555 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
1556 | }; | |
1557 | ||
1558 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
55143438 | 1559 | static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = { |
844a3b63 PW |
1560 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | |
1561 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1562 | }; | |
1563 | ||
1564 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1565 | .name = "mmc1", | |
844a3b63 PW |
1566 | .opt_clks = omap34xx_mmc1_opt_clks, |
1567 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1568 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1569 | .prcm = { |
1570 | .omap2 = { | |
1571 | .module_offs = CORE_MOD, | |
1572 | .prcm_reg_id = 1, | |
844a3b63 | 1573 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1574 | .idlest_reg_id = 1, |
844a3b63 | 1575 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1576 | }, |
1577 | }, | |
844a3b63 PW |
1578 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1579 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1580 | }; |
1581 | ||
844a3b63 PW |
1582 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1583 | .name = "mmc1", | |
844a3b63 PW |
1584 | .opt_clks = omap34xx_mmc1_opt_clks, |
1585 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1586 | .main_clk = "mmchs1_fck", | |
1587 | .prcm = { | |
1588 | .omap2 = { | |
1589 | .module_offs = CORE_MOD, | |
1590 | .prcm_reg_id = 1, | |
1591 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1592 | .idlest_reg_id = 1, | |
1593 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1594 | }, | |
70034d38 | 1595 | }, |
844a3b63 PW |
1596 | .dev_attr = &mmc1_dev_attr, |
1597 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1598 | }; |
1599 | ||
844a3b63 | 1600 | /* MMC/SD/SDIO2 */ |
70034d38 | 1601 | |
70034d38 | 1602 | |
70034d38 | 1603 | |
844a3b63 PW |
1604 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1605 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1606 | }; |
1607 | ||
844a3b63 | 1608 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
55143438 | 1609 | static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = { |
844a3b63 | 1610 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, |
70034d38 VC |
1611 | }; |
1612 | ||
844a3b63 PW |
1613 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1614 | .name = "mmc2", | |
844a3b63 PW |
1615 | .opt_clks = omap34xx_mmc2_opt_clks, |
1616 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1617 | .main_clk = "mmchs2_fck", | |
1618 | .prcm = { | |
1619 | .omap2 = { | |
1620 | .module_offs = CORE_MOD, | |
1621 | .prcm_reg_id = 1, | |
1622 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1623 | .idlest_reg_id = 1, | |
1624 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1625 | }, | |
70034d38 | 1626 | }, |
844a3b63 PW |
1627 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1628 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1629 | }; |
1630 | ||
844a3b63 PW |
1631 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1632 | .name = "mmc2", | |
844a3b63 PW |
1633 | .opt_clks = omap34xx_mmc2_opt_clks, |
1634 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1635 | .main_clk = "mmchs2_fck", | |
1636 | .prcm = { | |
1637 | .omap2 = { | |
1638 | .module_offs = CORE_MOD, | |
1639 | .prcm_reg_id = 1, | |
1640 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1641 | .idlest_reg_id = 1, | |
1642 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1643 | }, | |
1644 | }, | |
1645 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1646 | }; |
1647 | ||
844a3b63 PW |
1648 | /* MMC/SD/SDIO3 */ |
1649 | ||
70034d38 | 1650 | |
70034d38 | 1651 | |
844a3b63 PW |
1652 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1653 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1654 | }; |
1655 | ||
844a3b63 PW |
1656 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1657 | .name = "mmc3", | |
844a3b63 PW |
1658 | .opt_clks = omap34xx_mmc3_opt_clks, |
1659 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1660 | .main_clk = "mmchs3_fck", | |
1661 | .prcm = { | |
1662 | .omap2 = { | |
1663 | .prcm_reg_id = 1, | |
1664 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1665 | .idlest_reg_id = 1, | |
1666 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1667 | }, | |
1668 | }, | |
1669 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1670 | }; |
1671 | ||
1672 | /* | |
844a3b63 PW |
1673 | * 'usb_host_hs' class |
1674 | * high-speed multi-port usb host controller | |
70034d38 VC |
1675 | */ |
1676 | ||
844a3b63 | 1677 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1678 | .rev_offs = 0x0000, |
1679 | .sysc_offs = 0x0010, | |
1680 | .syss_offs = 0x0014, | |
844a3b63 PW |
1681 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1682 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
7f4d3641 RQ |
1683 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1684 | SYSS_HAS_RESET_STATUS), | |
844a3b63 PW |
1685 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1686 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1687 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1688 | }; |
1689 | ||
844a3b63 PW |
1690 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1691 | .name = "usb_host_hs", | |
1692 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1693 | }; |
1694 | ||
70034d38 | 1695 | |
844a3b63 PW |
1696 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1697 | .name = "usb_host_hs", | |
1698 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
c6c56697 | 1699 | .clkdm_name = "usbhost_clkdm", |
844a3b63 PW |
1700 | .main_clk = "usbhost_48m_fck", |
1701 | .prcm = { | |
70034d38 | 1702 | .omap2 = { |
844a3b63 | 1703 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1704 | .prcm_reg_id = 1, |
844a3b63 | 1705 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1706 | .idlest_reg_id = 1, |
844a3b63 PW |
1707 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1708 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1709 | }, |
1710 | }, | |
70034d38 | 1711 | |
844a3b63 PW |
1712 | /* |
1713 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1714 | * id: i660 | |
1715 | * | |
1716 | * Description: | |
1717 | * In the following configuration : | |
1718 | * - USBHOST module is set to smart-idle mode | |
1719 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1720 | * happens when the system is going to a low power mode : all ports | |
1721 | * have been suspended, the master part of the USBHOST module has | |
1722 | * entered the standby state, and SW has cut the functional clocks) | |
1723 | * - an USBHOST interrupt occurs before the module is able to answer | |
1724 | * idle_ack, typically a remote wakeup IRQ. | |
1725 | * Then the USB HOST module will enter a deadlock situation where it | |
1726 | * is no more accessible nor functional. | |
1727 | * | |
1728 | * Workaround: | |
1729 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1730 | */ | |
1731 | ||
1732 | /* | |
1733 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1734 | * Id: i571 | |
1735 | * | |
1736 | * Description: | |
1737 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1738 | * ready to enter the standby state (i.e. all ports are suspended and | |
1739 | * all attached devices are in suspend mode), then it can wrongly assert | |
1740 | * the Mstandby signal too early while there are still some residual OCP | |
1741 | * transactions ongoing. If this condition occurs, the internal state | |
1742 | * machine may go to an undefined state and the USB link may be stuck | |
1743 | * upon the next resume. | |
1744 | * | |
1745 | * Workaround: | |
1746 | * Don't use smart standby; use only force standby, | |
1747 | * hence HWMOD_SWSUP_MSTANDBY | |
1748 | */ | |
1749 | ||
7f4d3641 | 1750 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
70034d38 VC |
1751 | }; |
1752 | ||
844a3b63 PW |
1753 | /* |
1754 | * 'usb_tll_hs' class | |
1755 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1756 | */ | |
1757 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
1758 | .rev_offs = 0x0000, | |
1759 | .sysc_offs = 0x0010, | |
1760 | .syss_offs = 0x0014, | |
1761 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1762 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1763 | SYSC_HAS_AUTOIDLE), | |
1764 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1765 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1766 | }; |
1767 | ||
844a3b63 PW |
1768 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
1769 | .name = "usb_tll_hs", | |
1770 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
1771 | }; |
1772 | ||
70034d38 | 1773 | |
844a3b63 PW |
1774 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
1775 | .name = "usb_tll_hs", | |
1776 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
c6c56697 | 1777 | .clkdm_name = "core_l4_clkdm", |
844a3b63 PW |
1778 | .main_clk = "usbtll_fck", |
1779 | .prcm = { | |
70034d38 | 1780 | .omap2 = { |
844a3b63 PW |
1781 | .module_offs = CORE_MOD, |
1782 | .prcm_reg_id = 3, | |
1783 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1784 | .idlest_reg_id = 3, | |
1785 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
1786 | }, |
1787 | }, | |
70034d38 VC |
1788 | }; |
1789 | ||
45a4bb06 PW |
1790 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
1791 | .name = "hdq1w", | |
45a4bb06 PW |
1792 | .main_clk = "hdq_fck", |
1793 | .prcm = { | |
1794 | .omap2 = { | |
1795 | .module_offs = CORE_MOD, | |
1796 | .prcm_reg_id = 1, | |
1797 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
1798 | .idlest_reg_id = 1, | |
1799 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
1800 | }, | |
1801 | }, | |
1802 | .class = &omap2_hdq1w_class, | |
1803 | }; | |
1804 | ||
8f993a01 TK |
1805 | /* SAD2D */ |
1806 | static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { | |
1807 | { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, | |
1808 | { .name = "rst_modem_sw", .rst_shift = 1 }, | |
1809 | }; | |
1810 | ||
1811 | static struct omap_hwmod_class omap3xxx_sad2d_class = { | |
1812 | .name = "sad2d", | |
1813 | }; | |
1814 | ||
1815 | static struct omap_hwmod omap3xxx_sad2d_hwmod = { | |
1816 | .name = "sad2d", | |
1817 | .rst_lines = omap3xxx_sad2d_resets, | |
1818 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), | |
1819 | .main_clk = "sad2d_ick", | |
1820 | .prcm = { | |
1821 | .omap2 = { | |
1822 | .module_offs = CORE_MOD, | |
1823 | .prcm_reg_id = 1, | |
1824 | .module_bit = OMAP3430_EN_SAD2D_SHIFT, | |
1825 | .idlest_reg_id = 1, | |
1826 | .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, | |
1827 | }, | |
1828 | }, | |
1829 | .class = &omap3xxx_sad2d_class, | |
1830 | }; | |
1831 | ||
c8d82ff6 VH |
1832 | /* |
1833 | * '32K sync counter' class | |
1834 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
1835 | */ | |
1836 | static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { | |
1837 | .rev_offs = 0x0000, | |
1838 | .sysc_offs = 0x0004, | |
1839 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1840 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
1841 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1842 | }; | |
1843 | ||
1844 | static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { | |
1845 | .name = "counter", | |
1846 | .sysc = &omap3xxx_counter_sysc, | |
1847 | }; | |
1848 | ||
1849 | static struct omap_hwmod omap3xxx_counter_32k_hwmod = { | |
1850 | .name = "counter_32k", | |
1851 | .class = &omap3xxx_counter_hwmod_class, | |
1852 | .clkdm_name = "wkup_clkdm", | |
1853 | .flags = HWMOD_SWSUP_SIDLE, | |
1854 | .main_clk = "wkup_32k_fck", | |
1855 | .prcm = { | |
1856 | .omap2 = { | |
1857 | .module_offs = WKUP_MOD, | |
1858 | .prcm_reg_id = 1, | |
1859 | .module_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
1860 | .idlest_reg_id = 1, | |
1861 | .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
1862 | }, | |
1863 | }, | |
1864 | }; | |
1865 | ||
49484a60 AM |
1866 | /* |
1867 | * 'gpmc' class | |
1868 | * general purpose memory controller | |
1869 | */ | |
1870 | ||
1871 | static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { | |
1872 | .rev_offs = 0x0000, | |
1873 | .sysc_offs = 0x0010, | |
1874 | .syss_offs = 0x0014, | |
1875 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1876 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1877 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1878 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1879 | }; | |
1880 | ||
1881 | static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { | |
1882 | .name = "gpmc", | |
1883 | .sysc = &omap3xxx_gpmc_sysc, | |
1884 | }; | |
1885 | ||
49484a60 AM |
1886 | static struct omap_hwmod omap3xxx_gpmc_hwmod = { |
1887 | .name = "gpmc", | |
1888 | .class = &omap3xxx_gpmc_hwmod_class, | |
1889 | .clkdm_name = "core_l3_clkdm", | |
49484a60 | 1890 | .main_clk = "gpmc_fck", |
63aa945b TL |
1891 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
1892 | .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
49484a60 AM |
1893 | }; |
1894 | ||
844a3b63 PW |
1895 | /* |
1896 | * interfaces | |
1897 | */ | |
1898 | ||
1899 | /* L3 -> L4_CORE interface */ | |
1900 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
1901 | .master = &omap3xxx_l3_main_hwmod, | |
1902 | .slave = &omap3xxx_l4_core_hwmod, | |
1903 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
1904 | }; |
1905 | ||
844a3b63 PW |
1906 | /* L3 -> L4_PER interface */ |
1907 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
1908 | .master = &omap3xxx_l3_main_hwmod, | |
1909 | .slave = &omap3xxx_l4_per_hwmod, | |
1910 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
1911 | }; |
1912 | ||
70034d38 | 1913 | |
844a3b63 PW |
1914 | /* MPU -> L3 interface */ |
1915 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
1916 | .master = &omap3xxx_mpu_hwmod, | |
1917 | .slave = &omap3xxx_l3_main_hwmod, | |
844a3b63 | 1918 | .user = OCP_USER_MPU, |
70034d38 VC |
1919 | }; |
1920 | ||
c7dad45f JH |
1921 | |
1922 | /* l3 -> debugss */ | |
1923 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { | |
1924 | .master = &omap3xxx_l3_main_hwmod, | |
1925 | .slave = &omap3xxx_debugss_hwmod, | |
c7dad45f JH |
1926 | .user = OCP_USER_MPU, |
1927 | }; | |
1928 | ||
844a3b63 PW |
1929 | /* DSS -> l3 */ |
1930 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
1931 | .master = &omap3430es1_dss_core_hwmod, | |
1932 | .slave = &omap3xxx_l3_main_hwmod, | |
1933 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
1934 | }; |
1935 | ||
844a3b63 PW |
1936 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
1937 | .master = &omap3xxx_dss_core_hwmod, | |
1938 | .slave = &omap3xxx_l3_main_hwmod, | |
1939 | .fw = { | |
70034d38 | 1940 | .omap2 = { |
844a3b63 PW |
1941 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
1942 | .flags = OMAP_FIREWALL_L3, | |
d9d9cec0 | 1943 | }, |
70034d38 | 1944 | }, |
844a3b63 | 1945 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
1946 | }; |
1947 | ||
844a3b63 PW |
1948 | /* l3_core -> usbhsotg interface */ |
1949 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
1950 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
1951 | .slave = &omap3xxx_l3_main_hwmod, |
1952 | .clk = "core_l3_ick", | |
844a3b63 | 1953 | .user = OCP_USER_MPU, |
01438ab6 MK |
1954 | }; |
1955 | ||
844a3b63 PW |
1956 | /* l3_core -> am35xx_usbhsotg interface */ |
1957 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
1958 | .master = &am35xx_usbhsotg_hwmod, | |
1959 | .slave = &omap3xxx_l3_main_hwmod, | |
89ea2583 | 1960 | .clk = "hsotgusb_ick", |
844a3b63 | 1961 | .user = OCP_USER_MPU, |
01438ab6 | 1962 | }; |
89ea2583 | 1963 | |
8f993a01 TK |
1964 | /* l3_core -> sad2d interface */ |
1965 | static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { | |
1966 | .master = &omap3xxx_sad2d_hwmod, | |
1967 | .slave = &omap3xxx_l3_main_hwmod, | |
1968 | .clk = "core_l3_ick", | |
1969 | .user = OCP_USER_MPU, | |
1970 | }; | |
1971 | ||
844a3b63 PW |
1972 | /* L4_CORE -> L4_WKUP interface */ |
1973 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
1974 | .master = &omap3xxx_l4_core_hwmod, | |
1975 | .slave = &omap3xxx_l4_wkup_hwmod, | |
1976 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
1977 | }; |
1978 | ||
844a3b63 PW |
1979 | /* L4 CORE -> MMC1 interface */ |
1980 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 1981 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
1982 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
1983 | .clk = "mmchs1_ick", | |
01438ab6 | 1984 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d9d9cec0 | 1985 | .flags = OMAP_FIREWALL_L4, |
01438ab6 MK |
1986 | }; |
1987 | ||
844a3b63 PW |
1988 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
1989 | .master = &omap3xxx_l4_core_hwmod, | |
1990 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
1991 | .clk = "mmchs1_ick", | |
844a3b63 | 1992 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d9d9cec0 | 1993 | .flags = OMAP_FIREWALL_L4, |
01438ab6 MK |
1994 | }; |
1995 | ||
844a3b63 PW |
1996 | /* L4 CORE -> MMC2 interface */ |
1997 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
1998 | .master = &omap3xxx_l4_core_hwmod, | |
1999 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2000 | .clk = "mmchs2_ick", | |
844a3b63 | 2001 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d9d9cec0 | 2002 | .flags = OMAP_FIREWALL_L4, |
844a3b63 | 2003 | }; |
70034d38 | 2004 | |
844a3b63 PW |
2005 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2006 | .master = &omap3xxx_l4_core_hwmod, | |
2007 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2008 | .clk = "mmchs2_ick", | |
844a3b63 | 2009 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d9d9cec0 | 2010 | .flags = OMAP_FIREWALL_L4, |
70034d38 VC |
2011 | }; |
2012 | ||
844a3b63 | 2013 | /* L4 CORE -> MMC3 interface */ |
70034d38 | 2014 | |
844a3b63 PW |
2015 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2016 | .master = &omap3xxx_l4_core_hwmod, | |
2017 | .slave = &omap3xxx_mmc3_hwmod, | |
2018 | .clk = "mmchs3_ick", | |
844a3b63 | 2019 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d9d9cec0 | 2020 | .flags = OMAP_FIREWALL_L4, |
70034d38 VC |
2021 | }; |
2022 | ||
844a3b63 | 2023 | /* L4 CORE -> UART1 interface */ |
70034d38 | 2024 | |
844a3b63 | 2025 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2026 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2027 | .slave = &omap3xxx_uart1_hwmod, |
2028 | .clk = "uart1_ick", | |
dc48e5fc | 2029 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2030 | }; |
2031 | ||
844a3b63 | 2032 | /* L4 CORE -> UART2 interface */ |
70034d38 | 2033 | |
844a3b63 PW |
2034 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2035 | .master = &omap3xxx_l4_core_hwmod, | |
2036 | .slave = &omap3xxx_uart2_hwmod, | |
2037 | .clk = "uart2_ick", | |
844a3b63 | 2038 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2039 | }; |
2040 | ||
844a3b63 | 2041 | /* L4 PER -> UART3 interface */ |
70034d38 | 2042 | |
844a3b63 | 2043 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2044 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2045 | .slave = &omap3xxx_uart3_hwmod, |
2046 | .clk = "uart3_ick", | |
dc48e5fc | 2047 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2048 | }; |
2049 | ||
844a3b63 | 2050 | /* L4 PER -> UART4 interface */ |
70034d38 | 2051 | |
844a3b63 PW |
2052 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2053 | .master = &omap3xxx_l4_per_hwmod, | |
2054 | .slave = &omap36xx_uart4_hwmod, | |
2055 | .clk = "uart4_ick", | |
844a3b63 | 2056 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2057 | }; |
2058 | ||
844a3b63 | 2059 | /* AM35xx: L4 CORE -> UART4 interface */ |
70034d38 | 2060 | |
844a3b63 PW |
2061 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2062 | .master = &omap3xxx_l4_core_hwmod, | |
2063 | .slave = &am35xx_uart4_hwmod, | |
2064 | .clk = "uart4_ick", | |
dc48e5fc C |
2065 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2066 | }; | |
2067 | ||
844a3b63 PW |
2068 | /* L4 CORE -> I2C1 interface */ |
2069 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2070 | .master = &omap3xxx_l4_core_hwmod, | |
2071 | .slave = &omap3xxx_i2c1_hwmod, | |
2072 | .clk = "i2c1_ick", | |
844a3b63 PW |
2073 | .fw = { |
2074 | .omap2 = { | |
2075 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2076 | .l4_prot_group = 7, | |
2077 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2078 | }, |
844a3b63 PW |
2079 | }, |
2080 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2081 | }; |
2082 | ||
844a3b63 PW |
2083 | /* L4 CORE -> I2C2 interface */ |
2084 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2085 | .master = &omap3xxx_l4_core_hwmod, | |
2086 | .slave = &omap3xxx_i2c2_hwmod, | |
2087 | .clk = "i2c2_ick", | |
844a3b63 | 2088 | .fw = { |
70034d38 | 2089 | .omap2 = { |
844a3b63 PW |
2090 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2091 | .l4_prot_group = 7, | |
2092 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2093 | }, |
70034d38 | 2094 | }, |
844a3b63 | 2095 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2096 | }; |
2097 | ||
844a3b63 | 2098 | /* L4 CORE -> I2C3 interface */ |
70034d38 | 2099 | |
844a3b63 PW |
2100 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2101 | .master = &omap3xxx_l4_core_hwmod, | |
2102 | .slave = &omap3xxx_i2c3_hwmod, | |
2103 | .clk = "i2c3_ick", | |
844a3b63 PW |
2104 | .fw = { |
2105 | .omap2 = { | |
2106 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2107 | .l4_prot_group = 7, | |
2108 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2109 | }, |
844a3b63 PW |
2110 | }, |
2111 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2112 | }; |
2113 | ||
844a3b63 | 2114 | /* L4 CORE -> SR1 interface */ |
17912508 TL |
2115 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { |
2116 | { | |
2117 | .pa_start = OMAP34XX_SR1_BASE, | |
2118 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2119 | .flags = ADDR_TYPE_RT, | |
2120 | }, | |
2121 | { }, | |
2122 | }; | |
70034d38 | 2123 | |
844a3b63 PW |
2124 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2125 | .master = &omap3xxx_l4_core_hwmod, | |
2126 | .slave = &omap34xx_sr1_hwmod, | |
2127 | .clk = "sr_l4_ick", | |
17912508 | 2128 | .addr = omap3_sr1_addr_space, |
844a3b63 | 2129 | .user = OCP_USER_MPU, |
70034d38 VC |
2130 | }; |
2131 | ||
844a3b63 PW |
2132 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2133 | .master = &omap3xxx_l4_core_hwmod, | |
2134 | .slave = &omap36xx_sr1_hwmod, | |
2135 | .clk = "sr_l4_ick", | |
17912508 | 2136 | .addr = omap3_sr1_addr_space, |
844a3b63 PW |
2137 | .user = OCP_USER_MPU, |
2138 | }; | |
2139 | ||
2140 | /* L4 CORE -> SR1 interface */ | |
17912508 TL |
2141 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { |
2142 | { | |
2143 | .pa_start = OMAP34XX_SR2_BASE, | |
2144 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2145 | .flags = ADDR_TYPE_RT, | |
2146 | }, | |
2147 | { }, | |
2148 | }; | |
70034d38 | 2149 | |
844a3b63 PW |
2150 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2151 | .master = &omap3xxx_l4_core_hwmod, | |
2152 | .slave = &omap34xx_sr2_hwmod, | |
2153 | .clk = "sr_l4_ick", | |
17912508 | 2154 | .addr = omap3_sr2_addr_space, |
844a3b63 | 2155 | .user = OCP_USER_MPU, |
70034d38 VC |
2156 | }; |
2157 | ||
844a3b63 PW |
2158 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2159 | .master = &omap3xxx_l4_core_hwmod, | |
2160 | .slave = &omap36xx_sr2_hwmod, | |
2161 | .clk = "sr_l4_ick", | |
17912508 | 2162 | .addr = omap3_sr2_addr_space, |
844a3b63 | 2163 | .user = OCP_USER_MPU, |
70034d38 VC |
2164 | }; |
2165 | ||
70034d38 | 2166 | |
844a3b63 PW |
2167 | /* l4_core -> usbhsotg */ |
2168 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2169 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2170 | .slave = &omap3xxx_usbhsotg_hwmod, |
2171 | .clk = "l4_ick", | |
844a3b63 | 2172 | .user = OCP_USER_MPU, |
dc48e5fc C |
2173 | }; |
2174 | ||
70034d38 | 2175 | |
844a3b63 PW |
2176 | /* l4_core -> usbhsotg */ |
2177 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2178 | .master = &omap3xxx_l4_core_hwmod, | |
2179 | .slave = &am35xx_usbhsotg_hwmod, | |
89ea2583 | 2180 | .clk = "hsotgusb_ick", |
844a3b63 | 2181 | .user = OCP_USER_MPU, |
01438ab6 MK |
2182 | }; |
2183 | ||
844a3b63 PW |
2184 | /* L4_WKUP -> L4_SEC interface */ |
2185 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2186 | .master = &omap3xxx_l4_wkup_hwmod, | |
2187 | .slave = &omap3xxx_l4_sec_hwmod, | |
2188 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2189 | }; |
2190 | ||
844a3b63 PW |
2191 | /* IVA2 <- L3 interface */ |
2192 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2193 | .master = &omap3xxx_l3_main_hwmod, | |
2194 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2195 | .clk = "core_l3_ick", |
844a3b63 | 2196 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2197 | }; |
2198 | ||
01438ab6 | 2199 | |
844a3b63 PW |
2200 | /* l4_wkup -> timer1 */ |
2201 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2202 | .master = &omap3xxx_l4_wkup_hwmod, | |
2203 | .slave = &omap3xxx_timer1_hwmod, | |
2204 | .clk = "gpt1_ick", | |
844a3b63 | 2205 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2206 | }; |
2207 | ||
01438ab6 | 2208 | |
844a3b63 PW |
2209 | /* l4_per -> timer2 */ |
2210 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2211 | .master = &omap3xxx_l4_per_hwmod, | |
2212 | .slave = &omap3xxx_timer2_hwmod, | |
2213 | .clk = "gpt2_ick", | |
844a3b63 | 2214 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2215 | }; |
2216 | ||
01438ab6 | 2217 | |
844a3b63 PW |
2218 | /* l4_per -> timer3 */ |
2219 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2220 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2221 | .slave = &omap3xxx_timer3_hwmod, |
2222 | .clk = "gpt3_ick", | |
844a3b63 | 2223 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2224 | }; |
2225 | ||
01438ab6 | 2226 | |
844a3b63 PW |
2227 | /* l4_per -> timer4 */ |
2228 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2229 | .master = &omap3xxx_l4_per_hwmod, | |
2230 | .slave = &omap3xxx_timer4_hwmod, | |
2231 | .clk = "gpt4_ick", | |
844a3b63 | 2232 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2233 | }; |
2234 | ||
d3442726 | 2235 | |
844a3b63 PW |
2236 | /* l4_per -> timer5 */ |
2237 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2238 | .master = &omap3xxx_l4_per_hwmod, | |
2239 | .slave = &omap3xxx_timer5_hwmod, | |
2240 | .clk = "gpt5_ick", | |
844a3b63 | 2241 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2242 | }; |
2243 | ||
cea6b942 | 2244 | |
844a3b63 PW |
2245 | /* l4_per -> timer6 */ |
2246 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2247 | .master = &omap3xxx_l4_per_hwmod, | |
2248 | .slave = &omap3xxx_timer6_hwmod, | |
2249 | .clk = "gpt6_ick", | |
844a3b63 | 2250 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2251 | }; |
2252 | ||
d3442726 | 2253 | |
844a3b63 PW |
2254 | /* l4_per -> timer7 */ |
2255 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2256 | .master = &omap3xxx_l4_per_hwmod, | |
2257 | .slave = &omap3xxx_timer7_hwmod, | |
2258 | .clk = "gpt7_ick", | |
844a3b63 | 2259 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
cea6b942 SG |
2260 | }; |
2261 | ||
d3442726 | 2262 | |
844a3b63 PW |
2263 | /* l4_per -> timer8 */ |
2264 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2265 | .master = &omap3xxx_l4_per_hwmod, | |
2266 | .slave = &omap3xxx_timer8_hwmod, | |
2267 | .clk = "gpt8_ick", | |
844a3b63 | 2268 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2269 | }; |
2270 | ||
0f9dfdd3 | 2271 | |
844a3b63 PW |
2272 | /* l4_per -> timer9 */ |
2273 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2274 | .master = &omap3xxx_l4_per_hwmod, | |
2275 | .slave = &omap3xxx_timer9_hwmod, | |
2276 | .clk = "gpt9_ick", | |
844a3b63 | 2277 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f9dfdd3 FC |
2278 | }; |
2279 | ||
844a3b63 PW |
2280 | /* l4_core -> timer10 */ |
2281 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2282 | .master = &omap3xxx_l4_core_hwmod, | |
2283 | .slave = &omap3xxx_timer10_hwmod, | |
2284 | .clk = "gpt10_ick", | |
844a3b63 | 2285 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f9dfdd3 FC |
2286 | }; |
2287 | ||
844a3b63 PW |
2288 | /* l4_core -> timer11 */ |
2289 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2290 | .master = &omap3xxx_l4_core_hwmod, | |
2291 | .slave = &omap3xxx_timer11_hwmod, | |
2292 | .clk = "gpt11_ick", | |
844a3b63 | 2293 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f9dfdd3 FC |
2294 | }; |
2295 | ||
0f9dfdd3 | 2296 | |
844a3b63 PW |
2297 | /* l4_core -> timer12 */ |
2298 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2299 | .master = &omap3xxx_l4_sec_hwmod, | |
2300 | .slave = &omap3xxx_timer12_hwmod, | |
2301 | .clk = "gpt12_ick", | |
0f9dfdd3 FC |
2302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2303 | }; | |
2304 | ||
844a3b63 | 2305 | /* l4_wkup -> wd_timer2 */ |
0f9dfdd3 | 2306 | |
844a3b63 PW |
2307 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2308 | .master = &omap3xxx_l4_wkup_hwmod, | |
2309 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2310 | .clk = "wdt2_ick", | |
844a3b63 PW |
2311 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2312 | }; | |
2313 | ||
2314 | /* l4_core -> dss */ | |
2315 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2316 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2317 | .slave = &omap3430es1_dss_core_hwmod, |
2318 | .clk = "dss_ick", | |
844a3b63 PW |
2319 | .fw = { |
2320 | .omap2 = { | |
2321 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2322 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2323 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2324 | }, |
844a3b63 | 2325 | }, |
0f616a4e C |
2326 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2327 | }; | |
2328 | ||
844a3b63 | 2329 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2330 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2331 | .slave = &omap3xxx_dss_core_hwmod, |
2332 | .clk = "dss_ick", | |
844a3b63 PW |
2333 | .fw = { |
2334 | .omap2 = { | |
2335 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2336 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2337 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2338 | }, |
844a3b63 | 2339 | }, |
0f616a4e C |
2340 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2341 | }; | |
2342 | ||
844a3b63 PW |
2343 | /* l4_core -> dss_dispc */ |
2344 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2345 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2346 | .slave = &omap3xxx_dss_dispc_hwmod, |
2347 | .clk = "dss_ick", | |
844a3b63 PW |
2348 | .fw = { |
2349 | .omap2 = { | |
2350 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2351 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2352 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2353 | }, |
844a3b63 | 2354 | }, |
0f616a4e C |
2355 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2356 | }; | |
2357 | ||
844a3b63 PW |
2358 | /* l4_core -> dss_dsi1 */ |
2359 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2360 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2361 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2362 | .clk = "dss_ick", | |
844a3b63 PW |
2363 | .fw = { |
2364 | .omap2 = { | |
2365 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2366 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2367 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2368 | }, |
844a3b63 | 2369 | }, |
0f616a4e C |
2370 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2371 | }; | |
2372 | ||
844a3b63 PW |
2373 | /* l4_core -> dss_rfbi */ |
2374 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2375 | .master = &omap3xxx_l4_core_hwmod, | |
2376 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2377 | .clk = "dss_ick", | |
844a3b63 | 2378 | .fw = { |
0f616a4e | 2379 | .omap2 = { |
844a3b63 PW |
2380 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2381 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2382 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2383 | }, |
0f616a4e | 2384 | }, |
844a3b63 | 2385 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2386 | }; |
2387 | ||
844a3b63 PW |
2388 | /* l4_core -> dss_venc */ |
2389 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2390 | .master = &omap3xxx_l4_core_hwmod, | |
2391 | .slave = &omap3xxx_dss_venc_hwmod, | |
2392 | .clk = "dss_ick", | |
844a3b63 | 2393 | .fw = { |
70034d38 | 2394 | .omap2 = { |
844a3b63 PW |
2395 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2396 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2397 | .flags = OMAP_FIREWALL_L4, | |
d9d9cec0 | 2398 | }, |
70034d38 | 2399 | }, |
844a3b63 PW |
2400 | .flags = OCPIF_SWSUP_IDLE, |
2401 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2402 | }; |
2403 | ||
844a3b63 | 2404 | /* l4_wkup -> gpio1 */ |
70034d38 | 2405 | |
844a3b63 PW |
2406 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2407 | .master = &omap3xxx_l4_wkup_hwmod, | |
2408 | .slave = &omap3xxx_gpio1_hwmod, | |
844a3b63 | 2409 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2410 | }; |
2411 | ||
844a3b63 | 2412 | /* l4_per -> gpio2 */ |
70034d38 | 2413 | |
844a3b63 PW |
2414 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2415 | .master = &omap3xxx_l4_per_hwmod, | |
2416 | .slave = &omap3xxx_gpio2_hwmod, | |
844a3b63 | 2417 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2418 | }; |
2419 | ||
844a3b63 | 2420 | /* l4_per -> gpio3 */ |
70034d38 | 2421 | |
844a3b63 PW |
2422 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2423 | .master = &omap3xxx_l4_per_hwmod, | |
2424 | .slave = &omap3xxx_gpio3_hwmod, | |
844a3b63 | 2425 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2426 | }; |
2427 | ||
5486474c PW |
2428 | /* |
2429 | * 'mmu' class | |
2430 | * The memory management unit performs virtual to physical address translation | |
2431 | * for its requestors. | |
2432 | */ | |
2433 | ||
2434 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2435 | .rev_offs = 0x000, | |
2436 | .sysc_offs = 0x010, | |
2437 | .syss_offs = 0x014, | |
2438 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2439 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2440 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2441 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2442 | }; | |
2443 | ||
2444 | static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { | |
2445 | .name = "mmu", | |
2446 | .sysc = &mmu_sysc, | |
2447 | }; | |
2448 | ||
2449 | /* mmu isp */ | |
5486474c | 2450 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod; |
5486474c PW |
2451 | |
2452 | /* l4_core -> mmu isp */ | |
2453 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { | |
2454 | .master = &omap3xxx_l4_core_hwmod, | |
2455 | .slave = &omap3xxx_mmu_isp_hwmod, | |
5486474c PW |
2456 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2457 | }; | |
2458 | ||
2459 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { | |
2460 | .name = "mmu_isp", | |
2461 | .class = &omap3xxx_mmu_hwmod_class, | |
5486474c | 2462 | .main_clk = "cam_ick", |
5486474c PW |
2463 | .flags = HWMOD_NO_IDLEST, |
2464 | }; | |
2465 | ||
5486474c PW |
2466 | /* mmu iva */ |
2467 | ||
5486474c | 2468 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod; |
5486474c PW |
2469 | |
2470 | static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { | |
2471 | { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, | |
2472 | }; | |
2473 | ||
5486474c PW |
2474 | /* l3_main -> iva mmu */ |
2475 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { | |
2476 | .master = &omap3xxx_l3_main_hwmod, | |
2477 | .slave = &omap3xxx_mmu_iva_hwmod, | |
5486474c PW |
2478 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2479 | }; | |
2480 | ||
2481 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { | |
2482 | .name = "mmu_iva", | |
2483 | .class = &omap3xxx_mmu_hwmod_class, | |
200a274f | 2484 | .clkdm_name = "iva2_clkdm", |
5486474c PW |
2485 | .rst_lines = omap3xxx_mmu_iva_resets, |
2486 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), | |
2487 | .main_clk = "iva2_ck", | |
2488 | .prcm = { | |
2489 | .omap2 = { | |
2490 | .module_offs = OMAP3430_IVA2_MOD, | |
200a274f SA |
2491 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
2492 | .idlest_reg_id = 1, | |
2493 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
5486474c PW |
2494 | }, |
2495 | }, | |
5486474c PW |
2496 | .flags = HWMOD_NO_IDLEST, |
2497 | }; | |
2498 | ||
844a3b63 | 2499 | /* l4_per -> gpio4 */ |
70034d38 | 2500 | |
844a3b63 PW |
2501 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
2502 | .master = &omap3xxx_l4_per_hwmod, | |
2503 | .slave = &omap3xxx_gpio4_hwmod, | |
844a3b63 | 2504 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2505 | }; |
2506 | ||
844a3b63 | 2507 | /* l4_per -> gpio5 */ |
01438ab6 | 2508 | |
844a3b63 PW |
2509 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
2510 | .master = &omap3xxx_l4_per_hwmod, | |
2511 | .slave = &omap3xxx_gpio5_hwmod, | |
844a3b63 | 2512 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2513 | }; |
2514 | ||
844a3b63 | 2515 | /* l4_per -> gpio6 */ |
01438ab6 | 2516 | |
844a3b63 PW |
2517 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
2518 | .master = &omap3xxx_l4_per_hwmod, | |
2519 | .slave = &omap3xxx_gpio6_hwmod, | |
844a3b63 | 2520 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2521 | }; |
2522 | ||
844a3b63 PW |
2523 | /* dma_system -> L3 */ |
2524 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
2525 | .master = &omap3xxx_dma_system_hwmod, | |
2526 | .slave = &omap3xxx_l3_main_hwmod, | |
2527 | .clk = "core_l3_ick", | |
2528 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2529 | }; |
2530 | ||
844a3b63 PW |
2531 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
2532 | { | |
2533 | .pa_start = 0x48056000, | |
2534 | .pa_end = 0x48056fff, | |
d9d9cec0 | 2535 | .flags = ADDR_TYPE_RT, |
01438ab6 | 2536 | }, |
d9d9cec0 | 2537 | { }, |
01438ab6 MK |
2538 | }; |
2539 | ||
844a3b63 PW |
2540 | /* l4_cfg -> dma_system */ |
2541 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
2542 | .master = &omap3xxx_l4_core_hwmod, | |
2543 | .slave = &omap3xxx_dma_system_hwmod, | |
2544 | .clk = "core_l4_ick", | |
2545 | .addr = omap3xxx_dma_system_addrs, | |
2546 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2547 | }; |
2548 | ||
d3442726 | 2549 | |
844a3b63 PW |
2550 | /* l4_core -> mcbsp1 */ |
2551 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
2552 | .master = &omap3xxx_l4_core_hwmod, | |
2553 | .slave = &omap3xxx_mcbsp1_hwmod, | |
2554 | .clk = "mcbsp1_ick", | |
844a3b63 | 2555 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2556 | }; |
2557 | ||
d3442726 | 2558 | |
844a3b63 PW |
2559 | /* l4_per -> mcbsp2 */ |
2560 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
2561 | .master = &omap3xxx_l4_per_hwmod, | |
2562 | .slave = &omap3xxx_mcbsp2_hwmod, | |
2563 | .clk = "mcbsp2_ick", | |
844a3b63 | 2564 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2565 | }; |
2566 | ||
d3442726 | 2567 | |
844a3b63 PW |
2568 | /* l4_per -> mcbsp3 */ |
2569 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
2570 | .master = &omap3xxx_l4_per_hwmod, | |
2571 | .slave = &omap3xxx_mcbsp3_hwmod, | |
2572 | .clk = "mcbsp3_ick", | |
844a3b63 | 2573 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
a52e2ab6 PW |
2574 | }; |
2575 | ||
a52e2ab6 | 2576 | |
844a3b63 PW |
2577 | /* l4_per -> mcbsp4 */ |
2578 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
2579 | .master = &omap3xxx_l4_per_hwmod, | |
2580 | .slave = &omap3xxx_mcbsp4_hwmod, | |
2581 | .clk = "mcbsp4_ick", | |
844a3b63 | 2582 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2583 | }; |
2584 | ||
b163605e | 2585 | |
844a3b63 PW |
2586 | /* l4_core -> mcbsp5 */ |
2587 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
2588 | .master = &omap3xxx_l4_core_hwmod, | |
2589 | .slave = &omap3xxx_mcbsp5_hwmod, | |
2590 | .clk = "mcbsp5_ick", | |
844a3b63 | 2591 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2592 | }; |
2593 | ||
d3442726 | 2594 | |
844a3b63 PW |
2595 | /* l4_per -> mcbsp2_sidetone */ |
2596 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
2597 | .master = &omap3xxx_l4_per_hwmod, | |
2598 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
2599 | .clk = "mcbsp2_ick", | |
844a3b63 | 2600 | .user = OCP_USER_MPU, |
b163605e PW |
2601 | }; |
2602 | ||
a52e2ab6 | 2603 | |
844a3b63 PW |
2604 | /* l4_per -> mcbsp3_sidetone */ |
2605 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
2606 | .master = &omap3xxx_l4_per_hwmod, | |
2607 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
2608 | .clk = "mcbsp3_ick", | |
844a3b63 | 2609 | .user = OCP_USER_MPU, |
a52e2ab6 PW |
2610 | }; |
2611 | ||
844a3b63 PW |
2612 | /* l4_core -> mailbox */ |
2613 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
2614 | .master = &omap3xxx_l4_core_hwmod, | |
2615 | .slave = &omap3xxx_mailbox_hwmod, | |
844a3b63 PW |
2616 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2617 | }; | |
b163605e | 2618 | |
844a3b63 PW |
2619 | /* l4 core -> mcspi1 interface */ |
2620 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
2621 | .master = &omap3xxx_l4_core_hwmod, | |
2622 | .slave = &omap34xx_mcspi1, | |
2623 | .clk = "mcspi1_ick", | |
844a3b63 | 2624 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
b163605e PW |
2625 | }; |
2626 | ||
844a3b63 PW |
2627 | /* l4 core -> mcspi2 interface */ |
2628 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
2629 | .master = &omap3xxx_l4_core_hwmod, | |
2630 | .slave = &omap34xx_mcspi2, | |
2631 | .clk = "mcspi2_ick", | |
844a3b63 | 2632 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
b163605e PW |
2633 | }; |
2634 | ||
844a3b63 PW |
2635 | /* l4 core -> mcspi3 interface */ |
2636 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
2637 | .master = &omap3xxx_l4_core_hwmod, | |
2638 | .slave = &omap34xx_mcspi3, | |
2639 | .clk = "mcspi3_ick", | |
844a3b63 | 2640 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
b163605e PW |
2641 | }; |
2642 | ||
844a3b63 | 2643 | /* l4 core -> mcspi4 interface */ |
844a3b63 PW |
2644 | |
2645 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
2646 | .master = &omap3xxx_l4_core_hwmod, | |
2647 | .slave = &omap34xx_mcspi4, | |
2648 | .clk = "mcspi4_ick", | |
844a3b63 | 2649 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
d3442726 TG |
2650 | }; |
2651 | ||
de231388 KM |
2652 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
2653 | .master = &omap3xxx_usb_host_hs_hwmod, | |
2654 | .slave = &omap3xxx_l3_main_hwmod, | |
2655 | .clk = "core_l3_ick", | |
2656 | .user = OCP_USER_MPU, | |
2657 | }; | |
2658 | ||
de231388 KM |
2659 | |
2660 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
2661 | .master = &omap3xxx_l4_core_hwmod, | |
2662 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
2663 | .clk = "usbhost_ick", | |
de231388 KM |
2664 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2665 | }; | |
2666 | ||
de231388 KM |
2667 | |
2668 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
2669 | .master = &omap3xxx_l4_core_hwmod, | |
2670 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
2671 | .clk = "usbtll_ick", | |
de231388 KM |
2672 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2673 | }; | |
2674 | ||
45a4bb06 PW |
2675 | /* l4_core -> hdq1w interface */ |
2676 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
2677 | .master = &omap3xxx_l4_core_hwmod, | |
2678 | .slave = &omap3xxx_hdq1w_hwmod, | |
2679 | .clk = "hdq_ick", | |
45a4bb06 PW |
2680 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2681 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
2682 | }; | |
2683 | ||
c8d82ff6 | 2684 | /* l4_wkup -> 32ksync_counter */ |
c8d82ff6 | 2685 | |
49484a60 | 2686 | |
c8d82ff6 VH |
2687 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { |
2688 | .master = &omap3xxx_l4_wkup_hwmod, | |
2689 | .slave = &omap3xxx_counter_32k_hwmod, | |
2690 | .clk = "omap_32ksync_ick", | |
c8d82ff6 VH |
2691 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2692 | }; | |
2693 | ||
31ba8808 MG |
2694 | /* am35xx has Davinci MDIO & EMAC */ |
2695 | static struct omap_hwmod_class am35xx_mdio_class = { | |
2696 | .name = "davinci_mdio", | |
2697 | }; | |
2698 | ||
2699 | static struct omap_hwmod am35xx_mdio_hwmod = { | |
2700 | .name = "davinci_mdio", | |
2701 | .class = &am35xx_mdio_class, | |
2702 | .flags = HWMOD_NO_IDLEST, | |
2703 | }; | |
2704 | ||
2705 | /* | |
2706 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
2707 | * but this will probably require some additional hwmod core support, | |
2708 | * so is left as a future to-do item. | |
2709 | */ | |
2710 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | |
2711 | .master = &am35xx_mdio_hwmod, | |
2712 | .slave = &omap3xxx_l3_main_hwmod, | |
2713 | .clk = "emac_fck", | |
2714 | .user = OCP_USER_MPU, | |
2715 | }; | |
2716 | ||
31ba8808 MG |
2717 | /* l4_core -> davinci mdio */ |
2718 | /* | |
2719 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
2720 | * but this will probably require some additional hwmod core support, | |
2721 | * so is left as a future to-do item. | |
2722 | */ | |
2723 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | |
2724 | .master = &omap3xxx_l4_core_hwmod, | |
2725 | .slave = &am35xx_mdio_hwmod, | |
2726 | .clk = "emac_fck", | |
31ba8808 MG |
2727 | .user = OCP_USER_MPU, |
2728 | }; | |
2729 | ||
31ba8808 MG |
2730 | static struct omap_hwmod_class am35xx_emac_class = { |
2731 | .name = "davinci_emac", | |
2732 | }; | |
2733 | ||
2734 | static struct omap_hwmod am35xx_emac_hwmod = { | |
2735 | .name = "davinci_emac", | |
31ba8808 | 2736 | .class = &am35xx_emac_class, |
814a18a5 PW |
2737 | /* |
2738 | * According to Mark Greer, the MPU will not return from WFI | |
2739 | * when the EMAC signals an interrupt. | |
2740 | * http://www.spinics.net/lists/arm-kernel/msg174734.html | |
2741 | */ | |
2742 | .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), | |
31ba8808 MG |
2743 | }; |
2744 | ||
2745 | /* l3_core -> davinci emac interface */ | |
2746 | /* | |
2747 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
2748 | * but this will probably require some additional hwmod core support, | |
2749 | * so is left as a future to-do item. | |
2750 | */ | |
2751 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | |
2752 | .master = &am35xx_emac_hwmod, | |
2753 | .slave = &omap3xxx_l3_main_hwmod, | |
2754 | .clk = "emac_ick", | |
2755 | .user = OCP_USER_MPU, | |
2756 | }; | |
2757 | ||
31ba8808 MG |
2758 | /* l4_core -> davinci emac */ |
2759 | /* | |
2760 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
2761 | * but this will probably require some additional hwmod core support, | |
2762 | * so is left as a future to-do item. | |
2763 | */ | |
2764 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | |
2765 | .master = &omap3xxx_l4_core_hwmod, | |
2766 | .slave = &am35xx_emac_hwmod, | |
2767 | .clk = "emac_ick", | |
31ba8808 MG |
2768 | .user = OCP_USER_MPU, |
2769 | }; | |
2770 | ||
49484a60 AM |
2771 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { |
2772 | .master = &omap3xxx_l3_main_hwmod, | |
2773 | .slave = &omap3xxx_gpmc_hwmod, | |
2774 | .clk = "core_l3_ick", | |
49484a60 AM |
2775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2776 | }; | |
2777 | ||
26f88e6e MG |
2778 | /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ |
2779 | static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { | |
2780 | .sidle_shift = 4, | |
2781 | .srst_shift = 1, | |
2782 | .autoidle_shift = 0, | |
2783 | }; | |
2784 | ||
2785 | static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { | |
2786 | .rev_offs = 0x5c, | |
2787 | .sysc_offs = 0x60, | |
2788 | .syss_offs = 0x64, | |
2789 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2790 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
2791 | .sysc_fields = &omap3_sham_sysc_fields, | |
2792 | }; | |
2793 | ||
2794 | static struct omap_hwmod_class omap3xxx_sham_class = { | |
2795 | .name = "sham", | |
2796 | .sysc = &omap3_sham_sysc, | |
2797 | }; | |
2798 | ||
26f88e6e | 2799 | |
26f88e6e MG |
2800 | |
2801 | static struct omap_hwmod omap3xxx_sham_hwmod = { | |
2802 | .name = "sham", | |
26f88e6e MG |
2803 | .main_clk = "sha12_ick", |
2804 | .prcm = { | |
2805 | .omap2 = { | |
2806 | .module_offs = CORE_MOD, | |
2807 | .prcm_reg_id = 1, | |
2808 | .module_bit = OMAP3430_EN_SHA12_SHIFT, | |
2809 | .idlest_reg_id = 1, | |
2810 | .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, | |
2811 | }, | |
2812 | }, | |
2813 | .class = &omap3xxx_sham_class, | |
2814 | }; | |
2815 | ||
26f88e6e MG |
2816 | |
2817 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { | |
2818 | .master = &omap3xxx_l4_core_hwmod, | |
2819 | .slave = &omap3xxx_sham_hwmod, | |
2820 | .clk = "sha12_ick", | |
26f88e6e MG |
2821 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2822 | }; | |
2823 | ||
14ae5564 MG |
2824 | /* l4_core -> AES */ |
2825 | static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { | |
2826 | .sidle_shift = 6, | |
2827 | .srst_shift = 1, | |
2828 | .autoidle_shift = 0, | |
2829 | }; | |
2830 | ||
2831 | static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { | |
2832 | .rev_offs = 0x44, | |
2833 | .sysc_offs = 0x48, | |
2834 | .syss_offs = 0x4c, | |
2835 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2836 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
2837 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2838 | .sysc_fields = &omap3xxx_aes_sysc_fields, | |
2839 | }; | |
2840 | ||
2841 | static struct omap_hwmod_class omap3xxx_aes_class = { | |
2842 | .name = "aes", | |
2843 | .sysc = &omap3_aes_sysc, | |
2844 | }; | |
2845 | ||
14ae5564 MG |
2846 | |
2847 | static struct omap_hwmod omap3xxx_aes_hwmod = { | |
2848 | .name = "aes", | |
14ae5564 MG |
2849 | .main_clk = "aes2_ick", |
2850 | .prcm = { | |
2851 | .omap2 = { | |
2852 | .module_offs = CORE_MOD, | |
2853 | .prcm_reg_id = 1, | |
2854 | .module_bit = OMAP3430_EN_AES2_SHIFT, | |
2855 | .idlest_reg_id = 1, | |
2856 | .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, | |
2857 | }, | |
2858 | }, | |
2859 | .class = &omap3xxx_aes_class, | |
2860 | }; | |
2861 | ||
14ae5564 MG |
2862 | |
2863 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { | |
2864 | .master = &omap3xxx_l4_core_hwmod, | |
2865 | .slave = &omap3xxx_aes_hwmod, | |
2866 | .clk = "aes2_ick", | |
14ae5564 MG |
2867 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2868 | }; | |
2869 | ||
398917ce SR |
2870 | /* |
2871 | * 'ssi' class | |
2872 | * synchronous serial interface (multichannel and full-duplex serial if) | |
2873 | */ | |
2874 | ||
2875 | static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { | |
2876 | .rev_offs = 0x0000, | |
2877 | .sysc_offs = 0x0010, | |
2878 | .syss_offs = 0x0014, | |
dc94fabf TL |
2879 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE | |
2880 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2881 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
398917ce SR |
2882 | .sysc_fields = &omap_hwmod_sysc_type1, |
2883 | }; | |
2884 | ||
77112076 | 2885 | static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = { |
398917ce SR |
2886 | .name = "ssi", |
2887 | .sysc = &omap34xx_ssi_sysc, | |
2888 | }; | |
2889 | ||
77112076 | 2890 | static struct omap_hwmod omap3xxx_ssi_hwmod = { |
398917ce | 2891 | .name = "ssi", |
77112076 | 2892 | .class = &omap3xxx_ssi_hwmod_class, |
398917ce SR |
2893 | .clkdm_name = "core_l4_clkdm", |
2894 | .main_clk = "ssi_ssr_fck", | |
2895 | .prcm = { | |
2896 | .omap2 = { | |
2897 | .prcm_reg_id = 1, | |
2898 | .module_bit = OMAP3430_EN_SSI_SHIFT, | |
2899 | .module_offs = CORE_MOD, | |
2900 | .idlest_reg_id = 1, | |
2901 | .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, | |
2902 | }, | |
2903 | }, | |
2904 | }; | |
2905 | ||
2906 | /* L4 CORE -> SSI */ | |
77112076 | 2907 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = { |
398917ce | 2908 | .master = &omap3xxx_l4_core_hwmod, |
77112076 | 2909 | .slave = &omap3xxx_ssi_hwmod, |
398917ce SR |
2910 | .clk = "ssi_ick", |
2911 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2912 | }; | |
2913 | ||
0a78c5c5 PW |
2914 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
2915 | &omap3xxx_l3_main__l4_core, | |
2916 | &omap3xxx_l3_main__l4_per, | |
2917 | &omap3xxx_mpu__l3_main, | |
c7dad45f | 2918 | &omap3xxx_l3_main__l4_debugss, |
0a78c5c5 PW |
2919 | &omap3xxx_l4_core__l4_wkup, |
2920 | &omap3xxx_l4_core__mmc3, | |
2921 | &omap3_l4_core__uart1, | |
2922 | &omap3_l4_core__uart2, | |
2923 | &omap3_l4_per__uart3, | |
2924 | &omap3_l4_core__i2c1, | |
2925 | &omap3_l4_core__i2c2, | |
2926 | &omap3_l4_core__i2c3, | |
2927 | &omap3xxx_l4_wkup__l4_sec, | |
2928 | &omap3xxx_l4_wkup__timer1, | |
2929 | &omap3xxx_l4_per__timer2, | |
2930 | &omap3xxx_l4_per__timer3, | |
2931 | &omap3xxx_l4_per__timer4, | |
2932 | &omap3xxx_l4_per__timer5, | |
2933 | &omap3xxx_l4_per__timer6, | |
2934 | &omap3xxx_l4_per__timer7, | |
2935 | &omap3xxx_l4_per__timer8, | |
2936 | &omap3xxx_l4_per__timer9, | |
2937 | &omap3xxx_l4_core__timer10, | |
2938 | &omap3xxx_l4_core__timer11, | |
2939 | &omap3xxx_l4_wkup__wd_timer2, | |
2940 | &omap3xxx_l4_wkup__gpio1, | |
2941 | &omap3xxx_l4_per__gpio2, | |
2942 | &omap3xxx_l4_per__gpio3, | |
2943 | &omap3xxx_l4_per__gpio4, | |
2944 | &omap3xxx_l4_per__gpio5, | |
2945 | &omap3xxx_l4_per__gpio6, | |
2946 | &omap3xxx_dma_system__l3, | |
2947 | &omap3xxx_l4_core__dma_system, | |
2948 | &omap3xxx_l4_core__mcbsp1, | |
2949 | &omap3xxx_l4_per__mcbsp2, | |
2950 | &omap3xxx_l4_per__mcbsp3, | |
2951 | &omap3xxx_l4_per__mcbsp4, | |
2952 | &omap3xxx_l4_core__mcbsp5, | |
2953 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
2954 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
2955 | &omap34xx_l4_core__mcspi1, | |
2956 | &omap34xx_l4_core__mcspi2, | |
2957 | &omap34xx_l4_core__mcspi3, | |
2958 | &omap34xx_l4_core__mcspi4, | |
c8d82ff6 | 2959 | &omap3xxx_l4_wkup__counter_32k, |
49484a60 | 2960 | &omap3xxx_l3_main__gpmc, |
d6504acd PW |
2961 | NULL, |
2962 | }; | |
2963 | ||
0a78c5c5 | 2964 | /* GP-only hwmod links */ |
26f88e6e MG |
2965 | static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { |
2966 | &omap3xxx_l4_sec__timer12, | |
d9d9cec0 | 2967 | NULL, |
26f88e6e MG |
2968 | }; |
2969 | ||
2970 | static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { | |
0a78c5c5 | 2971 | &omap3xxx_l4_sec__timer12, |
d9d9cec0 | 2972 | NULL, |
26f88e6e MG |
2973 | }; |
2974 | ||
2975 | static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { | |
2976 | &omap3xxx_l4_sec__timer12, | |
d9d9cec0 | 2977 | NULL, |
a55a7445 PR |
2978 | }; |
2979 | ||
2980 | /* crypto hwmod links */ | |
2981 | static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { | |
2982 | &omap3xxx_l4_core__sham, | |
d9d9cec0 | 2983 | NULL, |
a55a7445 PR |
2984 | }; |
2985 | ||
2986 | static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { | |
2987 | &omap3xxx_l4_core__aes, | |
d9d9cec0 | 2988 | NULL, |
a55a7445 PR |
2989 | }; |
2990 | ||
2991 | static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { | |
2992 | &omap3xxx_l4_core__sham, | |
2993 | NULL | |
2994 | }; | |
2995 | ||
2996 | static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = { | |
2997 | &omap3xxx_l4_core__aes, | |
2998 | NULL | |
2999 | }; | |
3000 | ||
3001 | /* | |
3002 | * Apparently the SHA/MD5 and AES accelerator IP blocks are | |
3003 | * only present on some AM35xx chips, and no one knows which | |
3004 | * ones. See | |
3005 | * http://www.spinics.net/lists/arm-kernel/msg215466.html So | |
3006 | * if you need these IP blocks on an AM35xx, try uncommenting | |
3007 | * the following lines. | |
3008 | */ | |
3009 | static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { | |
26f88e6e | 3010 | /* &omap3xxx_l4_core__sham, */ |
a55a7445 PR |
3011 | NULL |
3012 | }; | |
3013 | ||
3014 | static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { | |
14ae5564 | 3015 | /* &omap3xxx_l4_core__aes, */ |
d9d9cec0 | 3016 | NULL, |
91a36bdb AK |
3017 | }; |
3018 | ||
0a78c5c5 PW |
3019 | /* 3430ES1-only hwmod links */ |
3020 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3021 | &omap3430es1_dss__l3, | |
3022 | &omap3430es1_l4_core__dss, | |
d9d9cec0 | 3023 | NULL, |
d6504acd PW |
3024 | }; |
3025 | ||
0a78c5c5 PW |
3026 | /* 3430ES2+-only hwmod links */ |
3027 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3028 | &omap3xxx_dss__l3, | |
3029 | &omap3xxx_l4_core__dss, | |
3030 | &omap3xxx_usbhsotg__l3, | |
3031 | &omap3xxx_l4_core__usbhsotg, | |
3032 | &omap3xxx_usb_host_hs__l3_main_2, | |
3033 | &omap3xxx_l4_core__usb_host_hs, | |
3034 | &omap3xxx_l4_core__usb_tll_hs, | |
d9d9cec0 | 3035 | NULL, |
d6504acd | 3036 | }; |
870ea2b8 | 3037 | |
0a78c5c5 PW |
3038 | /* <= 3430ES3-only hwmod links */ |
3039 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3040 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3041 | &omap3xxx_l4_core__pre_es3_mmc2, | |
d9d9cec0 | 3042 | NULL, |
a52e2ab6 PW |
3043 | }; |
3044 | ||
0a78c5c5 PW |
3045 | /* 3430ES3+-only hwmod links */ |
3046 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3047 | &omap3xxx_l4_core__es3plus_mmc1, | |
3048 | &omap3xxx_l4_core__es3plus_mmc2, | |
d9d9cec0 | 3049 | NULL, |
a52e2ab6 PW |
3050 | }; |
3051 | ||
0a78c5c5 PW |
3052 | /* 34xx-only hwmod links (all ES revisions) */ |
3053 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3054 | &omap3xxx_l3__iva, | |
3055 | &omap34xx_l4_core__sr1, | |
3056 | &omap34xx_l4_core__sr2, | |
3057 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3058 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3059 | &omap3xxx_sad2d__l3, |
5486474c | 3060 | &omap3xxx_l4_core__mmu_isp, |
5486474c | 3061 | &omap3xxx_l3_main__mmu_iva, |
77112076 | 3062 | &omap3xxx_l4_core__ssi, |
d9d9cec0 | 3063 | NULL, |
d6504acd | 3064 | }; |
273ff8c3 | 3065 | |
0a78c5c5 PW |
3066 | /* 36xx-only hwmod links (all ES revisions) */ |
3067 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3068 | &omap3xxx_l3__iva, | |
3069 | &omap36xx_l4_per__uart4, | |
3070 | &omap3xxx_dss__l3, | |
3071 | &omap3xxx_l4_core__dss, | |
3072 | &omap36xx_l4_core__sr1, | |
3073 | &omap36xx_l4_core__sr2, | |
3074 | &omap3xxx_usbhsotg__l3, | |
3075 | &omap3xxx_l4_core__usbhsotg, | |
3076 | &omap3xxx_l4_core__mailbox, | |
3077 | &omap3xxx_usb_host_hs__l3_main_2, | |
3078 | &omap3xxx_l4_core__usb_host_hs, | |
3079 | &omap3xxx_l4_core__usb_tll_hs, | |
3080 | &omap3xxx_l4_core__es3plus_mmc1, | |
3081 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3082 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3083 | &omap3xxx_sad2d__l3, |
5486474c | 3084 | &omap3xxx_l4_core__mmu_isp, |
5486474c | 3085 | &omap3xxx_l3_main__mmu_iva, |
77112076 | 3086 | &omap3xxx_l4_core__ssi, |
d9d9cec0 | 3087 | NULL, |
d6504acd PW |
3088 | }; |
3089 | ||
0a78c5c5 PW |
3090 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3091 | &omap3xxx_dss__l3, | |
3092 | &omap3xxx_l4_core__dss, | |
3093 | &am35xx_usbhsotg__l3, | |
3094 | &am35xx_l4_core__usbhsotg, | |
3095 | &am35xx_l4_core__uart4, | |
3096 | &omap3xxx_usb_host_hs__l3_main_2, | |
3097 | &omap3xxx_l4_core__usb_host_hs, | |
3098 | &omap3xxx_l4_core__usb_tll_hs, | |
3099 | &omap3xxx_l4_core__es3plus_mmc1, | |
3100 | &omap3xxx_l4_core__es3plus_mmc2, | |
b1a923d0 | 3101 | &omap3xxx_l4_core__hdq1w, |
31ba8808 MG |
3102 | &am35xx_mdio__l3, |
3103 | &am35xx_l4_core__mdio, | |
3104 | &am35xx_emac__l3, | |
3105 | &am35xx_l4_core__emac, | |
d9d9cec0 | 3106 | NULL, |
7359154e PW |
3107 | }; |
3108 | ||
0a78c5c5 PW |
3109 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3110 | &omap3xxx_l4_core__dss_dispc, | |
3111 | &omap3xxx_l4_core__dss_dsi1, | |
3112 | &omap3xxx_l4_core__dss_rfbi, | |
3113 | &omap3xxx_l4_core__dss_venc, | |
d9d9cec0 | 3114 | NULL, |
1d2f56c8 IY |
3115 | }; |
3116 | ||
a55a7445 PR |
3117 | /** |
3118 | * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible? | |
3119 | * @bus: struct device_node * for the top-level OMAP DT data | |
3120 | * @dev_name: device name used in the DT file | |
3121 | * | |
3122 | * Determine whether a "secure" IP block @dev_name is usable by Linux. | |
3123 | * There doesn't appear to be a 100% reliable way to determine this, | |
3124 | * so we rely on heuristics. If @bus is null, meaning there's no DT | |
3125 | * data, then we only assume the IP block is accessible if the OMAP is | |
3126 | * fused as a 'general-purpose' SoC. If however DT data is present, | |
3127 | * test to see if the IP block is described in the DT data and set to | |
3128 | * 'status = "okay"'. If so then we assume the ODM has configured the | |
3129 | * OMAP firewalls to allow access to the IP block. | |
3130 | * | |
3131 | * Return: 0 if device named @dev_name is not likely to be accessible, | |
3132 | * or 1 if it is likely to be accessible. | |
3133 | */ | |
10e5778f GR |
3134 | static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus, |
3135 | const char *dev_name) | |
a55a7445 | 3136 | { |
10e5778f GR |
3137 | struct device_node *node; |
3138 | bool available; | |
3139 | ||
a55a7445 | 3140 | if (!bus) |
10e5778f | 3141 | return omap_type() == OMAP2_DEVICE_TYPE_GP; |
a55a7445 | 3142 | |
10e5778f GR |
3143 | node = of_get_child_by_name(bus, dev_name); |
3144 | available = of_device_is_available(node); | |
3145 | of_node_put(node); | |
a55a7445 | 3146 | |
10e5778f | 3147 | return available; |
a55a7445 PR |
3148 | } |
3149 | ||
7359154e PW |
3150 | int __init omap3xxx_hwmod_init(void) |
3151 | { | |
d6504acd | 3152 | int r; |
a55a7445 PR |
3153 | struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL; |
3154 | struct omap_hwmod_ocp_if **h_aes = NULL; | |
3155 | struct device_node *bus = NULL; | |
d6504acd PW |
3156 | unsigned int rev; |
3157 | ||
9ebfd285 KH |
3158 | omap_hwmod_init(); |
3159 | ||
0a78c5c5 PW |
3160 | /* Register hwmod links common to all OMAP3 */ |
3161 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3162 | if (r < 0) |
d6504acd PW |
3163 | return r; |
3164 | ||
3165 | rev = omap_rev(); | |
3166 | ||
3167 | /* | |
0a78c5c5 | 3168 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3169 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3170 | * All possible revisions should be included in this conditional. | |
3171 | */ | |
3172 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3173 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3174 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3175 | h = omap34xx_hwmod_ocp_ifs; |
26f88e6e | 3176 | h_gp = omap34xx_gp_hwmod_ocp_ifs; |
a55a7445 PR |
3177 | h_sham = omap34xx_sham_hwmod_ocp_ifs; |
3178 | h_aes = omap34xx_aes_hwmod_ocp_ifs; | |
68a88b98 | 3179 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
0a78c5c5 | 3180 | h = am35xx_hwmod_ocp_ifs; |
26f88e6e | 3181 | h_gp = am35xx_gp_hwmod_ocp_ifs; |
a55a7445 PR |
3182 | h_sham = am35xx_sham_hwmod_ocp_ifs; |
3183 | h_aes = am35xx_aes_hwmod_ocp_ifs; | |
d6504acd PW |
3184 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3185 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3186 | h = omap36xx_hwmod_ocp_ifs; |
26f88e6e | 3187 | h_gp = omap36xx_gp_hwmod_ocp_ifs; |
a55a7445 PR |
3188 | h_sham = omap36xx_sham_hwmod_ocp_ifs; |
3189 | h_aes = omap36xx_aes_hwmod_ocp_ifs; | |
d6504acd PW |
3190 | } else { |
3191 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3192 | return -EINVAL; | |
c09fcc43 | 3193 | } |
d6504acd | 3194 | |
0a78c5c5 | 3195 | r = omap_hwmod_register_links(h); |
ace90216 | 3196 | if (r < 0) |
d6504acd PW |
3197 | return r; |
3198 | ||
26f88e6e MG |
3199 | /* Register GP-only hwmod links. */ |
3200 | if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { | |
3201 | r = omap_hwmod_register_links(h_gp); | |
3202 | if (r < 0) | |
3203 | return r; | |
3204 | } | |
3205 | ||
a55a7445 PR |
3206 | /* |
3207 | * Register crypto hwmod links only if they are not disabled in DT. | |
3208 | * If DT information is missing, enable them only for GP devices. | |
3209 | */ | |
3210 | ||
3211 | if (of_have_populated_dt()) | |
3212 | bus = of_find_node_by_name(NULL, "ocp"); | |
3213 | ||
3214 | if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { | |
3215 | r = omap_hwmod_register_links(h_sham); | |
b92675d9 GR |
3216 | if (r < 0) { |
3217 | of_node_put(bus); | |
a55a7445 | 3218 | return r; |
b92675d9 | 3219 | } |
a55a7445 PR |
3220 | } |
3221 | ||
3222 | if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) { | |
3223 | r = omap_hwmod_register_links(h_aes); | |
b92675d9 GR |
3224 | if (r < 0) { |
3225 | of_node_put(bus); | |
a55a7445 | 3226 | return r; |
b92675d9 | 3227 | } |
a55a7445 | 3228 | } |
b92675d9 | 3229 | of_node_put(bus); |
26f88e6e | 3230 | |
d6504acd | 3231 | /* |
0a78c5c5 | 3232 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3233 | * particular family of silicon (e.g., 34xx ES1.0) |
3234 | */ | |
3235 | h = NULL; | |
3236 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3237 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3238 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3239 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3240 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3241 | h = omap3430es2plus_hwmod_ocp_ifs; |
c09fcc43 | 3242 | } |
d6504acd | 3243 | |
a52e2ab6 | 3244 | if (h) { |
0a78c5c5 | 3245 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3246 | if (r < 0) |
3247 | return r; | |
3248 | } | |
3249 | ||
3250 | h = NULL; | |
3251 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3252 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3253 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3254 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3255 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3256 | h = omap3430_es3plus_hwmod_ocp_ifs; |
c09fcc43 | 3257 | } |
a52e2ab6 | 3258 | |
d6504acd | 3259 | if (h) |
0a78c5c5 | 3260 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3261 | if (r < 0) |
3262 | return r; | |
3263 | ||
3264 | /* | |
3265 | * DSS code presumes that dss_core hwmod is handled first, | |
3266 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3267 | * DSS hwmod links last to ensure that dss_core is already |
3268 | * registered. Otherwise some change things may happen, for | |
3269 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3270 | * in bootloader DISPC will be reset with outputs enabled | |
3271 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3272 | * long-term fix to this is to ensure hwmods are set up in | |
3273 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3274 | */ |
0a78c5c5 | 3275 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3276 | |
3277 | return r; | |
7359154e | 3278 | } |