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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
55d2cb08 BC |
2 | /* |
3 | * Hardware modules present on the OMAP44xx chips | |
4 | * | |
0a78c5c5 | 5 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
6 | * Copyright (C) 2009-2010 Nokia Corporation |
7 | * | |
8 | * Paul Walmsley | |
9 | * Benoit Cousson | |
10 | * | |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
3b9b1015 S |
16 | * Note that this file is currently not in sync with autogeneration scripts. |
17 | * The above note to be removed, once it is synced up. | |
55d2cb08 BC |
18 | */ |
19 | ||
20 | #include <linux/io.h> | |
2a296c8f | 21 | |
2a296c8f | 22 | #include "omap_hwmod.h" |
55d2cb08 | 23 | #include "omap_hwmod_common_data.h" |
d198b514 PW |
24 | #include "cm1_44xx.h" |
25 | #include "cm2_44xx.h" | |
26 | #include "prm44xx.h" | |
55d2cb08 BC |
27 | #include "prm-regbits-44xx.h" |
28 | ||
29 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
30 | #define OMAP44XX_IRQ_GIC_START 32 | |
31 | ||
55d2cb08 | 32 | /* |
844a3b63 | 33 | * IP blocks |
55d2cb08 BC |
34 | */ |
35 | ||
36 | /* | |
37 | * 'dmm' class | |
38 | * instance(s): dmm | |
39 | */ | |
40 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 41 | .name = "dmm", |
55d2cb08 BC |
42 | }; |
43 | ||
7e69ed97 | 44 | /* dmm */ |
55d2cb08 BC |
45 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
46 | .name = "dmm", | |
47 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 48 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
49 | .prcm = { |
50 | .omap4 = { | |
51 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 52 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
53 | }, |
54 | }, | |
55d2cb08 BC |
55 | }; |
56 | ||
55d2cb08 BC |
57 | /* |
58 | * 'l3' class | |
59 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
60 | */ | |
61 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 62 | .name = "l3", |
55d2cb08 BC |
63 | }; |
64 | ||
7e69ed97 | 65 | /* l3_instr */ |
55d2cb08 BC |
66 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
67 | .name = "l3_instr", | |
68 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 69 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
70 | .prcm = { |
71 | .omap4 = { | |
72 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 73 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 74 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
75 | }, |
76 | }, | |
55d2cb08 BC |
77 | }; |
78 | ||
7e69ed97 | 79 | /* l3_main_1 */ |
55d2cb08 BC |
80 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
81 | .name = "l3_main_1", | |
82 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 83 | .clkdm_name = "l3_1_clkdm", |
d0f0631d BC |
84 | .prcm = { |
85 | .omap4 = { | |
86 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 87 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
88 | }, |
89 | }, | |
55d2cb08 BC |
90 | }; |
91 | ||
7e69ed97 | 92 | /* l3_main_2 */ |
55d2cb08 BC |
93 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
94 | .name = "l3_main_2", | |
95 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 96 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
97 | .prcm = { |
98 | .omap4 = { | |
99 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 100 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
101 | }, |
102 | }, | |
55d2cb08 BC |
103 | }; |
104 | ||
7e69ed97 | 105 | /* l3_main_3 */ |
55d2cb08 BC |
106 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
107 | .name = "l3_main_3", | |
108 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 109 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
110 | .prcm = { |
111 | .omap4 = { | |
112 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 113 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 114 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
115 | }, |
116 | }, | |
55d2cb08 BC |
117 | }; |
118 | ||
119 | /* | |
120 | * 'l4' class | |
121 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
122 | */ | |
123 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 124 | .name = "l4", |
55d2cb08 BC |
125 | }; |
126 | ||
7e69ed97 | 127 | /* l4_cfg */ |
55d2cb08 BC |
128 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
129 | .name = "l4_cfg", | |
130 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 131 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
132 | .prcm = { |
133 | .omap4 = { | |
134 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 135 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
136 | }, |
137 | }, | |
55d2cb08 BC |
138 | }; |
139 | ||
7e69ed97 | 140 | /* l4_per */ |
55d2cb08 BC |
141 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
142 | .name = "l4_per", | |
143 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 144 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
145 | .prcm = { |
146 | .omap4 = { | |
147 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 148 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
149 | }, |
150 | }, | |
55d2cb08 BC |
151 | }; |
152 | ||
7e69ed97 | 153 | /* l4_wkup */ |
55d2cb08 BC |
154 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
155 | .name = "l4_wkup", | |
156 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 157 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
158 | .prcm = { |
159 | .omap4 = { | |
160 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 161 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
162 | }, |
163 | }, | |
55d2cb08 BC |
164 | }; |
165 | ||
f776471f | 166 | /* |
3b54baad BC |
167 | * 'mpu_bus' class |
168 | * instance(s): mpu_private | |
f776471f | 169 | */ |
3b54baad | 170 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 171 | .name = "mpu_bus", |
3b54baad | 172 | }; |
f776471f | 173 | |
7e69ed97 | 174 | /* mpu_private */ |
3b54baad BC |
175 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
176 | .name = "mpu_private", | |
177 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 178 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
179 | .prcm = { |
180 | .omap4 = { | |
181 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
182 | }, | |
183 | }, | |
3b54baad BC |
184 | }; |
185 | ||
9a817bc8 BC |
186 | /* |
187 | * 'ocp_wp_noc' class | |
188 | * instance(s): ocp_wp_noc | |
189 | */ | |
190 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
191 | .name = "ocp_wp_noc", | |
192 | }; | |
193 | ||
194 | /* ocp_wp_noc */ | |
195 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
196 | .name = "ocp_wp_noc", | |
197 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
198 | .clkdm_name = "l3_instr_clkdm", | |
199 | .prcm = { | |
200 | .omap4 = { | |
201 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
202 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
203 | .modulemode = MODULEMODE_HWCTRL, | |
204 | }, | |
205 | }, | |
206 | }; | |
207 | ||
3b54baad BC |
208 | /* |
209 | * Modules omap_hwmod structures | |
210 | * | |
211 | * The following IPs are excluded for the moment because: | |
212 | * - They do not need an explicit SW control using omap_hwmod API. | |
213 | * - They still need to be validated with the driver | |
214 | * properly adapted to omap_hwmod / omap_device | |
215 | * | |
96566043 | 216 | * usim |
3b54baad BC |
217 | */ |
218 | ||
a0b5d813 PW |
219 | /* |
220 | * 'ctrl_module' class | |
221 | * attila core control module + core pad control module + wkup pad control | |
222 | * module + attila wkup control module | |
223 | */ | |
224 | ||
225 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
226 | .rev_offs = 0x0000, | |
227 | .sysc_offs = 0x0010, | |
228 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
229 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
230 | SIDLE_SMART_WKUP), | |
231 | .sysc_fields = &omap_hwmod_sysc_type2, | |
232 | }; | |
233 | ||
234 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
235 | .name = "ctrl_module", | |
236 | .sysc = &omap44xx_ctrl_module_sysc, | |
237 | }; | |
238 | ||
239 | /* ctrl_module_core */ | |
a0b5d813 PW |
240 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { |
241 | .name = "ctrl_module_core", | |
242 | .class = &omap44xx_ctrl_module_hwmod_class, | |
243 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
244 | .prcm = { |
245 | .omap4 = { | |
246 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
247 | }, | |
248 | }, | |
a0b5d813 PW |
249 | }; |
250 | ||
251 | /* ctrl_module_pad_core */ | |
252 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
253 | .name = "ctrl_module_pad_core", | |
254 | .class = &omap44xx_ctrl_module_hwmod_class, | |
255 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
256 | .prcm = { |
257 | .omap4 = { | |
258 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
259 | }, | |
260 | }, | |
a0b5d813 PW |
261 | }; |
262 | ||
263 | /* ctrl_module_wkup */ | |
264 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
265 | .name = "ctrl_module_wkup", | |
266 | .class = &omap44xx_ctrl_module_hwmod_class, | |
267 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
268 | .prcm = { |
269 | .omap4 = { | |
270 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
271 | }, | |
272 | }, | |
a0b5d813 PW |
273 | }; |
274 | ||
275 | /* ctrl_module_pad_wkup */ | |
276 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
277 | .name = "ctrl_module_pad_wkup", | |
278 | .class = &omap44xx_ctrl_module_hwmod_class, | |
279 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
280 | .prcm = { |
281 | .omap4 = { | |
282 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
283 | }, | |
284 | }, | |
a0b5d813 PW |
285 | }; |
286 | ||
96566043 BC |
287 | /* |
288 | * 'debugss' class | |
289 | * debug and emulation sub system | |
290 | */ | |
291 | ||
292 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
293 | .name = "debugss", | |
294 | }; | |
295 | ||
296 | /* debugss */ | |
297 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
298 | .name = "debugss", | |
299 | .class = &omap44xx_debugss_hwmod_class, | |
300 | .clkdm_name = "emu_sys_clkdm", | |
301 | .main_clk = "trace_clk_div_ck", | |
302 | .prcm = { | |
303 | .omap4 = { | |
304 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
305 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
306 | }, | |
307 | }, | |
308 | }; | |
309 | ||
bf30f950 PW |
310 | /* |
311 | * 'emif' class | |
312 | * external memory interface no1 | |
313 | */ | |
314 | ||
315 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
316 | .rev_offs = 0x0000, | |
317 | }; | |
318 | ||
319 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
320 | .name = "emif", | |
321 | .sysc = &omap44xx_emif_sysc, | |
322 | }; | |
323 | ||
324 | /* emif1 */ | |
bf30f950 PW |
325 | static struct omap_hwmod omap44xx_emif1_hwmod = { |
326 | .name = "emif1", | |
327 | .class = &omap44xx_emif_hwmod_class, | |
328 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 329 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
330 | .main_clk = "ddrphy_ck", |
331 | .prcm = { | |
332 | .omap4 = { | |
333 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
334 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
335 | .modulemode = MODULEMODE_HWCTRL, | |
336 | }, | |
337 | }, | |
338 | }; | |
339 | ||
340 | /* emif2 */ | |
bf30f950 PW |
341 | static struct omap_hwmod omap44xx_emif2_hwmod = { |
342 | .name = "emif2", | |
343 | .class = &omap44xx_emif_hwmod_class, | |
344 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 345 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
346 | .main_clk = "ddrphy_ck", |
347 | .prcm = { | |
348 | .omap4 = { | |
349 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
350 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
351 | .modulemode = MODULEMODE_HWCTRL, | |
352 | }, | |
353 | }, | |
354 | }; | |
355 | ||
407a6888 BC |
356 | /* |
357 | * 'iss' class | |
358 | * external images sensor pixel data processor | |
359 | */ | |
360 | ||
361 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
362 | .rev_offs = 0x0000, | |
363 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
364 | /* |
365 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
366 | * accessing sysconfig again. | |
367 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
368 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
369 | * | |
370 | * TODO: Indicate errata when available. | |
371 | */ | |
372 | .srst_udelay = 2, | |
407a6888 BC |
373 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
374 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
375 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
376 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 377 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
378 | .sysc_fields = &omap_hwmod_sysc_type2, |
379 | }; | |
380 | ||
381 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
382 | .name = "iss", | |
383 | .sysc = &omap44xx_iss_sysc, | |
384 | }; | |
385 | ||
386 | /* iss */ | |
407a6888 BC |
387 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
388 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
389 | }; | |
390 | ||
391 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
392 | .name = "iss", | |
393 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 394 | .clkdm_name = "iss_clkdm", |
17b7e7d3 | 395 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 396 | .prcm = { |
407a6888 | 397 | .omap4 = { |
d0f0631d | 398 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 399 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 400 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
401 | }, |
402 | }, | |
403 | .opt_clks = iss_opt_clks, | |
404 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
405 | }; |
406 | ||
3b54baad BC |
407 | /* |
408 | * 'mpu' class | |
409 | * mpu sub-system | |
410 | */ | |
411 | ||
412 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 413 | .name = "mpu", |
db12ba53 BC |
414 | }; |
415 | ||
3b54baad | 416 | /* mpu */ |
3b54baad BC |
417 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
418 | .name = "mpu", | |
419 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 420 | .clkdm_name = "mpuss_clkdm", |
b2eb0002 | 421 | .flags = HWMOD_INIT_NO_IDLE, |
3b54baad | 422 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
423 | .prcm = { |
424 | .omap4 = { | |
d0f0631d | 425 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 426 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
427 | }, |
428 | }, | |
db12ba53 BC |
429 | }; |
430 | ||
e17f18c0 PW |
431 | /* |
432 | * 'ocmc_ram' class | |
433 | * top-level core on-chip ram | |
434 | */ | |
435 | ||
436 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
437 | .name = "ocmc_ram", | |
438 | }; | |
439 | ||
440 | /* ocmc_ram */ | |
441 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
442 | .name = "ocmc_ram", | |
443 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
444 | .clkdm_name = "l3_2_clkdm", | |
445 | .prcm = { | |
446 | .omap4 = { | |
447 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
448 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
449 | }, | |
450 | }, | |
451 | }; | |
452 | ||
0c668875 | 453 | |
794b480a PW |
454 | /* |
455 | * 'prcm' class | |
456 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
457 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
458 | */ | |
459 | ||
460 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
461 | .name = "prcm", | |
462 | }; | |
463 | ||
464 | /* prcm_mpu */ | |
465 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
466 | .name = "prcm_mpu", | |
467 | .class = &omap44xx_prcm_hwmod_class, | |
468 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 469 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
470 | .prcm = { |
471 | .omap4 = { | |
472 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
473 | }, | |
474 | }, | |
794b480a PW |
475 | }; |
476 | ||
477 | /* cm_core_aon */ | |
478 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
479 | .name = "cm_core_aon", | |
480 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 481 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
482 | .prcm = { |
483 | .omap4 = { | |
484 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
485 | }, | |
486 | }, | |
794b480a PW |
487 | }; |
488 | ||
489 | /* cm_core */ | |
490 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
491 | .name = "cm_core", | |
492 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 493 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
494 | .prcm = { |
495 | .omap4 = { | |
496 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
497 | }, | |
498 | }, | |
794b480a PW |
499 | }; |
500 | ||
501 | /* prm */ | |
794b480a PW |
502 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { |
503 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
504 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
505 | }; | |
506 | ||
507 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
508 | .name = "prm", | |
509 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
510 | .rst_lines = omap44xx_prm_resets, |
511 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
512 | }; | |
513 | ||
514 | /* | |
515 | * 'scrm' class | |
516 | * system clock and reset manager | |
517 | */ | |
518 | ||
519 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
520 | .name = "scrm", | |
521 | }; | |
522 | ||
523 | /* scrm */ | |
524 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
525 | .name = "scrm", | |
526 | .class = &omap44xx_scrm_hwmod_class, | |
527 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
528 | .prcm = { |
529 | .omap4 = { | |
530 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
531 | }, | |
532 | }, | |
794b480a PW |
533 | }; |
534 | ||
42b9e387 PW |
535 | /* |
536 | * 'sl2if' class | |
537 | * shared level 2 memory interface | |
538 | */ | |
539 | ||
540 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
541 | .name = "sl2if", | |
542 | }; | |
543 | ||
544 | /* sl2if */ | |
545 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
546 | .name = "sl2if", | |
547 | .class = &omap44xx_sl2if_hwmod_class, | |
548 | .clkdm_name = "ivahd_clkdm", | |
549 | .prcm = { | |
550 | .omap4 = { | |
551 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
552 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
553 | .modulemode = MODULEMODE_HWCTRL, | |
554 | }, | |
555 | }, | |
556 | }; | |
557 | ||
af88fa9a | 558 | /* |
844a3b63 | 559 | * interfaces |
af88fa9a | 560 | */ |
af88fa9a | 561 | |
844a3b63 PW |
562 | /* l3_main_1 -> dmm */ |
563 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
564 | .master = &omap44xx_l3_main_1_hwmod, | |
565 | .slave = &omap44xx_dmm_hwmod, | |
566 | .clk = "l3_div_ck", | |
567 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
568 | }; |
569 | ||
844a3b63 PW |
570 | /* mpu -> dmm */ |
571 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
572 | .master = &omap44xx_mpu_hwmod, | |
573 | .slave = &omap44xx_dmm_hwmod, | |
574 | .clk = "l3_div_ck", | |
844a3b63 PW |
575 | .user = OCP_USER_MPU, |
576 | }; | |
577 | ||
844a3b63 PW |
578 | /* l3_main_3 -> l3_instr */ |
579 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
580 | .master = &omap44xx_l3_main_3_hwmod, | |
581 | .slave = &omap44xx_l3_instr_hwmod, | |
582 | .clk = "l3_div_ck", | |
583 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
584 | }; | |
585 | ||
9a817bc8 BC |
586 | /* ocp_wp_noc -> l3_instr */ |
587 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
588 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
589 | .slave = &omap44xx_l3_instr_hwmod, | |
590 | .clk = "l3_div_ck", | |
591 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
592 | }; | |
593 | ||
844a3b63 PW |
594 | /* l3_main_2 -> l3_main_1 */ |
595 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
596 | .master = &omap44xx_l3_main_2_hwmod, | |
597 | .slave = &omap44xx_l3_main_1_hwmod, | |
598 | .clk = "l3_div_ck", | |
599 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
600 | }; | |
601 | ||
602 | /* l4_cfg -> l3_main_1 */ | |
603 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
604 | .master = &omap44xx_l4_cfg_hwmod, | |
605 | .slave = &omap44xx_l3_main_1_hwmod, | |
606 | .clk = "l4_div_ck", | |
607 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
608 | }; | |
609 | ||
844a3b63 PW |
610 | /* mpu -> l3_main_1 */ |
611 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
612 | .master = &omap44xx_mpu_hwmod, | |
613 | .slave = &omap44xx_l3_main_1_hwmod, | |
614 | .clk = "l3_div_ck", | |
844a3b63 PW |
615 | .user = OCP_USER_MPU, |
616 | }; | |
617 | ||
96566043 BC |
618 | /* debugss -> l3_main_2 */ |
619 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
620 | .master = &omap44xx_debugss_hwmod, | |
621 | .slave = &omap44xx_l3_main_2_hwmod, | |
622 | .clk = "dbgclk_mux_ck", | |
623 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
624 | }; | |
625 | ||
844a3b63 PW |
626 | /* iss -> l3_main_2 */ |
627 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
628 | .master = &omap44xx_iss_hwmod, | |
629 | .slave = &omap44xx_l3_main_2_hwmod, | |
630 | .clk = "l3_div_ck", | |
631 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
632 | }; | |
633 | ||
844a3b63 PW |
634 | /* l3_main_1 -> l3_main_2 */ |
635 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
636 | .master = &omap44xx_l3_main_1_hwmod, | |
637 | .slave = &omap44xx_l3_main_2_hwmod, | |
638 | .clk = "l3_div_ck", | |
844a3b63 PW |
639 | .user = OCP_USER_MPU, |
640 | }; | |
641 | ||
642 | /* l4_cfg -> l3_main_2 */ | |
643 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
644 | .master = &omap44xx_l4_cfg_hwmod, | |
645 | .slave = &omap44xx_l3_main_2_hwmod, | |
646 | .clk = "l4_div_ck", | |
647 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
648 | }; | |
649 | ||
844a3b63 PW |
650 | /* l3_main_1 -> l3_main_3 */ |
651 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
652 | .master = &omap44xx_l3_main_1_hwmod, | |
653 | .slave = &omap44xx_l3_main_3_hwmod, | |
654 | .clk = "l3_div_ck", | |
844a3b63 PW |
655 | .user = OCP_USER_MPU, |
656 | }; | |
657 | ||
658 | /* l3_main_2 -> l3_main_3 */ | |
659 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
660 | .master = &omap44xx_l3_main_2_hwmod, | |
661 | .slave = &omap44xx_l3_main_3_hwmod, | |
662 | .clk = "l3_div_ck", | |
663 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
664 | }; | |
665 | ||
666 | /* l4_cfg -> l3_main_3 */ | |
667 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
668 | .master = &omap44xx_l4_cfg_hwmod, | |
669 | .slave = &omap44xx_l3_main_3_hwmod, | |
670 | .clk = "l4_div_ck", | |
671 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
672 | }; | |
673 | ||
844a3b63 PW |
674 | /* l3_main_1 -> l4_cfg */ |
675 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
676 | .master = &omap44xx_l3_main_1_hwmod, | |
677 | .slave = &omap44xx_l4_cfg_hwmod, | |
678 | .clk = "l3_div_ck", | |
679 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
680 | }; | |
681 | ||
682 | /* l3_main_2 -> l4_per */ | |
683 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
684 | .master = &omap44xx_l3_main_2_hwmod, | |
685 | .slave = &omap44xx_l4_per_hwmod, | |
686 | .clk = "l3_div_ck", | |
687 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
688 | }; | |
689 | ||
690 | /* l4_cfg -> l4_wkup */ | |
691 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
692 | .master = &omap44xx_l4_cfg_hwmod, | |
693 | .slave = &omap44xx_l4_wkup_hwmod, | |
694 | .clk = "l4_div_ck", | |
695 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
696 | }; | |
697 | ||
698 | /* mpu -> mpu_private */ | |
699 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
700 | .master = &omap44xx_mpu_hwmod, | |
701 | .slave = &omap44xx_mpu_private_hwmod, | |
702 | .clk = "l3_div_ck", | |
703 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
704 | }; | |
705 | ||
9a817bc8 BC |
706 | /* l4_cfg -> ocp_wp_noc */ |
707 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
708 | .master = &omap44xx_l4_cfg_hwmod, | |
709 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
710 | .clk = "l4_div_ck", | |
9a817bc8 BC |
711 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
712 | }; | |
713 | ||
a0b5d813 PW |
714 | /* l4_cfg -> ctrl_module_core */ |
715 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
716 | .master = &omap44xx_l4_cfg_hwmod, | |
717 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
718 | .clk = "l4_div_ck", | |
a0b5d813 PW |
719 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
720 | }; | |
721 | ||
a0b5d813 PW |
722 | /* l4_cfg -> ctrl_module_pad_core */ |
723 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
724 | .master = &omap44xx_l4_cfg_hwmod, | |
725 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
726 | .clk = "l4_div_ck", | |
a0b5d813 PW |
727 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
728 | }; | |
729 | ||
a0b5d813 PW |
730 | /* l4_wkup -> ctrl_module_wkup */ |
731 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
732 | .master = &omap44xx_l4_wkup_hwmod, | |
733 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
734 | .clk = "l4_wkup_clk_mux_ck", | |
a0b5d813 PW |
735 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
736 | }; | |
737 | ||
a0b5d813 PW |
738 | /* l4_wkup -> ctrl_module_pad_wkup */ |
739 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
740 | .master = &omap44xx_l4_wkup_hwmod, | |
741 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
742 | .clk = "l4_wkup_clk_mux_ck", | |
a0b5d813 PW |
743 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
744 | }; | |
745 | ||
96566043 BC |
746 | /* l3_instr -> debugss */ |
747 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
748 | .master = &omap44xx_l3_instr_hwmod, | |
749 | .slave = &omap44xx_debugss_hwmod, | |
750 | .clk = "l3_div_ck", | |
96566043 BC |
751 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
752 | }; | |
753 | ||
844a3b63 PW |
754 | /* l3_main_2 -> iss */ |
755 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
756 | .master = &omap44xx_l3_main_2_hwmod, | |
757 | .slave = &omap44xx_iss_hwmod, | |
758 | .clk = "l3_div_ck", | |
844a3b63 PW |
759 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
760 | }; | |
761 | ||
e17f18c0 PW |
762 | /* l3_main_2 -> ocmc_ram */ |
763 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
764 | .master = &omap44xx_l3_main_2_hwmod, | |
765 | .slave = &omap44xx_ocmc_ram_hwmod, | |
766 | .clk = "l3_div_ck", | |
767 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
768 | }; | |
769 | ||
794b480a PW |
770 | /* mpu_private -> prcm_mpu */ |
771 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
772 | .master = &omap44xx_mpu_private_hwmod, | |
773 | .slave = &omap44xx_prcm_mpu_hwmod, | |
774 | .clk = "l3_div_ck", | |
794b480a PW |
775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
776 | }; | |
777 | ||
794b480a PW |
778 | /* l4_wkup -> cm_core_aon */ |
779 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
780 | .master = &omap44xx_l4_wkup_hwmod, | |
781 | .slave = &omap44xx_cm_core_aon_hwmod, | |
782 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
783 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
784 | }; | |
785 | ||
794b480a PW |
786 | /* l4_cfg -> cm_core */ |
787 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
788 | .master = &omap44xx_l4_cfg_hwmod, | |
789 | .slave = &omap44xx_cm_core_hwmod, | |
790 | .clk = "l4_div_ck", | |
794b480a PW |
791 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
792 | }; | |
793 | ||
794b480a PW |
794 | /* l4_wkup -> prm */ |
795 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
796 | .master = &omap44xx_l4_wkup_hwmod, | |
797 | .slave = &omap44xx_prm_hwmod, | |
798 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
799 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
800 | }; | |
801 | ||
794b480a PW |
802 | /* l4_wkup -> scrm */ |
803 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
804 | .master = &omap44xx_l4_wkup_hwmod, | |
805 | .slave = &omap44xx_scrm_hwmod, | |
806 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
807 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
808 | }; | |
809 | ||
42b9e387 | 810 | /* l3_main_2 -> sl2if */ |
b360124e | 811 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
812 | .master = &omap44xx_l3_main_2_hwmod, |
813 | .slave = &omap44xx_sl2if_hwmod, | |
814 | .clk = "l3_div_ck", | |
815 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
816 | }; | |
817 | ||
3b9b1015 S |
818 | /* mpu -> emif1 */ |
819 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { | |
820 | .master = &omap44xx_mpu_hwmod, | |
821 | .slave = &omap44xx_emif1_hwmod, | |
822 | .clk = "l3_div_ck", | |
823 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
824 | }; | |
825 | ||
826 | /* mpu -> emif2 */ | |
827 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { | |
828 | .master = &omap44xx_mpu_hwmod, | |
829 | .slave = &omap44xx_emif2_hwmod, | |
830 | .clk = "l3_div_ck", | |
831 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
832 | }; | |
833 | ||
0a78c5c5 PW |
834 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
835 | &omap44xx_l3_main_1__dmm, | |
836 | &omap44xx_mpu__dmm, | |
0a78c5c5 | 837 | &omap44xx_l3_main_3__l3_instr, |
9a817bc8 | 838 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
839 | &omap44xx_l3_main_2__l3_main_1, |
840 | &omap44xx_l4_cfg__l3_main_1, | |
0a78c5c5 | 841 | &omap44xx_mpu__l3_main_1, |
96566043 | 842 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 843 | &omap44xx_iss__l3_main_2, |
0a78c5c5 PW |
844 | &omap44xx_l3_main_1__l3_main_2, |
845 | &omap44xx_l4_cfg__l3_main_2, | |
0a78c5c5 PW |
846 | &omap44xx_l3_main_1__l3_main_3, |
847 | &omap44xx_l3_main_2__l3_main_3, | |
848 | &omap44xx_l4_cfg__l3_main_3, | |
0a78c5c5 PW |
849 | &omap44xx_l3_main_1__l4_cfg, |
850 | &omap44xx_l3_main_2__l4_per, | |
851 | &omap44xx_l4_cfg__l4_wkup, | |
852 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 853 | &omap44xx_l4_cfg__ocp_wp_noc, |
a0b5d813 PW |
854 | &omap44xx_l4_cfg__ctrl_module_core, |
855 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
856 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
857 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 858 | &omap44xx_l3_instr__debugss, |
0a78c5c5 | 859 | &omap44xx_l3_main_2__iss, |
e17f18c0 | 860 | &omap44xx_l3_main_2__ocmc_ram, |
794b480a PW |
861 | &omap44xx_mpu_private__prcm_mpu, |
862 | &omap44xx_l4_wkup__cm_core_aon, | |
863 | &omap44xx_l4_cfg__cm_core, | |
864 | &omap44xx_l4_wkup__prm, | |
865 | &omap44xx_l4_wkup__scrm, | |
b360124e | 866 | /* &omap44xx_l3_main_2__sl2if, */ |
3b9b1015 S |
867 | &omap44xx_mpu__emif1, |
868 | &omap44xx_mpu__emif2, | |
55d2cb08 BC |
869 | NULL, |
870 | }; | |
871 | ||
872 | int __init omap44xx_hwmod_init(void) | |
873 | { | |
9ebfd285 | 874 | omap_hwmod_init(); |
0a78c5c5 | 875 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
876 | } |
877 |