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OMAP4: hwmod data: enable HSMMC
[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
CommitLineData
55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
d63bd74f 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
55d2cb08
BC		 5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
9780a9cf 25#include <plat/gpio.h>
531ce0d5 26#include <plat/dma.h>
905a74d9 27#include <plat/mcspi.h>
55d2cb08
BC		 28
29#include "omap_hwmod_common_data.h"
30
d198b514
PW		 31#include "cm1_44xx.h"
32#include "cm2_44xx.h"
33#include "prm44xx.h"
55d2cb08 34#include "prm-regbits-44xx.h"
ff2516fb 35#include "wd_timer.h"
55d2cb08
BC		 36
37/* Base offset for all OMAP4 interrupts external to MPUSS */
38#define OMAP44XX_IRQ_GIC_START 32
39
40/* Base offset for all OMAP4 dma requests */
41#define OMAP44XX_DMA_REQ_START 1
42
43/* Backward references (IPs with Bus Master capability) */
407a6888 44static struct omap_hwmod omap44xx_aess_hwmod;
531ce0d5 45static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 46static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 47static struct omap_hwmod omap44xx_dsp_hwmod;
d63bd74f 48static struct omap_hwmod omap44xx_dss_hwmod;
55d2cb08 49static struct omap_hwmod omap44xx_emif_fw_hwmod;
407a6888
BC		 50static struct omap_hwmod omap44xx_hsi_hwmod;
51static struct omap_hwmod omap44xx_ipu_hwmod;
52static struct omap_hwmod omap44xx_iss_hwmod;
8f25bdc5 53static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 54static struct omap_hwmod omap44xx_l3_instr_hwmod;
55static struct omap_hwmod omap44xx_l3_main_1_hwmod;
56static struct omap_hwmod omap44xx_l3_main_2_hwmod;
57static struct omap_hwmod omap44xx_l3_main_3_hwmod;
58static struct omap_hwmod omap44xx_l4_abe_hwmod;
59static struct omap_hwmod omap44xx_l4_cfg_hwmod;
60static struct omap_hwmod omap44xx_l4_per_hwmod;
61static struct omap_hwmod omap44xx_l4_wkup_hwmod;
407a6888
BC		 62static struct omap_hwmod omap44xx_mmc1_hwmod;
63static struct omap_hwmod omap44xx_mmc2_hwmod;
55d2cb08
BC		 64static struct omap_hwmod omap44xx_mpu_hwmod;
65static struct omap_hwmod omap44xx_mpu_private_hwmod;
5844c4ea 66static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
55d2cb08
BC		 67
68/*
69 * Interconnects omap_hwmod structures
70 * hwmods that compose the global OMAP interconnect
71 */
72
73/*
74 * 'dmm' class
75 * instance(s): dmm
76 */
77static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 78 .name = "dmm",
55d2cb08
BC		 79};
80
81/* dmm interface data */
82/* l3_main_1 -> dmm */
83static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
84 .master = &omap44xx_l3_main_1_hwmod,
85 .slave = &omap44xx_dmm_hwmod,
86 .clk = "l3_div_ck",
659fa822
BC		 87 .user = OCP_USER_SDMA,
88};
89
90static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
91 {
92 .pa_start = 0x4e000000,
93 .pa_end = 0x4e0007ff,
94 .flags = ADDR_TYPE_RT
95 },
55d2cb08
BC		 96};
97
98/* mpu -> dmm */
99static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
100 .master = &omap44xx_mpu_hwmod,
101 .slave = &omap44xx_dmm_hwmod,
102 .clk = "l3_div_ck",
659fa822
BC		 103 .addr = omap44xx_dmm_addrs,
104 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
105 .user = OCP_USER_MPU,
55d2cb08
BC		 106};
107
108/* dmm slave ports */
109static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
110 &omap44xx_l3_main_1__dmm,
111 &omap44xx_mpu__dmm,
112};
113
114static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
115 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
116};
117
118static struct omap_hwmod omap44xx_dmm_hwmod = {
119 .name = "dmm",
120 .class = &omap44xx_dmm_hwmod_class,
121 .slaves = omap44xx_dmm_slaves,
122 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
123 .mpu_irqs = omap44xx_dmm_irqs,
124 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
125 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
126};
127
128/*
129 * 'emif_fw' class
130 * instance(s): emif_fw
131 */
132static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 133 .name = "emif_fw",
55d2cb08
BC		 134};
135
136/* emif_fw interface data */
137/* dmm -> emif_fw */
138static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
139 .master = &omap44xx_dmm_hwmod,
140 .slave = &omap44xx_emif_fw_hwmod,
141 .clk = "l3_div_ck",
142 .user = OCP_USER_MPU | OCP_USER_SDMA,
143};
144
659fa822
BC		 145static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
146 {
147 .pa_start = 0x4a20c000,
148 .pa_end = 0x4a20c0ff,
149 .flags = ADDR_TYPE_RT
150 },
151};
152
55d2cb08
BC		 153/* l4_cfg -> emif_fw */
154static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
155 .master = &omap44xx_l4_cfg_hwmod,
156 .slave = &omap44xx_emif_fw_hwmod,
157 .clk = "l4_div_ck",
659fa822
BC		 158 .addr = omap44xx_emif_fw_addrs,
159 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
160 .user = OCP_USER_MPU,
55d2cb08
BC		 161};
162
163/* emif_fw slave ports */
164static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
165 &omap44xx_dmm__emif_fw,
166 &omap44xx_l4_cfg__emif_fw,
167};
168
169static struct omap_hwmod omap44xx_emif_fw_hwmod = {
170 .name = "emif_fw",
171 .class = &omap44xx_emif_fw_hwmod_class,
172 .slaves = omap44xx_emif_fw_slaves,
173 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
175};
176
177/*
178 * 'l3' class
179 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
180 */
181static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 182 .name = "l3",
55d2cb08
BC		 183};
184
185/* l3_instr interface data */
8f25bdc5
BC		 186/* iva -> l3_instr */
187static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
188 .master = &omap44xx_iva_hwmod,
189 .slave = &omap44xx_l3_instr_hwmod,
190 .clk = "l3_div_ck",
191 .user = OCP_USER_MPU | OCP_USER_SDMA,
192};
193
55d2cb08
BC		 194/* l3_main_3 -> l3_instr */
195static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
196 .master = &omap44xx_l3_main_3_hwmod,
197 .slave = &omap44xx_l3_instr_hwmod,
198 .clk = "l3_div_ck",
199 .user = OCP_USER_MPU | OCP_USER_SDMA,
200};
201
202/* l3_instr slave ports */
203static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 204 &omap44xx_iva__l3_instr,
55d2cb08
BC		 205 &omap44xx_l3_main_3__l3_instr,
206};
207
208static struct omap_hwmod omap44xx_l3_instr_hwmod = {
209 .name = "l3_instr",
210 .class = &omap44xx_l3_hwmod_class,
211 .slaves = omap44xx_l3_instr_slaves,
212 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
213 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
214};
215
3b54baad 216/* l3_main_1 interface data */
8f25bdc5
BC		 217/* dsp -> l3_main_1 */
218static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
219 .master = &omap44xx_dsp_hwmod,
220 .slave = &omap44xx_l3_main_1_hwmod,
221 .clk = "l3_div_ck",
222 .user = OCP_USER_MPU | OCP_USER_SDMA,
223};
224
d63bd74f
BC		 225/* dss -> l3_main_1 */
226static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
227 .master = &omap44xx_dss_hwmod,
228 .slave = &omap44xx_l3_main_1_hwmod,
229 .clk = "l3_div_ck",
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
55d2cb08
BC		 233/* l3_main_2 -> l3_main_1 */
234static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
235 .master = &omap44xx_l3_main_2_hwmod,
236 .slave = &omap44xx_l3_main_1_hwmod,
237 .clk = "l3_div_ck",
238 .user = OCP_USER_MPU | OCP_USER_SDMA,
239};
240
241/* l4_cfg -> l3_main_1 */
242static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
243 .master = &omap44xx_l4_cfg_hwmod,
244 .slave = &omap44xx_l3_main_1_hwmod,
245 .clk = "l4_div_ck",
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247};
248
407a6888
BC		 249/* mmc1 -> l3_main_1 */
250static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
251 .master = &omap44xx_mmc1_hwmod,
252 .slave = &omap44xx_l3_main_1_hwmod,
253 .clk = "l3_div_ck",
254 .user = OCP_USER_MPU | OCP_USER_SDMA,
255};
256
257/* mmc2 -> l3_main_1 */
258static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
259 .master = &omap44xx_mmc2_hwmod,
260 .slave = &omap44xx_l3_main_1_hwmod,
261 .clk = "l3_div_ck",
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263};
264
55d2cb08
BC		 265/* mpu -> l3_main_1 */
266static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
267 .master = &omap44xx_mpu_hwmod,
268 .slave = &omap44xx_l3_main_1_hwmod,
269 .clk = "l3_div_ck",
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
271};
272
273/* l3_main_1 slave ports */
274static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 275 &omap44xx_dsp__l3_main_1,
d63bd74f 276 &omap44xx_dss__l3_main_1,
55d2cb08
BC		 277 &omap44xx_l3_main_2__l3_main_1,
278 &omap44xx_l4_cfg__l3_main_1,
407a6888
BC		 279 &omap44xx_mmc1__l3_main_1,
280 &omap44xx_mmc2__l3_main_1,
55d2cb08
BC		 281 &omap44xx_mpu__l3_main_1,
282};
283
284static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
285 .name = "l3_main_1",
286 .class = &omap44xx_l3_hwmod_class,
287 .slaves = omap44xx_l3_main_1_slaves,
288 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
290};
291
292/* l3_main_2 interface data */
d7cf5f33
BC		 293/* dma_system -> l3_main_2 */
294static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
295 .master = &omap44xx_dma_system_hwmod,
296 .slave = &omap44xx_l3_main_2_hwmod,
297 .clk = "l3_div_ck",
298 .user = OCP_USER_MPU | OCP_USER_SDMA,
299};
300
407a6888
BC		 301/* hsi -> l3_main_2 */
302static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
303 .master = &omap44xx_hsi_hwmod,
304 .slave = &omap44xx_l3_main_2_hwmod,
305 .clk = "l3_div_ck",
306 .user = OCP_USER_MPU | OCP_USER_SDMA,
307};
308
309/* ipu -> l3_main_2 */
310static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
311 .master = &omap44xx_ipu_hwmod,
312 .slave = &omap44xx_l3_main_2_hwmod,
313 .clk = "l3_div_ck",
314 .user = OCP_USER_MPU | OCP_USER_SDMA,
315};
316
317/* iss -> l3_main_2 */
318static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
319 .master = &omap44xx_iss_hwmod,
320 .slave = &omap44xx_l3_main_2_hwmod,
321 .clk = "l3_div_ck",
322 .user = OCP_USER_MPU | OCP_USER_SDMA,
323};
324
8f25bdc5
BC		 325/* iva -> l3_main_2 */
326static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
327 .master = &omap44xx_iva_hwmod,
328 .slave = &omap44xx_l3_main_2_hwmod,
329 .clk = "l3_div_ck",
330 .user = OCP_USER_MPU | OCP_USER_SDMA,
331};
332
55d2cb08
BC		 333/* l3_main_1 -> l3_main_2 */
334static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
335 .master = &omap44xx_l3_main_1_hwmod,
336 .slave = &omap44xx_l3_main_2_hwmod,
337 .clk = "l3_div_ck",
338 .user = OCP_USER_MPU | OCP_USER_SDMA,
339};
340
341/* l4_cfg -> l3_main_2 */
342static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
343 .master = &omap44xx_l4_cfg_hwmod,
344 .slave = &omap44xx_l3_main_2_hwmod,
345 .clk = "l4_div_ck",
346 .user = OCP_USER_MPU | OCP_USER_SDMA,
347};
348
5844c4ea
BC		 349/* usb_otg_hs -> l3_main_2 */
350static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
351 .master = &omap44xx_usb_otg_hs_hwmod,
352 .slave = &omap44xx_l3_main_2_hwmod,
353 .clk = "l3_div_ck",
354 .user = OCP_USER_MPU | OCP_USER_SDMA,
355};
356
55d2cb08
BC		 357/* l3_main_2 slave ports */
358static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 359 &omap44xx_dma_system__l3_main_2,
407a6888
BC		 360 &omap44xx_hsi__l3_main_2,
361 &omap44xx_ipu__l3_main_2,
362 &omap44xx_iss__l3_main_2,
8f25bdc5 363 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 364 &omap44xx_l3_main_1__l3_main_2,
365 &omap44xx_l4_cfg__l3_main_2,
5844c4ea 366 &omap44xx_usb_otg_hs__l3_main_2,
55d2cb08
BC		 367};
368
369static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
370 .name = "l3_main_2",
371 .class = &omap44xx_l3_hwmod_class,
372 .slaves = omap44xx_l3_main_2_slaves,
373 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
374 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
375};
376
377/* l3_main_3 interface data */
378/* l3_main_1 -> l3_main_3 */
379static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
380 .master = &omap44xx_l3_main_1_hwmod,
381 .slave = &omap44xx_l3_main_3_hwmod,
382 .clk = "l3_div_ck",
383 .user = OCP_USER_MPU | OCP_USER_SDMA,
384};
385
386/* l3_main_2 -> l3_main_3 */
387static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
388 .master = &omap44xx_l3_main_2_hwmod,
389 .slave = &omap44xx_l3_main_3_hwmod,
390 .clk = "l3_div_ck",
391 .user = OCP_USER_MPU | OCP_USER_SDMA,
392};
393
394/* l4_cfg -> l3_main_3 */
395static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
396 .master = &omap44xx_l4_cfg_hwmod,
397 .slave = &omap44xx_l3_main_3_hwmod,
398 .clk = "l4_div_ck",
399 .user = OCP_USER_MPU | OCP_USER_SDMA,
400};
401
402/* l3_main_3 slave ports */
403static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
404 &omap44xx_l3_main_1__l3_main_3,
405 &omap44xx_l3_main_2__l3_main_3,
406 &omap44xx_l4_cfg__l3_main_3,
407};
408
409static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
410 .name = "l3_main_3",
411 .class = &omap44xx_l3_hwmod_class,
412 .slaves = omap44xx_l3_main_3_slaves,
413 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
415};
416
417/*
418 * 'l4' class
419 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
420 */
421static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 422 .name = "l4",
55d2cb08
BC		 423};
424
425/* l4_abe interface data */
407a6888
BC		 426/* aess -> l4_abe */
427static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
428 .master = &omap44xx_aess_hwmod,
429 .slave = &omap44xx_l4_abe_hwmod,
430 .clk = "ocp_abe_iclk",
431 .user = OCP_USER_MPU | OCP_USER_SDMA,
432};
433
8f25bdc5
BC		 434/* dsp -> l4_abe */
435static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
436 .master = &omap44xx_dsp_hwmod,
437 .slave = &omap44xx_l4_abe_hwmod,
438 .clk = "ocp_abe_iclk",
439 .user = OCP_USER_MPU | OCP_USER_SDMA,
440};
441
55d2cb08
BC		 442/* l3_main_1 -> l4_abe */
443static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
444 .master = &omap44xx_l3_main_1_hwmod,
445 .slave = &omap44xx_l4_abe_hwmod,
446 .clk = "l3_div_ck",
447 .user = OCP_USER_MPU | OCP_USER_SDMA,
448};
449
450/* mpu -> l4_abe */
451static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
452 .master = &omap44xx_mpu_hwmod,
453 .slave = &omap44xx_l4_abe_hwmod,
454 .clk = "ocp_abe_iclk",
455 .user = OCP_USER_MPU | OCP_USER_SDMA,
456};
457
458/* l4_abe slave ports */
459static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
407a6888 460 &omap44xx_aess__l4_abe,
8f25bdc5 461 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 462 &omap44xx_l3_main_1__l4_abe,
463 &omap44xx_mpu__l4_abe,
464};
465
466static struct omap_hwmod omap44xx_l4_abe_hwmod = {
467 .name = "l4_abe",
468 .class = &omap44xx_l4_hwmod_class,
469 .slaves = omap44xx_l4_abe_slaves,
470 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
472};
473
474/* l4_cfg interface data */
475/* l3_main_1 -> l4_cfg */
476static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
477 .master = &omap44xx_l3_main_1_hwmod,
478 .slave = &omap44xx_l4_cfg_hwmod,
479 .clk = "l3_div_ck",
480 .user = OCP_USER_MPU | OCP_USER_SDMA,
481};
482
483/* l4_cfg slave ports */
484static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
485 &omap44xx_l3_main_1__l4_cfg,
486};
487
488static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
489 .name = "l4_cfg",
490 .class = &omap44xx_l4_hwmod_class,
491 .slaves = omap44xx_l4_cfg_slaves,
492 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
494};
495
496/* l4_per interface data */
497/* l3_main_2 -> l4_per */
498static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
499 .master = &omap44xx_l3_main_2_hwmod,
500 .slave = &omap44xx_l4_per_hwmod,
501 .clk = "l3_div_ck",
502 .user = OCP_USER_MPU | OCP_USER_SDMA,
503};
504
505/* l4_per slave ports */
506static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
507 &omap44xx_l3_main_2__l4_per,
508};
509
510static struct omap_hwmod omap44xx_l4_per_hwmod = {
511 .name = "l4_per",
512 .class = &omap44xx_l4_hwmod_class,
513 .slaves = omap44xx_l4_per_slaves,
514 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
515 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
516};
517
518/* l4_wkup interface data */
519/* l4_cfg -> l4_wkup */
520static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
521 .master = &omap44xx_l4_cfg_hwmod,
522 .slave = &omap44xx_l4_wkup_hwmod,
523 .clk = "l4_div_ck",
524 .user = OCP_USER_MPU | OCP_USER_SDMA,
525};
526
527/* l4_wkup slave ports */
528static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
529 &omap44xx_l4_cfg__l4_wkup,
530};
531
532static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
533 .name = "l4_wkup",
534 .class = &omap44xx_l4_hwmod_class,
535 .slaves = omap44xx_l4_wkup_slaves,
536 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
537 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
538};
539
f776471f 540/*
3b54baad
BC		 541 * 'mpu_bus' class
542 * instance(s): mpu_private
f776471f 543 */
3b54baad 544static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 545 .name = "mpu_bus",
3b54baad 546};
f776471f 547
3b54baad
BC		 548/* mpu_private interface data */
549/* mpu -> mpu_private */
550static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
551 .master = &omap44xx_mpu_hwmod,
552 .slave = &omap44xx_mpu_private_hwmod,
553 .clk = "l3_div_ck",
554 .user = OCP_USER_MPU | OCP_USER_SDMA,
555};
556
557/* mpu_private slave ports */
558static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
559 &omap44xx_mpu__mpu_private,
560};
561
562static struct omap_hwmod omap44xx_mpu_private_hwmod = {
563 .name = "mpu_private",
564 .class = &omap44xx_mpu_bus_hwmod_class,
565 .slaves = omap44xx_mpu_private_slaves,
566 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
568};
569
570/*
571 * Modules omap_hwmod structures
572 *
573 * The following IPs are excluded for the moment because:
574 * - They do not need an explicit SW control using omap_hwmod API.
575 * - They still need to be validated with the driver
576 * properly adapted to omap_hwmod / omap_device
577 *
3b54baad
BC		 578 * c2c
579 * c2c_target_fw
580 * cm_core
581 * cm_core_aon
3b54baad
BC		 582 * ctrl_module_core
583 * ctrl_module_pad_core
584 * ctrl_module_pad_wkup
585 * ctrl_module_wkup
586 * debugss
3b54baad
BC		 587 * efuse_ctrl_cust
588 * efuse_ctrl_std
589 * elm
590 * emif1
591 * emif2
592 * fdif
593 * gpmc
594 * gpu
595 * hdq1w
596 * hsi
3b54baad
BC		 597 * ocmc_ram
598 * ocp2scp_usb_phy
599 * ocp_wp_noc
3b54baad
BC		 600 * prcm_mpu
601 * prm
602 * scrm
603 * sl2if
604 * slimbus1
605 * slimbus2
3b54baad
BC		 606 * usb_host_fs
607 * usb_host_hs
3b54baad
BC		 608 * usb_phy_cm
609 * usb_tll_hs
610 * usim
611 */
612
407a6888
BC		 613/*
614 * 'aess' class
615 * audio engine sub system
616 */
617
618static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
619 .rev_offs = 0x0000,
620 .sysc_offs = 0x0010,
621 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
622 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
623 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
624 .sysc_fields = &omap_hwmod_sysc_type2,
625};
626
627static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
628 .name = "aess",
629 .sysc = &omap44xx_aess_sysc,
630};
631
632/* aess */
633static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
634 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
635};
636
637static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
638 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
639 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
640 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
641 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
642 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
643 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
644 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
645 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
646};
647
648/* aess master ports */
649static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
650 &omap44xx_aess__l4_abe,
651};
652
653static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
654 {
655 .pa_start = 0x401f1000,
656 .pa_end = 0x401f13ff,
657 .flags = ADDR_TYPE_RT
658 },
659};
660
661/* l4_abe -> aess */
662static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
663 .master = &omap44xx_l4_abe_hwmod,
664 .slave = &omap44xx_aess_hwmod,
665 .clk = "ocp_abe_iclk",
666 .addr = omap44xx_aess_addrs,
667 .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
668 .user = OCP_USER_MPU,
669};
670
671static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
672 {
673 .pa_start = 0x490f1000,
674 .pa_end = 0x490f13ff,
675 .flags = ADDR_TYPE_RT
676 },
677};
678
679/* l4_abe -> aess (dma) */
680static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
681 .master = &omap44xx_l4_abe_hwmod,
682 .slave = &omap44xx_aess_hwmod,
683 .clk = "ocp_abe_iclk",
684 .addr = omap44xx_aess_dma_addrs,
685 .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
686 .user = OCP_USER_SDMA,
687};
688
689/* aess slave ports */
690static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
691 &omap44xx_l4_abe__aess,
692 &omap44xx_l4_abe__aess_dma,
693};
694
695static struct omap_hwmod omap44xx_aess_hwmod = {
696 .name = "aess",
697 .class = &omap44xx_aess_hwmod_class,
698 .mpu_irqs = omap44xx_aess_irqs,
699 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
700 .sdma_reqs = omap44xx_aess_sdma_reqs,
701 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
702 .main_clk = "aess_fck",
703 .prcm = {
704 .omap4 = {
705 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
706 },
707 },
708 .slaves = omap44xx_aess_slaves,
709 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
710 .masters = omap44xx_aess_masters,
711 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
712 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
713};
714
715/*
716 * 'bandgap' class
717 * bangap reference for ldo regulators
718 */
719
720static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
721 .name = "bandgap",
722};
723
724/* bandgap */
725static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
726 { .role = "fclk", .clk = "bandgap_fclk" },
727};
728
729static struct omap_hwmod omap44xx_bandgap_hwmod = {
730 .name = "bandgap",
731 .class = &omap44xx_bandgap_hwmod_class,
732 .prcm = {
733 .omap4 = {
734 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
735 },
736 },
737 .opt_clks = bandgap_opt_clks,
738 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
739 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
740};
741
742/*
743 * 'counter' class
744 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
745 */
746
747static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
748 .rev_offs = 0x0000,
749 .sysc_offs = 0x0004,
750 .sysc_flags = SYSC_HAS_SIDLEMODE,
751 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
752 SIDLE_SMART_WKUP),
753 .sysc_fields = &omap_hwmod_sysc_type1,
754};
755
756static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
757 .name = "counter",
758 .sysc = &omap44xx_counter_sysc,
759};
760
761/* counter_32k */
762static struct omap_hwmod omap44xx_counter_32k_hwmod;
763static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
764 {
765 .pa_start = 0x4a304000,
766 .pa_end = 0x4a30401f,
767 .flags = ADDR_TYPE_RT
768 },
769};
770
771/* l4_wkup -> counter_32k */
772static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
773 .master = &omap44xx_l4_wkup_hwmod,
774 .slave = &omap44xx_counter_32k_hwmod,
775 .clk = "l4_wkup_clk_mux_ck",
776 .addr = omap44xx_counter_32k_addrs,
777 .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
778 .user = OCP_USER_MPU | OCP_USER_SDMA,
779};
780
781/* counter_32k slave ports */
782static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
783 &omap44xx_l4_wkup__counter_32k,
784};
785
786static struct omap_hwmod omap44xx_counter_32k_hwmod = {
787 .name = "counter_32k",
788 .class = &omap44xx_counter_hwmod_class,
789 .flags = HWMOD_SWSUP_SIDLE,
790 .main_clk = "sys_32k_ck",
791 .prcm = {
792 .omap4 = {
793 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
794 },
795 },
796 .slaves = omap44xx_counter_32k_slaves,
797 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
798 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
799};
800
d7cf5f33
BC		 801/*
802 * 'dma' class
803 * dma controller for data exchange between memory to memory (i.e. internal or
804 * external memory) and gp peripherals to memory or memory to gp peripherals
805 */
806
807static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
808 .rev_offs = 0x0000,
809 .sysc_offs = 0x002c,
810 .syss_offs = 0x0028,
811 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
812 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
813 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
814 SYSS_HAS_RESET_STATUS),
815 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
816 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
817 .sysc_fields = &omap_hwmod_sysc_type1,
818};
819
820static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
821 .name = "dma",
822 .sysc = &omap44xx_dma_sysc,
823};
824
825/* dma dev_attr */
826static struct omap_dma_dev_attr dma_dev_attr = {
827 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
828 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
829 .lch_count = 32,
830};
831
832/* dma_system */
833static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
834 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
835 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
836 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
837 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
838};
839
840/* dma_system master ports */
841static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
842 &omap44xx_dma_system__l3_main_2,
843};
844
845static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
846 {
847 .pa_start = 0x4a056000,
848 .pa_end = 0x4a0560ff,
849 .flags = ADDR_TYPE_RT
850 },
851};
852
853/* l4_cfg -> dma_system */
854static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
855 .master = &omap44xx_l4_cfg_hwmod,
856 .slave = &omap44xx_dma_system_hwmod,
857 .clk = "l4_div_ck",
858 .addr = omap44xx_dma_system_addrs,
859 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
860 .user = OCP_USER_MPU | OCP_USER_SDMA,
861};
862
863/* dma_system slave ports */
864static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
865 &omap44xx_l4_cfg__dma_system,
866};
867
868static struct omap_hwmod omap44xx_dma_system_hwmod = {
869 .name = "dma_system",
870 .class = &omap44xx_dma_hwmod_class,
871 .mpu_irqs = omap44xx_dma_system_irqs,
872 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
873 .main_clk = "l3_div_ck",
874 .prcm = {
875 .omap4 = {
876 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
877 },
878 },
879 .dev_attr = &dma_dev_attr,
880 .slaves = omap44xx_dma_system_slaves,
881 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
882 .masters = omap44xx_dma_system_masters,
883 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
884 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
885};
886
8ca476da
BC		 887/*
888 * 'dmic' class
889 * digital microphone controller
890 */
891
892static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
893 .rev_offs = 0x0000,
894 .sysc_offs = 0x0010,
895 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
896 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
897 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
898 SIDLE_SMART_WKUP),
899 .sysc_fields = &omap_hwmod_sysc_type2,
900};
901
902static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
903 .name = "dmic",
904 .sysc = &omap44xx_dmic_sysc,
905};
906
907/* dmic */
908static struct omap_hwmod omap44xx_dmic_hwmod;
909static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
910 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
911};
912
913static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
914 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
915};
916
917static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
918 {
919 .pa_start = 0x4012e000,
920 .pa_end = 0x4012e07f,
921 .flags = ADDR_TYPE_RT
922 },
923};
924
925/* l4_abe -> dmic */
926static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
927 .master = &omap44xx_l4_abe_hwmod,
928 .slave = &omap44xx_dmic_hwmod,
929 .clk = "ocp_abe_iclk",
930 .addr = omap44xx_dmic_addrs,
931 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
932 .user = OCP_USER_MPU,
933};
934
935static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
936 {
937 .pa_start = 0x4902e000,
938 .pa_end = 0x4902e07f,
939 .flags = ADDR_TYPE_RT
940 },
941};
942
943/* l4_abe -> dmic (dma) */
944static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
945 .master = &omap44xx_l4_abe_hwmod,
946 .slave = &omap44xx_dmic_hwmod,
947 .clk = "ocp_abe_iclk",
948 .addr = omap44xx_dmic_dma_addrs,
949 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
950 .user = OCP_USER_SDMA,
951};
952
953/* dmic slave ports */
954static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
955 &omap44xx_l4_abe__dmic,
956 &omap44xx_l4_abe__dmic_dma,
957};
958
959static struct omap_hwmod omap44xx_dmic_hwmod = {
960 .name = "dmic",
961 .class = &omap44xx_dmic_hwmod_class,
962 .mpu_irqs = omap44xx_dmic_irqs,
963 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
964 .sdma_reqs = omap44xx_dmic_sdma_reqs,
965 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
966 .main_clk = "dmic_fck",
967 .prcm = {
968 .omap4 = {
969 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
970 },
971 },
972 .slaves = omap44xx_dmic_slaves,
973 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
974 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
975};
976
8f25bdc5
BC		 977/*
978 * 'dsp' class
979 * dsp sub-system
980 */
981
982static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 983 .name = "dsp",
8f25bdc5
BC		 984};
985
986/* dsp */
987static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
988 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
989};
990
991static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
992 { .name = "mmu_cache", .rst_shift = 1 },
993};
994
995static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
996 { .name = "dsp", .rst_shift = 0 },
997};
998
999/* dsp -> iva */
1000static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1001 .master = &omap44xx_dsp_hwmod,
1002 .slave = &omap44xx_iva_hwmod,
1003 .clk = "dpll_iva_m5x2_ck",
1004};
1005
1006/* dsp master ports */
1007static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1008 &omap44xx_dsp__l3_main_1,
1009 &omap44xx_dsp__l4_abe,
1010 &omap44xx_dsp__iva,
1011};
1012
1013/* l4_cfg -> dsp */
1014static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1015 .master = &omap44xx_l4_cfg_hwmod,
1016 .slave = &omap44xx_dsp_hwmod,
1017 .clk = "l4_div_ck",
1018 .user = OCP_USER_MPU | OCP_USER_SDMA,
1019};
1020
1021/* dsp slave ports */
1022static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1023 &omap44xx_l4_cfg__dsp,
1024};
1025
1026/* Pseudo hwmod for reset control purpose only */
1027static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1028 .name = "dsp_c0",
1029 .class = &omap44xx_dsp_hwmod_class,
1030 .flags = HWMOD_INIT_NO_RESET,
1031 .rst_lines = omap44xx_dsp_c0_resets,
1032 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1033 .prcm = {
1034 .omap4 = {
1035 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1036 },
1037 },
1038 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1039};
1040
1041static struct omap_hwmod omap44xx_dsp_hwmod = {
1042 .name = "dsp",
1043 .class = &omap44xx_dsp_hwmod_class,
1044 .mpu_irqs = omap44xx_dsp_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
1046 .rst_lines = omap44xx_dsp_resets,
1047 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1048 .main_clk = "dsp_fck",
1049 .prcm = {
1050 .omap4 = {
1051 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1052 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1053 },
1054 },
1055 .slaves = omap44xx_dsp_slaves,
1056 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1057 .masters = omap44xx_dsp_masters,
1058 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1059 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1060};
1061
d63bd74f
BC		 1062/*
1063 * 'dss' class
1064 * display sub-system
1065 */
1066
1067static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1068 .rev_offs = 0x0000,
1069 .syss_offs = 0x0014,
1070 .sysc_flags = SYSS_HAS_RESET_STATUS,
1071};
1072
1073static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1074 .name = "dss",
1075 .sysc = &omap44xx_dss_sysc,
1076};
1077
1078/* dss */
1079/* dss master ports */
1080static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1081 &omap44xx_dss__l3_main_1,
1082};
1083
1084static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1085 {
1086 .pa_start = 0x58000000,
1087 .pa_end = 0x5800007f,
1088 .flags = ADDR_TYPE_RT
1089 },
1090};
1091
1092/* l3_main_2 -> dss */
1093static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1094 .master = &omap44xx_l3_main_2_hwmod,
1095 .slave = &omap44xx_dss_hwmod,
1096 .clk = "l3_div_ck",
1097 .addr = omap44xx_dss_dma_addrs,
1098 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1099 .user = OCP_USER_SDMA,
1100};
1101
1102static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1103 {
1104 .pa_start = 0x48040000,
1105 .pa_end = 0x4804007f,
1106 .flags = ADDR_TYPE_RT
1107 },
1108};
1109
1110/* l4_per -> dss */
1111static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1112 .master = &omap44xx_l4_per_hwmod,
1113 .slave = &omap44xx_dss_hwmod,
1114 .clk = "l4_div_ck",
1115 .addr = omap44xx_dss_addrs,
1116 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
1117 .user = OCP_USER_MPU,
1118};
1119
1120/* dss slave ports */
1121static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1122 &omap44xx_l3_main_2__dss,
1123 &omap44xx_l4_per__dss,
1124};
1125
1126static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1127 { .role = "sys_clk", .clk = "dss_sys_clk" },
1128 { .role = "tv_clk", .clk = "dss_tv_clk" },
1129 { .role = "dss_clk", .clk = "dss_dss_clk" },
1130 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1131};
1132
1133static struct omap_hwmod omap44xx_dss_hwmod = {
1134 .name = "dss_core",
1135 .class = &omap44xx_dss_hwmod_class,
1136 .main_clk = "dss_fck",
1137 .prcm = {
1138 .omap4 = {
1139 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1140 },
1141 },
1142 .opt_clks = dss_opt_clks,
1143 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1144 .slaves = omap44xx_dss_slaves,
1145 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1146 .masters = omap44xx_dss_masters,
1147 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1148 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1149};
1150
1151/*
1152 * 'dispc' class
1153 * display controller
1154 */
1155
1156static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1157 .rev_offs = 0x0000,
1158 .sysc_offs = 0x0010,
1159 .syss_offs = 0x0014,
1160 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1162 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1163 SYSS_HAS_RESET_STATUS),
1164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1165 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1166 .sysc_fields = &omap_hwmod_sysc_type1,
1167};
1168
1169static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1170 .name = "dispc",
1171 .sysc = &omap44xx_dispc_sysc,
1172};
1173
1174/* dss_dispc */
1175static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1176static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1177 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1178};
1179
1180static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1181 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1182};
1183
1184static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1185 {
1186 .pa_start = 0x58001000,
1187 .pa_end = 0x58001fff,
1188 .flags = ADDR_TYPE_RT
1189 },
1190};
1191
1192/* l3_main_2 -> dss_dispc */
1193static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1194 .master = &omap44xx_l3_main_2_hwmod,
1195 .slave = &omap44xx_dss_dispc_hwmod,
1196 .clk = "l3_div_ck",
1197 .addr = omap44xx_dss_dispc_dma_addrs,
1198 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1199 .user = OCP_USER_SDMA,
1200};
1201
1202static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1203 {
1204 .pa_start = 0x48041000,
1205 .pa_end = 0x48041fff,
1206 .flags = ADDR_TYPE_RT
1207 },
1208};
1209
1210/* l4_per -> dss_dispc */
1211static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1212 .master = &omap44xx_l4_per_hwmod,
1213 .slave = &omap44xx_dss_dispc_hwmod,
1214 .clk = "l4_div_ck",
1215 .addr = omap44xx_dss_dispc_addrs,
1216 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1217 .user = OCP_USER_MPU,
1218};
1219
1220/* dss_dispc slave ports */
1221static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1222 &omap44xx_l3_main_2__dss_dispc,
1223 &omap44xx_l4_per__dss_dispc,
1224};
1225
1226static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1227 .name = "dss_dispc",
1228 .class = &omap44xx_dispc_hwmod_class,
1229 .mpu_irqs = omap44xx_dss_dispc_irqs,
1230 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1231 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1232 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1233 .main_clk = "dss_fck",
1234 .prcm = {
1235 .omap4 = {
1236 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1237 },
1238 },
1239 .slaves = omap44xx_dss_dispc_slaves,
1240 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1241 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1242};
1243
1244/*
1245 * 'dsi' class
1246 * display serial interface controller
1247 */
1248
1249static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1250 .rev_offs = 0x0000,
1251 .sysc_offs = 0x0010,
1252 .syss_offs = 0x0014,
1253 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1254 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1255 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1256 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1257 .sysc_fields = &omap_hwmod_sysc_type1,
1258};
1259
1260static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1261 .name = "dsi",
1262 .sysc = &omap44xx_dsi_sysc,
1263};
1264
1265/* dss_dsi1 */
1266static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1267static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1268 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1269};
1270
1271static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1272 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1273};
1274
1275static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1276 {
1277 .pa_start = 0x58004000,
1278 .pa_end = 0x580041ff,
1279 .flags = ADDR_TYPE_RT
1280 },
1281};
1282
1283/* l3_main_2 -> dss_dsi1 */
1284static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1285 .master = &omap44xx_l3_main_2_hwmod,
1286 .slave = &omap44xx_dss_dsi1_hwmod,
1287 .clk = "l3_div_ck",
1288 .addr = omap44xx_dss_dsi1_dma_addrs,
1289 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1290 .user = OCP_USER_SDMA,
1291};
1292
1293static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1294 {
1295 .pa_start = 0x48044000,
1296 .pa_end = 0x480441ff,
1297 .flags = ADDR_TYPE_RT
1298 },
1299};
1300
1301/* l4_per -> dss_dsi1 */
1302static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1303 .master = &omap44xx_l4_per_hwmod,
1304 .slave = &omap44xx_dss_dsi1_hwmod,
1305 .clk = "l4_div_ck",
1306 .addr = omap44xx_dss_dsi1_addrs,
1307 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1308 .user = OCP_USER_MPU,
1309};
1310
1311/* dss_dsi1 slave ports */
1312static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1313 &omap44xx_l3_main_2__dss_dsi1,
1314 &omap44xx_l4_per__dss_dsi1,
1315};
1316
1317static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1318 .name = "dss_dsi1",
1319 .class = &omap44xx_dsi_hwmod_class,
1320 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1321 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1322 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1323 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1324 .main_clk = "dss_fck",
1325 .prcm = {
1326 .omap4 = {
1327 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1328 },
1329 },
1330 .slaves = omap44xx_dss_dsi1_slaves,
1331 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1332 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1333};
1334
1335/* dss_dsi2 */
1336static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1337static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1338 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1339};
1340
1341static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1342 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1343};
1344
1345static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1346 {
1347 .pa_start = 0x58005000,
1348 .pa_end = 0x580051ff,
1349 .flags = ADDR_TYPE_RT
1350 },
1351};
1352
1353/* l3_main_2 -> dss_dsi2 */
1354static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1355 .master = &omap44xx_l3_main_2_hwmod,
1356 .slave = &omap44xx_dss_dsi2_hwmod,
1357 .clk = "l3_div_ck",
1358 .addr = omap44xx_dss_dsi2_dma_addrs,
1359 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1360 .user = OCP_USER_SDMA,
1361};
1362
1363static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1364 {
1365 .pa_start = 0x48045000,
1366 .pa_end = 0x480451ff,
1367 .flags = ADDR_TYPE_RT
1368 },
1369};
1370
1371/* l4_per -> dss_dsi2 */
1372static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1373 .master = &omap44xx_l4_per_hwmod,
1374 .slave = &omap44xx_dss_dsi2_hwmod,
1375 .clk = "l4_div_ck",
1376 .addr = omap44xx_dss_dsi2_addrs,
1377 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1378 .user = OCP_USER_MPU,
1379};
1380
1381/* dss_dsi2 slave ports */
1382static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1383 &omap44xx_l3_main_2__dss_dsi2,
1384 &omap44xx_l4_per__dss_dsi2,
1385};
1386
1387static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1388 .name = "dss_dsi2",
1389 .class = &omap44xx_dsi_hwmod_class,
1390 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1391 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1392 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1393 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1394 .main_clk = "dss_fck",
1395 .prcm = {
1396 .omap4 = {
1397 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1398 },
1399 },
1400 .slaves = omap44xx_dss_dsi2_slaves,
1401 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1402 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1403};
1404
1405/*
1406 * 'hdmi' class
1407 * hdmi controller
1408 */
1409
1410static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1411 .rev_offs = 0x0000,
1412 .sysc_offs = 0x0010,
1413 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1414 SYSC_HAS_SOFTRESET),
1415 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1416 SIDLE_SMART_WKUP),
1417 .sysc_fields = &omap_hwmod_sysc_type2,
1418};
1419
1420static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1421 .name = "hdmi",
1422 .sysc = &omap44xx_hdmi_sysc,
1423};
1424
1425/* dss_hdmi */
1426static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1427static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1428 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1429};
1430
1431static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1432 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1433};
1434
1435static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1436 {
1437 .pa_start = 0x58006000,
1438 .pa_end = 0x58006fff,
1439 .flags = ADDR_TYPE_RT
1440 },
1441};
1442
1443/* l3_main_2 -> dss_hdmi */
1444static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1445 .master = &omap44xx_l3_main_2_hwmod,
1446 .slave = &omap44xx_dss_hdmi_hwmod,
1447 .clk = "l3_div_ck",
1448 .addr = omap44xx_dss_hdmi_dma_addrs,
1449 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1450 .user = OCP_USER_SDMA,
1451};
1452
1453static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1454 {
1455 .pa_start = 0x48046000,
1456 .pa_end = 0x48046fff,
1457 .flags = ADDR_TYPE_RT
1458 },
1459};
1460
1461/* l4_per -> dss_hdmi */
1462static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1463 .master = &omap44xx_l4_per_hwmod,
1464 .slave = &omap44xx_dss_hdmi_hwmod,
1465 .clk = "l4_div_ck",
1466 .addr = omap44xx_dss_hdmi_addrs,
1467 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1468 .user = OCP_USER_MPU,
1469};
1470
1471/* dss_hdmi slave ports */
1472static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1473 &omap44xx_l3_main_2__dss_hdmi,
1474 &omap44xx_l4_per__dss_hdmi,
1475};
1476
1477static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1478 .name = "dss_hdmi",
1479 .class = &omap44xx_hdmi_hwmod_class,
1480 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1481 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1482 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1483 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1484 .main_clk = "dss_fck",
1485 .prcm = {
1486 .omap4 = {
1487 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1488 },
1489 },
1490 .slaves = omap44xx_dss_hdmi_slaves,
1491 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1493};
1494
1495/*
1496 * 'rfbi' class
1497 * remote frame buffer interface
1498 */
1499
1500static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1501 .rev_offs = 0x0000,
1502 .sysc_offs = 0x0010,
1503 .syss_offs = 0x0014,
1504 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1505 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1506 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1507 .sysc_fields = &omap_hwmod_sysc_type1,
1508};
1509
1510static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1511 .name = "rfbi",
1512 .sysc = &omap44xx_rfbi_sysc,
1513};
1514
1515/* dss_rfbi */
1516static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1517static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1518 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1519};
1520
1521static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1522 {
1523 .pa_start = 0x58002000,
1524 .pa_end = 0x580020ff,
1525 .flags = ADDR_TYPE_RT
1526 },
1527};
1528
1529/* l3_main_2 -> dss_rfbi */
1530static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1531 .master = &omap44xx_l3_main_2_hwmod,
1532 .slave = &omap44xx_dss_rfbi_hwmod,
1533 .clk = "l3_div_ck",
1534 .addr = omap44xx_dss_rfbi_dma_addrs,
1535 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1536 .user = OCP_USER_SDMA,
1537};
1538
1539static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1540 {
1541 .pa_start = 0x48042000,
1542 .pa_end = 0x480420ff,
1543 .flags = ADDR_TYPE_RT
1544 },
1545};
1546
1547/* l4_per -> dss_rfbi */
1548static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1549 .master = &omap44xx_l4_per_hwmod,
1550 .slave = &omap44xx_dss_rfbi_hwmod,
1551 .clk = "l4_div_ck",
1552 .addr = omap44xx_dss_rfbi_addrs,
1553 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1554 .user = OCP_USER_MPU,
1555};
1556
1557/* dss_rfbi slave ports */
1558static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1559 &omap44xx_l3_main_2__dss_rfbi,
1560 &omap44xx_l4_per__dss_rfbi,
1561};
1562
1563static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1564 .name = "dss_rfbi",
1565 .class = &omap44xx_rfbi_hwmod_class,
1566 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1567 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1568 .main_clk = "dss_fck",
1569 .prcm = {
1570 .omap4 = {
1571 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1572 },
1573 },
1574 .slaves = omap44xx_dss_rfbi_slaves,
1575 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1577};
1578
1579/*
1580 * 'venc' class
1581 * video encoder
1582 */
1583
1584static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1585 .name = "venc",
1586};
1587
1588/* dss_venc */
1589static struct omap_hwmod omap44xx_dss_venc_hwmod;
1590static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1591 {
1592 .pa_start = 0x58003000,
1593 .pa_end = 0x580030ff,
1594 .flags = ADDR_TYPE_RT
1595 },
1596};
1597
1598/* l3_main_2 -> dss_venc */
1599static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1600 .master = &omap44xx_l3_main_2_hwmod,
1601 .slave = &omap44xx_dss_venc_hwmod,
1602 .clk = "l3_div_ck",
1603 .addr = omap44xx_dss_venc_dma_addrs,
1604 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1605 .user = OCP_USER_SDMA,
1606};
1607
1608static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1609 {
1610 .pa_start = 0x48043000,
1611 .pa_end = 0x480430ff,
1612 .flags = ADDR_TYPE_RT
1613 },
1614};
1615
1616/* l4_per -> dss_venc */
1617static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1618 .master = &omap44xx_l4_per_hwmod,
1619 .slave = &omap44xx_dss_venc_hwmod,
1620 .clk = "l4_div_ck",
1621 .addr = omap44xx_dss_venc_addrs,
1622 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1623 .user = OCP_USER_MPU,
1624};
1625
1626/* dss_venc slave ports */
1627static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1628 &omap44xx_l3_main_2__dss_venc,
1629 &omap44xx_l4_per__dss_venc,
1630};
1631
1632static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1633 .name = "dss_venc",
1634 .class = &omap44xx_venc_hwmod_class,
1635 .main_clk = "dss_fck",
1636 .prcm = {
1637 .omap4 = {
1638 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1639 },
1640 },
1641 .slaves = omap44xx_dss_venc_slaves,
1642 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1643 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1644};
1645
3b54baad
BC		 1646/*
1647 * 'gpio' class
1648 * general purpose io module
1649 */
1650
1651static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1652 .rev_offs = 0x0000,
f776471f 1653 .sysc_offs = 0x0010,
3b54baad 1654 .syss_offs = 0x0114,
0cfe8751
BC		 1655 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1656 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1657 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1658 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1659 SIDLE_SMART_WKUP),
f776471f
BC		 1660 .sysc_fields = &omap_hwmod_sysc_type1,
1661};
1662
3b54baad 1663static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 1664 .name = "gpio",
1665 .sysc = &omap44xx_gpio_sysc,
1666 .rev = 2,
f776471f
BC		 1667};
1668
3b54baad
BC		 1669/* gpio dev_attr */
1670static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 1671 .bank_width = 32,
1672 .dbck_flag = true,
f776471f
BC		 1673};
1674
3b54baad
BC		 1675/* gpio1 */
1676static struct omap_hwmod omap44xx_gpio1_hwmod;
1677static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1678 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1679};
1680
3b54baad 1681static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 1682 {
3b54baad
BC		 1683 .pa_start = 0x4a310000,
1684 .pa_end = 0x4a3101ff,
f776471f
BC		 1685 .flags = ADDR_TYPE_RT
1686 },
1687};
1688
3b54baad
BC		 1689/* l4_wkup -> gpio1 */
1690static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1691 .master = &omap44xx_l4_wkup_hwmod,
1692 .slave = &omap44xx_gpio1_hwmod,
b399bca8 1693 .clk = "l4_wkup_clk_mux_ck",
3b54baad
BC		 1694 .addr = omap44xx_gpio1_addrs,
1695 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
f776471f
BC		 1696 .user = OCP_USER_MPU | OCP_USER_SDMA,
1697};
1698
3b54baad
BC		 1699/* gpio1 slave ports */
1700static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1701 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 1702};
1703
3b54baad 1704static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 1705 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 1706};
1707
1708static struct omap_hwmod omap44xx_gpio1_hwmod = {
1709 .name = "gpio1",
1710 .class = &omap44xx_gpio_hwmod_class,
1711 .mpu_irqs = omap44xx_gpio1_irqs,
1712 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1713 .main_clk = "gpio1_ick",
f776471f
BC		 1714 .prcm = {
1715 .omap4 = {
3b54baad 1716 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
f776471f
BC		 1717 },
1718 },
3b54baad
BC		 1719 .opt_clks = gpio1_opt_clks,
1720 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1721 .dev_attr = &gpio_dev_attr,
1722 .slaves = omap44xx_gpio1_slaves,
1723 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 1724 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1725};
1726
3b54baad
BC		 1727/* gpio2 */
1728static struct omap_hwmod omap44xx_gpio2_hwmod;
1729static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1730 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1731};
1732
3b54baad 1733static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 1734 {
3b54baad
BC		 1735 .pa_start = 0x48055000,
1736 .pa_end = 0x480551ff,
f776471f
BC		 1737 .flags = ADDR_TYPE_RT
1738 },
1739};
1740
3b54baad
BC		 1741/* l4_per -> gpio2 */
1742static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 1743 .master = &omap44xx_l4_per_hwmod,
3b54baad 1744 .slave = &omap44xx_gpio2_hwmod,
b399bca8 1745 .clk = "l4_div_ck",
3b54baad
BC		 1746 .addr = omap44xx_gpio2_addrs,
1747 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
f776471f
BC		 1748 .user = OCP_USER_MPU | OCP_USER_SDMA,
1749};
1750
3b54baad
BC		 1751/* gpio2 slave ports */
1752static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1753 &omap44xx_l4_per__gpio2,
f776471f
BC		 1754};
1755
3b54baad 1756static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 1757 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 1758};
1759
1760static struct omap_hwmod omap44xx_gpio2_hwmod = {
1761 .name = "gpio2",
1762 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1763 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1764 .mpu_irqs = omap44xx_gpio2_irqs,
1765 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1766 .main_clk = "gpio2_ick",
f776471f
BC		 1767 .prcm = {
1768 .omap4 = {
3b54baad 1769 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
f776471f
BC		 1770 },
1771 },
3b54baad
BC		 1772 .opt_clks = gpio2_opt_clks,
1773 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1774 .dev_attr = &gpio_dev_attr,
1775 .slaves = omap44xx_gpio2_slaves,
1776 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 1777 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1778};
1779
3b54baad
BC		 1780/* gpio3 */
1781static struct omap_hwmod omap44xx_gpio3_hwmod;
1782static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1783 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1784};
1785
3b54baad 1786static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 1787 {
3b54baad
BC		 1788 .pa_start = 0x48057000,
1789 .pa_end = 0x480571ff,
f776471f
BC		 1790 .flags = ADDR_TYPE_RT
1791 },
1792};
1793
3b54baad
BC		 1794/* l4_per -> gpio3 */
1795static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 1796 .master = &omap44xx_l4_per_hwmod,
3b54baad 1797 .slave = &omap44xx_gpio3_hwmod,
b399bca8 1798 .clk = "l4_div_ck",
3b54baad
BC		 1799 .addr = omap44xx_gpio3_addrs,
1800 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
f776471f
BC		 1801 .user = OCP_USER_MPU | OCP_USER_SDMA,
1802};
1803
3b54baad
BC		 1804/* gpio3 slave ports */
1805static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1806 &omap44xx_l4_per__gpio3,
f776471f
BC		 1807};
1808
3b54baad 1809static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 1810 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 1811};
1812
1813static struct omap_hwmod omap44xx_gpio3_hwmod = {
1814 .name = "gpio3",
1815 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1816 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1817 .mpu_irqs = omap44xx_gpio3_irqs,
1818 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
1819 .main_clk = "gpio3_ick",
f776471f
BC		 1820 .prcm = {
1821 .omap4 = {
3b54baad 1822 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
f776471f
BC		 1823 },
1824 },
3b54baad
BC		 1825 .opt_clks = gpio3_opt_clks,
1826 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1827 .dev_attr = &gpio_dev_attr,
1828 .slaves = omap44xx_gpio3_slaves,
1829 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 1830 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1831};
1832
3b54baad
BC		 1833/* gpio4 */
1834static struct omap_hwmod omap44xx_gpio4_hwmod;
1835static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1836 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1837};
1838
3b54baad 1839static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 1840 {
3b54baad
BC		 1841 .pa_start = 0x48059000,
1842 .pa_end = 0x480591ff,
f776471f
BC		 1843 .flags = ADDR_TYPE_RT
1844 },
1845};
1846
3b54baad
BC		 1847/* l4_per -> gpio4 */
1848static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 1849 .master = &omap44xx_l4_per_hwmod,
3b54baad 1850 .slave = &omap44xx_gpio4_hwmod,
b399bca8 1851 .clk = "l4_div_ck",
3b54baad
BC		 1852 .addr = omap44xx_gpio4_addrs,
1853 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
f776471f
BC		 1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855};
1856
3b54baad
BC		 1857/* gpio4 slave ports */
1858static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1859 &omap44xx_l4_per__gpio4,
f776471f
BC		 1860};
1861
3b54baad 1862static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 1863 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 1864};
1865
1866static struct omap_hwmod omap44xx_gpio4_hwmod = {
1867 .name = "gpio4",
1868 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1869 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1870 .mpu_irqs = omap44xx_gpio4_irqs,
1871 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1872 .main_clk = "gpio4_ick",
f776471f
BC		 1873 .prcm = {
1874 .omap4 = {
3b54baad 1875 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
f776471f
BC		 1876 },
1877 },
3b54baad
BC		 1878 .opt_clks = gpio4_opt_clks,
1879 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1880 .dev_attr = &gpio_dev_attr,
1881 .slaves = omap44xx_gpio4_slaves,
1882 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 1883 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1884};
1885
3b54baad
BC		 1886/* gpio5 */
1887static struct omap_hwmod omap44xx_gpio5_hwmod;
1888static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1889 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
55d2cb08
BC		 1890};
1891
3b54baad
BC		 1892static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1893 {
1894 .pa_start = 0x4805b000,
1895 .pa_end = 0x4805b1ff,
1896 .flags = ADDR_TYPE_RT
1897 },
55d2cb08
BC		 1898};
1899
3b54baad
BC		 1900/* l4_per -> gpio5 */
1901static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1902 .master = &omap44xx_l4_per_hwmod,
1903 .slave = &omap44xx_gpio5_hwmod,
b399bca8 1904 .clk = "l4_div_ck",
3b54baad
BC		 1905 .addr = omap44xx_gpio5_addrs,
1906 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1907 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 1908};
1909
3b54baad
BC		 1910/* gpio5 slave ports */
1911static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1912 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 1913};
1914
3b54baad 1915static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 1916 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 1917};
1918
3b54baad
BC		 1919static struct omap_hwmod omap44xx_gpio5_hwmod = {
1920 .name = "gpio5",
1921 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1922 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1923 .mpu_irqs = omap44xx_gpio5_irqs,
1924 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1925 .main_clk = "gpio5_ick",
55d2cb08
BC		 1926 .prcm = {
1927 .omap4 = {
3b54baad 1928 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
55d2cb08
BC		 1929 },
1930 },
3b54baad
BC		 1931 .opt_clks = gpio5_opt_clks,
1932 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1933 .dev_attr = &gpio_dev_attr,
1934 .slaves = omap44xx_gpio5_slaves,
1935 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 1936 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1937};
1938
3b54baad
BC		 1939/* gpio6 */
1940static struct omap_hwmod omap44xx_gpio6_hwmod;
1941static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1942 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 1943};
1944
3b54baad 1945static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 1946 {
3b54baad
BC		 1947 .pa_start = 0x4805d000,
1948 .pa_end = 0x4805d1ff,
92b18d1c
BC		 1949 .flags = ADDR_TYPE_RT
1950 },
1951};
1952
3b54baad
BC		 1953/* l4_per -> gpio6 */
1954static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1955 .master = &omap44xx_l4_per_hwmod,
1956 .slave = &omap44xx_gpio6_hwmod,
b399bca8 1957 .clk = "l4_div_ck",
3b54baad
BC		 1958 .addr = omap44xx_gpio6_addrs,
1959 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
1960 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 1961};
1962
3b54baad
BC		 1963/* gpio6 slave ports */
1964static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1965 &omap44xx_l4_per__gpio6,
db12ba53
BC		 1966};
1967
3b54baad 1968static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 1969 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 1970};
1971
3b54baad
BC		 1972static struct omap_hwmod omap44xx_gpio6_hwmod = {
1973 .name = "gpio6",
1974 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1975 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1976 .mpu_irqs = omap44xx_gpio6_irqs,
1977 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
1978 .main_clk = "gpio6_ick",
1979 .prcm = {
1980 .omap4 = {
1981 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1982 },
db12ba53 1983 },
3b54baad
BC		 1984 .opt_clks = gpio6_opt_clks,
1985 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1986 .dev_attr = &gpio_dev_attr,
1987 .slaves = omap44xx_gpio6_slaves,
1988 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1989 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 1990};
1991
407a6888
BC		 1992/*
1993 * 'hsi' class
1994 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1995 * serial if)
1996 */
1997
1998static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1999 .rev_offs = 0x0000,
2000 .sysc_offs = 0x0010,
2001 .syss_offs = 0x0014,
2002 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2003 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2004 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2005 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2006 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2007 MSTANDBY_SMART),
2008 .sysc_fields = &omap_hwmod_sysc_type1,
2009};
2010
2011static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2012 .name = "hsi",
2013 .sysc = &omap44xx_hsi_sysc,
2014};
2015
2016/* hsi */
2017static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2018 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2019 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2020 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2021};
2022
2023/* hsi master ports */
2024static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2025 &omap44xx_hsi__l3_main_2,
2026};
2027
2028static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2029 {
2030 .pa_start = 0x4a058000,
2031 .pa_end = 0x4a05bfff,
2032 .flags = ADDR_TYPE_RT
2033 },
2034};
2035
2036/* l4_cfg -> hsi */
2037static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2038 .master = &omap44xx_l4_cfg_hwmod,
2039 .slave = &omap44xx_hsi_hwmod,
2040 .clk = "l4_div_ck",
2041 .addr = omap44xx_hsi_addrs,
2042 .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
2043 .user = OCP_USER_MPU | OCP_USER_SDMA,
2044};
2045
2046/* hsi slave ports */
2047static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2048 &omap44xx_l4_cfg__hsi,
2049};
2050
2051static struct omap_hwmod omap44xx_hsi_hwmod = {
2052 .name = "hsi",
2053 .class = &omap44xx_hsi_hwmod_class,
2054 .mpu_irqs = omap44xx_hsi_irqs,
2055 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
2056 .main_clk = "hsi_fck",
2057 .prcm = {
2058 .omap4 = {
2059 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2060 },
2061 },
2062 .slaves = omap44xx_hsi_slaves,
2063 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2064 .masters = omap44xx_hsi_masters,
2065 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2066 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2067};
2068
3b54baad
BC		 2069/*
2070 * 'i2c' class
2071 * multimaster high-speed i2c controller
2072 */
db12ba53 2073
3b54baad
BC		 2074static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2075 .sysc_offs = 0x0010,
2076 .syss_offs = 0x0090,
2077 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2078 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 2079 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2080 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2081 SIDLE_SMART_WKUP),
3b54baad 2082 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 2083};
2084
3b54baad 2085static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 2086 .name = "i2c",
2087 .sysc = &omap44xx_i2c_sysc,
db12ba53
BC		 2088};
2089
3b54baad
BC		 2090/* i2c1 */
2091static struct omap_hwmod omap44xx_i2c1_hwmod;
2092static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2093 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 2094};
2095
3b54baad
BC		 2096static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2097 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2098 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 2099};
2100
3b54baad 2101static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 2102 {
3b54baad
BC		 2103 .pa_start = 0x48070000,
2104 .pa_end = 0x480700ff,
db12ba53
BC		 2105 .flags = ADDR_TYPE_RT
2106 },
2107};
2108
3b54baad
BC		 2109/* l4_per -> i2c1 */
2110static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2111 .master = &omap44xx_l4_per_hwmod,
2112 .slave = &omap44xx_i2c1_hwmod,
2113 .clk = "l4_div_ck",
2114 .addr = omap44xx_i2c1_addrs,
2115 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
92b18d1c
BC		 2116 .user = OCP_USER_MPU | OCP_USER_SDMA,
2117};
2118
3b54baad
BC		 2119/* i2c1 slave ports */
2120static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2121 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 2122};
2123
3b54baad
BC		 2124static struct omap_hwmod omap44xx_i2c1_hwmod = {
2125 .name = "i2c1",
2126 .class = &omap44xx_i2c_hwmod_class,
2127 .flags = HWMOD_INIT_NO_RESET,
2128 .mpu_irqs = omap44xx_i2c1_irqs,
2129 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
2130 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2131 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2132 .main_clk = "i2c1_fck",
92b18d1c
BC		 2133 .prcm = {
2134 .omap4 = {
3b54baad 2135 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
92b18d1c
BC		 2136 },
2137 },
3b54baad
BC		 2138 .slaves = omap44xx_i2c1_slaves,
2139 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
92b18d1c
BC		 2140 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2141};
2142
3b54baad
BC		 2143/* i2c2 */
2144static struct omap_hwmod omap44xx_i2c2_hwmod;
2145static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2146 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 2147};
2148
3b54baad
BC		 2149static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2150 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2151 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2152};
2153
2154static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 2155 {
3b54baad
BC		 2156 .pa_start = 0x48072000,
2157 .pa_end = 0x480720ff,
92b18d1c
BC		 2158 .flags = ADDR_TYPE_RT
2159 },
2160};
2161
3b54baad
BC		 2162/* l4_per -> i2c2 */
2163static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 2164 .master = &omap44xx_l4_per_hwmod,
3b54baad 2165 .slave = &omap44xx_i2c2_hwmod,
db12ba53 2166 .clk = "l4_div_ck",
3b54baad
BC		 2167 .addr = omap44xx_i2c2_addrs,
2168 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
db12ba53
BC		 2169 .user = OCP_USER_MPU | OCP_USER_SDMA,
2170};
2171
3b54baad
BC		 2172/* i2c2 slave ports */
2173static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2174 &omap44xx_l4_per__i2c2,
db12ba53
BC		 2175};
2176
3b54baad
BC		 2177static struct omap_hwmod omap44xx_i2c2_hwmod = {
2178 .name = "i2c2",
2179 .class = &omap44xx_i2c_hwmod_class,
2180 .flags = HWMOD_INIT_NO_RESET,
2181 .mpu_irqs = omap44xx_i2c2_irqs,
2182 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
2183 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2184 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2185 .main_clk = "i2c2_fck",
db12ba53
BC		 2186 .prcm = {
2187 .omap4 = {
3b54baad 2188 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
db12ba53
BC		 2189 },
2190 },
3b54baad
BC		 2191 .slaves = omap44xx_i2c2_slaves,
2192 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
db12ba53
BC		 2193 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2194};
2195
3b54baad
BC		 2196/* i2c3 */
2197static struct omap_hwmod omap44xx_i2c3_hwmod;
2198static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2199 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 2200};
2201
3b54baad
BC		 2202static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2203 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2204 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
92b18d1c
BC		 2205};
2206
3b54baad 2207static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 2208 {
3b54baad
BC		 2209 .pa_start = 0x48060000,
2210 .pa_end = 0x480600ff,
92b18d1c
BC		 2211 .flags = ADDR_TYPE_RT
2212 },
2213};
2214
3b54baad
BC		 2215/* l4_per -> i2c3 */
2216static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 2217 .master = &omap44xx_l4_per_hwmod,
3b54baad 2218 .slave = &omap44xx_i2c3_hwmod,
db12ba53 2219 .clk = "l4_div_ck",
3b54baad
BC		 2220 .addr = omap44xx_i2c3_addrs,
2221 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
db12ba53
BC		 2222 .user = OCP_USER_MPU | OCP_USER_SDMA,
2223};
2224
3b54baad
BC		 2225/* i2c3 slave ports */
2226static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2227 &omap44xx_l4_per__i2c3,
db12ba53
BC		 2228};
2229
3b54baad
BC		 2230static struct omap_hwmod omap44xx_i2c3_hwmod = {
2231 .name = "i2c3",
2232 .class = &omap44xx_i2c_hwmod_class,
2233 .flags = HWMOD_INIT_NO_RESET,
2234 .mpu_irqs = omap44xx_i2c3_irqs,
2235 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
2236 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2237 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2238 .main_clk = "i2c3_fck",
db12ba53
BC		 2239 .prcm = {
2240 .omap4 = {
3b54baad 2241 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
db12ba53
BC		 2242 },
2243 },
3b54baad
BC		 2244 .slaves = omap44xx_i2c3_slaves,
2245 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
db12ba53
BC		 2246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2247};
2248
3b54baad
BC		 2249/* i2c4 */
2250static struct omap_hwmod omap44xx_i2c4_hwmod;
2251static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2252 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 2253};
2254
3b54baad
BC		 2255static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2256 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2257 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 2258};
2259
3b54baad 2260static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 2261 {
3b54baad
BC		 2262 .pa_start = 0x48350000,
2263 .pa_end = 0x483500ff,
db12ba53
BC		 2264 .flags = ADDR_TYPE_RT
2265 },
2266};
2267
3b54baad
BC		 2268/* l4_per -> i2c4 */
2269static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2270 .master = &omap44xx_l4_per_hwmod,
2271 .slave = &omap44xx_i2c4_hwmod,
2272 .clk = "l4_div_ck",
2273 .addr = omap44xx_i2c4_addrs,
2274 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
2275 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 2276};
2277
3b54baad
BC		 2278/* i2c4 slave ports */
2279static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2280 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 2281};
2282
3b54baad
BC		 2283static struct omap_hwmod omap44xx_i2c4_hwmod = {
2284 .name = "i2c4",
2285 .class = &omap44xx_i2c_hwmod_class,
2286 .flags = HWMOD_INIT_NO_RESET,
2287 .mpu_irqs = omap44xx_i2c4_irqs,
2288 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
2289 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2290 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2291 .main_clk = "i2c4_fck",
92b18d1c
BC		 2292 .prcm = {
2293 .omap4 = {
3b54baad 2294 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
92b18d1c
BC		 2295 },
2296 },
3b54baad
BC		 2297 .slaves = omap44xx_i2c4_slaves,
2298 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
92b18d1c
BC		 2299 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2300};
2301
407a6888
BC		 2302/*
2303 * 'ipu' class
2304 * imaging processor unit
2305 */
2306
2307static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2308 .name = "ipu",
2309};
2310
2311/* ipu */
2312static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2313 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2314};
2315
2316static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2317 { .name = "cpu0", .rst_shift = 0 },
2318};
2319
2320static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2321 { .name = "cpu1", .rst_shift = 1 },
2322};
2323
2324static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2325 { .name = "mmu_cache", .rst_shift = 2 },
2326};
2327
2328/* ipu master ports */
2329static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2330 &omap44xx_ipu__l3_main_2,
2331};
2332
2333/* l3_main_2 -> ipu */
2334static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2335 .master = &omap44xx_l3_main_2_hwmod,
2336 .slave = &omap44xx_ipu_hwmod,
2337 .clk = "l3_div_ck",
2338 .user = OCP_USER_MPU | OCP_USER_SDMA,
2339};
2340
2341/* ipu slave ports */
2342static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2343 &omap44xx_l3_main_2__ipu,
2344};
2345
2346/* Pseudo hwmod for reset control purpose only */
2347static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2348 .name = "ipu_c0",
2349 .class = &omap44xx_ipu_hwmod_class,
2350 .flags = HWMOD_INIT_NO_RESET,
2351 .rst_lines = omap44xx_ipu_c0_resets,
2352 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2353 .prcm = {
2354 .omap4 = {
2355 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2356 },
2357 },
2358 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2359};
2360
2361/* Pseudo hwmod for reset control purpose only */
2362static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2363 .name = "ipu_c1",
2364 .class = &omap44xx_ipu_hwmod_class,
2365 .flags = HWMOD_INIT_NO_RESET,
2366 .rst_lines = omap44xx_ipu_c1_resets,
2367 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2368 .prcm = {
2369 .omap4 = {
2370 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2371 },
2372 },
2373 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2374};
2375
2376static struct omap_hwmod omap44xx_ipu_hwmod = {
2377 .name = "ipu",
2378 .class = &omap44xx_ipu_hwmod_class,
2379 .mpu_irqs = omap44xx_ipu_irqs,
2380 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
2381 .rst_lines = omap44xx_ipu_resets,
2382 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2383 .main_clk = "ipu_fck",
2384 .prcm = {
2385 .omap4 = {
2386 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2387 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2388 },
2389 },
2390 .slaves = omap44xx_ipu_slaves,
2391 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2392 .masters = omap44xx_ipu_masters,
2393 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2395};
2396
2397/*
2398 * 'iss' class
2399 * external images sensor pixel data processor
2400 */
2401
2402static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2403 .rev_offs = 0x0000,
2404 .sysc_offs = 0x0010,
2405 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2406 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2408 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2409 MSTANDBY_SMART),
2410 .sysc_fields = &omap_hwmod_sysc_type2,
2411};
2412
2413static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2414 .name = "iss",
2415 .sysc = &omap44xx_iss_sysc,
2416};
2417
2418/* iss */
2419static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2420 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2421};
2422
2423static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2424 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2425 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2426 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2427 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2428};
2429
2430/* iss master ports */
2431static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2432 &omap44xx_iss__l3_main_2,
2433};
2434
2435static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2436 {
2437 .pa_start = 0x52000000,
2438 .pa_end = 0x520000ff,
2439 .flags = ADDR_TYPE_RT
2440 },
2441};
2442
2443/* l3_main_2 -> iss */
2444static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2445 .master = &omap44xx_l3_main_2_hwmod,
2446 .slave = &omap44xx_iss_hwmod,
2447 .clk = "l3_div_ck",
2448 .addr = omap44xx_iss_addrs,
2449 .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
2450 .user = OCP_USER_MPU | OCP_USER_SDMA,
2451};
2452
2453/* iss slave ports */
2454static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2455 &omap44xx_l3_main_2__iss,
2456};
2457
2458static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2459 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2460};
2461
2462static struct omap_hwmod omap44xx_iss_hwmod = {
2463 .name = "iss",
2464 .class = &omap44xx_iss_hwmod_class,
2465 .mpu_irqs = omap44xx_iss_irqs,
2466 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
2467 .sdma_reqs = omap44xx_iss_sdma_reqs,
2468 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2469 .main_clk = "iss_fck",
2470 .prcm = {
2471 .omap4 = {
2472 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2473 },
2474 },
2475 .opt_clks = iss_opt_clks,
2476 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2477 .slaves = omap44xx_iss_slaves,
2478 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2479 .masters = omap44xx_iss_masters,
2480 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2481 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2482};
2483
8f25bdc5
BC		 2484/*
2485 * 'iva' class
2486 * multi-standard video encoder/decoder hardware accelerator
2487 */
2488
2489static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 2490 .name = "iva",
8f25bdc5
BC		 2491};
2492
2493/* iva */
2494static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2495 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2496 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2497 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2498};
2499
2500static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2501 { .name = "logic", .rst_shift = 2 },
2502};
2503
2504static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2505 { .name = "seq0", .rst_shift = 0 },
2506};
2507
2508static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2509 { .name = "seq1", .rst_shift = 1 },
2510};
2511
2512/* iva master ports */
2513static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2514 &omap44xx_iva__l3_main_2,
2515 &omap44xx_iva__l3_instr,
2516};
2517
2518static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2519 {
2520 .pa_start = 0x5a000000,
2521 .pa_end = 0x5a07ffff,
2522 .flags = ADDR_TYPE_RT
2523 },
2524};
2525
2526/* l3_main_2 -> iva */
2527static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2528 .master = &omap44xx_l3_main_2_hwmod,
2529 .slave = &omap44xx_iva_hwmod,
2530 .clk = "l3_div_ck",
2531 .addr = omap44xx_iva_addrs,
2532 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
2533 .user = OCP_USER_MPU,
2534};
2535
2536/* iva slave ports */
2537static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2538 &omap44xx_dsp__iva,
2539 &omap44xx_l3_main_2__iva,
2540};
2541
2542/* Pseudo hwmod for reset control purpose only */
2543static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2544 .name = "iva_seq0",
2545 .class = &omap44xx_iva_hwmod_class,
2546 .flags = HWMOD_INIT_NO_RESET,
2547 .rst_lines = omap44xx_iva_seq0_resets,
2548 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2549 .prcm = {
2550 .omap4 = {
2551 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2552 },
2553 },
2554 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2555};
2556
2557/* Pseudo hwmod for reset control purpose only */
2558static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2559 .name = "iva_seq1",
2560 .class = &omap44xx_iva_hwmod_class,
2561 .flags = HWMOD_INIT_NO_RESET,
2562 .rst_lines = omap44xx_iva_seq1_resets,
2563 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2564 .prcm = {
2565 .omap4 = {
2566 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2567 },
2568 },
2569 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2570};
2571
2572static struct omap_hwmod omap44xx_iva_hwmod = {
2573 .name = "iva",
2574 .class = &omap44xx_iva_hwmod_class,
2575 .mpu_irqs = omap44xx_iva_irqs,
2576 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
2577 .rst_lines = omap44xx_iva_resets,
2578 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2579 .main_clk = "iva_fck",
2580 .prcm = {
2581 .omap4 = {
2582 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2583 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2584 },
2585 },
2586 .slaves = omap44xx_iva_slaves,
2587 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2588 .masters = omap44xx_iva_masters,
2589 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2590 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2591};
2592
407a6888
BC		 2593/*
2594 * 'kbd' class
2595 * keyboard controller
2596 */
2597
2598static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2599 .rev_offs = 0x0000,
2600 .sysc_offs = 0x0010,
2601 .syss_offs = 0x0014,
2602 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2603 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2604 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2605 SYSS_HAS_RESET_STATUS),
2606 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2607 .sysc_fields = &omap_hwmod_sysc_type1,
2608};
2609
2610static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2611 .name = "kbd",
2612 .sysc = &omap44xx_kbd_sysc,
2613};
2614
2615/* kbd */
2616static struct omap_hwmod omap44xx_kbd_hwmod;
2617static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2618 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2619};
2620
2621static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2622 {
2623 .pa_start = 0x4a31c000,
2624 .pa_end = 0x4a31c07f,
2625 .flags = ADDR_TYPE_RT
2626 },
2627};
2628
2629/* l4_wkup -> kbd */
2630static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2631 .master = &omap44xx_l4_wkup_hwmod,
2632 .slave = &omap44xx_kbd_hwmod,
2633 .clk = "l4_wkup_clk_mux_ck",
2634 .addr = omap44xx_kbd_addrs,
2635 .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637};
2638
2639/* kbd slave ports */
2640static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2641 &omap44xx_l4_wkup__kbd,
2642};
2643
2644static struct omap_hwmod omap44xx_kbd_hwmod = {
2645 .name = "kbd",
2646 .class = &omap44xx_kbd_hwmod_class,
2647 .mpu_irqs = omap44xx_kbd_irqs,
2648 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
2649 .main_clk = "kbd_fck",
2650 .prcm = {
2651 .omap4 = {
2652 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2653 },
2654 },
2655 .slaves = omap44xx_kbd_slaves,
2656 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2657 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2658};
2659
ec5df927
BC		 2660/*
2661 * 'mailbox' class
2662 * mailbox module allowing communication between the on-chip processors using a
2663 * queued mailbox-interrupt mechanism.
2664 */
2665
2666static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2667 .rev_offs = 0x0000,
2668 .sysc_offs = 0x0010,
2669 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2670 SYSC_HAS_SOFTRESET),
2671 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2672 .sysc_fields = &omap_hwmod_sysc_type2,
2673};
2674
2675static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2676 .name = "mailbox",
2677 .sysc = &omap44xx_mailbox_sysc,
2678};
2679
2680/* mailbox */
2681static struct omap_hwmod omap44xx_mailbox_hwmod;
2682static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2683 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2684};
2685
2686static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2687 {
2688 .pa_start = 0x4a0f4000,
2689 .pa_end = 0x4a0f41ff,
2690 .flags = ADDR_TYPE_RT
2691 },
2692};
2693
2694/* l4_cfg -> mailbox */
2695static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2696 .master = &omap44xx_l4_cfg_hwmod,
2697 .slave = &omap44xx_mailbox_hwmod,
2698 .clk = "l4_div_ck",
2699 .addr = omap44xx_mailbox_addrs,
2700 .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
2701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2702};
2703
2704/* mailbox slave ports */
2705static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2706 &omap44xx_l4_cfg__mailbox,
2707};
2708
2709static struct omap_hwmod omap44xx_mailbox_hwmod = {
2710 .name = "mailbox",
2711 .class = &omap44xx_mailbox_hwmod_class,
2712 .mpu_irqs = omap44xx_mailbox_irqs,
2713 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
2714 .prcm = {
2715 .omap4 = {
2716 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2717 },
2718 },
2719 .slaves = omap44xx_mailbox_slaves,
2720 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2721 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2722};
2723
4ddff493
BC		 2724/*
2725 * 'mcbsp' class
2726 * multi channel buffered serial port controller
2727 */
2728
2729static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2730 .sysc_offs = 0x008c,
2731 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2732 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2733 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2734 .sysc_fields = &omap_hwmod_sysc_type1,
2735};
2736
2737static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2738 .name = "mcbsp",
2739 .sysc = &omap44xx_mcbsp_sysc,
2740};
2741
2742/* mcbsp1 */
2743static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2744static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2745 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2746};
2747
2748static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2749 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2750 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2751};
2752
2753static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2754 {
2755 .pa_start = 0x40122000,
2756 .pa_end = 0x401220ff,
2757 .flags = ADDR_TYPE_RT
2758 },
2759};
2760
2761/* l4_abe -> mcbsp1 */
2762static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2763 .master = &omap44xx_l4_abe_hwmod,
2764 .slave = &omap44xx_mcbsp1_hwmod,
2765 .clk = "ocp_abe_iclk",
2766 .addr = omap44xx_mcbsp1_addrs,
2767 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2768 .user = OCP_USER_MPU,
2769};
2770
2771static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2772 {
2773 .pa_start = 0x49022000,
2774 .pa_end = 0x490220ff,
2775 .flags = ADDR_TYPE_RT
2776 },
2777};
2778
2779/* l4_abe -> mcbsp1 (dma) */
2780static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2781 .master = &omap44xx_l4_abe_hwmod,
2782 .slave = &omap44xx_mcbsp1_hwmod,
2783 .clk = "ocp_abe_iclk",
2784 .addr = omap44xx_mcbsp1_dma_addrs,
2785 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2786 .user = OCP_USER_SDMA,
2787};
2788
2789/* mcbsp1 slave ports */
2790static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2791 &omap44xx_l4_abe__mcbsp1,
2792 &omap44xx_l4_abe__mcbsp1_dma,
2793};
2794
2795static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2796 .name = "mcbsp1",
2797 .class = &omap44xx_mcbsp_hwmod_class,
2798 .mpu_irqs = omap44xx_mcbsp1_irqs,
2799 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2800 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
2801 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2802 .main_clk = "mcbsp1_fck",
2803 .prcm = {
2804 .omap4 = {
2805 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2806 },
2807 },
2808 .slaves = omap44xx_mcbsp1_slaves,
2809 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2810 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2811};
2812
2813/* mcbsp2 */
2814static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2815static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2816 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2817};
2818
2819static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2820 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2821 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2822};
2823
2824static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2825 {
2826 .pa_start = 0x40124000,
2827 .pa_end = 0x401240ff,
2828 .flags = ADDR_TYPE_RT
2829 },
2830};
2831
2832/* l4_abe -> mcbsp2 */
2833static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2834 .master = &omap44xx_l4_abe_hwmod,
2835 .slave = &omap44xx_mcbsp2_hwmod,
2836 .clk = "ocp_abe_iclk",
2837 .addr = omap44xx_mcbsp2_addrs,
2838 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2839 .user = OCP_USER_MPU,
2840};
2841
2842static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2843 {
2844 .pa_start = 0x49024000,
2845 .pa_end = 0x490240ff,
2846 .flags = ADDR_TYPE_RT
2847 },
2848};
2849
2850/* l4_abe -> mcbsp2 (dma) */
2851static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2852 .master = &omap44xx_l4_abe_hwmod,
2853 .slave = &omap44xx_mcbsp2_hwmod,
2854 .clk = "ocp_abe_iclk",
2855 .addr = omap44xx_mcbsp2_dma_addrs,
2856 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2857 .user = OCP_USER_SDMA,
2858};
2859
2860/* mcbsp2 slave ports */
2861static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2862 &omap44xx_l4_abe__mcbsp2,
2863 &omap44xx_l4_abe__mcbsp2_dma,
2864};
2865
2866static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2867 .name = "mcbsp2",
2868 .class = &omap44xx_mcbsp_hwmod_class,
2869 .mpu_irqs = omap44xx_mcbsp2_irqs,
2870 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2871 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2872 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2873 .main_clk = "mcbsp2_fck",
2874 .prcm = {
2875 .omap4 = {
2876 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2877 },
2878 },
2879 .slaves = omap44xx_mcbsp2_slaves,
2880 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2881 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2882};
2883
2884/* mcbsp3 */
2885static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2886static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2887 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2888};
2889
2890static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2891 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2892 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2893};
2894
2895static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2896 {
2897 .pa_start = 0x40126000,
2898 .pa_end = 0x401260ff,
2899 .flags = ADDR_TYPE_RT
2900 },
2901};
2902
2903/* l4_abe -> mcbsp3 */
2904static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2905 .master = &omap44xx_l4_abe_hwmod,
2906 .slave = &omap44xx_mcbsp3_hwmod,
2907 .clk = "ocp_abe_iclk",
2908 .addr = omap44xx_mcbsp3_addrs,
2909 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2910 .user = OCP_USER_MPU,
2911};
2912
2913static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2914 {
2915 .pa_start = 0x49026000,
2916 .pa_end = 0x490260ff,
2917 .flags = ADDR_TYPE_RT
2918 },
2919};
2920
2921/* l4_abe -> mcbsp3 (dma) */
2922static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2923 .master = &omap44xx_l4_abe_hwmod,
2924 .slave = &omap44xx_mcbsp3_hwmod,
2925 .clk = "ocp_abe_iclk",
2926 .addr = omap44xx_mcbsp3_dma_addrs,
2927 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2928 .user = OCP_USER_SDMA,
2929};
2930
2931/* mcbsp3 slave ports */
2932static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2933 &omap44xx_l4_abe__mcbsp3,
2934 &omap44xx_l4_abe__mcbsp3_dma,
2935};
2936
2937static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2938 .name = "mcbsp3",
2939 .class = &omap44xx_mcbsp_hwmod_class,
2940 .mpu_irqs = omap44xx_mcbsp3_irqs,
2941 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2942 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2943 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2944 .main_clk = "mcbsp3_fck",
2945 .prcm = {
2946 .omap4 = {
2947 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2948 },
2949 },
2950 .slaves = omap44xx_mcbsp3_slaves,
2951 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2952 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2953};
2954
2955/* mcbsp4 */
2956static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2957static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2958 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2959};
2960
2961static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2962 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2963 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2964};
2965
2966static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2967 {
2968 .pa_start = 0x48096000,
2969 .pa_end = 0x480960ff,
2970 .flags = ADDR_TYPE_RT
2971 },
2972};
2973
2974/* l4_per -> mcbsp4 */
2975static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2976 .master = &omap44xx_l4_per_hwmod,
2977 .slave = &omap44xx_mcbsp4_hwmod,
2978 .clk = "l4_div_ck",
2979 .addr = omap44xx_mcbsp4_addrs,
2980 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
2981 .user = OCP_USER_MPU | OCP_USER_SDMA,
2982};
2983
2984/* mcbsp4 slave ports */
2985static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
2986 &omap44xx_l4_per__mcbsp4,
2987};
2988
2989static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2990 .name = "mcbsp4",
2991 .class = &omap44xx_mcbsp_hwmod_class,
2992 .mpu_irqs = omap44xx_mcbsp4_irqs,
2993 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
2994 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2995 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
2996 .main_clk = "mcbsp4_fck",
2997 .prcm = {
2998 .omap4 = {
2999 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3000 },
3001 },
3002 .slaves = omap44xx_mcbsp4_slaves,
3003 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3004 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3005};
3006
407a6888
BC		 3007/*
3008 * 'mcpdm' class
3009 * multi channel pdm controller (proprietary interface with phoenix power
3010 * ic)
3011 */
3012
3013static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3014 .rev_offs = 0x0000,
3015 .sysc_offs = 0x0010,
3016 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3017 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3018 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3019 SIDLE_SMART_WKUP),
3020 .sysc_fields = &omap_hwmod_sysc_type2,
3021};
3022
3023static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3024 .name = "mcpdm",
3025 .sysc = &omap44xx_mcpdm_sysc,
3026};
3027
3028/* mcpdm */
3029static struct omap_hwmod omap44xx_mcpdm_hwmod;
3030static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3031 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3032};
3033
3034static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3035 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3036 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3037};
3038
3039static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3040 {
3041 .pa_start = 0x40132000,
3042 .pa_end = 0x4013207f,
3043 .flags = ADDR_TYPE_RT
3044 },
3045};
3046
3047/* l4_abe -> mcpdm */
3048static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3049 .master = &omap44xx_l4_abe_hwmod,
3050 .slave = &omap44xx_mcpdm_hwmod,
3051 .clk = "ocp_abe_iclk",
3052 .addr = omap44xx_mcpdm_addrs,
3053 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3054 .user = OCP_USER_MPU,
3055};
3056
3057static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3058 {
3059 .pa_start = 0x49032000,
3060 .pa_end = 0x4903207f,
3061 .flags = ADDR_TYPE_RT
3062 },
3063};
3064
3065/* l4_abe -> mcpdm (dma) */
3066static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3067 .master = &omap44xx_l4_abe_hwmod,
3068 .slave = &omap44xx_mcpdm_hwmod,
3069 .clk = "ocp_abe_iclk",
3070 .addr = omap44xx_mcpdm_dma_addrs,
3071 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3072 .user = OCP_USER_SDMA,
3073};
3074
3075/* mcpdm slave ports */
3076static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3077 &omap44xx_l4_abe__mcpdm,
3078 &omap44xx_l4_abe__mcpdm_dma,
3079};
3080
3081static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3082 .name = "mcpdm",
3083 .class = &omap44xx_mcpdm_hwmod_class,
3084 .mpu_irqs = omap44xx_mcpdm_irqs,
3085 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3086 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3087 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3088 .main_clk = "mcpdm_fck",
3089 .prcm = {
3090 .omap4 = {
3091 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3092 },
3093 },
3094 .slaves = omap44xx_mcpdm_slaves,
3095 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3096 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3097};
3098
9bcbd7f0
BC		 3099/*
3100 * 'mcspi' class
3101 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3102 * bus
3103 */
3104
3105static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3106 .rev_offs = 0x0000,
3107 .sysc_offs = 0x0010,
3108 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3109 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3110 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3111 SIDLE_SMART_WKUP),
3112 .sysc_fields = &omap_hwmod_sysc_type2,
3113};
3114
3115static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3116 .name = "mcspi",
3117 .sysc = &omap44xx_mcspi_sysc,
905a74d9 3118 .rev = OMAP4_MCSPI_REV,
9bcbd7f0
BC		 3119};
3120
3121/* mcspi1 */
3122static struct omap_hwmod omap44xx_mcspi1_hwmod;
3123static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3124 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3125};
3126
3127static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3128 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3129 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3130 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3131 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3132 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3133 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3134 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3135 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3136};
3137
3138static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3139 {
3140 .pa_start = 0x48098000,
3141 .pa_end = 0x480981ff,
3142 .flags = ADDR_TYPE_RT
3143 },
3144};
3145
3146/* l4_per -> mcspi1 */
3147static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3148 .master = &omap44xx_l4_per_hwmod,
3149 .slave = &omap44xx_mcspi1_hwmod,
3150 .clk = "l4_div_ck",
3151 .addr = omap44xx_mcspi1_addrs,
3152 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3153 .user = OCP_USER_MPU | OCP_USER_SDMA,
3154};
3155
3156/* mcspi1 slave ports */
3157static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3158 &omap44xx_l4_per__mcspi1,
3159};
3160
905a74d9
BC		 3161/* mcspi1 dev_attr */
3162static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3163 .num_chipselect = 4,
3164};
3165
9bcbd7f0
BC		 3166static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3167 .name = "mcspi1",
3168 .class = &omap44xx_mcspi_hwmod_class,
3169 .mpu_irqs = omap44xx_mcspi1_irqs,
3170 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3171 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3172 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3173 .main_clk = "mcspi1_fck",
3174 .prcm = {
3175 .omap4 = {
3176 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3177 },
3178 },
905a74d9 3179 .dev_attr = &mcspi1_dev_attr,
9bcbd7f0
BC		 3180 .slaves = omap44xx_mcspi1_slaves,
3181 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3183};
3184
3185/* mcspi2 */
3186static struct omap_hwmod omap44xx_mcspi2_hwmod;
3187static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3188 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3189};
3190
3191static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3192 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3193 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3194 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3195 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3196};
3197
3198static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3199 {
3200 .pa_start = 0x4809a000,
3201 .pa_end = 0x4809a1ff,
3202 .flags = ADDR_TYPE_RT
3203 },
3204};
3205
3206/* l4_per -> mcspi2 */
3207static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3208 .master = &omap44xx_l4_per_hwmod,
3209 .slave = &omap44xx_mcspi2_hwmod,
3210 .clk = "l4_div_ck",
3211 .addr = omap44xx_mcspi2_addrs,
3212 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3213 .user = OCP_USER_MPU | OCP_USER_SDMA,
3214};
3215
3216/* mcspi2 slave ports */
3217static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3218 &omap44xx_l4_per__mcspi2,
3219};
3220
905a74d9
BC		 3221/* mcspi2 dev_attr */
3222static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3223 .num_chipselect = 2,
3224};
3225
9bcbd7f0
BC		 3226static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3227 .name = "mcspi2",
3228 .class = &omap44xx_mcspi_hwmod_class,
3229 .mpu_irqs = omap44xx_mcspi2_irqs,
3230 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3231 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3232 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3233 .main_clk = "mcspi2_fck",
3234 .prcm = {
3235 .omap4 = {
3236 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3237 },
3238 },
905a74d9 3239 .dev_attr = &mcspi2_dev_attr,
9bcbd7f0
BC		 3240 .slaves = omap44xx_mcspi2_slaves,
3241 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3243};
3244
3245/* mcspi3 */
3246static struct omap_hwmod omap44xx_mcspi3_hwmod;
3247static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3248 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3249};
3250
3251static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3252 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3253 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3254 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3255 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3256};
3257
3258static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3259 {
3260 .pa_start = 0x480b8000,
3261 .pa_end = 0x480b81ff,
3262 .flags = ADDR_TYPE_RT
3263 },
3264};
3265
3266/* l4_per -> mcspi3 */
3267static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3268 .master = &omap44xx_l4_per_hwmod,
3269 .slave = &omap44xx_mcspi3_hwmod,
3270 .clk = "l4_div_ck",
3271 .addr = omap44xx_mcspi3_addrs,
3272 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3273 .user = OCP_USER_MPU | OCP_USER_SDMA,
3274};
3275
3276/* mcspi3 slave ports */
3277static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3278 &omap44xx_l4_per__mcspi3,
3279};
3280
905a74d9
BC		 3281/* mcspi3 dev_attr */
3282static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3283 .num_chipselect = 2,
3284};
3285
9bcbd7f0
BC		 3286static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3287 .name = "mcspi3",
3288 .class = &omap44xx_mcspi_hwmod_class,
3289 .mpu_irqs = omap44xx_mcspi3_irqs,
3290 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3291 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3292 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3293 .main_clk = "mcspi3_fck",
3294 .prcm = {
3295 .omap4 = {
3296 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3297 },
3298 },
905a74d9 3299 .dev_attr = &mcspi3_dev_attr,
9bcbd7f0
BC		 3300 .slaves = omap44xx_mcspi3_slaves,
3301 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3303};
3304
3305/* mcspi4 */
3306static struct omap_hwmod omap44xx_mcspi4_hwmod;
3307static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3308 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3309};
3310
3311static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3312 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3313 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3314};
3315
3316static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3317 {
3318 .pa_start = 0x480ba000,
3319 .pa_end = 0x480ba1ff,
3320 .flags = ADDR_TYPE_RT
3321 },
3322};
3323
3324/* l4_per -> mcspi4 */
3325static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3326 .master = &omap44xx_l4_per_hwmod,
3327 .slave = &omap44xx_mcspi4_hwmod,
3328 .clk = "l4_div_ck",
3329 .addr = omap44xx_mcspi4_addrs,
3330 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3331 .user = OCP_USER_MPU | OCP_USER_SDMA,
3332};
3333
3334/* mcspi4 slave ports */
3335static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3336 &omap44xx_l4_per__mcspi4,
3337};
3338
905a74d9
BC		 3339/* mcspi4 dev_attr */
3340static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3341 .num_chipselect = 1,
3342};
3343
9bcbd7f0
BC		 3344static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3345 .name = "mcspi4",
3346 .class = &omap44xx_mcspi_hwmod_class,
3347 .mpu_irqs = omap44xx_mcspi4_irqs,
3348 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3349 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3350 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3351 .main_clk = "mcspi4_fck",
3352 .prcm = {
3353 .omap4 = {
3354 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3355 },
3356 },
905a74d9 3357 .dev_attr = &mcspi4_dev_attr,
9bcbd7f0
BC		 3358 .slaves = omap44xx_mcspi4_slaves,
3359 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3360 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3361};
3362
407a6888
BC		 3363/*
3364 * 'mmc' class
3365 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3366 */
3367
3368static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3369 .rev_offs = 0x0000,
3370 .sysc_offs = 0x0010,
3371 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3372 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3373 SYSC_HAS_SOFTRESET),
3374 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3375 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3376 MSTANDBY_SMART),
3377 .sysc_fields = &omap_hwmod_sysc_type2,
3378};
3379
3380static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3381 .name = "mmc",
3382 .sysc = &omap44xx_mmc_sysc,
3383};
3384
3385/* mmc1 */
3386static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3387 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3388};
3389
3390static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3391 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3392 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3393};
3394
3395/* mmc1 master ports */
3396static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3397 &omap44xx_mmc1__l3_main_1,
3398};
3399
3400static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3401 {
3402 .pa_start = 0x4809c000,
3403 .pa_end = 0x4809c3ff,
3404 .flags = ADDR_TYPE_RT
3405 },
3406};
3407
3408/* l4_per -> mmc1 */
3409static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3410 .master = &omap44xx_l4_per_hwmod,
3411 .slave = &omap44xx_mmc1_hwmod,
3412 .clk = "l4_div_ck",
3413 .addr = omap44xx_mmc1_addrs,
3414 .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416};
3417
3418/* mmc1 slave ports */
3419static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3420 &omap44xx_l4_per__mmc1,
3421};
3422
3423static struct omap_hwmod omap44xx_mmc1_hwmod = {
3424 .name = "mmc1",
3425 .class = &omap44xx_mmc_hwmod_class,
3426 .mpu_irqs = omap44xx_mmc1_irqs,
3427 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
3428 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3429 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3430 .main_clk = "mmc1_fck",
3431 .prcm = {
3432 .omap4 = {
3433 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3434 },
3435 },
3436 .slaves = omap44xx_mmc1_slaves,
3437 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3438 .masters = omap44xx_mmc1_masters,
3439 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3440 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3441};
3442
3443/* mmc2 */
3444static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3445 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3446};
3447
3448static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3449 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3450 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3451};
3452
3453/* mmc2 master ports */
3454static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3455 &omap44xx_mmc2__l3_main_1,
3456};
3457
3458static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3459 {
3460 .pa_start = 0x480b4000,
3461 .pa_end = 0x480b43ff,
3462 .flags = ADDR_TYPE_RT
3463 },
3464};
3465
3466/* l4_per -> mmc2 */
3467static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3468 .master = &omap44xx_l4_per_hwmod,
3469 .slave = &omap44xx_mmc2_hwmod,
3470 .clk = "l4_div_ck",
3471 .addr = omap44xx_mmc2_addrs,
3472 .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
3473 .user = OCP_USER_MPU | OCP_USER_SDMA,
3474};
3475
3476/* mmc2 slave ports */
3477static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3478 &omap44xx_l4_per__mmc2,
3479};
3480
3481static struct omap_hwmod omap44xx_mmc2_hwmod = {
3482 .name = "mmc2",
3483 .class = &omap44xx_mmc_hwmod_class,
3484 .mpu_irqs = omap44xx_mmc2_irqs,
3485 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
3486 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3487 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3488 .main_clk = "mmc2_fck",
3489 .prcm = {
3490 .omap4 = {
3491 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3492 },
3493 },
3494 .slaves = omap44xx_mmc2_slaves,
3495 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3496 .masters = omap44xx_mmc2_masters,
3497 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3499};
3500
3501/* mmc3 */
3502static struct omap_hwmod omap44xx_mmc3_hwmod;
3503static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3504 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3505};
3506
3507static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3508 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3509 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3510};
3511
3512static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3513 {
3514 .pa_start = 0x480ad000,
3515 .pa_end = 0x480ad3ff,
3516 .flags = ADDR_TYPE_RT
3517 },
3518};
3519
3520/* l4_per -> mmc3 */
3521static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3522 .master = &omap44xx_l4_per_hwmod,
3523 .slave = &omap44xx_mmc3_hwmod,
3524 .clk = "l4_div_ck",
3525 .addr = omap44xx_mmc3_addrs,
3526 .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
3527 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528};
3529
3530/* mmc3 slave ports */
3531static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3532 &omap44xx_l4_per__mmc3,
3533};
3534
3535static struct omap_hwmod omap44xx_mmc3_hwmod = {
3536 .name = "mmc3",
3537 .class = &omap44xx_mmc_hwmod_class,
3538 .mpu_irqs = omap44xx_mmc3_irqs,
3539 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
3540 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3541 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3542 .main_clk = "mmc3_fck",
3543 .prcm = {
3544 .omap4 = {
3545 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3546 },
3547 },
3548 .slaves = omap44xx_mmc3_slaves,
3549 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3550 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3551};
3552
3553/* mmc4 */
3554static struct omap_hwmod omap44xx_mmc4_hwmod;
3555static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3556 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3557};
3558
3559static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3560 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3561 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3562};
3563
3564static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3565 {
3566 .pa_start = 0x480d1000,
3567 .pa_end = 0x480d13ff,
3568 .flags = ADDR_TYPE_RT
3569 },
3570};
3571
3572/* l4_per -> mmc4 */
3573static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3574 .master = &omap44xx_l4_per_hwmod,
3575 .slave = &omap44xx_mmc4_hwmod,
3576 .clk = "l4_div_ck",
3577 .addr = omap44xx_mmc4_addrs,
3578 .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
3579 .user = OCP_USER_MPU | OCP_USER_SDMA,
3580};
3581
3582/* mmc4 slave ports */
3583static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3584 &omap44xx_l4_per__mmc4,
3585};
3586
3587static struct omap_hwmod omap44xx_mmc4_hwmod = {
3588 .name = "mmc4",
3589 .class = &omap44xx_mmc_hwmod_class,
3590 .mpu_irqs = omap44xx_mmc4_irqs,
3591 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
3592 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3593 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3594 .main_clk = "mmc4_fck",
3595 .prcm = {
3596 .omap4 = {
3597 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3598 },
3599 },
3600 .slaves = omap44xx_mmc4_slaves,
3601 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3602 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3603};
3604
3605/* mmc5 */
3606static struct omap_hwmod omap44xx_mmc5_hwmod;
3607static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3608 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3609};
3610
3611static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3612 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3613 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3614};
3615
3616static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3617 {
3618 .pa_start = 0x480d5000,
3619 .pa_end = 0x480d53ff,
3620 .flags = ADDR_TYPE_RT
3621 },
3622};
3623
3624/* l4_per -> mmc5 */
3625static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3626 .master = &omap44xx_l4_per_hwmod,
3627 .slave = &omap44xx_mmc5_hwmod,
3628 .clk = "l4_div_ck",
3629 .addr = omap44xx_mmc5_addrs,
3630 .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
3631 .user = OCP_USER_MPU | OCP_USER_SDMA,
3632};
3633
3634/* mmc5 slave ports */
3635static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3636 &omap44xx_l4_per__mmc5,
3637};
3638
3639static struct omap_hwmod omap44xx_mmc5_hwmod = {
3640 .name = "mmc5",
3641 .class = &omap44xx_mmc_hwmod_class,
3642 .mpu_irqs = omap44xx_mmc5_irqs,
3643 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
3644 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3645 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3646 .main_clk = "mmc5_fck",
3647 .prcm = {
3648 .omap4 = {
3649 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3650 },
3651 },
3652 .slaves = omap44xx_mmc5_slaves,
3653 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3654 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3655};
3656
3b54baad
BC		 3657/*
3658 * 'mpu' class
3659 * mpu sub-system
3660 */
3661
3662static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 3663 .name = "mpu",
db12ba53
BC		 3664};
3665
3b54baad
BC		 3666/* mpu */
3667static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3668 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3669 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3670 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 3671};
3672
3b54baad
BC		 3673/* mpu master ports */
3674static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3675 &omap44xx_mpu__l3_main_1,
3676 &omap44xx_mpu__l4_abe,
3677 &omap44xx_mpu__dmm,
3678};
3679
3680static struct omap_hwmod omap44xx_mpu_hwmod = {
3681 .name = "mpu",
3682 .class = &omap44xx_mpu_hwmod_class,
3683 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3684 .mpu_irqs = omap44xx_mpu_irqs,
3685 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
3686 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 3687 .prcm = {
3688 .omap4 = {
3b54baad 3689 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
db12ba53
BC		 3690 },
3691 },
3b54baad
BC		 3692 .masters = omap44xx_mpu_masters,
3693 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 3694 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3695};
3696
1f6a717f
BC		 3697/*
3698 * 'smartreflex' class
3699 * smartreflex module (monitor silicon performance and outputs a measure of
3700 * performance error)
3701 */
3702
3703/* The IP is not compliant to type1 / type2 scheme */
3704static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3705 .sidle_shift = 24,
3706 .enwkup_shift = 26,
3707};
3708
3709static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3710 .sysc_offs = 0x0038,
3711 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3712 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3713 SIDLE_SMART_WKUP),
3714 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3715};
3716
3717static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 3718 .name = "smartreflex",
3719 .sysc = &omap44xx_smartreflex_sysc,
3720 .rev = 2,
1f6a717f
BC		 3721};
3722
3723/* smartreflex_core */
3724static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3725static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3726 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3727};
3728
3729static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3730 {
3731 .pa_start = 0x4a0dd000,
3732 .pa_end = 0x4a0dd03f,
3733 .flags = ADDR_TYPE_RT
3734 },
3735};
3736
3737/* l4_cfg -> smartreflex_core */
3738static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3739 .master = &omap44xx_l4_cfg_hwmod,
3740 .slave = &omap44xx_smartreflex_core_hwmod,
3741 .clk = "l4_div_ck",
3742 .addr = omap44xx_smartreflex_core_addrs,
3743 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3744 .user = OCP_USER_MPU | OCP_USER_SDMA,
3745};
3746
3747/* smartreflex_core slave ports */
3748static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3749 &omap44xx_l4_cfg__smartreflex_core,
3750};
3751
3752static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3753 .name = "smartreflex_core",
3754 .class = &omap44xx_smartreflex_hwmod_class,
3755 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3756 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3757 .main_clk = "smartreflex_core_fck",
3758 .vdd_name = "core",
3759 .prcm = {
3760 .omap4 = {
3761 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3762 },
3763 },
3764 .slaves = omap44xx_smartreflex_core_slaves,
3765 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3766 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3767};
3768
3769/* smartreflex_iva */
3770static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3771static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3772 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3773};
3774
3775static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3776 {
3777 .pa_start = 0x4a0db000,
3778 .pa_end = 0x4a0db03f,
3779 .flags = ADDR_TYPE_RT
3780 },
3781};
3782
3783/* l4_cfg -> smartreflex_iva */
3784static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3785 .master = &omap44xx_l4_cfg_hwmod,
3786 .slave = &omap44xx_smartreflex_iva_hwmod,
3787 .clk = "l4_div_ck",
3788 .addr = omap44xx_smartreflex_iva_addrs,
3789 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3790 .user = OCP_USER_MPU | OCP_USER_SDMA,
3791};
3792
3793/* smartreflex_iva slave ports */
3794static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3795 &omap44xx_l4_cfg__smartreflex_iva,
3796};
3797
3798static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3799 .name = "smartreflex_iva",
3800 .class = &omap44xx_smartreflex_hwmod_class,
3801 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3802 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3803 .main_clk = "smartreflex_iva_fck",
3804 .vdd_name = "iva",
3805 .prcm = {
3806 .omap4 = {
3807 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3808 },
3809 },
3810 .slaves = omap44xx_smartreflex_iva_slaves,
3811 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3812 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3813};
3814
3815/* smartreflex_mpu */
3816static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3817static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3818 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3819};
3820
3821static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3822 {
3823 .pa_start = 0x4a0d9000,
3824 .pa_end = 0x4a0d903f,
3825 .flags = ADDR_TYPE_RT
3826 },
3827};
3828
3829/* l4_cfg -> smartreflex_mpu */
3830static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3831 .master = &omap44xx_l4_cfg_hwmod,
3832 .slave = &omap44xx_smartreflex_mpu_hwmod,
3833 .clk = "l4_div_ck",
3834 .addr = omap44xx_smartreflex_mpu_addrs,
3835 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3836 .user = OCP_USER_MPU | OCP_USER_SDMA,
3837};
3838
3839/* smartreflex_mpu slave ports */
3840static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3841 &omap44xx_l4_cfg__smartreflex_mpu,
3842};
3843
3844static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3845 .name = "smartreflex_mpu",
3846 .class = &omap44xx_smartreflex_hwmod_class,
3847 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3848 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3849 .main_clk = "smartreflex_mpu_fck",
3850 .vdd_name = "mpu",
3851 .prcm = {
3852 .omap4 = {
3853 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3854 },
3855 },
3856 .slaves = omap44xx_smartreflex_mpu_slaves,
3857 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3858 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3859};
3860
d11c217f
BC		 3861/*
3862 * 'spinlock' class
3863 * spinlock provides hardware assistance for synchronizing the processes
3864 * running on multiple processors
3865 */
3866
3867static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3868 .rev_offs = 0x0000,
3869 .sysc_offs = 0x0010,
3870 .syss_offs = 0x0014,
3871 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3872 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3873 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3874 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3875 SIDLE_SMART_WKUP),
3876 .sysc_fields = &omap_hwmod_sysc_type1,
3877};
3878
3879static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3880 .name = "spinlock",
3881 .sysc = &omap44xx_spinlock_sysc,
3882};
3883
3884/* spinlock */
3885static struct omap_hwmod omap44xx_spinlock_hwmod;
3886static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3887 {
3888 .pa_start = 0x4a0f6000,
3889 .pa_end = 0x4a0f6fff,
3890 .flags = ADDR_TYPE_RT
3891 },
3892};
3893
3894/* l4_cfg -> spinlock */
3895static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3896 .master = &omap44xx_l4_cfg_hwmod,
3897 .slave = &omap44xx_spinlock_hwmod,
3898 .clk = "l4_div_ck",
3899 .addr = omap44xx_spinlock_addrs,
3900 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
3901 .user = OCP_USER_MPU | OCP_USER_SDMA,
3902};
3903
3904/* spinlock slave ports */
3905static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3906 &omap44xx_l4_cfg__spinlock,
3907};
3908
3909static struct omap_hwmod omap44xx_spinlock_hwmod = {
3910 .name = "spinlock",
3911 .class = &omap44xx_spinlock_hwmod_class,
3912 .prcm = {
3913 .omap4 = {
3914 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3915 },
3916 },
3917 .slaves = omap44xx_spinlock_slaves,
3918 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
3919 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3920};
3921
35d1a66a
BC		 3922/*
3923 * 'timer' class
3924 * general purpose timer module with accurate 1ms tick
3925 * This class contains several variants: ['timer_1ms', 'timer']
3926 */
3927
3928static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3929 .rev_offs = 0x0000,
3930 .sysc_offs = 0x0010,
3931 .syss_offs = 0x0014,
3932 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3933 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3934 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3935 SYSS_HAS_RESET_STATUS),
3936 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3937 .sysc_fields = &omap_hwmod_sysc_type1,
3938};
3939
3940static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3941 .name = "timer",
3942 .sysc = &omap44xx_timer_1ms_sysc,
3943};
3944
3945static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3946 .rev_offs = 0x0000,
3947 .sysc_offs = 0x0010,
3948 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3949 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3950 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3951 SIDLE_SMART_WKUP),
3952 .sysc_fields = &omap_hwmod_sysc_type2,
3953};
3954
3955static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3956 .name = "timer",
3957 .sysc = &omap44xx_timer_sysc,
3958};
3959
3960/* timer1 */
3961static struct omap_hwmod omap44xx_timer1_hwmod;
3962static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3963 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3964};
3965
3966static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3967 {
3968 .pa_start = 0x4a318000,
3969 .pa_end = 0x4a31807f,
3970 .flags = ADDR_TYPE_RT
3971 },
3972};
3973
3974/* l4_wkup -> timer1 */
3975static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3976 .master = &omap44xx_l4_wkup_hwmod,
3977 .slave = &omap44xx_timer1_hwmod,
3978 .clk = "l4_wkup_clk_mux_ck",
3979 .addr = omap44xx_timer1_addrs,
3980 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
3981 .user = OCP_USER_MPU | OCP_USER_SDMA,
3982};
3983
3984/* timer1 slave ports */
3985static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3986 &omap44xx_l4_wkup__timer1,
3987};
3988
3989static struct omap_hwmod omap44xx_timer1_hwmod = {
3990 .name = "timer1",
3991 .class = &omap44xx_timer_1ms_hwmod_class,
3b03b58d 3992 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
35d1a66a
BC		 3993 .mpu_irqs = omap44xx_timer1_irqs,
3994 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
3995 .main_clk = "timer1_fck",
3996 .prcm = {
3997 .omap4 = {
3998 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
3999 },
4000 },
4001 .slaves = omap44xx_timer1_slaves,
4002 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4003 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4004};
4005
4006/* timer2 */
4007static struct omap_hwmod omap44xx_timer2_hwmod;
4008static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4009 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4010};
4011
4012static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4013 {
4014 .pa_start = 0x48032000,
4015 .pa_end = 0x4803207f,
4016 .flags = ADDR_TYPE_RT
4017 },
4018};
4019
4020/* l4_per -> timer2 */
4021static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4022 .master = &omap44xx_l4_per_hwmod,
4023 .slave = &omap44xx_timer2_hwmod,
4024 .clk = "l4_div_ck",
4025 .addr = omap44xx_timer2_addrs,
4026 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
4027 .user = OCP_USER_MPU | OCP_USER_SDMA,
4028};
4029
4030/* timer2 slave ports */
4031static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4032 &omap44xx_l4_per__timer2,
4033};
4034
4035static struct omap_hwmod omap44xx_timer2_hwmod = {
4036 .name = "timer2",
4037 .class = &omap44xx_timer_1ms_hwmod_class,
4038 .mpu_irqs = omap44xx_timer2_irqs,
4039 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
4040 .main_clk = "timer2_fck",
4041 .prcm = {
4042 .omap4 = {
4043 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4044 },
4045 },
4046 .slaves = omap44xx_timer2_slaves,
4047 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4048 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4049};
4050
4051/* timer3 */
4052static struct omap_hwmod omap44xx_timer3_hwmod;
4053static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4054 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4055};
4056
4057static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4058 {
4059 .pa_start = 0x48034000,
4060 .pa_end = 0x4803407f,
4061 .flags = ADDR_TYPE_RT
4062 },
4063};
4064
4065/* l4_per -> timer3 */
4066static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4067 .master = &omap44xx_l4_per_hwmod,
4068 .slave = &omap44xx_timer3_hwmod,
4069 .clk = "l4_div_ck",
4070 .addr = omap44xx_timer3_addrs,
4071 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
4072 .user = OCP_USER_MPU | OCP_USER_SDMA,
4073};
4074
4075/* timer3 slave ports */
4076static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4077 &omap44xx_l4_per__timer3,
4078};
4079
4080static struct omap_hwmod omap44xx_timer3_hwmod = {
4081 .name = "timer3",
4082 .class = &omap44xx_timer_hwmod_class,
4083 .mpu_irqs = omap44xx_timer3_irqs,
4084 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
4085 .main_clk = "timer3_fck",
4086 .prcm = {
4087 .omap4 = {
4088 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4089 },
4090 },
4091 .slaves = omap44xx_timer3_slaves,
4092 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4093 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4094};
4095
4096/* timer4 */
4097static struct omap_hwmod omap44xx_timer4_hwmod;
4098static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4099 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4100};
4101
4102static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4103 {
4104 .pa_start = 0x48036000,
4105 .pa_end = 0x4803607f,
4106 .flags = ADDR_TYPE_RT
4107 },
4108};
4109
4110/* l4_per -> timer4 */
4111static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4112 .master = &omap44xx_l4_per_hwmod,
4113 .slave = &omap44xx_timer4_hwmod,
4114 .clk = "l4_div_ck",
4115 .addr = omap44xx_timer4_addrs,
4116 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
4117 .user = OCP_USER_MPU | OCP_USER_SDMA,
4118};
4119
4120/* timer4 slave ports */
4121static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4122 &omap44xx_l4_per__timer4,
4123};
4124
4125static struct omap_hwmod omap44xx_timer4_hwmod = {
4126 .name = "timer4",
4127 .class = &omap44xx_timer_hwmod_class,
4128 .mpu_irqs = omap44xx_timer4_irqs,
4129 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
4130 .main_clk = "timer4_fck",
4131 .prcm = {
4132 .omap4 = {
4133 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4134 },
4135 },
4136 .slaves = omap44xx_timer4_slaves,
4137 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4139};
4140
4141/* timer5 */
4142static struct omap_hwmod omap44xx_timer5_hwmod;
4143static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4144 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4145};
4146
4147static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4148 {
4149 .pa_start = 0x40138000,
4150 .pa_end = 0x4013807f,
4151 .flags = ADDR_TYPE_RT
4152 },
4153};
4154
4155/* l4_abe -> timer5 */
4156static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4157 .master = &omap44xx_l4_abe_hwmod,
4158 .slave = &omap44xx_timer5_hwmod,
4159 .clk = "ocp_abe_iclk",
4160 .addr = omap44xx_timer5_addrs,
4161 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
4162 .user = OCP_USER_MPU,
4163};
4164
4165static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4166 {
4167 .pa_start = 0x49038000,
4168 .pa_end = 0x4903807f,
4169 .flags = ADDR_TYPE_RT
4170 },
4171};
4172
4173/* l4_abe -> timer5 (dma) */
4174static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4175 .master = &omap44xx_l4_abe_hwmod,
4176 .slave = &omap44xx_timer5_hwmod,
4177 .clk = "ocp_abe_iclk",
4178 .addr = omap44xx_timer5_dma_addrs,
4179 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4180 .user = OCP_USER_SDMA,
4181};
4182
4183/* timer5 slave ports */
4184static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4185 &omap44xx_l4_abe__timer5,
4186 &omap44xx_l4_abe__timer5_dma,
4187};
4188
4189static struct omap_hwmod omap44xx_timer5_hwmod = {
4190 .name = "timer5",
4191 .class = &omap44xx_timer_hwmod_class,
4192 .mpu_irqs = omap44xx_timer5_irqs,
4193 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
4194 .main_clk = "timer5_fck",
4195 .prcm = {
4196 .omap4 = {
4197 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4198 },
4199 },
4200 .slaves = omap44xx_timer5_slaves,
4201 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4202 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4203};
4204
4205/* timer6 */
4206static struct omap_hwmod omap44xx_timer6_hwmod;
4207static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4208 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4209};
4210
4211static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4212 {
4213 .pa_start = 0x4013a000,
4214 .pa_end = 0x4013a07f,
4215 .flags = ADDR_TYPE_RT
4216 },
4217};
4218
4219/* l4_abe -> timer6 */
4220static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4221 .master = &omap44xx_l4_abe_hwmod,
4222 .slave = &omap44xx_timer6_hwmod,
4223 .clk = "ocp_abe_iclk",
4224 .addr = omap44xx_timer6_addrs,
4225 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
4226 .user = OCP_USER_MPU,
4227};
4228
4229static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4230 {
4231 .pa_start = 0x4903a000,
4232 .pa_end = 0x4903a07f,
4233 .flags = ADDR_TYPE_RT
4234 },
4235};
4236
4237/* l4_abe -> timer6 (dma) */
4238static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4239 .master = &omap44xx_l4_abe_hwmod,
4240 .slave = &omap44xx_timer6_hwmod,
4241 .clk = "ocp_abe_iclk",
4242 .addr = omap44xx_timer6_dma_addrs,
4243 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4244 .user = OCP_USER_SDMA,
4245};
4246
4247/* timer6 slave ports */
4248static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4249 &omap44xx_l4_abe__timer6,
4250 &omap44xx_l4_abe__timer6_dma,
4251};
4252
4253static struct omap_hwmod omap44xx_timer6_hwmod = {
4254 .name = "timer6",
4255 .class = &omap44xx_timer_hwmod_class,
4256 .mpu_irqs = omap44xx_timer6_irqs,
4257 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
4258 .main_clk = "timer6_fck",
4259 .prcm = {
4260 .omap4 = {
4261 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4262 },
4263 },
4264 .slaves = omap44xx_timer6_slaves,
4265 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4266 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4267};
4268
4269/* timer7 */
4270static struct omap_hwmod omap44xx_timer7_hwmod;
4271static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4272 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4273};
4274
4275static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4276 {
4277 .pa_start = 0x4013c000,
4278 .pa_end = 0x4013c07f,
4279 .flags = ADDR_TYPE_RT
4280 },
4281};
4282
4283/* l4_abe -> timer7 */
4284static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4285 .master = &omap44xx_l4_abe_hwmod,
4286 .slave = &omap44xx_timer7_hwmod,
4287 .clk = "ocp_abe_iclk",
4288 .addr = omap44xx_timer7_addrs,
4289 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
4290 .user = OCP_USER_MPU,
4291};
4292
4293static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4294 {
4295 .pa_start = 0x4903c000,
4296 .pa_end = 0x4903c07f,
4297 .flags = ADDR_TYPE_RT
4298 },
4299};
4300
4301/* l4_abe -> timer7 (dma) */
4302static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4303 .master = &omap44xx_l4_abe_hwmod,
4304 .slave = &omap44xx_timer7_hwmod,
4305 .clk = "ocp_abe_iclk",
4306 .addr = omap44xx_timer7_dma_addrs,
4307 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4308 .user = OCP_USER_SDMA,
4309};
4310
4311/* timer7 slave ports */
4312static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4313 &omap44xx_l4_abe__timer7,
4314 &omap44xx_l4_abe__timer7_dma,
4315};
4316
4317static struct omap_hwmod omap44xx_timer7_hwmod = {
4318 .name = "timer7",
4319 .class = &omap44xx_timer_hwmod_class,
4320 .mpu_irqs = omap44xx_timer7_irqs,
4321 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
4322 .main_clk = "timer7_fck",
4323 .prcm = {
4324 .omap4 = {
4325 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4326 },
4327 },
4328 .slaves = omap44xx_timer7_slaves,
4329 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4330 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4331};
4332
4333/* timer8 */
4334static struct omap_hwmod omap44xx_timer8_hwmod;
4335static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4336 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4337};
4338
4339static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4340 {
4341 .pa_start = 0x4013e000,
4342 .pa_end = 0x4013e07f,
4343 .flags = ADDR_TYPE_RT
4344 },
4345};
4346
4347/* l4_abe -> timer8 */
4348static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4349 .master = &omap44xx_l4_abe_hwmod,
4350 .slave = &omap44xx_timer8_hwmod,
4351 .clk = "ocp_abe_iclk",
4352 .addr = omap44xx_timer8_addrs,
4353 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
4354 .user = OCP_USER_MPU,
4355};
4356
4357static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4358 {
4359 .pa_start = 0x4903e000,
4360 .pa_end = 0x4903e07f,
4361 .flags = ADDR_TYPE_RT
4362 },
4363};
4364
4365/* l4_abe -> timer8 (dma) */
4366static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4367 .master = &omap44xx_l4_abe_hwmod,
4368 .slave = &omap44xx_timer8_hwmod,
4369 .clk = "ocp_abe_iclk",
4370 .addr = omap44xx_timer8_dma_addrs,
4371 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4372 .user = OCP_USER_SDMA,
4373};
4374
4375/* timer8 slave ports */
4376static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4377 &omap44xx_l4_abe__timer8,
4378 &omap44xx_l4_abe__timer8_dma,
4379};
4380
4381static struct omap_hwmod omap44xx_timer8_hwmod = {
4382 .name = "timer8",
4383 .class = &omap44xx_timer_hwmod_class,
4384 .mpu_irqs = omap44xx_timer8_irqs,
4385 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
4386 .main_clk = "timer8_fck",
4387 .prcm = {
4388 .omap4 = {
4389 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4390 },
4391 },
4392 .slaves = omap44xx_timer8_slaves,
4393 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4395};
4396
4397/* timer9 */
4398static struct omap_hwmod omap44xx_timer9_hwmod;
4399static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4400 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4401};
4402
4403static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4404 {
4405 .pa_start = 0x4803e000,
4406 .pa_end = 0x4803e07f,
4407 .flags = ADDR_TYPE_RT
4408 },
4409};
4410
4411/* l4_per -> timer9 */
4412static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4413 .master = &omap44xx_l4_per_hwmod,
4414 .slave = &omap44xx_timer9_hwmod,
4415 .clk = "l4_div_ck",
4416 .addr = omap44xx_timer9_addrs,
4417 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
4418 .user = OCP_USER_MPU | OCP_USER_SDMA,
4419};
4420
4421/* timer9 slave ports */
4422static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4423 &omap44xx_l4_per__timer9,
4424};
4425
4426static struct omap_hwmod omap44xx_timer9_hwmod = {
4427 .name = "timer9",
4428 .class = &omap44xx_timer_hwmod_class,
4429 .mpu_irqs = omap44xx_timer9_irqs,
4430 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
4431 .main_clk = "timer9_fck",
4432 .prcm = {
4433 .omap4 = {
4434 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4435 },
4436 },
4437 .slaves = omap44xx_timer9_slaves,
4438 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4439 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4440};
4441
4442/* timer10 */
4443static struct omap_hwmod omap44xx_timer10_hwmod;
4444static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4445 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4446};
4447
4448static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4449 {
4450 .pa_start = 0x48086000,
4451 .pa_end = 0x4808607f,
4452 .flags = ADDR_TYPE_RT
4453 },
4454};
4455
4456/* l4_per -> timer10 */
4457static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4458 .master = &omap44xx_l4_per_hwmod,
4459 .slave = &omap44xx_timer10_hwmod,
4460 .clk = "l4_div_ck",
4461 .addr = omap44xx_timer10_addrs,
4462 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
4463 .user = OCP_USER_MPU | OCP_USER_SDMA,
4464};
4465
4466/* timer10 slave ports */
4467static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4468 &omap44xx_l4_per__timer10,
4469};
4470
4471static struct omap_hwmod omap44xx_timer10_hwmod = {
4472 .name = "timer10",
4473 .class = &omap44xx_timer_1ms_hwmod_class,
4474 .mpu_irqs = omap44xx_timer10_irqs,
4475 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
4476 .main_clk = "timer10_fck",
4477 .prcm = {
4478 .omap4 = {
4479 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4480 },
4481 },
4482 .slaves = omap44xx_timer10_slaves,
4483 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4484 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4485};
4486
4487/* timer11 */
4488static struct omap_hwmod omap44xx_timer11_hwmod;
4489static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4490 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4491};
4492
4493static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4494 {
4495 .pa_start = 0x48088000,
4496 .pa_end = 0x4808807f,
4497 .flags = ADDR_TYPE_RT
4498 },
4499};
4500
4501/* l4_per -> timer11 */
4502static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4503 .master = &omap44xx_l4_per_hwmod,
4504 .slave = &omap44xx_timer11_hwmod,
4505 .clk = "l4_div_ck",
4506 .addr = omap44xx_timer11_addrs,
4507 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
4508 .user = OCP_USER_MPU | OCP_USER_SDMA,
4509};
4510
4511/* timer11 slave ports */
4512static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4513 &omap44xx_l4_per__timer11,
4514};
4515
4516static struct omap_hwmod omap44xx_timer11_hwmod = {
4517 .name = "timer11",
4518 .class = &omap44xx_timer_hwmod_class,
4519 .mpu_irqs = omap44xx_timer11_irqs,
4520 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
4521 .main_clk = "timer11_fck",
4522 .prcm = {
4523 .omap4 = {
4524 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4525 },
4526 },
4527 .slaves = omap44xx_timer11_slaves,
4528 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4529 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4530};
4531
9780a9cf 4532/*
3b54baad
BC		 4533 * 'uart' class
4534 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 4535 */
4536
3b54baad
BC		 4537static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4538 .rev_offs = 0x0050,
4539 .sysc_offs = 0x0054,
4540 .syss_offs = 0x0058,
4541 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 4542 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4543 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4545 SIDLE_SMART_WKUP),
9780a9cf
BC		 4546 .sysc_fields = &omap_hwmod_sysc_type1,
4547};
4548
3b54baad 4549static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 4550 .name = "uart",
4551 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 4552};
4553
3b54baad
BC		 4554/* uart1 */
4555static struct omap_hwmod omap44xx_uart1_hwmod;
4556static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4557 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4558};
4559
3b54baad
BC		 4560static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4561 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4562 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
9780a9cf
BC		 4563};
4564
3b54baad 4565static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 4566 {
3b54baad
BC		 4567 .pa_start = 0x4806a000,
4568 .pa_end = 0x4806a0ff,
9780a9cf
BC		 4569 .flags = ADDR_TYPE_RT
4570 },
4571};
4572
3b54baad
BC		 4573/* l4_per -> uart1 */
4574static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4575 .master = &omap44xx_l4_per_hwmod,
4576 .slave = &omap44xx_uart1_hwmod,
4577 .clk = "l4_div_ck",
4578 .addr = omap44xx_uart1_addrs,
4579 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
9780a9cf
BC		 4580 .user = OCP_USER_MPU | OCP_USER_SDMA,
4581};
4582
3b54baad
BC		 4583/* uart1 slave ports */
4584static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4585 &omap44xx_l4_per__uart1,
9780a9cf
BC		 4586};
4587
3b54baad
BC		 4588static struct omap_hwmod omap44xx_uart1_hwmod = {
4589 .name = "uart1",
4590 .class = &omap44xx_uart_hwmod_class,
4591 .mpu_irqs = omap44xx_uart1_irqs,
4592 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
4593 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4594 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4595 .main_clk = "uart1_fck",
9780a9cf
BC		 4596 .prcm = {
4597 .omap4 = {
3b54baad 4598 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
9780a9cf
BC		 4599 },
4600 },
3b54baad
BC		 4601 .slaves = omap44xx_uart1_slaves,
4602 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 4603 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4604};
4605
3b54baad
BC		 4606/* uart2 */
4607static struct omap_hwmod omap44xx_uart2_hwmod;
4608static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4609 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4610};
4611
3b54baad
BC		 4612static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4613 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4614 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4615};
4616
4617static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 4618 {
3b54baad
BC		 4619 .pa_start = 0x4806c000,
4620 .pa_end = 0x4806c0ff,
9780a9cf
BC		 4621 .flags = ADDR_TYPE_RT
4622 },
4623};
4624
3b54baad
BC		 4625/* l4_per -> uart2 */
4626static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 4627 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4628 .slave = &omap44xx_uart2_hwmod,
4629 .clk = "l4_div_ck",
4630 .addr = omap44xx_uart2_addrs,
4631 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
9780a9cf
BC		 4632 .user = OCP_USER_MPU | OCP_USER_SDMA,
4633};
4634
3b54baad
BC		 4635/* uart2 slave ports */
4636static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4637 &omap44xx_l4_per__uart2,
9780a9cf
BC		 4638};
4639
3b54baad
BC		 4640static struct omap_hwmod omap44xx_uart2_hwmod = {
4641 .name = "uart2",
4642 .class = &omap44xx_uart_hwmod_class,
4643 .mpu_irqs = omap44xx_uart2_irqs,
4644 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
4645 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4646 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4647 .main_clk = "uart2_fck",
9780a9cf
BC		 4648 .prcm = {
4649 .omap4 = {
3b54baad 4650 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
9780a9cf
BC		 4651 },
4652 },
3b54baad
BC		 4653 .slaves = omap44xx_uart2_slaves,
4654 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 4655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4656};
4657
3b54baad
BC		 4658/* uart3 */
4659static struct omap_hwmod omap44xx_uart3_hwmod;
4660static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4661 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4662};
4663
3b54baad
BC		 4664static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4665 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4666 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4667};
4668
4669static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 4670 {
3b54baad
BC		 4671 .pa_start = 0x48020000,
4672 .pa_end = 0x480200ff,
9780a9cf
BC		 4673 .flags = ADDR_TYPE_RT
4674 },
4675};
4676
3b54baad
BC		 4677/* l4_per -> uart3 */
4678static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 4679 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4680 .slave = &omap44xx_uart3_hwmod,
4681 .clk = "l4_div_ck",
4682 .addr = omap44xx_uart3_addrs,
4683 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
9780a9cf
BC		 4684 .user = OCP_USER_MPU | OCP_USER_SDMA,
4685};
4686
3b54baad
BC		 4687/* uart3 slave ports */
4688static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4689 &omap44xx_l4_per__uart3,
4690};
4691
4692static struct omap_hwmod omap44xx_uart3_hwmod = {
4693 .name = "uart3",
4694 .class = &omap44xx_uart_hwmod_class,
4695 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4696 .mpu_irqs = omap44xx_uart3_irqs,
4697 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
4698 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4699 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4700 .main_clk = "uart3_fck",
9780a9cf
BC		 4701 .prcm = {
4702 .omap4 = {
3b54baad 4703 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
9780a9cf
BC		 4704 },
4705 },
3b54baad
BC		 4706 .slaves = omap44xx_uart3_slaves,
4707 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 4708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4709};
4710
3b54baad
BC		 4711/* uart4 */
4712static struct omap_hwmod omap44xx_uart4_hwmod;
4713static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4714 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4715};
4716
3b54baad
BC		 4717static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4718 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4719 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4720};
4721
4722static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 4723 {
3b54baad
BC		 4724 .pa_start = 0x4806e000,
4725 .pa_end = 0x4806e0ff,
9780a9cf
BC		 4726 .flags = ADDR_TYPE_RT
4727 },
4728};
4729
3b54baad
BC		 4730/* l4_per -> uart4 */
4731static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 4732 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4733 .slave = &omap44xx_uart4_hwmod,
4734 .clk = "l4_div_ck",
4735 .addr = omap44xx_uart4_addrs,
4736 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
9780a9cf
BC		 4737 .user = OCP_USER_MPU | OCP_USER_SDMA,
4738};
4739
3b54baad
BC		 4740/* uart4 slave ports */
4741static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4742 &omap44xx_l4_per__uart4,
9780a9cf
BC		 4743};
4744
3b54baad
BC		 4745static struct omap_hwmod omap44xx_uart4_hwmod = {
4746 .name = "uart4",
4747 .class = &omap44xx_uart_hwmod_class,
4748 .mpu_irqs = omap44xx_uart4_irqs,
4749 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
4750 .sdma_reqs = omap44xx_uart4_sdma_reqs,
4751 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4752 .main_clk = "uart4_fck",
9780a9cf
BC		 4753 .prcm = {
4754 .omap4 = {
3b54baad 4755 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
9780a9cf
BC		 4756 },
4757 },
3b54baad
BC		 4758 .slaves = omap44xx_uart4_slaves,
4759 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 4760 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4761};
4762
5844c4ea
BC		 4763/*
4764 * 'usb_otg_hs' class
4765 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4766 */
4767
4768static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4769 .rev_offs = 0x0400,
4770 .sysc_offs = 0x0404,
4771 .syss_offs = 0x0408,
4772 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4773 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4774 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4775 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4776 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4777 MSTANDBY_SMART),
4778 .sysc_fields = &omap_hwmod_sysc_type1,
4779};
4780
4781static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4782 .name = "usb_otg_hs",
4783 .sysc = &omap44xx_usb_otg_hs_sysc,
4784};
4785
4786/* usb_otg_hs */
4787static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4788 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4789 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4790};
4791
4792/* usb_otg_hs master ports */
4793static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4794 &omap44xx_usb_otg_hs__l3_main_2,
4795};
4796
4797static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4798 {
4799 .pa_start = 0x4a0ab000,
4800 .pa_end = 0x4a0ab003,
4801 .flags = ADDR_TYPE_RT
4802 },
4803};
4804
4805/* l4_cfg -> usb_otg_hs */
4806static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4807 .master = &omap44xx_l4_cfg_hwmod,
4808 .slave = &omap44xx_usb_otg_hs_hwmod,
4809 .clk = "l4_div_ck",
4810 .addr = omap44xx_usb_otg_hs_addrs,
4811 .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4812 .user = OCP_USER_MPU | OCP_USER_SDMA,
4813};
4814
4815/* usb_otg_hs slave ports */
4816static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4817 &omap44xx_l4_cfg__usb_otg_hs,
4818};
4819
4820static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4821 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4822};
4823
4824static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4825 .name = "usb_otg_hs",
4826 .class = &omap44xx_usb_otg_hs_hwmod_class,
4827 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4828 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
4829 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4830 .main_clk = "usb_otg_hs_ick",
4831 .prcm = {
4832 .omap4 = {
4833 .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4834 },
4835 },
4836 .opt_clks = usb_otg_hs_opt_clks,
4837 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4838 .slaves = omap44xx_usb_otg_hs_slaves,
4839 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4840 .masters = omap44xx_usb_otg_hs_masters,
4841 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4842 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4843};
4844
3b54baad
BC		 4845/*
4846 * 'wd_timer' class
4847 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4848 * overflow condition
4849 */
4850
4851static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4852 .rev_offs = 0x0000,
4853 .sysc_offs = 0x0010,
4854 .syss_offs = 0x0014,
4855 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 4856 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4857 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4858 SIDLE_SMART_WKUP),
3b54baad 4859 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 4860};
4861
3b54baad
BC		 4862static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4863 .name = "wd_timer",
4864 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 4865 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 4866};
4867
4868/* wd_timer2 */
4869static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4870static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4871 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4872};
4873
4874static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 4875 {
3b54baad
BC		 4876 .pa_start = 0x4a314000,
4877 .pa_end = 0x4a31407f,
9780a9cf
BC		 4878 .flags = ADDR_TYPE_RT
4879 },
4880};
4881
3b54baad
BC		 4882/* l4_wkup -> wd_timer2 */
4883static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4884 .master = &omap44xx_l4_wkup_hwmod,
4885 .slave = &omap44xx_wd_timer2_hwmod,
4886 .clk = "l4_wkup_clk_mux_ck",
4887 .addr = omap44xx_wd_timer2_addrs,
4888 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
9780a9cf
BC		 4889 .user = OCP_USER_MPU | OCP_USER_SDMA,
4890};
4891
3b54baad
BC		 4892/* wd_timer2 slave ports */
4893static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4894 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 4895};
4896
3b54baad
BC		 4897static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4898 .name = "wd_timer2",
4899 .class = &omap44xx_wd_timer_hwmod_class,
4900 .mpu_irqs = omap44xx_wd_timer2_irqs,
4901 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4902 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 4903 .prcm = {
4904 .omap4 = {
3b54baad 4905 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
9780a9cf
BC		 4906 },
4907 },
3b54baad
BC		 4908 .slaves = omap44xx_wd_timer2_slaves,
4909 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 4910 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4911};
4912
3b54baad
BC		 4913/* wd_timer3 */
4914static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4915static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4916 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4917};
4918
3b54baad 4919static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 4920 {
3b54baad
BC		 4921 .pa_start = 0x40130000,
4922 .pa_end = 0x4013007f,
9780a9cf
BC		 4923 .flags = ADDR_TYPE_RT
4924 },
4925};
4926
3b54baad
BC		 4927/* l4_abe -> wd_timer3 */
4928static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4929 .master = &omap44xx_l4_abe_hwmod,
4930 .slave = &omap44xx_wd_timer3_hwmod,
4931 .clk = "ocp_abe_iclk",
4932 .addr = omap44xx_wd_timer3_addrs,
4933 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4934 .user = OCP_USER_MPU,
9780a9cf
BC		 4935};
4936
3b54baad
BC		 4937static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4938 {
4939 .pa_start = 0x49030000,
4940 .pa_end = 0x4903007f,
4941 .flags = ADDR_TYPE_RT
4942 },
9780a9cf
BC		 4943};
4944
3b54baad
BC		 4945/* l4_abe -> wd_timer3 (dma) */
4946static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4947 .master = &omap44xx_l4_abe_hwmod,
4948 .slave = &omap44xx_wd_timer3_hwmod,
4949 .clk = "ocp_abe_iclk",
4950 .addr = omap44xx_wd_timer3_dma_addrs,
4951 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
4952 .user = OCP_USER_SDMA,
9780a9cf
BC		 4953};
4954
3b54baad
BC		 4955/* wd_timer3 slave ports */
4956static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
4957 &omap44xx_l4_abe__wd_timer3,
4958 &omap44xx_l4_abe__wd_timer3_dma,
4959};
4960
4961static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
4962 .name = "wd_timer3",
4963 .class = &omap44xx_wd_timer_hwmod_class,
4964 .mpu_irqs = omap44xx_wd_timer3_irqs,
4965 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
4966 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 4967 .prcm = {
4968 .omap4 = {
3b54baad 4969 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
9780a9cf
BC		 4970 },
4971 },
3b54baad
BC		 4972 .slaves = omap44xx_wd_timer3_slaves,
4973 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 4974 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4975};
531ce0d5 4976
55d2cb08 4977static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 4978
55d2cb08
BC		 4979 /* dmm class */
4980 &omap44xx_dmm_hwmod,
3b54baad 4981
55d2cb08
BC		 4982 /* emif_fw class */
4983 &omap44xx_emif_fw_hwmod,
3b54baad 4984
55d2cb08
BC		 4985 /* l3 class */
4986 &omap44xx_l3_instr_hwmod,
4987 &omap44xx_l3_main_1_hwmod,
4988 &omap44xx_l3_main_2_hwmod,
4989 &omap44xx_l3_main_3_hwmod,
3b54baad 4990
55d2cb08
BC		 4991 /* l4 class */
4992 &omap44xx_l4_abe_hwmod,
4993 &omap44xx_l4_cfg_hwmod,
4994 &omap44xx_l4_per_hwmod,
4995 &omap44xx_l4_wkup_hwmod,
531ce0d5 4996
55d2cb08
BC		 4997 /* mpu_bus class */
4998 &omap44xx_mpu_private_hwmod,
4999
407a6888
BC		 5000 /* aess class */
5001/* &omap44xx_aess_hwmod, */
5002
5003 /* bandgap class */
5004 &omap44xx_bandgap_hwmod,
5005
5006 /* counter class */
5007/* &omap44xx_counter_32k_hwmod, */
5008
d7cf5f33
BC		 5009 /* dma class */
5010 &omap44xx_dma_system_hwmod,
5011
8ca476da
BC		 5012 /* dmic class */
5013 &omap44xx_dmic_hwmod,
5014
8f25bdc5
BC		 5015 /* dsp class */
5016 &omap44xx_dsp_hwmod,
5017 &omap44xx_dsp_c0_hwmod,
5018
d63bd74f
BC		 5019 /* dss class */
5020 &omap44xx_dss_hwmod,
5021 &omap44xx_dss_dispc_hwmod,
5022 &omap44xx_dss_dsi1_hwmod,
5023 &omap44xx_dss_dsi2_hwmod,
5024 &omap44xx_dss_hdmi_hwmod,
5025 &omap44xx_dss_rfbi_hwmod,
5026 &omap44xx_dss_venc_hwmod,
5027
9780a9cf
BC		 5028 /* gpio class */
5029 &omap44xx_gpio1_hwmod,
5030 &omap44xx_gpio2_hwmod,
5031 &omap44xx_gpio3_hwmod,
5032 &omap44xx_gpio4_hwmod,
5033 &omap44xx_gpio5_hwmod,
5034 &omap44xx_gpio6_hwmod,
5035
407a6888
BC		 5036 /* hsi class */
5037/* &omap44xx_hsi_hwmod, */
5038
3b54baad
BC		 5039 /* i2c class */
5040 &omap44xx_i2c1_hwmod,
5041 &omap44xx_i2c2_hwmod,
5042 &omap44xx_i2c3_hwmod,
5043 &omap44xx_i2c4_hwmod,
5044
407a6888
BC		 5045 /* ipu class */
5046 &omap44xx_ipu_hwmod,
5047 &omap44xx_ipu_c0_hwmod,
5048 &omap44xx_ipu_c1_hwmod,
5049
5050 /* iss class */
5051/* &omap44xx_iss_hwmod, */
5052
8f25bdc5
BC		 5053 /* iva class */
5054 &omap44xx_iva_hwmod,
5055 &omap44xx_iva_seq0_hwmod,
5056 &omap44xx_iva_seq1_hwmod,
5057
407a6888
BC		 5058 /* kbd class */
5059/* &omap44xx_kbd_hwmod, */
5060
ec5df927
BC		 5061 /* mailbox class */
5062 &omap44xx_mailbox_hwmod,
5063
4ddff493
BC		 5064 /* mcbsp class */
5065 &omap44xx_mcbsp1_hwmod,
5066 &omap44xx_mcbsp2_hwmod,
5067 &omap44xx_mcbsp3_hwmod,
5068 &omap44xx_mcbsp4_hwmod,
5069
407a6888
BC		 5070 /* mcpdm class */
5071/* &omap44xx_mcpdm_hwmod, */
5072
9bcbd7f0
BC		 5073 /* mcspi class */
5074 &omap44xx_mcspi1_hwmod,
5075 &omap44xx_mcspi2_hwmod,
5076 &omap44xx_mcspi3_hwmod,
5077 &omap44xx_mcspi4_hwmod,
5078
407a6888 5079 /* mmc class */
17203bda
AG		 5080 &omap44xx_mmc1_hwmod,
5081 &omap44xx_mmc2_hwmod,
5082 &omap44xx_mmc3_hwmod,
5083 &omap44xx_mmc4_hwmod,
5084 &omap44xx_mmc5_hwmod,
407a6888 5085
55d2cb08
BC		 5086 /* mpu class */
5087 &omap44xx_mpu_hwmod,
db12ba53 5088
1f6a717f
BC		 5089 /* smartreflex class */
5090 &omap44xx_smartreflex_core_hwmod,
5091 &omap44xx_smartreflex_iva_hwmod,
5092 &omap44xx_smartreflex_mpu_hwmod,
5093
d11c217f
BC		 5094 /* spinlock class */
5095 &omap44xx_spinlock_hwmod,
5096
35d1a66a
BC		 5097 /* timer class */
5098 &omap44xx_timer1_hwmod,
5099 &omap44xx_timer2_hwmod,
5100 &omap44xx_timer3_hwmod,
5101 &omap44xx_timer4_hwmod,
5102 &omap44xx_timer5_hwmod,
5103 &omap44xx_timer6_hwmod,
5104 &omap44xx_timer7_hwmod,
5105 &omap44xx_timer8_hwmod,
5106 &omap44xx_timer9_hwmod,
5107 &omap44xx_timer10_hwmod,
5108 &omap44xx_timer11_hwmod,
5109
db12ba53
BC		 5110 /* uart class */
5111 &omap44xx_uart1_hwmod,
5112 &omap44xx_uart2_hwmod,
5113 &omap44xx_uart3_hwmod,
5114 &omap44xx_uart4_hwmod,
3b54baad 5115
5844c4ea
BC		 5116 /* usb_otg_hs class */
5117 &omap44xx_usb_otg_hs_hwmod,
5118
3b54baad
BC		 5119 /* wd_timer class */
5120 &omap44xx_wd_timer2_hwmod,
5121 &omap44xx_wd_timer3_hwmod,
5122
55d2cb08
BC		 5123 NULL,
5124};
5125
5126int __init omap44xx_hwmod_init(void)
5127{
550c8092 5128 return omap_hwmod_register(omap44xx_hwmods);
55d2cb08
BC		 5129}
5130
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