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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
3b9b1015 S |
15 | * Note that this file is currently not in sync with autogeneration scripts. |
16 | * The above note to be removed, once it is synced up. | |
55d2cb08 BC |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License version 2 as | |
20 | * published by the Free Software Foundation. | |
21 | */ | |
22 | ||
23 | #include <linux/io.h> | |
b86aeafc | 24 | #include <linux/power/smartreflex.h> |
55d2cb08 | 25 | |
45c3eb7d | 26 | #include <linux/omap-dma.h> |
2a296c8f | 27 | |
2a296c8f | 28 | #include "omap_hwmod.h" |
55d2cb08 | 29 | #include "omap_hwmod_common_data.h" |
d198b514 PW |
30 | #include "cm1_44xx.h" |
31 | #include "cm2_44xx.h" | |
32 | #include "prm44xx.h" | |
55d2cb08 | 33 | #include "prm-regbits-44xx.h" |
ff2516fb | 34 | #include "wd_timer.h" |
55d2cb08 BC |
35 | |
36 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
37 | #define OMAP44XX_IRQ_GIC_START 32 | |
38 | ||
39 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 40 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
41 | |
42 | /* | |
844a3b63 | 43 | * IP blocks |
55d2cb08 BC |
44 | */ |
45 | ||
46 | /* | |
47 | * 'dmm' class | |
48 | * instance(s): dmm | |
49 | */ | |
50 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 51 | .name = "dmm", |
55d2cb08 BC |
52 | }; |
53 | ||
7e69ed97 | 54 | /* dmm */ |
55d2cb08 BC |
55 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
56 | .name = "dmm", | |
57 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 58 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
59 | .prcm = { |
60 | .omap4 = { | |
61 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 62 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
63 | }, |
64 | }, | |
55d2cb08 BC |
65 | }; |
66 | ||
55d2cb08 BC |
67 | /* |
68 | * 'l3' class | |
69 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
70 | */ | |
71 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 72 | .name = "l3", |
55d2cb08 BC |
73 | }; |
74 | ||
7e69ed97 | 75 | /* l3_instr */ |
55d2cb08 BC |
76 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
77 | .name = "l3_instr", | |
78 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 79 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
80 | .prcm = { |
81 | .omap4 = { | |
82 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 83 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 84 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
85 | }, |
86 | }, | |
55d2cb08 BC |
87 | }; |
88 | ||
7e69ed97 | 89 | /* l3_main_1 */ |
55d2cb08 BC |
90 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
91 | .name = "l3_main_1", | |
92 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 93 | .clkdm_name = "l3_1_clkdm", |
d0f0631d BC |
94 | .prcm = { |
95 | .omap4 = { | |
96 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 97 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
98 | }, |
99 | }, | |
55d2cb08 BC |
100 | }; |
101 | ||
7e69ed97 | 102 | /* l3_main_2 */ |
55d2cb08 BC |
103 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
104 | .name = "l3_main_2", | |
105 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 106 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
107 | .prcm = { |
108 | .omap4 = { | |
109 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 110 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
111 | }, |
112 | }, | |
55d2cb08 BC |
113 | }; |
114 | ||
7e69ed97 | 115 | /* l3_main_3 */ |
55d2cb08 BC |
116 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
117 | .name = "l3_main_3", | |
118 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 119 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
120 | .prcm = { |
121 | .omap4 = { | |
122 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 123 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 124 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
125 | }, |
126 | }, | |
55d2cb08 BC |
127 | }; |
128 | ||
129 | /* | |
130 | * 'l4' class | |
131 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
132 | */ | |
133 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 134 | .name = "l4", |
55d2cb08 BC |
135 | }; |
136 | ||
7e69ed97 | 137 | /* l4_abe */ |
55d2cb08 BC |
138 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
139 | .name = "l4_abe", | |
140 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 141 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
142 | .prcm = { |
143 | .omap4 = { | |
144 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
ce80979a TK |
145 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
146 | .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, | |
46b3af27 | 147 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
d0f0631d BC |
148 | }, |
149 | }, | |
55d2cb08 BC |
150 | }; |
151 | ||
7e69ed97 | 152 | /* l4_cfg */ |
55d2cb08 BC |
153 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
154 | .name = "l4_cfg", | |
155 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 156 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
157 | .prcm = { |
158 | .omap4 = { | |
159 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 160 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
161 | }, |
162 | }, | |
55d2cb08 BC |
163 | }; |
164 | ||
7e69ed97 | 165 | /* l4_per */ |
55d2cb08 BC |
166 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
167 | .name = "l4_per", | |
168 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 169 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
170 | .prcm = { |
171 | .omap4 = { | |
172 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 173 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
174 | }, |
175 | }, | |
55d2cb08 BC |
176 | }; |
177 | ||
7e69ed97 | 178 | /* l4_wkup */ |
55d2cb08 BC |
179 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
180 | .name = "l4_wkup", | |
181 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 182 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
183 | .prcm = { |
184 | .omap4 = { | |
185 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 186 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
187 | }, |
188 | }, | |
55d2cb08 BC |
189 | }; |
190 | ||
f776471f | 191 | /* |
3b54baad BC |
192 | * 'mpu_bus' class |
193 | * instance(s): mpu_private | |
f776471f | 194 | */ |
3b54baad | 195 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 196 | .name = "mpu_bus", |
3b54baad | 197 | }; |
f776471f | 198 | |
7e69ed97 | 199 | /* mpu_private */ |
3b54baad BC |
200 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
201 | .name = "mpu_private", | |
202 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 203 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
204 | .prcm = { |
205 | .omap4 = { | |
206 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
207 | }, | |
208 | }, | |
3b54baad BC |
209 | }; |
210 | ||
9a817bc8 BC |
211 | /* |
212 | * 'ocp_wp_noc' class | |
213 | * instance(s): ocp_wp_noc | |
214 | */ | |
215 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
216 | .name = "ocp_wp_noc", | |
217 | }; | |
218 | ||
219 | /* ocp_wp_noc */ | |
220 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
221 | .name = "ocp_wp_noc", | |
222 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
223 | .clkdm_name = "l3_instr_clkdm", | |
224 | .prcm = { | |
225 | .omap4 = { | |
226 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
227 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
228 | .modulemode = MODULEMODE_HWCTRL, | |
229 | }, | |
230 | }, | |
231 | }; | |
232 | ||
3b54baad BC |
233 | /* |
234 | * Modules omap_hwmod structures | |
235 | * | |
236 | * The following IPs are excluded for the moment because: | |
237 | * - They do not need an explicit SW control using omap_hwmod API. | |
238 | * - They still need to be validated with the driver | |
239 | * properly adapted to omap_hwmod / omap_device | |
240 | * | |
96566043 | 241 | * usim |
3b54baad BC |
242 | */ |
243 | ||
407a6888 BC |
244 | /* |
245 | * 'aess' class | |
246 | * audio engine sub system | |
247 | */ | |
248 | ||
249 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
250 | .rev_offs = 0x0000, | |
251 | .sysc_offs = 0x0010, | |
252 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
253 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
254 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
255 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
256 | .sysc_fields = &omap_hwmod_sysc_type2, |
257 | }; | |
258 | ||
259 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
260 | .name = "aess", | |
261 | .sysc = &omap44xx_aess_sysc, | |
c02060d8 | 262 | .enable_preprogram = omap_hwmod_aess_preprogram, |
407a6888 BC |
263 | }; |
264 | ||
265 | /* aess */ | |
407a6888 BC |
266 | static struct omap_hwmod omap44xx_aess_hwmod = { |
267 | .name = "aess", | |
268 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 269 | .clkdm_name = "abe_clkdm", |
9f0c5996 | 270 | .main_clk = "aess_fclk", |
00fe610b | 271 | .prcm = { |
407a6888 | 272 | .omap4 = { |
d0f0631d | 273 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 274 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
ce80979a | 275 | .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, |
03fdefe5 | 276 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
277 | }, |
278 | }, | |
407a6888 BC |
279 | }; |
280 | ||
42b9e387 PW |
281 | /* |
282 | * 'c2c' class | |
283 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
284 | * soc | |
285 | */ | |
286 | ||
287 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
288 | .name = "c2c", | |
289 | }; | |
290 | ||
291 | /* c2c */ | |
42b9e387 PW |
292 | static struct omap_hwmod omap44xx_c2c_hwmod = { |
293 | .name = "c2c", | |
294 | .class = &omap44xx_c2c_hwmod_class, | |
295 | .clkdm_name = "d2d_clkdm", | |
42b9e387 PW |
296 | .prcm = { |
297 | .omap4 = { | |
298 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
299 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
300 | }, | |
301 | }, | |
302 | }; | |
303 | ||
407a6888 BC |
304 | /* |
305 | * 'counter' class | |
306 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
307 | */ | |
308 | ||
309 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
310 | .rev_offs = 0x0000, | |
311 | .sysc_offs = 0x0004, | |
312 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 313 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
314 | .sysc_fields = &omap_hwmod_sysc_type1, |
315 | }; | |
316 | ||
317 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
318 | .name = "counter", | |
319 | .sysc = &omap44xx_counter_sysc, | |
320 | }; | |
321 | ||
322 | /* counter_32k */ | |
407a6888 BC |
323 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
324 | .name = "counter_32k", | |
325 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 326 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
327 | .flags = HWMOD_SWSUP_SIDLE, |
328 | .main_clk = "sys_32k_ck", | |
00fe610b | 329 | .prcm = { |
407a6888 | 330 | .omap4 = { |
d0f0631d | 331 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 332 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
333 | }, |
334 | }, | |
407a6888 BC |
335 | }; |
336 | ||
a0b5d813 PW |
337 | /* |
338 | * 'ctrl_module' class | |
339 | * attila core control module + core pad control module + wkup pad control | |
340 | * module + attila wkup control module | |
341 | */ | |
342 | ||
343 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
344 | .rev_offs = 0x0000, | |
345 | .sysc_offs = 0x0010, | |
346 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
347 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
348 | SIDLE_SMART_WKUP), | |
349 | .sysc_fields = &omap_hwmod_sysc_type2, | |
350 | }; | |
351 | ||
352 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
353 | .name = "ctrl_module", | |
354 | .sysc = &omap44xx_ctrl_module_sysc, | |
355 | }; | |
356 | ||
357 | /* ctrl_module_core */ | |
a0b5d813 PW |
358 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { |
359 | .name = "ctrl_module_core", | |
360 | .class = &omap44xx_ctrl_module_hwmod_class, | |
361 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
362 | .prcm = { |
363 | .omap4 = { | |
364 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
365 | }, | |
366 | }, | |
a0b5d813 PW |
367 | }; |
368 | ||
369 | /* ctrl_module_pad_core */ | |
370 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
371 | .name = "ctrl_module_pad_core", | |
372 | .class = &omap44xx_ctrl_module_hwmod_class, | |
373 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
374 | .prcm = { |
375 | .omap4 = { | |
376 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
377 | }, | |
378 | }, | |
a0b5d813 PW |
379 | }; |
380 | ||
381 | /* ctrl_module_wkup */ | |
382 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
383 | .name = "ctrl_module_wkup", | |
384 | .class = &omap44xx_ctrl_module_hwmod_class, | |
385 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
386 | .prcm = { |
387 | .omap4 = { | |
388 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
389 | }, | |
390 | }, | |
a0b5d813 PW |
391 | }; |
392 | ||
393 | /* ctrl_module_pad_wkup */ | |
394 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
395 | .name = "ctrl_module_pad_wkup", | |
396 | .class = &omap44xx_ctrl_module_hwmod_class, | |
397 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
398 | .prcm = { |
399 | .omap4 = { | |
400 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
401 | }, | |
402 | }, | |
a0b5d813 PW |
403 | }; |
404 | ||
96566043 BC |
405 | /* |
406 | * 'debugss' class | |
407 | * debug and emulation sub system | |
408 | */ | |
409 | ||
410 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
411 | .name = "debugss", | |
412 | }; | |
413 | ||
414 | /* debugss */ | |
415 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
416 | .name = "debugss", | |
417 | .class = &omap44xx_debugss_hwmod_class, | |
418 | .clkdm_name = "emu_sys_clkdm", | |
419 | .main_clk = "trace_clk_div_ck", | |
420 | .prcm = { | |
421 | .omap4 = { | |
422 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
423 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
424 | }, | |
425 | }, | |
426 | }; | |
427 | ||
d7cf5f33 BC |
428 | /* |
429 | * 'dma' class | |
430 | * dma controller for data exchange between memory to memory (i.e. internal or | |
431 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
432 | */ | |
433 | ||
434 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
435 | .rev_offs = 0x0000, | |
436 | .sysc_offs = 0x002c, | |
437 | .syss_offs = 0x0028, | |
438 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
439 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
440 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
441 | SYSS_HAS_RESET_STATUS), | |
442 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
443 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
444 | .sysc_fields = &omap_hwmod_sysc_type1, | |
445 | }; | |
446 | ||
447 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
448 | .name = "dma", | |
449 | .sysc = &omap44xx_dma_sysc, | |
450 | }; | |
451 | ||
452 | /* dma dev_attr */ | |
453 | static struct omap_dma_dev_attr dma_dev_attr = { | |
454 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
455 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
456 | .lch_count = 32, | |
457 | }; | |
458 | ||
459 | /* dma_system */ | |
d7cf5f33 BC |
460 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
461 | .name = "dma_system", | |
462 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 463 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 BC |
464 | .main_clk = "l3_div_ck", |
465 | .prcm = { | |
466 | .omap4 = { | |
d0f0631d | 467 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 468 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
469 | }, |
470 | }, | |
471 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
472 | }; |
473 | ||
8ca476da BC |
474 | /* |
475 | * 'dmic' class | |
476 | * digital microphone controller | |
477 | */ | |
478 | ||
479 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
480 | .rev_offs = 0x0000, | |
481 | .sysc_offs = 0x0010, | |
482 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
483 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
484 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
485 | SIDLE_SMART_WKUP), | |
486 | .sysc_fields = &omap_hwmod_sysc_type2, | |
487 | }; | |
488 | ||
489 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
490 | .name = "dmic", | |
491 | .sysc = &omap44xx_dmic_sysc, | |
492 | }; | |
493 | ||
494 | /* dmic */ | |
8ca476da BC |
495 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
496 | .name = "dmic", | |
497 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 498 | .clkdm_name = "abe_clkdm", |
ee877acd | 499 | .main_clk = "func_dmic_abe_gfclk", |
00fe610b | 500 | .prcm = { |
8ca476da | 501 | .omap4 = { |
d0f0631d | 502 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 503 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 504 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
505 | }, |
506 | }, | |
8ca476da BC |
507 | }; |
508 | ||
8f25bdc5 BC |
509 | /* |
510 | * 'dsp' class | |
511 | * dsp sub-system | |
512 | */ | |
513 | ||
514 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 515 | .name = "dsp", |
8f25bdc5 BC |
516 | }; |
517 | ||
518 | /* dsp */ | |
8f25bdc5 | 519 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { |
8f25bdc5 BC |
520 | { .name = "dsp", .rst_shift = 0 }, |
521 | }; | |
522 | ||
8f25bdc5 BC |
523 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
524 | .name = "dsp", | |
525 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 526 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 BC |
527 | .rst_lines = omap44xx_dsp_resets, |
528 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
298ea44f | 529 | .main_clk = "dpll_iva_m4x2_ck", |
8f25bdc5 BC |
530 | .prcm = { |
531 | .omap4 = { | |
d0f0631d | 532 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 533 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 534 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 535 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
536 | }, |
537 | }, | |
8f25bdc5 BC |
538 | }; |
539 | ||
d63bd74f BC |
540 | /* |
541 | * 'dss' class | |
542 | * display sub-system | |
543 | */ | |
544 | ||
545 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
546 | .rev_offs = 0x0000, | |
547 | .syss_offs = 0x0014, | |
548 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
549 | }; | |
550 | ||
551 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
552 | .name = "dss", | |
553 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 554 | .reset = omap_dss_reset, |
d63bd74f BC |
555 | }; |
556 | ||
557 | /* dss */ | |
d63bd74f BC |
558 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
559 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
560 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 561 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
562 | }; |
563 | ||
564 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
565 | .name = "dss_core", | |
37ad0855 | 566 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 567 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 568 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 569 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
570 | .prcm = { |
571 | .omap4 = { | |
d0f0631d | 572 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 573 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
7ede8561 | 574 | .modulemode = MODULEMODE_SWCTRL, |
d63bd74f BC |
575 | }, |
576 | }, | |
577 | .opt_clks = dss_opt_clks, | |
578 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
579 | }; |
580 | ||
581 | /* | |
582 | * 'dispc' class | |
583 | * display controller | |
584 | */ | |
585 | ||
586 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
587 | .rev_offs = 0x0000, | |
588 | .sysc_offs = 0x0010, | |
589 | .syss_offs = 0x0014, | |
590 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
591 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
592 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
593 | SYSS_HAS_RESET_STATUS), | |
594 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
595 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
596 | .sysc_fields = &omap_hwmod_sysc_type1, | |
597 | }; | |
598 | ||
599 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
600 | .name = "dispc", | |
601 | .sysc = &omap44xx_dispc_sysc, | |
602 | }; | |
603 | ||
604 | /* dss_dispc */ | |
b923d40d AT |
605 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
606 | .manager_count = 3, | |
607 | .has_framedonetv_irq = 1 | |
608 | }; | |
609 | ||
d63bd74f BC |
610 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
611 | .name = "dss_dispc", | |
612 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 613 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 614 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
615 | .prcm = { |
616 | .omap4 = { | |
d0f0631d | 617 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 618 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
619 | }, |
620 | }, | |
543b2847 TV |
621 | .dev_attr = &omap44xx_dss_dispc_dev_attr, |
622 | .parent_hwmod = &omap44xx_dss_hwmod, | |
d63bd74f BC |
623 | }; |
624 | ||
625 | /* | |
626 | * 'dsi' class | |
627 | * display serial interface controller | |
628 | */ | |
629 | ||
630 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
631 | .rev_offs = 0x0000, | |
632 | .sysc_offs = 0x0010, | |
633 | .syss_offs = 0x0014, | |
634 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
635 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
636 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
637 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
638 | .sysc_fields = &omap_hwmod_sysc_type1, | |
639 | }; | |
640 | ||
641 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
642 | .name = "dsi", | |
643 | .sysc = &omap44xx_dsi_sysc, | |
644 | }; | |
645 | ||
646 | /* dss_dsi1 */ | |
3a23aafc TV |
647 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
648 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
649 | }; | |
650 | ||
d63bd74f BC |
651 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
652 | .name = "dss_dsi1", | |
653 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 654 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 655 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
656 | .prcm = { |
657 | .omap4 = { | |
d0f0631d | 658 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 659 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
660 | }, |
661 | }, | |
3a23aafc TV |
662 | .opt_clks = dss_dsi1_opt_clks, |
663 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
543b2847 | 664 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
665 | }; |
666 | ||
667 | /* dss_dsi2 */ | |
3a23aafc TV |
668 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
669 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
670 | }; | |
671 | ||
d63bd74f BC |
672 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
673 | .name = "dss_dsi2", | |
674 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 675 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 676 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
677 | .prcm = { |
678 | .omap4 = { | |
d0f0631d | 679 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 680 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
681 | }, |
682 | }, | |
3a23aafc TV |
683 | .opt_clks = dss_dsi2_opt_clks, |
684 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
543b2847 | 685 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
686 | }; |
687 | ||
688 | /* | |
689 | * 'hdmi' class | |
690 | * hdmi controller | |
691 | */ | |
692 | ||
693 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
694 | .rev_offs = 0x0000, | |
695 | .sysc_offs = 0x0010, | |
696 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
697 | SYSC_HAS_SOFTRESET), | |
698 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
699 | SIDLE_SMART_WKUP), | |
700 | .sysc_fields = &omap_hwmod_sysc_type2, | |
701 | }; | |
702 | ||
703 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
704 | .name = "hdmi", | |
705 | .sysc = &omap44xx_hdmi_sysc, | |
706 | }; | |
707 | ||
708 | /* dss_hdmi */ | |
3a23aafc TV |
709 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
710 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
24d8d498 | 711 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
3a23aafc TV |
712 | }; |
713 | ||
d63bd74f BC |
714 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
715 | .name = "dss_hdmi", | |
716 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 717 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
718 | /* |
719 | * HDMI audio requires to use no-idle mode. Hence, | |
720 | * set idle mode by software. | |
721 | */ | |
24d8d498 | 722 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED, |
4d0698d9 | 723 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
724 | .prcm = { |
725 | .omap4 = { | |
d0f0631d | 726 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 727 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
728 | }, |
729 | }, | |
3a23aafc TV |
730 | .opt_clks = dss_hdmi_opt_clks, |
731 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
543b2847 | 732 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
733 | }; |
734 | ||
735 | /* | |
736 | * 'rfbi' class | |
737 | * remote frame buffer interface | |
738 | */ | |
739 | ||
740 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
741 | .rev_offs = 0x0000, | |
742 | .sysc_offs = 0x0010, | |
743 | .syss_offs = 0x0014, | |
744 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
745 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
746 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
747 | .sysc_fields = &omap_hwmod_sysc_type1, | |
748 | }; | |
749 | ||
750 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
751 | .name = "rfbi", | |
752 | .sysc = &omap44xx_rfbi_sysc, | |
753 | }; | |
754 | ||
755 | /* dss_rfbi */ | |
3a23aafc | 756 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
2cc84f46 | 757 | { .role = "ick", .clk = "l3_div_ck" }, |
3a23aafc TV |
758 | }; |
759 | ||
d63bd74f BC |
760 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
761 | .name = "dss_rfbi", | |
762 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 763 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 764 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
765 | .prcm = { |
766 | .omap4 = { | |
d0f0631d | 767 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 768 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
769 | }, |
770 | }, | |
3a23aafc TV |
771 | .opt_clks = dss_rfbi_opt_clks, |
772 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
543b2847 | 773 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
774 | }; |
775 | ||
776 | /* | |
777 | * 'venc' class | |
778 | * video encoder | |
779 | */ | |
780 | ||
781 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
782 | .name = "venc", | |
783 | }; | |
784 | ||
785 | /* dss_venc */ | |
24d8d498 TK |
786 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
787 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
788 | }; | |
789 | ||
d63bd74f BC |
790 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
791 | .name = "dss_venc", | |
792 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 793 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 794 | .main_clk = "dss_tv_clk", |
24d8d498 | 795 | .flags = HWMOD_OPT_CLKS_NEEDED, |
d63bd74f BC |
796 | .prcm = { |
797 | .omap4 = { | |
d0f0631d | 798 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 799 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
800 | }, |
801 | }, | |
543b2847 | 802 | .parent_hwmod = &omap44xx_dss_hwmod, |
24d8d498 TK |
803 | .opt_clks = dss_venc_opt_clks, |
804 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
d63bd74f BC |
805 | }; |
806 | ||
1df5eaa6 TK |
807 | /* sha0 HIB2 (the 'P' (public) device) */ |
808 | static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = { | |
809 | .rev_offs = 0x100, | |
810 | .sysc_offs = 0x110, | |
811 | .syss_offs = 0x114, | |
812 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
813 | }; | |
814 | ||
815 | static struct omap_hwmod_class omap44xx_sha0_hwmod_class = { | |
816 | .name = "sham", | |
817 | .sysc = &omap44xx_sha0_sysc, | |
818 | }; | |
819 | ||
820 | struct omap_hwmod omap44xx_sha0_hwmod = { | |
821 | .name = "sham", | |
822 | .class = &omap44xx_sha0_hwmod_class, | |
823 | .clkdm_name = "l4_secure_clkdm", | |
824 | .main_clk = "l3_div_ck", | |
825 | .prcm = { | |
826 | .omap4 = { | |
827 | .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET, | |
828 | .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET, | |
829 | .modulemode = MODULEMODE_SWCTRL, | |
830 | }, | |
831 | }, | |
832 | }; | |
833 | ||
42b9e387 PW |
834 | /* |
835 | * 'elm' class | |
836 | * bch error location module | |
837 | */ | |
838 | ||
839 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
840 | .rev_offs = 0x0000, | |
841 | .sysc_offs = 0x0010, | |
842 | .syss_offs = 0x0014, | |
843 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
844 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
845 | SYSS_HAS_RESET_STATUS), | |
846 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
847 | .sysc_fields = &omap_hwmod_sysc_type1, | |
848 | }; | |
849 | ||
850 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
851 | .name = "elm", | |
852 | .sysc = &omap44xx_elm_sysc, | |
853 | }; | |
854 | ||
855 | /* elm */ | |
42b9e387 PW |
856 | static struct omap_hwmod omap44xx_elm_hwmod = { |
857 | .name = "elm", | |
858 | .class = &omap44xx_elm_hwmod_class, | |
859 | .clkdm_name = "l4_per_clkdm", | |
42b9e387 PW |
860 | .prcm = { |
861 | .omap4 = { | |
862 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
863 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
864 | }, | |
865 | }, | |
866 | }; | |
867 | ||
bf30f950 PW |
868 | /* |
869 | * 'emif' class | |
870 | * external memory interface no1 | |
871 | */ | |
872 | ||
873 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
874 | .rev_offs = 0x0000, | |
875 | }; | |
876 | ||
877 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
878 | .name = "emif", | |
879 | .sysc = &omap44xx_emif_sysc, | |
880 | }; | |
881 | ||
882 | /* emif1 */ | |
bf30f950 PW |
883 | static struct omap_hwmod omap44xx_emif1_hwmod = { |
884 | .name = "emif1", | |
885 | .class = &omap44xx_emif_hwmod_class, | |
886 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 887 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
888 | .main_clk = "ddrphy_ck", |
889 | .prcm = { | |
890 | .omap4 = { | |
891 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
892 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
893 | .modulemode = MODULEMODE_HWCTRL, | |
894 | }, | |
895 | }, | |
896 | }; | |
897 | ||
898 | /* emif2 */ | |
bf30f950 PW |
899 | static struct omap_hwmod omap44xx_emif2_hwmod = { |
900 | .name = "emif2", | |
901 | .class = &omap44xx_emif_hwmod_class, | |
902 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 903 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
904 | .main_clk = "ddrphy_ck", |
905 | .prcm = { | |
906 | .omap4 = { | |
907 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
908 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
909 | .modulemode = MODULEMODE_HWCTRL, | |
910 | }, | |
911 | }, | |
912 | }; | |
913 | ||
9a9ded89 SR |
914 | /* |
915 | Crypto modules AES0/1 belong to: | |
916 | PD_L4_PER power domain | |
917 | CD_L4_SEC clock domain | |
918 | On the L3, the AES modules are mapped to | |
919 | L3_CLK2: Peripherals and multimedia sub clock domain | |
920 | */ | |
921 | static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = { | |
922 | .rev_offs = 0x80, | |
923 | .sysc_offs = 0x84, | |
924 | .syss_offs = 0x88, | |
925 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
926 | }; | |
927 | ||
928 | static struct omap_hwmod_class omap44xx_aes_hwmod_class = { | |
929 | .name = "aes", | |
930 | .sysc = &omap44xx_aes_sysc, | |
931 | }; | |
932 | ||
933 | static struct omap_hwmod omap44xx_aes1_hwmod = { | |
934 | .name = "aes1", | |
935 | .class = &omap44xx_aes_hwmod_class, | |
936 | .clkdm_name = "l4_secure_clkdm", | |
937 | .main_clk = "l3_div_ck", | |
938 | .prcm = { | |
939 | .omap4 = { | |
940 | .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET, | |
941 | .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET, | |
942 | .modulemode = MODULEMODE_SWCTRL, | |
943 | }, | |
944 | }, | |
945 | }; | |
946 | ||
947 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = { | |
948 | .master = &omap44xx_l4_per_hwmod, | |
949 | .slave = &omap44xx_aes1_hwmod, | |
950 | .clk = "l3_div_ck", | |
951 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
952 | }; | |
953 | ||
478523dd SR |
954 | static struct omap_hwmod omap44xx_aes2_hwmod = { |
955 | .name = "aes2", | |
956 | .class = &omap44xx_aes_hwmod_class, | |
957 | .clkdm_name = "l4_secure_clkdm", | |
958 | .main_clk = "l3_div_ck", | |
959 | .prcm = { | |
960 | .omap4 = { | |
961 | .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET, | |
962 | .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET, | |
963 | .modulemode = MODULEMODE_SWCTRL, | |
964 | }, | |
965 | }, | |
966 | }; | |
967 | ||
968 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = { | |
969 | .master = &omap44xx_l4_per_hwmod, | |
970 | .slave = &omap44xx_aes2_hwmod, | |
971 | .clk = "l3_div_ck", | |
972 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
973 | }; | |
974 | ||
ebea90df SR |
975 | /* |
976 | * 'des' class for DES3DES module | |
977 | */ | |
978 | static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = { | |
979 | .rev_offs = 0x30, | |
980 | .sysc_offs = 0x34, | |
981 | .syss_offs = 0x38, | |
982 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
983 | }; | |
984 | ||
985 | static struct omap_hwmod_class omap44xx_des_hwmod_class = { | |
986 | .name = "des", | |
987 | .sysc = &omap44xx_des_sysc, | |
988 | }; | |
989 | ||
990 | static struct omap_hwmod omap44xx_des_hwmod = { | |
991 | .name = "des", | |
992 | .class = &omap44xx_des_hwmod_class, | |
993 | .clkdm_name = "l4_secure_clkdm", | |
994 | .main_clk = "l3_div_ck", | |
995 | .prcm = { | |
996 | .omap4 = { | |
997 | .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET, | |
998 | .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET, | |
999 | .modulemode = MODULEMODE_SWCTRL, | |
1000 | }, | |
1001 | }, | |
1002 | }; | |
1003 | ||
1004 | struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = { | |
1005 | .master = &omap44xx_l3_main_2_hwmod, | |
1006 | .slave = &omap44xx_des_hwmod, | |
1007 | .clk = "l3_div_ck", | |
1008 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1009 | }; | |
1010 | ||
b050f688 ML |
1011 | /* |
1012 | * 'fdif' class | |
1013 | * face detection hw accelerator module | |
1014 | */ | |
1015 | ||
1016 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
1017 | .rev_offs = 0x0000, | |
1018 | .sysc_offs = 0x0010, | |
1019 | /* | |
1020 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
1021 | * accessing sysconfig again. | |
1022 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1023 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1024 | * | |
1025 | * TODO: Indicate errata when available. | |
1026 | */ | |
1027 | .srst_udelay = 2, | |
1028 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
1029 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1030 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1031 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1032 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1033 | }; | |
1034 | ||
1035 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1036 | .name = "fdif", | |
1037 | .sysc = &omap44xx_fdif_sysc, | |
1038 | }; | |
1039 | ||
1040 | /* fdif */ | |
b050f688 ML |
1041 | static struct omap_hwmod omap44xx_fdif_hwmod = { |
1042 | .name = "fdif", | |
1043 | .class = &omap44xx_fdif_hwmod_class, | |
1044 | .clkdm_name = "iss_clkdm", | |
b050f688 ML |
1045 | .main_clk = "fdif_fck", |
1046 | .prcm = { | |
1047 | .omap4 = { | |
1048 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1049 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1050 | .modulemode = MODULEMODE_SWCTRL, | |
1051 | }, | |
1052 | }, | |
1053 | }; | |
1054 | ||
eb42b5d3 BC |
1055 | /* |
1056 | * 'gpmc' class | |
1057 | * general purpose memory controller | |
1058 | */ | |
1059 | ||
1060 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1061 | .rev_offs = 0x0000, | |
1062 | .sysc_offs = 0x0010, | |
1063 | .syss_offs = 0x0014, | |
1064 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1065 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1066 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1067 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1068 | }; | |
1069 | ||
1070 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1071 | .name = "gpmc", | |
1072 | .sysc = &omap44xx_gpmc_sysc, | |
1073 | }; | |
1074 | ||
1075 | /* gpmc */ | |
eb42b5d3 BC |
1076 | static struct omap_hwmod omap44xx_gpmc_hwmod = { |
1077 | .name = "gpmc", | |
1078 | .class = &omap44xx_gpmc_hwmod_class, | |
1079 | .clkdm_name = "l3_2_clkdm", | |
63aa945b TL |
1080 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
1081 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
eb42b5d3 BC |
1082 | .prcm = { |
1083 | .omap4 = { | |
1084 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1085 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1086 | .modulemode = MODULEMODE_HWCTRL, | |
1087 | }, | |
1088 | }, | |
1089 | }; | |
1090 | ||
9def390e PW |
1091 | /* |
1092 | * 'gpu' class | |
1093 | * 2d/3d graphics accelerator | |
1094 | */ | |
1095 | ||
1096 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1097 | .rev_offs = 0x1fc00, | |
1098 | .sysc_offs = 0x1fc10, | |
1099 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1100 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1101 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1102 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1103 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1104 | }; | |
1105 | ||
1106 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1107 | .name = "gpu", | |
1108 | .sysc = &omap44xx_gpu_sysc, | |
1109 | }; | |
1110 | ||
1111 | /* gpu */ | |
9def390e PW |
1112 | static struct omap_hwmod omap44xx_gpu_hwmod = { |
1113 | .name = "gpu", | |
1114 | .class = &omap44xx_gpu_hwmod_class, | |
1115 | .clkdm_name = "l3_gfx_clkdm", | |
ee877acd | 1116 | .main_clk = "sgx_clk_mux", |
9def390e PW |
1117 | .prcm = { |
1118 | .omap4 = { | |
1119 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1120 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1121 | .modulemode = MODULEMODE_SWCTRL, | |
1122 | }, | |
1123 | }, | |
1124 | }; | |
1125 | ||
a091c08e PW |
1126 | /* |
1127 | * 'hdq1w' class | |
1128 | * hdq / 1-wire serial interface controller | |
1129 | */ | |
1130 | ||
1131 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1132 | .rev_offs = 0x0000, | |
1133 | .sysc_offs = 0x0014, | |
1134 | .syss_offs = 0x0018, | |
1135 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1136 | SYSS_HAS_RESET_STATUS), | |
1137 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1138 | }; | |
1139 | ||
1140 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1141 | .name = "hdq1w", | |
1142 | .sysc = &omap44xx_hdq1w_sysc, | |
1143 | }; | |
1144 | ||
1145 | /* hdq1w */ | |
a091c08e PW |
1146 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { |
1147 | .name = "hdq1w", | |
1148 | .class = &omap44xx_hdq1w_hwmod_class, | |
1149 | .clkdm_name = "l4_per_clkdm", | |
1150 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
17b7e7d3 | 1151 | .main_clk = "func_12m_fclk", |
a091c08e PW |
1152 | .prcm = { |
1153 | .omap4 = { | |
1154 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1155 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1156 | .modulemode = MODULEMODE_SWCTRL, | |
1157 | }, | |
1158 | }, | |
1159 | }; | |
1160 | ||
407a6888 BC |
1161 | /* |
1162 | * 'hsi' class | |
1163 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1164 | * serial if) | |
1165 | */ | |
1166 | ||
1167 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1168 | .rev_offs = 0x0000, | |
1169 | .sysc_offs = 0x0010, | |
1170 | .syss_offs = 0x0014, | |
1171 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1172 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1173 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1174 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1175 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1176 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1177 | .sysc_fields = &omap_hwmod_sysc_type1, |
1178 | }; | |
1179 | ||
1180 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1181 | .name = "hsi", | |
1182 | .sysc = &omap44xx_hsi_sysc, | |
1183 | }; | |
1184 | ||
1185 | /* hsi */ | |
407a6888 BC |
1186 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1187 | .name = "hsi", | |
1188 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1189 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1190 | .main_clk = "hsi_fck", |
00fe610b | 1191 | .prcm = { |
407a6888 | 1192 | .omap4 = { |
d0f0631d | 1193 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1194 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1195 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1196 | }, |
1197 | }, | |
407a6888 BC |
1198 | }; |
1199 | ||
407a6888 BC |
1200 | /* |
1201 | * 'ipu' class | |
1202 | * imaging processor unit | |
1203 | */ | |
1204 | ||
1205 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1206 | .name = "ipu", | |
1207 | }; | |
1208 | ||
1209 | /* ipu */ | |
f2f5736c | 1210 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1211 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1212 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1213 | }; |
1214 | ||
407a6888 BC |
1215 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1216 | .name = "ipu", | |
1217 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1218 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
1219 | .rst_lines = omap44xx_ipu_resets, |
1220 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
298ea44f | 1221 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1222 | .prcm = { |
407a6888 | 1223 | .omap4 = { |
d0f0631d | 1224 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1225 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1226 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1227 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1228 | }, |
1229 | }, | |
407a6888 BC |
1230 | }; |
1231 | ||
1232 | /* | |
1233 | * 'iss' class | |
1234 | * external images sensor pixel data processor | |
1235 | */ | |
1236 | ||
1237 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1238 | .rev_offs = 0x0000, | |
1239 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1240 | /* |
1241 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1242 | * accessing sysconfig again. | |
1243 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1244 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1245 | * | |
1246 | * TODO: Indicate errata when available. | |
1247 | */ | |
1248 | .srst_udelay = 2, | |
407a6888 BC |
1249 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1250 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1251 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1252 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1253 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1254 | .sysc_fields = &omap_hwmod_sysc_type2, |
1255 | }; | |
1256 | ||
1257 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1258 | .name = "iss", | |
1259 | .sysc = &omap44xx_iss_sysc, | |
1260 | }; | |
1261 | ||
1262 | /* iss */ | |
407a6888 BC |
1263 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1264 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1265 | }; | |
1266 | ||
1267 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1268 | .name = "iss", | |
1269 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1270 | .clkdm_name = "iss_clkdm", |
17b7e7d3 | 1271 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1272 | .prcm = { |
407a6888 | 1273 | .omap4 = { |
d0f0631d | 1274 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1275 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1276 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1277 | }, |
1278 | }, | |
1279 | .opt_clks = iss_opt_clks, | |
1280 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1281 | }; |
1282 | ||
8f25bdc5 BC |
1283 | /* |
1284 | * 'iva' class | |
1285 | * multi-standard video encoder/decoder hardware accelerator | |
1286 | */ | |
1287 | ||
1288 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1289 | .name = "iva", |
8f25bdc5 BC |
1290 | }; |
1291 | ||
1292 | /* iva */ | |
8f25bdc5 | 1293 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { |
8f25bdc5 | 1294 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1295 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1296 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1297 | }; |
1298 | ||
8f25bdc5 BC |
1299 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1300 | .name = "iva", | |
1301 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1302 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
1303 | .rst_lines = omap44xx_iva_resets, |
1304 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
17b7e7d3 | 1305 | .main_clk = "dpll_iva_m5x2_ck", |
8f25bdc5 BC |
1306 | .prcm = { |
1307 | .omap4 = { | |
d0f0631d | 1308 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1309 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1310 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1311 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1312 | }, |
1313 | }, | |
8f25bdc5 BC |
1314 | }; |
1315 | ||
407a6888 BC |
1316 | /* |
1317 | * 'kbd' class | |
1318 | * keyboard controller | |
1319 | */ | |
1320 | ||
1321 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1322 | .rev_offs = 0x0000, | |
1323 | .sysc_offs = 0x0010, | |
1324 | .syss_offs = 0x0014, | |
1325 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1326 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1327 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1328 | SYSS_HAS_RESET_STATUS), | |
1329 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1330 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1331 | }; | |
1332 | ||
1333 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1334 | .name = "kbd", | |
1335 | .sysc = &omap44xx_kbd_sysc, | |
1336 | }; | |
1337 | ||
1338 | /* kbd */ | |
407a6888 BC |
1339 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1340 | .name = "kbd", | |
1341 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1342 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 1343 | .main_clk = "sys_32k_ck", |
00fe610b | 1344 | .prcm = { |
407a6888 | 1345 | .omap4 = { |
d0f0631d | 1346 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1347 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1348 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1349 | }, |
1350 | }, | |
407a6888 BC |
1351 | }; |
1352 | ||
ec5df927 BC |
1353 | /* |
1354 | * 'mailbox' class | |
1355 | * mailbox module allowing communication between the on-chip processors using a | |
1356 | * queued mailbox-interrupt mechanism. | |
1357 | */ | |
1358 | ||
1359 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1360 | .rev_offs = 0x0000, | |
1361 | .sysc_offs = 0x0010, | |
1362 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1363 | SYSC_HAS_SOFTRESET), | |
1364 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1365 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1366 | }; | |
1367 | ||
1368 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1369 | .name = "mailbox", | |
1370 | .sysc = &omap44xx_mailbox_sysc, | |
1371 | }; | |
1372 | ||
1373 | /* mailbox */ | |
ec5df927 BC |
1374 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1375 | .name = "mailbox", | |
1376 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1377 | .clkdm_name = "l4_cfg_clkdm", |
00fe610b | 1378 | .prcm = { |
ec5df927 | 1379 | .omap4 = { |
d0f0631d | 1380 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1381 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1382 | }, |
1383 | }, | |
ec5df927 BC |
1384 | }; |
1385 | ||
896d4e98 BC |
1386 | /* |
1387 | * 'mcasp' class | |
1388 | * multi-channel audio serial port controller | |
1389 | */ | |
1390 | ||
1391 | /* The IP is not compliant to type1 / type2 scheme */ | |
896d4e98 | 1392 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { |
103fd8e7 | 1393 | .rev_offs = 0, |
896d4e98 BC |
1394 | .sysc_offs = 0x0004, |
1395 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1396 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1397 | SIDLE_SMART_WKUP), | |
1398 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1399 | }; | |
1400 | ||
1401 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1402 | .name = "mcasp", | |
1403 | .sysc = &omap44xx_mcasp_sysc, | |
1404 | }; | |
1405 | ||
1406 | /* mcasp */ | |
896d4e98 BC |
1407 | static struct omap_hwmod omap44xx_mcasp_hwmod = { |
1408 | .name = "mcasp", | |
1409 | .class = &omap44xx_mcasp_hwmod_class, | |
1410 | .clkdm_name = "abe_clkdm", | |
ee877acd | 1411 | .main_clk = "func_mcasp_abe_gfclk", |
896d4e98 BC |
1412 | .prcm = { |
1413 | .omap4 = { | |
1414 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1415 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1416 | .modulemode = MODULEMODE_SWCTRL, | |
1417 | }, | |
1418 | }, | |
1419 | }; | |
1420 | ||
4ddff493 BC |
1421 | /* |
1422 | * 'mcbsp' class | |
1423 | * multi channel buffered serial port controller | |
1424 | */ | |
1425 | ||
1426 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
103fd8e7 | 1427 | .rev_offs = -ENODEV, |
4ddff493 BC |
1428 | .sysc_offs = 0x008c, |
1429 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1430 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1431 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1432 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1433 | }; | |
1434 | ||
1435 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1436 | .name = "mcbsp", | |
1437 | .sysc = &omap44xx_mcbsp_sysc, | |
1438 | }; | |
1439 | ||
1440 | /* mcbsp1 */ | |
503d0ea2 PW |
1441 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1442 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1443 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1444 | }; |
1445 | ||
4ddff493 BC |
1446 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1447 | .name = "mcbsp1", | |
1448 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1449 | .clkdm_name = "abe_clkdm", |
ee877acd | 1450 | .main_clk = "func_mcbsp1_gfclk", |
4ddff493 BC |
1451 | .prcm = { |
1452 | .omap4 = { | |
d0f0631d | 1453 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1454 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1455 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1456 | }, |
1457 | }, | |
503d0ea2 PW |
1458 | .opt_clks = mcbsp1_opt_clks, |
1459 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1460 | }; |
1461 | ||
1462 | /* mcbsp2 */ | |
844a3b63 PW |
1463 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1464 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1465 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
1466 | }; |
1467 | ||
4ddff493 BC |
1468 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1469 | .name = "mcbsp2", | |
1470 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1471 | .clkdm_name = "abe_clkdm", |
ee877acd | 1472 | .main_clk = "func_mcbsp2_gfclk", |
4ddff493 BC |
1473 | .prcm = { |
1474 | .omap4 = { | |
d0f0631d | 1475 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1476 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1477 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1478 | }, |
1479 | }, | |
503d0ea2 PW |
1480 | .opt_clks = mcbsp2_opt_clks, |
1481 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1482 | }; |
1483 | ||
1484 | /* mcbsp3 */ | |
503d0ea2 PW |
1485 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1486 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1487 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
1488 | }; |
1489 | ||
4ddff493 BC |
1490 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1491 | .name = "mcbsp3", | |
1492 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1493 | .clkdm_name = "abe_clkdm", |
ee877acd | 1494 | .main_clk = "func_mcbsp3_gfclk", |
4ddff493 BC |
1495 | .prcm = { |
1496 | .omap4 = { | |
d0f0631d | 1497 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1498 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1499 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1500 | }, |
1501 | }, | |
503d0ea2 PW |
1502 | .opt_clks = mcbsp3_opt_clks, |
1503 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1504 | }; |
1505 | ||
1506 | /* mcbsp4 */ | |
503d0ea2 PW |
1507 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
1508 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1509 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
1510 | }; |
1511 | ||
4ddff493 BC |
1512 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
1513 | .name = "mcbsp4", | |
1514 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1515 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 1516 | .main_clk = "per_mcbsp4_gfclk", |
4ddff493 BC |
1517 | .prcm = { |
1518 | .omap4 = { | |
d0f0631d | 1519 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 1520 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 1521 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1522 | }, |
1523 | }, | |
503d0ea2 PW |
1524 | .opt_clks = mcbsp4_opt_clks, |
1525 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
1526 | }; |
1527 | ||
407a6888 BC |
1528 | /* |
1529 | * 'mcpdm' class | |
1530 | * multi channel pdm controller (proprietary interface with phoenix power | |
1531 | * ic) | |
1532 | */ | |
1533 | ||
1534 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
1535 | .rev_offs = 0x0000, | |
1536 | .sysc_offs = 0x0010, | |
1537 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1538 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1539 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1540 | SIDLE_SMART_WKUP), | |
1541 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1542 | }; | |
1543 | ||
1544 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
1545 | .name = "mcpdm", | |
1546 | .sysc = &omap44xx_mcpdm_sysc, | |
1547 | }; | |
1548 | ||
1549 | /* mcpdm */ | |
407a6888 BC |
1550 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
1551 | .name = "mcpdm", | |
1552 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 1553 | .clkdm_name = "abe_clkdm", |
bc05244e PW |
1554 | /* |
1555 | * It's suspected that the McPDM requires an off-chip main | |
1556 | * functional clock, controlled via I2C. This IP block is | |
1557 | * currently reset very early during boot, before I2C is | |
1558 | * available, so it doesn't seem that we have any choice in | |
1559 | * the kernel other than to avoid resetting it. | |
12d82e4b PU |
1560 | * |
1561 | * Also, McPDM needs to be configured to NO_IDLE mode when it | |
1562 | * is in used otherwise vital clocks will be gated which | |
1563 | * results 'slow motion' audio playback. | |
bc05244e | 1564 | */ |
12d82e4b | 1565 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, |
17b7e7d3 | 1566 | .main_clk = "pad_clks_ck", |
00fe610b | 1567 | .prcm = { |
407a6888 | 1568 | .omap4 = { |
d0f0631d | 1569 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 1570 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 1571 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1572 | }, |
1573 | }, | |
407a6888 BC |
1574 | }; |
1575 | ||
230844db ORL |
1576 | /* |
1577 | * 'mmu' class | |
1578 | * The memory management unit performs virtual to physical address translation | |
1579 | * for its requestors. | |
1580 | */ | |
1581 | ||
1582 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
1583 | .rev_offs = 0x000, | |
1584 | .sysc_offs = 0x010, | |
1585 | .syss_offs = 0x014, | |
1586 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1587 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1588 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1589 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1590 | }; | |
1591 | ||
1592 | static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { | |
1593 | .name = "mmu", | |
1594 | .sysc = &mmu_sysc, | |
1595 | }; | |
1596 | ||
1597 | /* mmu ipu */ | |
1598 | ||
230844db | 1599 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; |
230844db ORL |
1600 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { |
1601 | { .name = "mmu_cache", .rst_shift = 2 }, | |
1602 | }; | |
1603 | ||
230844db ORL |
1604 | /* l3_main_2 -> mmu_ipu */ |
1605 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { | |
1606 | .master = &omap44xx_l3_main_2_hwmod, | |
1607 | .slave = &omap44xx_mmu_ipu_hwmod, | |
1608 | .clk = "l3_div_ck", | |
230844db ORL |
1609 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1610 | }; | |
1611 | ||
1612 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |
1613 | .name = "mmu_ipu", | |
1614 | .class = &omap44xx_mmu_hwmod_class, | |
1615 | .clkdm_name = "ducati_clkdm", | |
230844db ORL |
1616 | .rst_lines = omap44xx_mmu_ipu_resets, |
1617 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | |
1618 | .main_clk = "ducati_clk_mux_ck", | |
1619 | .prcm = { | |
1620 | .omap4 = { | |
1621 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, | |
1622 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, | |
1623 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, | |
1624 | .modulemode = MODULEMODE_HWCTRL, | |
1625 | }, | |
1626 | }, | |
230844db ORL |
1627 | }; |
1628 | ||
1629 | /* mmu dsp */ | |
1630 | ||
230844db | 1631 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; |
230844db ORL |
1632 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { |
1633 | { .name = "mmu_cache", .rst_shift = 1 }, | |
1634 | }; | |
1635 | ||
230844db ORL |
1636 | /* l4_cfg -> dsp */ |
1637 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { | |
1638 | .master = &omap44xx_l4_cfg_hwmod, | |
1639 | .slave = &omap44xx_mmu_dsp_hwmod, | |
1640 | .clk = "l4_div_ck", | |
230844db ORL |
1641 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1642 | }; | |
1643 | ||
1644 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |
1645 | .name = "mmu_dsp", | |
1646 | .class = &omap44xx_mmu_hwmod_class, | |
1647 | .clkdm_name = "tesla_clkdm", | |
230844db ORL |
1648 | .rst_lines = omap44xx_mmu_dsp_resets, |
1649 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | |
1650 | .main_clk = "dpll_iva_m4x2_ck", | |
1651 | .prcm = { | |
1652 | .omap4 = { | |
1653 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, | |
1654 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, | |
1655 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, | |
1656 | .modulemode = MODULEMODE_HWCTRL, | |
1657 | }, | |
1658 | }, | |
230844db ORL |
1659 | }; |
1660 | ||
3b54baad BC |
1661 | /* |
1662 | * 'mpu' class | |
1663 | * mpu sub-system | |
1664 | */ | |
1665 | ||
1666 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 1667 | .name = "mpu", |
db12ba53 BC |
1668 | }; |
1669 | ||
3b54baad | 1670 | /* mpu */ |
3b54baad BC |
1671 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
1672 | .name = "mpu", | |
1673 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 1674 | .clkdm_name = "mpuss_clkdm", |
b2eb0002 | 1675 | .flags = HWMOD_INIT_NO_IDLE, |
3b54baad | 1676 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
1677 | .prcm = { |
1678 | .omap4 = { | |
d0f0631d | 1679 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 1680 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
1681 | }, |
1682 | }, | |
db12ba53 BC |
1683 | }; |
1684 | ||
e17f18c0 PW |
1685 | /* |
1686 | * 'ocmc_ram' class | |
1687 | * top-level core on-chip ram | |
1688 | */ | |
1689 | ||
1690 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
1691 | .name = "ocmc_ram", | |
1692 | }; | |
1693 | ||
1694 | /* ocmc_ram */ | |
1695 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
1696 | .name = "ocmc_ram", | |
1697 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
1698 | .clkdm_name = "l3_2_clkdm", | |
1699 | .prcm = { | |
1700 | .omap4 = { | |
1701 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
1702 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
1703 | }, | |
1704 | }, | |
1705 | }; | |
1706 | ||
0c668875 BC |
1707 | /* |
1708 | * 'ocp2scp' class | |
1709 | * bridge to transform ocp interface protocol to scp (serial control port) | |
1710 | * protocol | |
1711 | */ | |
1712 | ||
33c976ec BC |
1713 | static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { |
1714 | .rev_offs = 0x0000, | |
1715 | .sysc_offs = 0x0010, | |
1716 | .syss_offs = 0x0014, | |
1717 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1718 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1719 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1720 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1721 | }; | |
1722 | ||
0c668875 BC |
1723 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { |
1724 | .name = "ocp2scp", | |
33c976ec | 1725 | .sysc = &omap44xx_ocp2scp_sysc, |
0c668875 BC |
1726 | }; |
1727 | ||
1728 | /* ocp2scp_usb_phy */ | |
0c668875 BC |
1729 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
1730 | .name = "ocp2scp_usb_phy", | |
1731 | .class = &omap44xx_ocp2scp_hwmod_class, | |
1732 | .clkdm_name = "l3_init_clkdm", | |
f4d7a536 KVA |
1733 | /* |
1734 | * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP | |
1735 | * block as an "optional clock," and normally should never be | |
1736 | * specified as the main_clk for an OMAP IP block. However it | |
1737 | * turns out that this clock is actually the main clock for | |
1738 | * the ocp2scp_usb_phy IP block: | |
1739 | * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html | |
1740 | * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems | |
1741 | * to be the best workaround. | |
1742 | */ | |
1743 | .main_clk = "ocp2scp_usb_phy_phy_48m", | |
0c668875 BC |
1744 | .prcm = { |
1745 | .omap4 = { | |
1746 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
1747 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
1748 | .modulemode = MODULEMODE_HWCTRL, | |
1749 | }, | |
1750 | }, | |
0c668875 BC |
1751 | }; |
1752 | ||
794b480a PW |
1753 | /* |
1754 | * 'prcm' class | |
1755 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
1756 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
1757 | */ | |
1758 | ||
1759 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
1760 | .name = "prcm", | |
1761 | }; | |
1762 | ||
1763 | /* prcm_mpu */ | |
1764 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
1765 | .name = "prcm_mpu", | |
1766 | .class = &omap44xx_prcm_hwmod_class, | |
1767 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 1768 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
1769 | .prcm = { |
1770 | .omap4 = { | |
1771 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
1772 | }, | |
1773 | }, | |
794b480a PW |
1774 | }; |
1775 | ||
1776 | /* cm_core_aon */ | |
1777 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
1778 | .name = "cm_core_aon", | |
1779 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 1780 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
1781 | .prcm = { |
1782 | .omap4 = { | |
1783 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
1784 | }, | |
1785 | }, | |
794b480a PW |
1786 | }; |
1787 | ||
1788 | /* cm_core */ | |
1789 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
1790 | .name = "cm_core", | |
1791 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 1792 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
1793 | .prcm = { |
1794 | .omap4 = { | |
1795 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
1796 | }, | |
1797 | }, | |
794b480a PW |
1798 | }; |
1799 | ||
1800 | /* prm */ | |
794b480a PW |
1801 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { |
1802 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
1803 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
1804 | }; | |
1805 | ||
1806 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
1807 | .name = "prm", | |
1808 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
1809 | .rst_lines = omap44xx_prm_resets, |
1810 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
1811 | }; | |
1812 | ||
1813 | /* | |
1814 | * 'scrm' class | |
1815 | * system clock and reset manager | |
1816 | */ | |
1817 | ||
1818 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
1819 | .name = "scrm", | |
1820 | }; | |
1821 | ||
1822 | /* scrm */ | |
1823 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
1824 | .name = "scrm", | |
1825 | .class = &omap44xx_scrm_hwmod_class, | |
1826 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
1827 | .prcm = { |
1828 | .omap4 = { | |
1829 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
1830 | }, | |
1831 | }, | |
794b480a PW |
1832 | }; |
1833 | ||
42b9e387 PW |
1834 | /* |
1835 | * 'sl2if' class | |
1836 | * shared level 2 memory interface | |
1837 | */ | |
1838 | ||
1839 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
1840 | .name = "sl2if", | |
1841 | }; | |
1842 | ||
1843 | /* sl2if */ | |
1844 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
1845 | .name = "sl2if", | |
1846 | .class = &omap44xx_sl2if_hwmod_class, | |
1847 | .clkdm_name = "ivahd_clkdm", | |
1848 | .prcm = { | |
1849 | .omap4 = { | |
1850 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
1851 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
1852 | .modulemode = MODULEMODE_HWCTRL, | |
1853 | }, | |
1854 | }, | |
1855 | }; | |
1856 | ||
1e3b5e59 BC |
1857 | /* |
1858 | * 'slimbus' class | |
1859 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
1860 | * the device and external components | |
1861 | */ | |
1862 | ||
1863 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
1864 | .rev_offs = 0x0000, | |
1865 | .sysc_offs = 0x0010, | |
1866 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1867 | SYSC_HAS_SOFTRESET), | |
1868 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1869 | SIDLE_SMART_WKUP), | |
1870 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1871 | }; | |
1872 | ||
1873 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
1874 | .name = "slimbus", | |
1875 | .sysc = &omap44xx_slimbus_sysc, | |
1876 | }; | |
1877 | ||
1878 | /* slimbus1 */ | |
1e3b5e59 BC |
1879 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { |
1880 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
1881 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
1882 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
1883 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
1884 | }; | |
1885 | ||
1886 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
1887 | .name = "slimbus1", | |
1888 | .class = &omap44xx_slimbus_hwmod_class, | |
1889 | .clkdm_name = "abe_clkdm", | |
1e3b5e59 BC |
1890 | .prcm = { |
1891 | .omap4 = { | |
1892 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
1893 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
1894 | .modulemode = MODULEMODE_SWCTRL, | |
1895 | }, | |
1896 | }, | |
1897 | .opt_clks = slimbus1_opt_clks, | |
1898 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
1899 | }; | |
1900 | ||
1901 | /* slimbus2 */ | |
1e3b5e59 BC |
1902 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { |
1903 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
1904 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
1905 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
1906 | }; | |
1907 | ||
1908 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
1909 | .name = "slimbus2", | |
1910 | .class = &omap44xx_slimbus_hwmod_class, | |
1911 | .clkdm_name = "l4_per_clkdm", | |
1e3b5e59 BC |
1912 | .prcm = { |
1913 | .omap4 = { | |
1914 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
1915 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
1916 | .modulemode = MODULEMODE_SWCTRL, | |
1917 | }, | |
1918 | }, | |
1919 | .opt_clks = slimbus2_opt_clks, | |
1920 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
1921 | }; | |
1922 | ||
1f6a717f BC |
1923 | /* |
1924 | * 'smartreflex' class | |
1925 | * smartreflex module (monitor silicon performance and outputs a measure of | |
1926 | * performance error) | |
1927 | */ | |
1928 | ||
1929 | /* The IP is not compliant to type1 / type2 scheme */ | |
1f6a717f | 1930 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { |
103fd8e7 | 1931 | .rev_offs = -ENODEV, |
1f6a717f BC |
1932 | .sysc_offs = 0x0038, |
1933 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
1934 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1935 | SIDLE_SMART_WKUP), | |
bf807052 | 1936 | .sysc_fields = &omap36xx_sr_sysc_fields, |
1f6a717f BC |
1937 | }; |
1938 | ||
1939 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
1940 | .name = "smartreflex", |
1941 | .sysc = &omap44xx_smartreflex_sysc, | |
1f6a717f BC |
1942 | }; |
1943 | ||
1944 | /* smartreflex_core */ | |
cea6b942 SG |
1945 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
1946 | .sensor_voltdm_name = "core", | |
1947 | }; | |
1948 | ||
1f6a717f BC |
1949 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
1950 | .name = "smartreflex_core", | |
1951 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 1952 | .clkdm_name = "l4_ao_clkdm", |
212738a4 | 1953 | |
1f6a717f | 1954 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
1955 | .prcm = { |
1956 | .omap4 = { | |
d0f0631d | 1957 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 1958 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 1959 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
1960 | }, |
1961 | }, | |
cea6b942 | 1962 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
1963 | }; |
1964 | ||
1965 | /* smartreflex_iva */ | |
cea6b942 SG |
1966 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
1967 | .sensor_voltdm_name = "iva", | |
1968 | }; | |
1969 | ||
1f6a717f BC |
1970 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
1971 | .name = "smartreflex_iva", | |
1972 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 1973 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 1974 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
1975 | .prcm = { |
1976 | .omap4 = { | |
d0f0631d | 1977 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 1978 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 1979 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
1980 | }, |
1981 | }, | |
cea6b942 | 1982 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
1983 | }; |
1984 | ||
1985 | /* smartreflex_mpu */ | |
cea6b942 SG |
1986 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
1987 | .sensor_voltdm_name = "mpu", | |
1988 | }; | |
1989 | ||
1f6a717f BC |
1990 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
1991 | .name = "smartreflex_mpu", | |
1992 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 1993 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 1994 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
1995 | .prcm = { |
1996 | .omap4 = { | |
d0f0631d | 1997 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 1998 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 1999 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2000 | }, |
2001 | }, | |
cea6b942 | 2002 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2003 | }; |
2004 | ||
d11c217f BC |
2005 | /* |
2006 | * 'spinlock' class | |
2007 | * spinlock provides hardware assistance for synchronizing the processes | |
2008 | * running on multiple processors | |
2009 | */ | |
2010 | ||
2011 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2012 | .rev_offs = 0x0000, | |
2013 | .sysc_offs = 0x0010, | |
2014 | .syss_offs = 0x0014, | |
2015 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2016 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2017 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
77319669 | 2018 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
d11c217f BC |
2019 | .sysc_fields = &omap_hwmod_sysc_type1, |
2020 | }; | |
2021 | ||
2022 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2023 | .name = "spinlock", | |
2024 | .sysc = &omap44xx_spinlock_sysc, | |
2025 | }; | |
2026 | ||
2027 | /* spinlock */ | |
d11c217f BC |
2028 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2029 | .name = "spinlock", | |
2030 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2031 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2032 | .prcm = { |
2033 | .omap4 = { | |
d0f0631d | 2034 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2035 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2036 | }, |
2037 | }, | |
d11c217f BC |
2038 | }; |
2039 | ||
35d1a66a BC |
2040 | /* |
2041 | * 'timer' class | |
2042 | * general purpose timer module with accurate 1ms tick | |
2043 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2044 | */ | |
2045 | ||
2046 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2047 | .rev_offs = 0x0000, | |
2048 | .sysc_offs = 0x0010, | |
2049 | .syss_offs = 0x0014, | |
2050 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2051 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2052 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2053 | SYSS_HAS_RESET_STATUS), | |
2054 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2055 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2056 | }; | |
2057 | ||
2058 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2059 | .name = "timer", | |
2060 | .sysc = &omap44xx_timer_1ms_sysc, | |
2061 | }; | |
2062 | ||
2063 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2064 | .rev_offs = 0x0000, | |
2065 | .sysc_offs = 0x0010, | |
2066 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2067 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2068 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2069 | SIDLE_SMART_WKUP), | |
2070 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2071 | }; | |
2072 | ||
2073 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2074 | .name = "timer", | |
2075 | .sysc = &omap44xx_timer_sysc, | |
2076 | }; | |
2077 | ||
2078 | /* timer1 */ | |
35d1a66a BC |
2079 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2080 | .name = "timer1", | |
2081 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2082 | .clkdm_name = "l4_wkup_clkdm", |
10759e82 | 2083 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2084 | .main_clk = "dmt1_clk_mux", |
35d1a66a BC |
2085 | .prcm = { |
2086 | .omap4 = { | |
d0f0631d | 2087 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2088 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2089 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2090 | }, |
2091 | }, | |
35d1a66a BC |
2092 | }; |
2093 | ||
2094 | /* timer2 */ | |
35d1a66a BC |
2095 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2096 | .name = "timer2", | |
2097 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2098 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2099 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2100 | .main_clk = "cm2_dm2_mux", |
35d1a66a BC |
2101 | .prcm = { |
2102 | .omap4 = { | |
d0f0631d | 2103 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2104 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2105 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2106 | }, |
2107 | }, | |
35d1a66a BC |
2108 | }; |
2109 | ||
2110 | /* timer3 */ | |
35d1a66a BC |
2111 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2112 | .name = "timer3", | |
2113 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2114 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2115 | .main_clk = "cm2_dm3_mux", |
35d1a66a BC |
2116 | .prcm = { |
2117 | .omap4 = { | |
d0f0631d | 2118 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2119 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2120 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2121 | }, |
2122 | }, | |
35d1a66a BC |
2123 | }; |
2124 | ||
2125 | /* timer4 */ | |
35d1a66a BC |
2126 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2127 | .name = "timer4", | |
2128 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2129 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2130 | .main_clk = "cm2_dm4_mux", |
35d1a66a BC |
2131 | .prcm = { |
2132 | .omap4 = { | |
d0f0631d | 2133 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2134 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2135 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2136 | }, |
2137 | }, | |
35d1a66a BC |
2138 | }; |
2139 | ||
2140 | /* timer5 */ | |
35d1a66a BC |
2141 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2142 | .name = "timer5", | |
2143 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2144 | .clkdm_name = "abe_clkdm", |
ee877acd | 2145 | .main_clk = "timer5_sync_mux", |
35d1a66a BC |
2146 | .prcm = { |
2147 | .omap4 = { | |
d0f0631d | 2148 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2149 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2150 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2151 | }, |
2152 | }, | |
35d1a66a BC |
2153 | }; |
2154 | ||
2155 | /* timer6 */ | |
35d1a66a BC |
2156 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
2157 | .name = "timer6", | |
2158 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2159 | .clkdm_name = "abe_clkdm", |
ee877acd | 2160 | .main_clk = "timer6_sync_mux", |
35d1a66a BC |
2161 | .prcm = { |
2162 | .omap4 = { | |
d0f0631d | 2163 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 2164 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 2165 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2166 | }, |
2167 | }, | |
35d1a66a BC |
2168 | }; |
2169 | ||
2170 | /* timer7 */ | |
35d1a66a BC |
2171 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
2172 | .name = "timer7", | |
2173 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2174 | .clkdm_name = "abe_clkdm", |
ee877acd | 2175 | .main_clk = "timer7_sync_mux", |
35d1a66a BC |
2176 | .prcm = { |
2177 | .omap4 = { | |
d0f0631d | 2178 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 2179 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 2180 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2181 | }, |
2182 | }, | |
35d1a66a BC |
2183 | }; |
2184 | ||
2185 | /* timer8 */ | |
35d1a66a BC |
2186 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
2187 | .name = "timer8", | |
2188 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2189 | .clkdm_name = "abe_clkdm", |
ee877acd | 2190 | .main_clk = "timer8_sync_mux", |
35d1a66a BC |
2191 | .prcm = { |
2192 | .omap4 = { | |
d0f0631d | 2193 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 2194 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 2195 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2196 | }, |
2197 | }, | |
35d1a66a BC |
2198 | }; |
2199 | ||
2200 | /* timer9 */ | |
35d1a66a BC |
2201 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
2202 | .name = "timer9", | |
2203 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2204 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2205 | .main_clk = "cm2_dm9_mux", |
35d1a66a BC |
2206 | .prcm = { |
2207 | .omap4 = { | |
d0f0631d | 2208 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 2209 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 2210 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2211 | }, |
2212 | }, | |
35d1a66a BC |
2213 | }; |
2214 | ||
2215 | /* timer10 */ | |
35d1a66a BC |
2216 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
2217 | .name = "timer10", | |
2218 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2219 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2220 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2221 | .main_clk = "cm2_dm10_mux", |
35d1a66a BC |
2222 | .prcm = { |
2223 | .omap4 = { | |
d0f0631d | 2224 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 2225 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 2226 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2227 | }, |
2228 | }, | |
35d1a66a BC |
2229 | }; |
2230 | ||
2231 | /* timer11 */ | |
35d1a66a BC |
2232 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
2233 | .name = "timer11", | |
2234 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2235 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2236 | .main_clk = "cm2_dm11_mux", |
35d1a66a BC |
2237 | .prcm = { |
2238 | .omap4 = { | |
d0f0631d | 2239 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 2240 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 2241 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2242 | }, |
2243 | }, | |
35d1a66a BC |
2244 | }; |
2245 | ||
0c668875 BC |
2246 | /* |
2247 | * 'usb_host_fs' class | |
2248 | * full-speed usb host controller | |
2249 | */ | |
2250 | ||
2251 | /* The IP is not compliant to type1 / type2 scheme */ | |
0c668875 BC |
2252 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { |
2253 | .rev_offs = 0x0000, | |
2254 | .sysc_offs = 0x0210, | |
2255 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2256 | SYSC_HAS_SOFTRESET), | |
2257 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2258 | SIDLE_SMART_WKUP), | |
2259 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
2260 | }; | |
2261 | ||
2262 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
2263 | .name = "usb_host_fs", | |
2264 | .sysc = &omap44xx_usb_host_fs_sysc, | |
2265 | }; | |
2266 | ||
2267 | /* usb_host_fs */ | |
0c668875 BC |
2268 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { |
2269 | .name = "usb_host_fs", | |
2270 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
2271 | .clkdm_name = "l3_init_clkdm", | |
0c668875 BC |
2272 | .main_clk = "usb_host_fs_fck", |
2273 | .prcm = { | |
2274 | .omap4 = { | |
2275 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
2276 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
2277 | .modulemode = MODULEMODE_SWCTRL, | |
2278 | }, | |
2279 | }, | |
2280 | }; | |
2281 | ||
5844c4ea | 2282 | /* |
844a3b63 PW |
2283 | * 'usb_host_hs' class |
2284 | * high-speed multi-port usb host controller | |
5844c4ea BC |
2285 | */ |
2286 | ||
844a3b63 PW |
2287 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
2288 | .rev_offs = 0x0000, | |
2289 | .sysc_offs = 0x0010, | |
2290 | .syss_offs = 0x0014, | |
2291 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
b483a4a5 | 2292 | SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS), |
5844c4ea BC |
2293 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2294 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
2295 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
2296 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
2297 | }; |
2298 | ||
844a3b63 PW |
2299 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
2300 | .name = "usb_host_hs", | |
2301 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
2302 | }; |
2303 | ||
844a3b63 | 2304 | /* usb_host_hs */ |
844a3b63 PW |
2305 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
2306 | .name = "usb_host_hs", | |
2307 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 2308 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 2309 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
2310 | .prcm = { |
2311 | .omap4 = { | |
844a3b63 PW |
2312 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
2313 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
2314 | .modulemode = MODULEMODE_SWCTRL, | |
2315 | }, | |
2316 | }, | |
844a3b63 PW |
2317 | |
2318 | /* | |
2319 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
2320 | * id: i660 | |
2321 | * | |
2322 | * Description: | |
2323 | * In the following configuration : | |
2324 | * - USBHOST module is set to smart-idle mode | |
2325 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
2326 | * happens when the system is going to a low power mode : all ports | |
2327 | * have been suspended, the master part of the USBHOST module has | |
2328 | * entered the standby state, and SW has cut the functional clocks) | |
2329 | * - an USBHOST interrupt occurs before the module is able to answer | |
2330 | * idle_ack, typically a remote wakeup IRQ. | |
2331 | * Then the USB HOST module will enter a deadlock situation where it | |
2332 | * is no more accessible nor functional. | |
2333 | * | |
2334 | * Workaround: | |
2335 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
2336 | */ | |
2337 | ||
2338 | /* | |
2339 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
2340 | * Id: i571 | |
2341 | * | |
2342 | * Description: | |
2343 | * When the USBHOST module is set to smart-standby mode, and when it is | |
2344 | * ready to enter the standby state (i.e. all ports are suspended and | |
2345 | * all attached devices are in suspend mode), then it can wrongly assert | |
2346 | * the Mstandby signal too early while there are still some residual OCP | |
2347 | * transactions ongoing. If this condition occurs, the internal state | |
2348 | * machine may go to an undefined state and the USB link may be stuck | |
2349 | * upon the next resume. | |
2350 | * | |
2351 | * Workaround: | |
2352 | * Don't use smart standby; use only force standby, | |
2353 | * hence HWMOD_SWSUP_MSTANDBY | |
2354 | */ | |
2355 | ||
b483a4a5 | 2356 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
844a3b63 PW |
2357 | }; |
2358 | ||
2359 | /* | |
2360 | * 'usb_otg_hs' class | |
2361 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
2362 | */ | |
2363 | ||
2364 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
2365 | .rev_offs = 0x0400, | |
2366 | .sysc_offs = 0x0404, | |
2367 | .syss_offs = 0x0408, | |
2368 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
2369 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2370 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2371 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2372 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
2373 | MSTANDBY_SMART), | |
2374 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2375 | }; | |
2376 | ||
2377 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
2378 | .name = "usb_otg_hs", | |
2379 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
2380 | }; | |
2381 | ||
2382 | /* usb_otg_hs */ | |
844a3b63 PW |
2383 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { |
2384 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
2385 | }; | |
2386 | ||
2387 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
2388 | .name = "usb_otg_hs", | |
2389 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
2390 | .clkdm_name = "l3_init_clkdm", | |
2391 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
844a3b63 PW |
2392 | .main_clk = "usb_otg_hs_ick", |
2393 | .prcm = { | |
2394 | .omap4 = { | |
2395 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
2396 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
2397 | .modulemode = MODULEMODE_HWCTRL, | |
2398 | }, | |
2399 | }, | |
2400 | .opt_clks = usb_otg_hs_opt_clks, | |
2401 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
2402 | }; | |
2403 | ||
2404 | /* | |
2405 | * 'usb_tll_hs' class | |
2406 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
2407 | */ | |
2408 | ||
2409 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
2410 | .rev_offs = 0x0000, | |
2411 | .sysc_offs = 0x0010, | |
2412 | .syss_offs = 0x0014, | |
2413 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2414 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2415 | SYSC_HAS_AUTOIDLE), | |
2416 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2417 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2418 | }; | |
2419 | ||
2420 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
2421 | .name = "usb_tll_hs", | |
2422 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
2423 | }; | |
2424 | ||
844a3b63 PW |
2425 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { |
2426 | .name = "usb_tll_hs", | |
2427 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
2428 | .clkdm_name = "l3_init_clkdm", | |
844a3b63 PW |
2429 | .main_clk = "usb_tll_hs_ick", |
2430 | .prcm = { | |
2431 | .omap4 = { | |
2432 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
2433 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
2434 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
2435 | }, |
2436 | }, | |
5844c4ea BC |
2437 | }; |
2438 | ||
3b54baad BC |
2439 | /* |
2440 | * 'wd_timer' class | |
2441 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
2442 | * overflow condition | |
2443 | */ | |
2444 | ||
2445 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
2446 | .rev_offs = 0x0000, | |
2447 | .sysc_offs = 0x0010, | |
2448 | .syss_offs = 0x0014, | |
2449 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 2450 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
2451 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2452 | SIDLE_SMART_WKUP), | |
3b54baad | 2453 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
2454 | }; |
2455 | ||
3b54baad BC |
2456 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
2457 | .name = "wd_timer", | |
2458 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 2459 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 2460 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
2461 | }; |
2462 | ||
2463 | /* wd_timer2 */ | |
3b54baad BC |
2464 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
2465 | .name = "wd_timer2", | |
2466 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 2467 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 2468 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
2469 | .prcm = { |
2470 | .omap4 = { | |
d0f0631d | 2471 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 2472 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 2473 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2474 | }, |
2475 | }, | |
9780a9cf BC |
2476 | }; |
2477 | ||
3b54baad | 2478 | /* wd_timer3 */ |
3b54baad BC |
2479 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
2480 | .name = "wd_timer3", | |
2481 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 2482 | .clkdm_name = "abe_clkdm", |
17b7e7d3 | 2483 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
2484 | .prcm = { |
2485 | .omap4 = { | |
d0f0631d | 2486 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 2487 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 2488 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2489 | }, |
2490 | }, | |
9780a9cf | 2491 | }; |
531ce0d5 | 2492 | |
844a3b63 | 2493 | |
af88fa9a | 2494 | /* |
844a3b63 | 2495 | * interfaces |
af88fa9a | 2496 | */ |
af88fa9a | 2497 | |
844a3b63 PW |
2498 | /* l3_main_1 -> dmm */ |
2499 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
2500 | .master = &omap44xx_l3_main_1_hwmod, | |
2501 | .slave = &omap44xx_dmm_hwmod, | |
2502 | .clk = "l3_div_ck", | |
2503 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
2504 | }; |
2505 | ||
844a3b63 PW |
2506 | /* mpu -> dmm */ |
2507 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
2508 | .master = &omap44xx_mpu_hwmod, | |
2509 | .slave = &omap44xx_dmm_hwmod, | |
2510 | .clk = "l3_div_ck", | |
844a3b63 PW |
2511 | .user = OCP_USER_MPU, |
2512 | }; | |
2513 | ||
2514 | /* iva -> l3_instr */ | |
2515 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
2516 | .master = &omap44xx_iva_hwmod, | |
2517 | .slave = &omap44xx_l3_instr_hwmod, | |
2518 | .clk = "l3_div_ck", | |
2519 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2520 | }; | |
2521 | ||
2522 | /* l3_main_3 -> l3_instr */ | |
2523 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
2524 | .master = &omap44xx_l3_main_3_hwmod, | |
2525 | .slave = &omap44xx_l3_instr_hwmod, | |
2526 | .clk = "l3_div_ck", | |
2527 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2528 | }; | |
2529 | ||
9a817bc8 BC |
2530 | /* ocp_wp_noc -> l3_instr */ |
2531 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
2532 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
2533 | .slave = &omap44xx_l3_instr_hwmod, | |
2534 | .clk = "l3_div_ck", | |
2535 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2536 | }; | |
2537 | ||
844a3b63 PW |
2538 | /* dsp -> l3_main_1 */ |
2539 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
2540 | .master = &omap44xx_dsp_hwmod, | |
2541 | .slave = &omap44xx_l3_main_1_hwmod, | |
2542 | .clk = "l3_div_ck", | |
2543 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2544 | }; | |
2545 | ||
2546 | /* dss -> l3_main_1 */ | |
2547 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
2548 | .master = &omap44xx_dss_hwmod, | |
2549 | .slave = &omap44xx_l3_main_1_hwmod, | |
2550 | .clk = "l3_div_ck", | |
2551 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2552 | }; | |
2553 | ||
2554 | /* l3_main_2 -> l3_main_1 */ | |
2555 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
2556 | .master = &omap44xx_l3_main_2_hwmod, | |
2557 | .slave = &omap44xx_l3_main_1_hwmod, | |
2558 | .clk = "l3_div_ck", | |
2559 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2560 | }; | |
2561 | ||
2562 | /* l4_cfg -> l3_main_1 */ | |
2563 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
2564 | .master = &omap44xx_l4_cfg_hwmod, | |
2565 | .slave = &omap44xx_l3_main_1_hwmod, | |
2566 | .clk = "l4_div_ck", | |
2567 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2568 | }; | |
2569 | ||
844a3b63 PW |
2570 | /* mpu -> l3_main_1 */ |
2571 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
2572 | .master = &omap44xx_mpu_hwmod, | |
2573 | .slave = &omap44xx_l3_main_1_hwmod, | |
2574 | .clk = "l3_div_ck", | |
844a3b63 PW |
2575 | .user = OCP_USER_MPU, |
2576 | }; | |
2577 | ||
96566043 BC |
2578 | /* debugss -> l3_main_2 */ |
2579 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
2580 | .master = &omap44xx_debugss_hwmod, | |
2581 | .slave = &omap44xx_l3_main_2_hwmod, | |
2582 | .clk = "dbgclk_mux_ck", | |
2583 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2584 | }; | |
2585 | ||
844a3b63 PW |
2586 | /* dma_system -> l3_main_2 */ |
2587 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
2588 | .master = &omap44xx_dma_system_hwmod, | |
2589 | .slave = &omap44xx_l3_main_2_hwmod, | |
2590 | .clk = "l3_div_ck", | |
2591 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2592 | }; | |
2593 | ||
b050f688 ML |
2594 | /* fdif -> l3_main_2 */ |
2595 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
2596 | .master = &omap44xx_fdif_hwmod, | |
2597 | .slave = &omap44xx_l3_main_2_hwmod, | |
2598 | .clk = "l3_div_ck", | |
2599 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2600 | }; | |
2601 | ||
9def390e PW |
2602 | /* gpu -> l3_main_2 */ |
2603 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
2604 | .master = &omap44xx_gpu_hwmod, | |
2605 | .slave = &omap44xx_l3_main_2_hwmod, | |
2606 | .clk = "l3_div_ck", | |
2607 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2608 | }; | |
2609 | ||
844a3b63 PW |
2610 | /* hsi -> l3_main_2 */ |
2611 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
2612 | .master = &omap44xx_hsi_hwmod, | |
2613 | .slave = &omap44xx_l3_main_2_hwmod, | |
2614 | .clk = "l3_div_ck", | |
2615 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2616 | }; | |
2617 | ||
2618 | /* ipu -> l3_main_2 */ | |
2619 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
2620 | .master = &omap44xx_ipu_hwmod, | |
2621 | .slave = &omap44xx_l3_main_2_hwmod, | |
2622 | .clk = "l3_div_ck", | |
2623 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2624 | }; | |
2625 | ||
2626 | /* iss -> l3_main_2 */ | |
2627 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
2628 | .master = &omap44xx_iss_hwmod, | |
2629 | .slave = &omap44xx_l3_main_2_hwmod, | |
2630 | .clk = "l3_div_ck", | |
2631 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2632 | }; | |
2633 | ||
2634 | /* iva -> l3_main_2 */ | |
2635 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
2636 | .master = &omap44xx_iva_hwmod, | |
2637 | .slave = &omap44xx_l3_main_2_hwmod, | |
2638 | .clk = "l3_div_ck", | |
2639 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2640 | }; | |
2641 | ||
844a3b63 PW |
2642 | /* l3_main_1 -> l3_main_2 */ |
2643 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
2644 | .master = &omap44xx_l3_main_1_hwmod, | |
2645 | .slave = &omap44xx_l3_main_2_hwmod, | |
2646 | .clk = "l3_div_ck", | |
844a3b63 PW |
2647 | .user = OCP_USER_MPU, |
2648 | }; | |
2649 | ||
2650 | /* l4_cfg -> l3_main_2 */ | |
2651 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
2652 | .master = &omap44xx_l4_cfg_hwmod, | |
2653 | .slave = &omap44xx_l3_main_2_hwmod, | |
2654 | .clk = "l4_div_ck", | |
2655 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2656 | }; | |
2657 | ||
0c668875 | 2658 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 2659 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
2660 | .master = &omap44xx_usb_host_fs_hwmod, |
2661 | .slave = &omap44xx_l3_main_2_hwmod, | |
2662 | .clk = "l3_div_ck", | |
2663 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2664 | }; | |
2665 | ||
844a3b63 PW |
2666 | /* usb_host_hs -> l3_main_2 */ |
2667 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
2668 | .master = &omap44xx_usb_host_hs_hwmod, | |
2669 | .slave = &omap44xx_l3_main_2_hwmod, | |
2670 | .clk = "l3_div_ck", | |
2671 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2672 | }; | |
2673 | ||
2674 | /* usb_otg_hs -> l3_main_2 */ | |
2675 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
2676 | .master = &omap44xx_usb_otg_hs_hwmod, | |
2677 | .slave = &omap44xx_l3_main_2_hwmod, | |
2678 | .clk = "l3_div_ck", | |
2679 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2680 | }; | |
2681 | ||
844a3b63 PW |
2682 | /* l3_main_1 -> l3_main_3 */ |
2683 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
2684 | .master = &omap44xx_l3_main_1_hwmod, | |
2685 | .slave = &omap44xx_l3_main_3_hwmod, | |
2686 | .clk = "l3_div_ck", | |
844a3b63 PW |
2687 | .user = OCP_USER_MPU, |
2688 | }; | |
2689 | ||
2690 | /* l3_main_2 -> l3_main_3 */ | |
2691 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
2692 | .master = &omap44xx_l3_main_2_hwmod, | |
2693 | .slave = &omap44xx_l3_main_3_hwmod, | |
2694 | .clk = "l3_div_ck", | |
2695 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2696 | }; | |
2697 | ||
2698 | /* l4_cfg -> l3_main_3 */ | |
2699 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
2700 | .master = &omap44xx_l4_cfg_hwmod, | |
2701 | .slave = &omap44xx_l3_main_3_hwmod, | |
2702 | .clk = "l4_div_ck", | |
2703 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2704 | }; | |
2705 | ||
2706 | /* aess -> l4_abe */ | |
b0a70cc8 | 2707 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
2708 | .master = &omap44xx_aess_hwmod, |
2709 | .slave = &omap44xx_l4_abe_hwmod, | |
2710 | .clk = "ocp_abe_iclk", | |
2711 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2712 | }; | |
2713 | ||
2714 | /* dsp -> l4_abe */ | |
2715 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
2716 | .master = &omap44xx_dsp_hwmod, | |
2717 | .slave = &omap44xx_l4_abe_hwmod, | |
2718 | .clk = "ocp_abe_iclk", | |
2719 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2720 | }; | |
2721 | ||
2722 | /* l3_main_1 -> l4_abe */ | |
2723 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
2724 | .master = &omap44xx_l3_main_1_hwmod, | |
2725 | .slave = &omap44xx_l4_abe_hwmod, | |
2726 | .clk = "l3_div_ck", | |
2727 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2728 | }; | |
2729 | ||
2730 | /* mpu -> l4_abe */ | |
2731 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
2732 | .master = &omap44xx_mpu_hwmod, | |
2733 | .slave = &omap44xx_l4_abe_hwmod, | |
2734 | .clk = "ocp_abe_iclk", | |
2735 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2736 | }; | |
2737 | ||
2738 | /* l3_main_1 -> l4_cfg */ | |
2739 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
2740 | .master = &omap44xx_l3_main_1_hwmod, | |
2741 | .slave = &omap44xx_l4_cfg_hwmod, | |
2742 | .clk = "l3_div_ck", | |
2743 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2744 | }; | |
2745 | ||
2746 | /* l3_main_2 -> l4_per */ | |
2747 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
2748 | .master = &omap44xx_l3_main_2_hwmod, | |
2749 | .slave = &omap44xx_l4_per_hwmod, | |
2750 | .clk = "l3_div_ck", | |
2751 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2752 | }; | |
2753 | ||
2754 | /* l4_cfg -> l4_wkup */ | |
2755 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
2756 | .master = &omap44xx_l4_cfg_hwmod, | |
2757 | .slave = &omap44xx_l4_wkup_hwmod, | |
2758 | .clk = "l4_div_ck", | |
2759 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2760 | }; | |
2761 | ||
2762 | /* mpu -> mpu_private */ | |
2763 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
2764 | .master = &omap44xx_mpu_hwmod, | |
2765 | .slave = &omap44xx_mpu_private_hwmod, | |
2766 | .clk = "l3_div_ck", | |
2767 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2768 | }; | |
2769 | ||
9a817bc8 BC |
2770 | /* l4_cfg -> ocp_wp_noc */ |
2771 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
2772 | .master = &omap44xx_l4_cfg_hwmod, | |
2773 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
2774 | .clk = "l4_div_ck", | |
9a817bc8 BC |
2775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2776 | }; | |
2777 | ||
844a3b63 | 2778 | /* l4_abe -> aess */ |
b0a70cc8 | 2779 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
2780 | .master = &omap44xx_l4_abe_hwmod, |
2781 | .slave = &omap44xx_aess_hwmod, | |
2782 | .clk = "ocp_abe_iclk", | |
844a3b63 PW |
2783 | .user = OCP_USER_MPU, |
2784 | }; | |
2785 | ||
844a3b63 | 2786 | /* l4_abe -> aess (dma) */ |
b0a70cc8 | 2787 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
2788 | .master = &omap44xx_l4_abe_hwmod, |
2789 | .slave = &omap44xx_aess_hwmod, | |
2790 | .clk = "ocp_abe_iclk", | |
844a3b63 PW |
2791 | .user = OCP_USER_SDMA, |
2792 | }; | |
2793 | ||
42b9e387 PW |
2794 | /* l3_main_2 -> c2c */ |
2795 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
2796 | .master = &omap44xx_l3_main_2_hwmod, | |
2797 | .slave = &omap44xx_c2c_hwmod, | |
2798 | .clk = "l3_div_ck", | |
2799 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2800 | }; | |
2801 | ||
844a3b63 PW |
2802 | /* l4_wkup -> counter_32k */ |
2803 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
2804 | .master = &omap44xx_l4_wkup_hwmod, | |
2805 | .slave = &omap44xx_counter_32k_hwmod, | |
2806 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
2807 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2808 | }; | |
2809 | ||
a0b5d813 PW |
2810 | /* l4_cfg -> ctrl_module_core */ |
2811 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
2812 | .master = &omap44xx_l4_cfg_hwmod, | |
2813 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
2814 | .clk = "l4_div_ck", | |
a0b5d813 PW |
2815 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2816 | }; | |
2817 | ||
a0b5d813 PW |
2818 | /* l4_cfg -> ctrl_module_pad_core */ |
2819 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
2820 | .master = &omap44xx_l4_cfg_hwmod, | |
2821 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
2822 | .clk = "l4_div_ck", | |
a0b5d813 PW |
2823 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2824 | }; | |
2825 | ||
a0b5d813 PW |
2826 | /* l4_wkup -> ctrl_module_wkup */ |
2827 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
2828 | .master = &omap44xx_l4_wkup_hwmod, | |
2829 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
2830 | .clk = "l4_wkup_clk_mux_ck", | |
a0b5d813 PW |
2831 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2832 | }; | |
2833 | ||
a0b5d813 PW |
2834 | /* l4_wkup -> ctrl_module_pad_wkup */ |
2835 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
2836 | .master = &omap44xx_l4_wkup_hwmod, | |
2837 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
2838 | .clk = "l4_wkup_clk_mux_ck", | |
a0b5d813 PW |
2839 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2840 | }; | |
2841 | ||
96566043 BC |
2842 | /* l3_instr -> debugss */ |
2843 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
2844 | .master = &omap44xx_l3_instr_hwmod, | |
2845 | .slave = &omap44xx_debugss_hwmod, | |
2846 | .clk = "l3_div_ck", | |
96566043 BC |
2847 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2848 | }; | |
2849 | ||
844a3b63 PW |
2850 | /* l4_cfg -> dma_system */ |
2851 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
2852 | .master = &omap44xx_l4_cfg_hwmod, | |
2853 | .slave = &omap44xx_dma_system_hwmod, | |
2854 | .clk = "l4_div_ck", | |
844a3b63 PW |
2855 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2856 | }; | |
2857 | ||
844a3b63 PW |
2858 | /* l4_abe -> dmic */ |
2859 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
2860 | .master = &omap44xx_l4_abe_hwmod, | |
2861 | .slave = &omap44xx_dmic_hwmod, | |
2862 | .clk = "ocp_abe_iclk", | |
e3491795 | 2863 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
2864 | }; |
2865 | ||
2866 | /* dsp -> iva */ | |
2867 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
2868 | .master = &omap44xx_dsp_hwmod, | |
2869 | .slave = &omap44xx_iva_hwmod, | |
2870 | .clk = "dpll_iva_m5x2_ck", | |
2871 | .user = OCP_USER_DSP, | |
2872 | }; | |
2873 | ||
42b9e387 | 2874 | /* dsp -> sl2if */ |
b360124e | 2875 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
42b9e387 PW |
2876 | .master = &omap44xx_dsp_hwmod, |
2877 | .slave = &omap44xx_sl2if_hwmod, | |
2878 | .clk = "dpll_iva_m5x2_ck", | |
2879 | .user = OCP_USER_DSP, | |
2880 | }; | |
2881 | ||
844a3b63 PW |
2882 | /* l4_cfg -> dsp */ |
2883 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
2884 | .master = &omap44xx_l4_cfg_hwmod, | |
2885 | .slave = &omap44xx_dsp_hwmod, | |
2886 | .clk = "l4_div_ck", | |
2887 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2888 | }; | |
2889 | ||
844a3b63 PW |
2890 | /* l3_main_2 -> dss */ |
2891 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
2892 | .master = &omap44xx_l3_main_2_hwmod, | |
2893 | .slave = &omap44xx_dss_hwmod, | |
7ede8561 | 2894 | .clk = "l3_div_ck", |
844a3b63 PW |
2895 | .user = OCP_USER_SDMA, |
2896 | }; | |
2897 | ||
844a3b63 PW |
2898 | /* l4_per -> dss */ |
2899 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
2900 | .master = &omap44xx_l4_per_hwmod, | |
2901 | .slave = &omap44xx_dss_hwmod, | |
2902 | .clk = "l4_div_ck", | |
844a3b63 PW |
2903 | .user = OCP_USER_MPU, |
2904 | }; | |
2905 | ||
844a3b63 PW |
2906 | /* l3_main_2 -> dss_dispc */ |
2907 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
2908 | .master = &omap44xx_l3_main_2_hwmod, | |
2909 | .slave = &omap44xx_dss_dispc_hwmod, | |
7ede8561 | 2910 | .clk = "l3_div_ck", |
844a3b63 PW |
2911 | .user = OCP_USER_SDMA, |
2912 | }; | |
2913 | ||
844a3b63 PW |
2914 | /* l4_per -> dss_dispc */ |
2915 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
2916 | .master = &omap44xx_l4_per_hwmod, | |
2917 | .slave = &omap44xx_dss_dispc_hwmod, | |
2918 | .clk = "l4_div_ck", | |
844a3b63 PW |
2919 | .user = OCP_USER_MPU, |
2920 | }; | |
2921 | ||
844a3b63 PW |
2922 | /* l3_main_2 -> dss_dsi1 */ |
2923 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
2924 | .master = &omap44xx_l3_main_2_hwmod, | |
2925 | .slave = &omap44xx_dss_dsi1_hwmod, | |
7ede8561 | 2926 | .clk = "l3_div_ck", |
844a3b63 PW |
2927 | .user = OCP_USER_SDMA, |
2928 | }; | |
2929 | ||
844a3b63 PW |
2930 | /* l4_per -> dss_dsi1 */ |
2931 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
2932 | .master = &omap44xx_l4_per_hwmod, | |
2933 | .slave = &omap44xx_dss_dsi1_hwmod, | |
2934 | .clk = "l4_div_ck", | |
844a3b63 PW |
2935 | .user = OCP_USER_MPU, |
2936 | }; | |
2937 | ||
844a3b63 PW |
2938 | /* l3_main_2 -> dss_dsi2 */ |
2939 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
2940 | .master = &omap44xx_l3_main_2_hwmod, | |
2941 | .slave = &omap44xx_dss_dsi2_hwmod, | |
7ede8561 | 2942 | .clk = "l3_div_ck", |
844a3b63 PW |
2943 | .user = OCP_USER_SDMA, |
2944 | }; | |
2945 | ||
844a3b63 PW |
2946 | /* l4_per -> dss_dsi2 */ |
2947 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
2948 | .master = &omap44xx_l4_per_hwmod, | |
2949 | .slave = &omap44xx_dss_dsi2_hwmod, | |
2950 | .clk = "l4_div_ck", | |
844a3b63 PW |
2951 | .user = OCP_USER_MPU, |
2952 | }; | |
2953 | ||
844a3b63 PW |
2954 | /* l3_main_2 -> dss_hdmi */ |
2955 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
2956 | .master = &omap44xx_l3_main_2_hwmod, | |
2957 | .slave = &omap44xx_dss_hdmi_hwmod, | |
7ede8561 | 2958 | .clk = "l3_div_ck", |
844a3b63 PW |
2959 | .user = OCP_USER_SDMA, |
2960 | }; | |
2961 | ||
844a3b63 PW |
2962 | /* l4_per -> dss_hdmi */ |
2963 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
2964 | .master = &omap44xx_l4_per_hwmod, | |
2965 | .slave = &omap44xx_dss_hdmi_hwmod, | |
2966 | .clk = "l4_div_ck", | |
844a3b63 PW |
2967 | .user = OCP_USER_MPU, |
2968 | }; | |
2969 | ||
844a3b63 PW |
2970 | /* l3_main_2 -> dss_rfbi */ |
2971 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
2972 | .master = &omap44xx_l3_main_2_hwmod, | |
2973 | .slave = &omap44xx_dss_rfbi_hwmod, | |
7ede8561 | 2974 | .clk = "l3_div_ck", |
844a3b63 PW |
2975 | .user = OCP_USER_SDMA, |
2976 | }; | |
2977 | ||
844a3b63 PW |
2978 | /* l4_per -> dss_rfbi */ |
2979 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
2980 | .master = &omap44xx_l4_per_hwmod, | |
2981 | .slave = &omap44xx_dss_rfbi_hwmod, | |
2982 | .clk = "l4_div_ck", | |
844a3b63 PW |
2983 | .user = OCP_USER_MPU, |
2984 | }; | |
2985 | ||
844a3b63 PW |
2986 | /* l3_main_2 -> dss_venc */ |
2987 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
2988 | .master = &omap44xx_l3_main_2_hwmod, | |
2989 | .slave = &omap44xx_dss_venc_hwmod, | |
7ede8561 | 2990 | .clk = "l3_div_ck", |
844a3b63 PW |
2991 | .user = OCP_USER_SDMA, |
2992 | }; | |
2993 | ||
844a3b63 PW |
2994 | /* l4_per -> dss_venc */ |
2995 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
2996 | .master = &omap44xx_l4_per_hwmod, | |
2997 | .slave = &omap44xx_dss_venc_hwmod, | |
2998 | .clk = "l4_div_ck", | |
844a3b63 PW |
2999 | .user = OCP_USER_MPU, |
3000 | }; | |
3001 | ||
1df5eaa6 TK |
3002 | /* l3_main_2 -> sham */ |
3003 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = { | |
3004 | .master = &omap44xx_l3_main_2_hwmod, | |
3005 | .slave = &omap44xx_sha0_hwmod, | |
3006 | .clk = "l3_div_ck", | |
3007 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3008 | }; | |
3009 | ||
42b9e387 PW |
3010 | /* l4_per -> elm */ |
3011 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
3012 | .master = &omap44xx_l4_per_hwmod, | |
3013 | .slave = &omap44xx_elm_hwmod, | |
3014 | .clk = "l4_div_ck", | |
42b9e387 PW |
3015 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3016 | }; | |
3017 | ||
b050f688 ML |
3018 | /* l4_cfg -> fdif */ |
3019 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
3020 | .master = &omap44xx_l4_cfg_hwmod, | |
3021 | .slave = &omap44xx_fdif_hwmod, | |
3022 | .clk = "l4_div_ck", | |
b050f688 ML |
3023 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3024 | }; | |
3025 | ||
eb42b5d3 BC |
3026 | /* l3_main_2 -> gpmc */ |
3027 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
3028 | .master = &omap44xx_l3_main_2_hwmod, | |
3029 | .slave = &omap44xx_gpmc_hwmod, | |
3030 | .clk = "l3_div_ck", | |
eb42b5d3 BC |
3031 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3032 | }; | |
3033 | ||
9def390e PW |
3034 | /* l3_main_2 -> gpu */ |
3035 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
3036 | .master = &omap44xx_l3_main_2_hwmod, | |
3037 | .slave = &omap44xx_gpu_hwmod, | |
3038 | .clk = "l3_div_ck", | |
9def390e PW |
3039 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3040 | }; | |
3041 | ||
a091c08e PW |
3042 | /* l4_per -> hdq1w */ |
3043 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
3044 | .master = &omap44xx_l4_per_hwmod, | |
3045 | .slave = &omap44xx_hdq1w_hwmod, | |
3046 | .clk = "l4_div_ck", | |
a091c08e PW |
3047 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3048 | }; | |
3049 | ||
844a3b63 PW |
3050 | /* l4_cfg -> hsi */ |
3051 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
3052 | .master = &omap44xx_l4_cfg_hwmod, | |
3053 | .slave = &omap44xx_hsi_hwmod, | |
3054 | .clk = "l4_div_ck", | |
844a3b63 PW |
3055 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3056 | }; | |
3057 | ||
844a3b63 PW |
3058 | /* l3_main_2 -> ipu */ |
3059 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
3060 | .master = &omap44xx_l3_main_2_hwmod, | |
3061 | .slave = &omap44xx_ipu_hwmod, | |
3062 | .clk = "l3_div_ck", | |
3063 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3064 | }; | |
3065 | ||
844a3b63 PW |
3066 | /* l3_main_2 -> iss */ |
3067 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
3068 | .master = &omap44xx_l3_main_2_hwmod, | |
3069 | .slave = &omap44xx_iss_hwmod, | |
3070 | .clk = "l3_div_ck", | |
844a3b63 PW |
3071 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3072 | }; | |
3073 | ||
42b9e387 | 3074 | /* iva -> sl2if */ |
b360124e | 3075 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
42b9e387 PW |
3076 | .master = &omap44xx_iva_hwmod, |
3077 | .slave = &omap44xx_sl2if_hwmod, | |
3078 | .clk = "dpll_iva_m5x2_ck", | |
3079 | .user = OCP_USER_IVA, | |
3080 | }; | |
3081 | ||
844a3b63 PW |
3082 | /* l3_main_2 -> iva */ |
3083 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
3084 | .master = &omap44xx_l3_main_2_hwmod, | |
3085 | .slave = &omap44xx_iva_hwmod, | |
3086 | .clk = "l3_div_ck", | |
844a3b63 PW |
3087 | .user = OCP_USER_MPU, |
3088 | }; | |
3089 | ||
844a3b63 PW |
3090 | /* l4_wkup -> kbd */ |
3091 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
3092 | .master = &omap44xx_l4_wkup_hwmod, | |
3093 | .slave = &omap44xx_kbd_hwmod, | |
3094 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3095 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3096 | }; | |
3097 | ||
844a3b63 PW |
3098 | /* l4_cfg -> mailbox */ |
3099 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
3100 | .master = &omap44xx_l4_cfg_hwmod, | |
3101 | .slave = &omap44xx_mailbox_hwmod, | |
3102 | .clk = "l4_div_ck", | |
844a3b63 PW |
3103 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3104 | }; | |
3105 | ||
896d4e98 BC |
3106 | /* l4_abe -> mcasp */ |
3107 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
3108 | .master = &omap44xx_l4_abe_hwmod, | |
3109 | .slave = &omap44xx_mcasp_hwmod, | |
3110 | .clk = "ocp_abe_iclk", | |
896d4e98 BC |
3111 | .user = OCP_USER_MPU, |
3112 | }; | |
3113 | ||
896d4e98 BC |
3114 | /* l4_abe -> mcasp (dma) */ |
3115 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
3116 | .master = &omap44xx_l4_abe_hwmod, | |
3117 | .slave = &omap44xx_mcasp_hwmod, | |
3118 | .clk = "ocp_abe_iclk", | |
896d4e98 BC |
3119 | .user = OCP_USER_SDMA, |
3120 | }; | |
3121 | ||
844a3b63 PW |
3122 | /* l4_abe -> mcbsp1 */ |
3123 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
3124 | .master = &omap44xx_l4_abe_hwmod, | |
3125 | .slave = &omap44xx_mcbsp1_hwmod, | |
3126 | .clk = "ocp_abe_iclk", | |
e3491795 | 3127 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3128 | }; |
3129 | ||
844a3b63 PW |
3130 | /* l4_abe -> mcbsp2 */ |
3131 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
3132 | .master = &omap44xx_l4_abe_hwmod, | |
3133 | .slave = &omap44xx_mcbsp2_hwmod, | |
3134 | .clk = "ocp_abe_iclk", | |
e3491795 | 3135 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3136 | }; |
3137 | ||
844a3b63 PW |
3138 | /* l4_abe -> mcbsp3 */ |
3139 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
3140 | .master = &omap44xx_l4_abe_hwmod, | |
3141 | .slave = &omap44xx_mcbsp3_hwmod, | |
3142 | .clk = "ocp_abe_iclk", | |
e3491795 | 3143 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3144 | }; |
3145 | ||
844a3b63 PW |
3146 | /* l4_per -> mcbsp4 */ |
3147 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
3148 | .master = &omap44xx_l4_per_hwmod, | |
3149 | .slave = &omap44xx_mcbsp4_hwmod, | |
3150 | .clk = "l4_div_ck", | |
844a3b63 PW |
3151 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3152 | }; | |
3153 | ||
844a3b63 PW |
3154 | /* l4_abe -> mcpdm */ |
3155 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
3156 | .master = &omap44xx_l4_abe_hwmod, | |
3157 | .slave = &omap44xx_mcpdm_hwmod, | |
3158 | .clk = "ocp_abe_iclk", | |
e3491795 | 3159 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3160 | }; |
3161 | ||
e17f18c0 PW |
3162 | /* l3_main_2 -> ocmc_ram */ |
3163 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
3164 | .master = &omap44xx_l3_main_2_hwmod, | |
3165 | .slave = &omap44xx_ocmc_ram_hwmod, | |
3166 | .clk = "l3_div_ck", | |
3167 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3168 | }; | |
3169 | ||
0c668875 BC |
3170 | /* l4_cfg -> ocp2scp_usb_phy */ |
3171 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
3172 | .master = &omap44xx_l4_cfg_hwmod, | |
3173 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
3174 | .clk = "l4_div_ck", | |
3175 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3176 | }; | |
3177 | ||
794b480a PW |
3178 | /* mpu_private -> prcm_mpu */ |
3179 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
3180 | .master = &omap44xx_mpu_private_hwmod, | |
3181 | .slave = &omap44xx_prcm_mpu_hwmod, | |
3182 | .clk = "l3_div_ck", | |
794b480a PW |
3183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3184 | }; | |
3185 | ||
794b480a PW |
3186 | /* l4_wkup -> cm_core_aon */ |
3187 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
3188 | .master = &omap44xx_l4_wkup_hwmod, | |
3189 | .slave = &omap44xx_cm_core_aon_hwmod, | |
3190 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
3191 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3192 | }; | |
3193 | ||
794b480a PW |
3194 | /* l4_cfg -> cm_core */ |
3195 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
3196 | .master = &omap44xx_l4_cfg_hwmod, | |
3197 | .slave = &omap44xx_cm_core_hwmod, | |
3198 | .clk = "l4_div_ck", | |
794b480a PW |
3199 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3200 | }; | |
3201 | ||
794b480a PW |
3202 | /* l4_wkup -> prm */ |
3203 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
3204 | .master = &omap44xx_l4_wkup_hwmod, | |
3205 | .slave = &omap44xx_prm_hwmod, | |
3206 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
3207 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3208 | }; | |
3209 | ||
794b480a PW |
3210 | /* l4_wkup -> scrm */ |
3211 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
3212 | .master = &omap44xx_l4_wkup_hwmod, | |
3213 | .slave = &omap44xx_scrm_hwmod, | |
3214 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
3215 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3216 | }; | |
3217 | ||
42b9e387 | 3218 | /* l3_main_2 -> sl2if */ |
b360124e | 3219 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
3220 | .master = &omap44xx_l3_main_2_hwmod, |
3221 | .slave = &omap44xx_sl2if_hwmod, | |
3222 | .clk = "l3_div_ck", | |
3223 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3224 | }; | |
3225 | ||
1e3b5e59 BC |
3226 | /* l4_abe -> slimbus1 */ |
3227 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
3228 | .master = &omap44xx_l4_abe_hwmod, | |
3229 | .slave = &omap44xx_slimbus1_hwmod, | |
3230 | .clk = "ocp_abe_iclk", | |
1e3b5e59 BC |
3231 | .user = OCP_USER_MPU, |
3232 | }; | |
3233 | ||
1e3b5e59 BC |
3234 | /* l4_abe -> slimbus1 (dma) */ |
3235 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
3236 | .master = &omap44xx_l4_abe_hwmod, | |
3237 | .slave = &omap44xx_slimbus1_hwmod, | |
3238 | .clk = "ocp_abe_iclk", | |
1e3b5e59 BC |
3239 | .user = OCP_USER_SDMA, |
3240 | }; | |
3241 | ||
1e3b5e59 BC |
3242 | /* l4_per -> slimbus2 */ |
3243 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
3244 | .master = &omap44xx_l4_per_hwmod, | |
3245 | .slave = &omap44xx_slimbus2_hwmod, | |
3246 | .clk = "l4_div_ck", | |
1e3b5e59 BC |
3247 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3248 | }; | |
3249 | ||
844a3b63 PW |
3250 | /* l4_cfg -> smartreflex_core */ |
3251 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
3252 | .master = &omap44xx_l4_cfg_hwmod, | |
3253 | .slave = &omap44xx_smartreflex_core_hwmod, | |
3254 | .clk = "l4_div_ck", | |
844a3b63 PW |
3255 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3256 | }; | |
3257 | ||
844a3b63 PW |
3258 | /* l4_cfg -> smartreflex_iva */ |
3259 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
3260 | .master = &omap44xx_l4_cfg_hwmod, | |
3261 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
3262 | .clk = "l4_div_ck", | |
844a3b63 PW |
3263 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3264 | }; | |
3265 | ||
844a3b63 PW |
3266 | /* l4_cfg -> smartreflex_mpu */ |
3267 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
3268 | .master = &omap44xx_l4_cfg_hwmod, | |
3269 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
3270 | .clk = "l4_div_ck", | |
844a3b63 PW |
3271 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3272 | }; | |
3273 | ||
844a3b63 PW |
3274 | /* l4_cfg -> spinlock */ |
3275 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
3276 | .master = &omap44xx_l4_cfg_hwmod, | |
3277 | .slave = &omap44xx_spinlock_hwmod, | |
3278 | .clk = "l4_div_ck", | |
844a3b63 PW |
3279 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3280 | }; | |
3281 | ||
844a3b63 PW |
3282 | /* l4_wkup -> timer1 */ |
3283 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
3284 | .master = &omap44xx_l4_wkup_hwmod, | |
3285 | .slave = &omap44xx_timer1_hwmod, | |
3286 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3287 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3288 | }; | |
3289 | ||
844a3b63 PW |
3290 | /* l4_per -> timer2 */ |
3291 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
3292 | .master = &omap44xx_l4_per_hwmod, | |
3293 | .slave = &omap44xx_timer2_hwmod, | |
3294 | .clk = "l4_div_ck", | |
844a3b63 PW |
3295 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3296 | }; | |
3297 | ||
844a3b63 PW |
3298 | /* l4_per -> timer3 */ |
3299 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
3300 | .master = &omap44xx_l4_per_hwmod, | |
3301 | .slave = &omap44xx_timer3_hwmod, | |
3302 | .clk = "l4_div_ck", | |
844a3b63 PW |
3303 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3304 | }; | |
3305 | ||
844a3b63 PW |
3306 | /* l4_per -> timer4 */ |
3307 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
3308 | .master = &omap44xx_l4_per_hwmod, | |
3309 | .slave = &omap44xx_timer4_hwmod, | |
3310 | .clk = "l4_div_ck", | |
844a3b63 PW |
3311 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3312 | }; | |
3313 | ||
844a3b63 PW |
3314 | /* l4_abe -> timer5 */ |
3315 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
3316 | .master = &omap44xx_l4_abe_hwmod, | |
3317 | .slave = &omap44xx_timer5_hwmod, | |
3318 | .clk = "ocp_abe_iclk", | |
e3491795 | 3319 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3320 | }; |
3321 | ||
844a3b63 PW |
3322 | /* l4_abe -> timer6 */ |
3323 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
3324 | .master = &omap44xx_l4_abe_hwmod, | |
3325 | .slave = &omap44xx_timer6_hwmod, | |
3326 | .clk = "ocp_abe_iclk", | |
e3491795 | 3327 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3328 | }; |
3329 | ||
844a3b63 PW |
3330 | /* l4_abe -> timer7 */ |
3331 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
3332 | .master = &omap44xx_l4_abe_hwmod, | |
3333 | .slave = &omap44xx_timer7_hwmod, | |
3334 | .clk = "ocp_abe_iclk", | |
e3491795 | 3335 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3336 | }; |
3337 | ||
844a3b63 PW |
3338 | /* l4_abe -> timer8 */ |
3339 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
3340 | .master = &omap44xx_l4_abe_hwmod, | |
3341 | .slave = &omap44xx_timer8_hwmod, | |
3342 | .clk = "ocp_abe_iclk", | |
e3491795 | 3343 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3344 | }; |
3345 | ||
844a3b63 PW |
3346 | /* l4_per -> timer9 */ |
3347 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
3348 | .master = &omap44xx_l4_per_hwmod, | |
3349 | .slave = &omap44xx_timer9_hwmod, | |
3350 | .clk = "l4_div_ck", | |
844a3b63 PW |
3351 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3352 | }; | |
3353 | ||
844a3b63 PW |
3354 | /* l4_per -> timer10 */ |
3355 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
3356 | .master = &omap44xx_l4_per_hwmod, | |
3357 | .slave = &omap44xx_timer10_hwmod, | |
3358 | .clk = "l4_div_ck", | |
844a3b63 PW |
3359 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3360 | }; | |
3361 | ||
844a3b63 PW |
3362 | /* l4_per -> timer11 */ |
3363 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
3364 | .master = &omap44xx_l4_per_hwmod, | |
3365 | .slave = &omap44xx_timer11_hwmod, | |
3366 | .clk = "l4_div_ck", | |
af88fa9a BC |
3367 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3368 | }; | |
3369 | ||
0c668875 | 3370 | /* l4_cfg -> usb_host_fs */ |
b0a70cc8 | 3371 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
3372 | .master = &omap44xx_l4_cfg_hwmod, |
3373 | .slave = &omap44xx_usb_host_fs_hwmod, | |
3374 | .clk = "l4_div_ck", | |
0c668875 BC |
3375 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3376 | }; | |
3377 | ||
844a3b63 PW |
3378 | /* l4_cfg -> usb_host_hs */ |
3379 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
3380 | .master = &omap44xx_l4_cfg_hwmod, | |
3381 | .slave = &omap44xx_usb_host_hs_hwmod, | |
3382 | .clk = "l4_div_ck", | |
844a3b63 PW |
3383 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3384 | }; | |
3385 | ||
844a3b63 PW |
3386 | /* l4_cfg -> usb_otg_hs */ |
3387 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
3388 | .master = &omap44xx_l4_cfg_hwmod, | |
3389 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
3390 | .clk = "l4_div_ck", | |
844a3b63 | 3391 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
af88fa9a BC |
3392 | }; |
3393 | ||
844a3b63 | 3394 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
3395 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
3396 | .master = &omap44xx_l4_cfg_hwmod, | |
3397 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
3398 | .clk = "l4_div_ck", | |
af88fa9a BC |
3399 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3400 | }; | |
3401 | ||
844a3b63 PW |
3402 | /* l4_wkup -> wd_timer2 */ |
3403 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
3404 | .master = &omap44xx_l4_wkup_hwmod, | |
3405 | .slave = &omap44xx_wd_timer2_hwmod, | |
3406 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3407 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3408 | }; | |
3409 | ||
844a3b63 PW |
3410 | /* l4_abe -> wd_timer3 */ |
3411 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
3412 | .master = &omap44xx_l4_abe_hwmod, | |
3413 | .slave = &omap44xx_wd_timer3_hwmod, | |
3414 | .clk = "ocp_abe_iclk", | |
844a3b63 PW |
3415 | .user = OCP_USER_MPU, |
3416 | }; | |
3417 | ||
844a3b63 PW |
3418 | /* l4_abe -> wd_timer3 (dma) */ |
3419 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
3420 | .master = &omap44xx_l4_abe_hwmod, | |
3421 | .slave = &omap44xx_wd_timer3_hwmod, | |
3422 | .clk = "ocp_abe_iclk", | |
844a3b63 | 3423 | .user = OCP_USER_SDMA, |
af88fa9a BC |
3424 | }; |
3425 | ||
3b9b1015 S |
3426 | /* mpu -> emif1 */ |
3427 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { | |
3428 | .master = &omap44xx_mpu_hwmod, | |
3429 | .slave = &omap44xx_emif1_hwmod, | |
3430 | .clk = "l3_div_ck", | |
3431 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3432 | }; | |
3433 | ||
3434 | /* mpu -> emif2 */ | |
3435 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { | |
3436 | .master = &omap44xx_mpu_hwmod, | |
3437 | .slave = &omap44xx_emif2_hwmod, | |
3438 | .clk = "l3_div_ck", | |
3439 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3440 | }; | |
3441 | ||
0a78c5c5 PW |
3442 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
3443 | &omap44xx_l3_main_1__dmm, | |
3444 | &omap44xx_mpu__dmm, | |
0a78c5c5 PW |
3445 | &omap44xx_iva__l3_instr, |
3446 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 3447 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
3448 | &omap44xx_dsp__l3_main_1, |
3449 | &omap44xx_dss__l3_main_1, | |
3450 | &omap44xx_l3_main_2__l3_main_1, | |
3451 | &omap44xx_l4_cfg__l3_main_1, | |
0a78c5c5 | 3452 | &omap44xx_mpu__l3_main_1, |
96566043 | 3453 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 3454 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 3455 | &omap44xx_fdif__l3_main_2, |
9def390e | 3456 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
3457 | &omap44xx_hsi__l3_main_2, |
3458 | &omap44xx_ipu__l3_main_2, | |
3459 | &omap44xx_iss__l3_main_2, | |
3460 | &omap44xx_iva__l3_main_2, | |
3461 | &omap44xx_l3_main_1__l3_main_2, | |
3462 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 3463 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
3464 | &omap44xx_usb_host_hs__l3_main_2, |
3465 | &omap44xx_usb_otg_hs__l3_main_2, | |
3466 | &omap44xx_l3_main_1__l3_main_3, | |
3467 | &omap44xx_l3_main_2__l3_main_3, | |
3468 | &omap44xx_l4_cfg__l3_main_3, | |
5cebb23c | 3469 | &omap44xx_aess__l4_abe, |
0a78c5c5 PW |
3470 | &omap44xx_dsp__l4_abe, |
3471 | &omap44xx_l3_main_1__l4_abe, | |
3472 | &omap44xx_mpu__l4_abe, | |
3473 | &omap44xx_l3_main_1__l4_cfg, | |
3474 | &omap44xx_l3_main_2__l4_per, | |
3475 | &omap44xx_l4_cfg__l4_wkup, | |
3476 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 3477 | &omap44xx_l4_cfg__ocp_wp_noc, |
5cebb23c SG |
3478 | &omap44xx_l4_abe__aess, |
3479 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 3480 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 3481 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
3482 | &omap44xx_l4_cfg__ctrl_module_core, |
3483 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
3484 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
3485 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 3486 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
3487 | &omap44xx_l4_cfg__dma_system, |
3488 | &omap44xx_l4_abe__dmic, | |
0a78c5c5 | 3489 | &omap44xx_dsp__iva, |
b360124e | 3490 | /* &omap44xx_dsp__sl2if, */ |
0a78c5c5 PW |
3491 | &omap44xx_l4_cfg__dsp, |
3492 | &omap44xx_l3_main_2__dss, | |
3493 | &omap44xx_l4_per__dss, | |
3494 | &omap44xx_l3_main_2__dss_dispc, | |
3495 | &omap44xx_l4_per__dss_dispc, | |
3496 | &omap44xx_l3_main_2__dss_dsi1, | |
3497 | &omap44xx_l4_per__dss_dsi1, | |
3498 | &omap44xx_l3_main_2__dss_dsi2, | |
3499 | &omap44xx_l4_per__dss_dsi2, | |
3500 | &omap44xx_l3_main_2__dss_hdmi, | |
3501 | &omap44xx_l4_per__dss_hdmi, | |
3502 | &omap44xx_l3_main_2__dss_rfbi, | |
3503 | &omap44xx_l4_per__dss_rfbi, | |
3504 | &omap44xx_l3_main_2__dss_venc, | |
3505 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 3506 | &omap44xx_l4_per__elm, |
b050f688 | 3507 | &omap44xx_l4_cfg__fdif, |
eb42b5d3 | 3508 | &omap44xx_l3_main_2__gpmc, |
9def390e | 3509 | &omap44xx_l3_main_2__gpu, |
a091c08e | 3510 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 | 3511 | &omap44xx_l4_cfg__hsi, |
0a78c5c5 PW |
3512 | &omap44xx_l3_main_2__ipu, |
3513 | &omap44xx_l3_main_2__iss, | |
b360124e | 3514 | /* &omap44xx_iva__sl2if, */ |
0a78c5c5 PW |
3515 | &omap44xx_l3_main_2__iva, |
3516 | &omap44xx_l4_wkup__kbd, | |
3517 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
3518 | &omap44xx_l4_abe__mcasp, |
3519 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 | 3520 | &omap44xx_l4_abe__mcbsp1, |
0a78c5c5 | 3521 | &omap44xx_l4_abe__mcbsp2, |
0a78c5c5 | 3522 | &omap44xx_l4_abe__mcbsp3, |
0a78c5c5 PW |
3523 | &omap44xx_l4_per__mcbsp4, |
3524 | &omap44xx_l4_abe__mcpdm, | |
230844db ORL |
3525 | &omap44xx_l3_main_2__mmu_ipu, |
3526 | &omap44xx_l4_cfg__mmu_dsp, | |
e17f18c0 | 3527 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 3528 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
3529 | &omap44xx_mpu_private__prcm_mpu, |
3530 | &omap44xx_l4_wkup__cm_core_aon, | |
3531 | &omap44xx_l4_cfg__cm_core, | |
3532 | &omap44xx_l4_wkup__prm, | |
3533 | &omap44xx_l4_wkup__scrm, | |
b360124e | 3534 | /* &omap44xx_l3_main_2__sl2if, */ |
1e3b5e59 BC |
3535 | &omap44xx_l4_abe__slimbus1, |
3536 | &omap44xx_l4_abe__slimbus1_dma, | |
3537 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
3538 | &omap44xx_l4_cfg__smartreflex_core, |
3539 | &omap44xx_l4_cfg__smartreflex_iva, | |
3540 | &omap44xx_l4_cfg__smartreflex_mpu, | |
3541 | &omap44xx_l4_cfg__spinlock, | |
3542 | &omap44xx_l4_wkup__timer1, | |
3543 | &omap44xx_l4_per__timer2, | |
3544 | &omap44xx_l4_per__timer3, | |
3545 | &omap44xx_l4_per__timer4, | |
3546 | &omap44xx_l4_abe__timer5, | |
0a78c5c5 | 3547 | &omap44xx_l4_abe__timer6, |
0a78c5c5 | 3548 | &omap44xx_l4_abe__timer7, |
0a78c5c5 | 3549 | &omap44xx_l4_abe__timer8, |
0a78c5c5 PW |
3550 | &omap44xx_l4_per__timer9, |
3551 | &omap44xx_l4_per__timer10, | |
3552 | &omap44xx_l4_per__timer11, | |
b0a70cc8 | 3553 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
3554 | &omap44xx_l4_cfg__usb_host_hs, |
3555 | &omap44xx_l4_cfg__usb_otg_hs, | |
3556 | &omap44xx_l4_cfg__usb_tll_hs, | |
3557 | &omap44xx_l4_wkup__wd_timer2, | |
3558 | &omap44xx_l4_abe__wd_timer3, | |
3559 | &omap44xx_l4_abe__wd_timer3_dma, | |
3b9b1015 S |
3560 | &omap44xx_mpu__emif1, |
3561 | &omap44xx_mpu__emif2, | |
9a9ded89 | 3562 | &omap44xx_l3_main_2__aes1, |
478523dd | 3563 | &omap44xx_l3_main_2__aes2, |
ebea90df | 3564 | &omap44xx_l3_main_2__des, |
1df5eaa6 | 3565 | &omap44xx_l3_main_2__sha0, |
55d2cb08 BC |
3566 | NULL, |
3567 | }; | |
3568 | ||
3569 | int __init omap44xx_hwmod_init(void) | |
3570 | { | |
9ebfd285 | 3571 | omap_hwmod_init(); |
0a78c5c5 | 3572 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
3573 | } |
3574 |