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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
4b25408f | 22 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 23 | #include <linux/power/smartreflex.h> |
637874dd | 24 | #include <linux/platform_data/omap_ocp2scp.h> |
3a8761c0 | 25 | #include <linux/i2c-omap.h> |
55d2cb08 | 26 | |
45c3eb7d | 27 | #include <linux/omap-dma.h> |
2a296c8f | 28 | |
2203747c AB |
29 | #include <linux/platform_data/spi-omap2-mcspi.h> |
30 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
2ab7c848 | 31 | #include <linux/platform_data/iommu-omap.h> |
c345c8b0 | 32 | #include <plat/dmtimer.h> |
55d2cb08 | 33 | |
2a296c8f | 34 | #include "omap_hwmod.h" |
55d2cb08 | 35 | #include "omap_hwmod_common_data.h" |
d198b514 PW |
36 | #include "cm1_44xx.h" |
37 | #include "cm2_44xx.h" | |
38 | #include "prm44xx.h" | |
55d2cb08 | 39 | #include "prm-regbits-44xx.h" |
3a8761c0 | 40 | #include "i2c.h" |
68f39e74 | 41 | #include "mmc.h" |
ff2516fb | 42 | #include "wd_timer.h" |
55d2cb08 BC |
43 | |
44 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
45 | #define OMAP44XX_IRQ_GIC_START 32 | |
46 | ||
47 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 48 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
49 | |
50 | /* | |
844a3b63 | 51 | * IP blocks |
55d2cb08 BC |
52 | */ |
53 | ||
42b9e387 PW |
54 | /* |
55 | * 'c2c_target_fw' class | |
56 | * instance(s): c2c_target_fw | |
57 | */ | |
58 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | |
59 | .name = "c2c_target_fw", | |
60 | }; | |
61 | ||
62 | /* c2c_target_fw */ | |
63 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | |
64 | .name = "c2c_target_fw", | |
65 | .class = &omap44xx_c2c_target_fw_hwmod_class, | |
66 | .clkdm_name = "d2d_clkdm", | |
67 | .prcm = { | |
68 | .omap4 = { | |
69 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | |
70 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | |
71 | }, | |
72 | }, | |
73 | }; | |
74 | ||
55d2cb08 BC |
75 | /* |
76 | * 'dmm' class | |
77 | * instance(s): dmm | |
78 | */ | |
79 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 80 | .name = "dmm", |
55d2cb08 BC |
81 | }; |
82 | ||
7e69ed97 BC |
83 | /* dmm */ |
84 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
85 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
86 | { .irq = -1 } | |
87 | }; | |
88 | ||
55d2cb08 BC |
89 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
90 | .name = "dmm", | |
91 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 92 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 93 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
94 | .prcm = { |
95 | .omap4 = { | |
96 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 97 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
98 | }, |
99 | }, | |
55d2cb08 BC |
100 | }; |
101 | ||
102 | /* | |
103 | * 'emif_fw' class | |
104 | * instance(s): emif_fw | |
105 | */ | |
106 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 107 | .name = "emif_fw", |
55d2cb08 BC |
108 | }; |
109 | ||
7e69ed97 | 110 | /* emif_fw */ |
55d2cb08 BC |
111 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
112 | .name = "emif_fw", | |
113 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 114 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
115 | .prcm = { |
116 | .omap4 = { | |
117 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 118 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
119 | }, |
120 | }, | |
55d2cb08 BC |
121 | }; |
122 | ||
123 | /* | |
124 | * 'l3' class | |
125 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
126 | */ | |
127 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 128 | .name = "l3", |
55d2cb08 BC |
129 | }; |
130 | ||
7e69ed97 | 131 | /* l3_instr */ |
55d2cb08 BC |
132 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
133 | .name = "l3_instr", | |
134 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 135 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
136 | .prcm = { |
137 | .omap4 = { | |
138 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 139 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 140 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
141 | }, |
142 | }, | |
55d2cb08 BC |
143 | }; |
144 | ||
7e69ed97 | 145 | /* l3_main_1 */ |
9b4021be BC |
146 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
147 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
148 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
149 | { .irq = -1 } | |
150 | }; | |
151 | ||
55d2cb08 BC |
152 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
153 | .name = "l3_main_1", | |
154 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 155 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 156 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
157 | .prcm = { |
158 | .omap4 = { | |
159 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 160 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
161 | }, |
162 | }, | |
55d2cb08 BC |
163 | }; |
164 | ||
7e69ed97 | 165 | /* l3_main_2 */ |
55d2cb08 BC |
166 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
167 | .name = "l3_main_2", | |
168 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 169 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
170 | .prcm = { |
171 | .omap4 = { | |
172 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 173 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
174 | }, |
175 | }, | |
55d2cb08 BC |
176 | }; |
177 | ||
7e69ed97 | 178 | /* l3_main_3 */ |
55d2cb08 BC |
179 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
180 | .name = "l3_main_3", | |
181 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 182 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
183 | .prcm = { |
184 | .omap4 = { | |
185 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 186 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 187 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
188 | }, |
189 | }, | |
55d2cb08 BC |
190 | }; |
191 | ||
192 | /* | |
193 | * 'l4' class | |
194 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
195 | */ | |
196 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 197 | .name = "l4", |
55d2cb08 BC |
198 | }; |
199 | ||
7e69ed97 | 200 | /* l4_abe */ |
55d2cb08 BC |
201 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
202 | .name = "l4_abe", | |
203 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 204 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
205 | .prcm = { |
206 | .omap4 = { | |
207 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
ce80979a TK |
208 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
209 | .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, | |
46b3af27 | 210 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
d0f0631d BC |
211 | }, |
212 | }, | |
55d2cb08 BC |
213 | }; |
214 | ||
7e69ed97 | 215 | /* l4_cfg */ |
55d2cb08 BC |
216 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
217 | .name = "l4_cfg", | |
218 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 219 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
220 | .prcm = { |
221 | .omap4 = { | |
222 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 223 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
224 | }, |
225 | }, | |
55d2cb08 BC |
226 | }; |
227 | ||
7e69ed97 | 228 | /* l4_per */ |
55d2cb08 BC |
229 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
230 | .name = "l4_per", | |
231 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 232 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
233 | .prcm = { |
234 | .omap4 = { | |
235 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 236 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
237 | }, |
238 | }, | |
55d2cb08 BC |
239 | }; |
240 | ||
7e69ed97 | 241 | /* l4_wkup */ |
55d2cb08 BC |
242 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
243 | .name = "l4_wkup", | |
244 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 245 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
246 | .prcm = { |
247 | .omap4 = { | |
248 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 249 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
250 | }, |
251 | }, | |
55d2cb08 BC |
252 | }; |
253 | ||
f776471f | 254 | /* |
3b54baad BC |
255 | * 'mpu_bus' class |
256 | * instance(s): mpu_private | |
f776471f | 257 | */ |
3b54baad | 258 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 259 | .name = "mpu_bus", |
3b54baad | 260 | }; |
f776471f | 261 | |
7e69ed97 | 262 | /* mpu_private */ |
3b54baad BC |
263 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
264 | .name = "mpu_private", | |
265 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 266 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
267 | .prcm = { |
268 | .omap4 = { | |
269 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
270 | }, | |
271 | }, | |
3b54baad BC |
272 | }; |
273 | ||
9a817bc8 BC |
274 | /* |
275 | * 'ocp_wp_noc' class | |
276 | * instance(s): ocp_wp_noc | |
277 | */ | |
278 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
279 | .name = "ocp_wp_noc", | |
280 | }; | |
281 | ||
282 | /* ocp_wp_noc */ | |
283 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
284 | .name = "ocp_wp_noc", | |
285 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
286 | .clkdm_name = "l3_instr_clkdm", | |
287 | .prcm = { | |
288 | .omap4 = { | |
289 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
290 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
291 | .modulemode = MODULEMODE_HWCTRL, | |
292 | }, | |
293 | }, | |
294 | }; | |
295 | ||
3b54baad BC |
296 | /* |
297 | * Modules omap_hwmod structures | |
298 | * | |
299 | * The following IPs are excluded for the moment because: | |
300 | * - They do not need an explicit SW control using omap_hwmod API. | |
301 | * - They still need to be validated with the driver | |
302 | * properly adapted to omap_hwmod / omap_device | |
303 | * | |
96566043 | 304 | * usim |
3b54baad BC |
305 | */ |
306 | ||
407a6888 BC |
307 | /* |
308 | * 'aess' class | |
309 | * audio engine sub system | |
310 | */ | |
311 | ||
312 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
313 | .rev_offs = 0x0000, | |
314 | .sysc_offs = 0x0010, | |
315 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
316 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
317 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
318 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
319 | .sysc_fields = &omap_hwmod_sysc_type2, |
320 | }; | |
321 | ||
322 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
323 | .name = "aess", | |
324 | .sysc = &omap44xx_aess_sysc, | |
c02060d8 | 325 | .enable_preprogram = omap_hwmod_aess_preprogram, |
407a6888 BC |
326 | }; |
327 | ||
328 | /* aess */ | |
329 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
330 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 331 | { .irq = -1 } |
407a6888 BC |
332 | }; |
333 | ||
334 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
335 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
336 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
337 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
338 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
339 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
340 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
341 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
342 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 343 | { .dma_req = -1 } |
407a6888 BC |
344 | }; |
345 | ||
407a6888 BC |
346 | static struct omap_hwmod omap44xx_aess_hwmod = { |
347 | .name = "aess", | |
348 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 349 | .clkdm_name = "abe_clkdm", |
407a6888 | 350 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 351 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
9f0c5996 | 352 | .main_clk = "aess_fclk", |
00fe610b | 353 | .prcm = { |
407a6888 | 354 | .omap4 = { |
d0f0631d | 355 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 356 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
ce80979a | 357 | .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, |
03fdefe5 | 358 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
359 | }, |
360 | }, | |
407a6888 BC |
361 | }; |
362 | ||
42b9e387 PW |
363 | /* |
364 | * 'c2c' class | |
365 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
366 | * soc | |
367 | */ | |
368 | ||
369 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
370 | .name = "c2c", | |
371 | }; | |
372 | ||
373 | /* c2c */ | |
374 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | |
375 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | |
376 | { .irq = -1 } | |
377 | }; | |
378 | ||
379 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | |
380 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | |
381 | { .dma_req = -1 } | |
382 | }; | |
383 | ||
384 | static struct omap_hwmod omap44xx_c2c_hwmod = { | |
385 | .name = "c2c", | |
386 | .class = &omap44xx_c2c_hwmod_class, | |
387 | .clkdm_name = "d2d_clkdm", | |
388 | .mpu_irqs = omap44xx_c2c_irqs, | |
389 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | |
390 | .prcm = { | |
391 | .omap4 = { | |
392 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
393 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
394 | }, | |
395 | }, | |
396 | }; | |
397 | ||
407a6888 BC |
398 | /* |
399 | * 'counter' class | |
400 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
401 | */ | |
402 | ||
403 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
404 | .rev_offs = 0x0000, | |
405 | .sysc_offs = 0x0004, | |
406 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 407 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
408 | .sysc_fields = &omap_hwmod_sysc_type1, |
409 | }; | |
410 | ||
411 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
412 | .name = "counter", | |
413 | .sysc = &omap44xx_counter_sysc, | |
414 | }; | |
415 | ||
416 | /* counter_32k */ | |
407a6888 BC |
417 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
418 | .name = "counter_32k", | |
419 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 420 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
421 | .flags = HWMOD_SWSUP_SIDLE, |
422 | .main_clk = "sys_32k_ck", | |
00fe610b | 423 | .prcm = { |
407a6888 | 424 | .omap4 = { |
d0f0631d | 425 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 426 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
427 | }, |
428 | }, | |
407a6888 BC |
429 | }; |
430 | ||
a0b5d813 PW |
431 | /* |
432 | * 'ctrl_module' class | |
433 | * attila core control module + core pad control module + wkup pad control | |
434 | * module + attila wkup control module | |
435 | */ | |
436 | ||
437 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
438 | .rev_offs = 0x0000, | |
439 | .sysc_offs = 0x0010, | |
440 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
441 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
442 | SIDLE_SMART_WKUP), | |
443 | .sysc_fields = &omap_hwmod_sysc_type2, | |
444 | }; | |
445 | ||
446 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
447 | .name = "ctrl_module", | |
448 | .sysc = &omap44xx_ctrl_module_sysc, | |
449 | }; | |
450 | ||
451 | /* ctrl_module_core */ | |
452 | static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { | |
453 | { .irq = 8 + OMAP44XX_IRQ_GIC_START }, | |
454 | { .irq = -1 } | |
455 | }; | |
456 | ||
457 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { | |
458 | .name = "ctrl_module_core", | |
459 | .class = &omap44xx_ctrl_module_hwmod_class, | |
460 | .clkdm_name = "l4_cfg_clkdm", | |
461 | .mpu_irqs = omap44xx_ctrl_module_core_irqs, | |
46b3af27 TK |
462 | .prcm = { |
463 | .omap4 = { | |
464 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
465 | }, | |
466 | }, | |
a0b5d813 PW |
467 | }; |
468 | ||
469 | /* ctrl_module_pad_core */ | |
470 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
471 | .name = "ctrl_module_pad_core", | |
472 | .class = &omap44xx_ctrl_module_hwmod_class, | |
473 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
474 | .prcm = { |
475 | .omap4 = { | |
476 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
477 | }, | |
478 | }, | |
a0b5d813 PW |
479 | }; |
480 | ||
481 | /* ctrl_module_wkup */ | |
482 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
483 | .name = "ctrl_module_wkup", | |
484 | .class = &omap44xx_ctrl_module_hwmod_class, | |
485 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
486 | .prcm = { |
487 | .omap4 = { | |
488 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
489 | }, | |
490 | }, | |
a0b5d813 PW |
491 | }; |
492 | ||
493 | /* ctrl_module_pad_wkup */ | |
494 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
495 | .name = "ctrl_module_pad_wkup", | |
496 | .class = &omap44xx_ctrl_module_hwmod_class, | |
497 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
498 | .prcm = { |
499 | .omap4 = { | |
500 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
501 | }, | |
502 | }, | |
a0b5d813 PW |
503 | }; |
504 | ||
96566043 BC |
505 | /* |
506 | * 'debugss' class | |
507 | * debug and emulation sub system | |
508 | */ | |
509 | ||
510 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
511 | .name = "debugss", | |
512 | }; | |
513 | ||
514 | /* debugss */ | |
515 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
516 | .name = "debugss", | |
517 | .class = &omap44xx_debugss_hwmod_class, | |
518 | .clkdm_name = "emu_sys_clkdm", | |
519 | .main_clk = "trace_clk_div_ck", | |
520 | .prcm = { | |
521 | .omap4 = { | |
522 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
523 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
524 | }, | |
525 | }, | |
526 | }; | |
527 | ||
d7cf5f33 BC |
528 | /* |
529 | * 'dma' class | |
530 | * dma controller for data exchange between memory to memory (i.e. internal or | |
531 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
532 | */ | |
533 | ||
534 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
535 | .rev_offs = 0x0000, | |
536 | .sysc_offs = 0x002c, | |
537 | .syss_offs = 0x0028, | |
538 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
539 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
540 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
541 | SYSS_HAS_RESET_STATUS), | |
542 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
543 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
544 | .sysc_fields = &omap_hwmod_sysc_type1, | |
545 | }; | |
546 | ||
547 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
548 | .name = "dma", | |
549 | .sysc = &omap44xx_dma_sysc, | |
550 | }; | |
551 | ||
552 | /* dma dev_attr */ | |
553 | static struct omap_dma_dev_attr dma_dev_attr = { | |
554 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
555 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
556 | .lch_count = 32, | |
557 | }; | |
558 | ||
559 | /* dma_system */ | |
560 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
561 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
562 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
563 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
564 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 565 | { .irq = -1 } |
d7cf5f33 BC |
566 | }; |
567 | ||
d7cf5f33 BC |
568 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
569 | .name = "dma_system", | |
570 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 571 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 572 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
573 | .main_clk = "l3_div_ck", |
574 | .prcm = { | |
575 | .omap4 = { | |
d0f0631d | 576 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 577 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
578 | }, |
579 | }, | |
580 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
581 | }; |
582 | ||
8ca476da BC |
583 | /* |
584 | * 'dmic' class | |
585 | * digital microphone controller | |
586 | */ | |
587 | ||
588 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
589 | .rev_offs = 0x0000, | |
590 | .sysc_offs = 0x0010, | |
591 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
592 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
593 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
594 | SIDLE_SMART_WKUP), | |
595 | .sysc_fields = &omap_hwmod_sysc_type2, | |
596 | }; | |
597 | ||
598 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
599 | .name = "dmic", | |
600 | .sysc = &omap44xx_dmic_sysc, | |
601 | }; | |
602 | ||
603 | /* dmic */ | |
8ca476da BC |
604 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
605 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 606 | { .irq = -1 } |
8ca476da BC |
607 | }; |
608 | ||
609 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
610 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 611 | { .dma_req = -1 } |
8ca476da BC |
612 | }; |
613 | ||
8ca476da BC |
614 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
615 | .name = "dmic", | |
616 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 617 | .clkdm_name = "abe_clkdm", |
8ca476da | 618 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 619 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
ee877acd | 620 | .main_clk = "func_dmic_abe_gfclk", |
00fe610b | 621 | .prcm = { |
8ca476da | 622 | .omap4 = { |
d0f0631d | 623 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 624 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 625 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
626 | }, |
627 | }, | |
8ca476da BC |
628 | }; |
629 | ||
8f25bdc5 BC |
630 | /* |
631 | * 'dsp' class | |
632 | * dsp sub-system | |
633 | */ | |
634 | ||
635 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 636 | .name = "dsp", |
8f25bdc5 BC |
637 | }; |
638 | ||
639 | /* dsp */ | |
640 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
641 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 642 | { .irq = -1 } |
8f25bdc5 BC |
643 | }; |
644 | ||
645 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 BC |
646 | { .name = "dsp", .rst_shift = 0 }, |
647 | }; | |
648 | ||
8f25bdc5 BC |
649 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
650 | .name = "dsp", | |
651 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 652 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 653 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
654 | .rst_lines = omap44xx_dsp_resets, |
655 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
298ea44f | 656 | .main_clk = "dpll_iva_m4x2_ck", |
8f25bdc5 BC |
657 | .prcm = { |
658 | .omap4 = { | |
d0f0631d | 659 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 660 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 661 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 662 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
663 | }, |
664 | }, | |
8f25bdc5 BC |
665 | }; |
666 | ||
d63bd74f BC |
667 | /* |
668 | * 'dss' class | |
669 | * display sub-system | |
670 | */ | |
671 | ||
672 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
673 | .rev_offs = 0x0000, | |
674 | .syss_offs = 0x0014, | |
675 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
676 | }; | |
677 | ||
678 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
679 | .name = "dss", | |
680 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 681 | .reset = omap_dss_reset, |
d63bd74f BC |
682 | }; |
683 | ||
684 | /* dss */ | |
d63bd74f BC |
685 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
686 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
687 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 688 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
689 | }; |
690 | ||
691 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
692 | .name = "dss_core", | |
37ad0855 | 693 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 694 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 695 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 696 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
697 | .prcm = { |
698 | .omap4 = { | |
d0f0631d | 699 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 700 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
701 | }, |
702 | }, | |
703 | .opt_clks = dss_opt_clks, | |
704 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
705 | }; |
706 | ||
707 | /* | |
708 | * 'dispc' class | |
709 | * display controller | |
710 | */ | |
711 | ||
712 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
713 | .rev_offs = 0x0000, | |
714 | .sysc_offs = 0x0010, | |
715 | .syss_offs = 0x0014, | |
716 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
717 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
718 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
719 | SYSS_HAS_RESET_STATUS), | |
720 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
721 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
722 | .sysc_fields = &omap_hwmod_sysc_type1, | |
723 | }; | |
724 | ||
725 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
726 | .name = "dispc", | |
727 | .sysc = &omap44xx_dispc_sysc, | |
728 | }; | |
729 | ||
730 | /* dss_dispc */ | |
d63bd74f BC |
731 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
732 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 733 | { .irq = -1 } |
d63bd74f BC |
734 | }; |
735 | ||
736 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
737 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 738 | { .dma_req = -1 } |
d63bd74f BC |
739 | }; |
740 | ||
b923d40d AT |
741 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
742 | .manager_count = 3, | |
743 | .has_framedonetv_irq = 1 | |
744 | }; | |
745 | ||
d63bd74f BC |
746 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
747 | .name = "dss_dispc", | |
748 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 749 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 750 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 751 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 752 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
753 | .prcm = { |
754 | .omap4 = { | |
d0f0631d | 755 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 756 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
757 | }, |
758 | }, | |
b923d40d | 759 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
760 | }; |
761 | ||
762 | /* | |
763 | * 'dsi' class | |
764 | * display serial interface controller | |
765 | */ | |
766 | ||
767 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
768 | .rev_offs = 0x0000, | |
769 | .sysc_offs = 0x0010, | |
770 | .syss_offs = 0x0014, | |
771 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
772 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
773 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
774 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
775 | .sysc_fields = &omap_hwmod_sysc_type1, | |
776 | }; | |
777 | ||
778 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
779 | .name = "dsi", | |
780 | .sysc = &omap44xx_dsi_sysc, | |
781 | }; | |
782 | ||
783 | /* dss_dsi1 */ | |
d63bd74f BC |
784 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
785 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 786 | { .irq = -1 } |
d63bd74f BC |
787 | }; |
788 | ||
789 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
790 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 791 | { .dma_req = -1 } |
d63bd74f BC |
792 | }; |
793 | ||
3a23aafc TV |
794 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
795 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
796 | }; | |
797 | ||
d63bd74f BC |
798 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
799 | .name = "dss_dsi1", | |
800 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 801 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 802 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 803 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 804 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
805 | .prcm = { |
806 | .omap4 = { | |
d0f0631d | 807 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 808 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
809 | }, |
810 | }, | |
3a23aafc TV |
811 | .opt_clks = dss_dsi1_opt_clks, |
812 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
813 | }; |
814 | ||
815 | /* dss_dsi2 */ | |
d63bd74f BC |
816 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
817 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 818 | { .irq = -1 } |
d63bd74f BC |
819 | }; |
820 | ||
821 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
822 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 823 | { .dma_req = -1 } |
d63bd74f BC |
824 | }; |
825 | ||
3a23aafc TV |
826 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
827 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
828 | }; | |
829 | ||
d63bd74f BC |
830 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
831 | .name = "dss_dsi2", | |
832 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 833 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 834 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 835 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 836 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
837 | .prcm = { |
838 | .omap4 = { | |
d0f0631d | 839 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 840 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
841 | }, |
842 | }, | |
3a23aafc TV |
843 | .opt_clks = dss_dsi2_opt_clks, |
844 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
845 | }; |
846 | ||
847 | /* | |
848 | * 'hdmi' class | |
849 | * hdmi controller | |
850 | */ | |
851 | ||
852 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
853 | .rev_offs = 0x0000, | |
854 | .sysc_offs = 0x0010, | |
855 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
856 | SYSC_HAS_SOFTRESET), | |
857 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
858 | SIDLE_SMART_WKUP), | |
859 | .sysc_fields = &omap_hwmod_sysc_type2, | |
860 | }; | |
861 | ||
862 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
863 | .name = "hdmi", | |
864 | .sysc = &omap44xx_hdmi_sysc, | |
865 | }; | |
866 | ||
867 | /* dss_hdmi */ | |
d63bd74f BC |
868 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
869 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 870 | { .irq = -1 } |
d63bd74f BC |
871 | }; |
872 | ||
873 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
874 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 875 | { .dma_req = -1 } |
d63bd74f BC |
876 | }; |
877 | ||
3a23aafc TV |
878 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
879 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
880 | }; | |
881 | ||
d63bd74f BC |
882 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
883 | .name = "dss_hdmi", | |
884 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 885 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
886 | /* |
887 | * HDMI audio requires to use no-idle mode. Hence, | |
888 | * set idle mode by software. | |
889 | */ | |
890 | .flags = HWMOD_SWSUP_SIDLE, | |
d63bd74f | 891 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 892 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 893 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
894 | .prcm = { |
895 | .omap4 = { | |
d0f0631d | 896 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 897 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
898 | }, |
899 | }, | |
3a23aafc TV |
900 | .opt_clks = dss_hdmi_opt_clks, |
901 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
902 | }; |
903 | ||
904 | /* | |
905 | * 'rfbi' class | |
906 | * remote frame buffer interface | |
907 | */ | |
908 | ||
909 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
910 | .rev_offs = 0x0000, | |
911 | .sysc_offs = 0x0010, | |
912 | .syss_offs = 0x0014, | |
913 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
914 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
915 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
916 | .sysc_fields = &omap_hwmod_sysc_type1, | |
917 | }; | |
918 | ||
919 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
920 | .name = "rfbi", | |
921 | .sysc = &omap44xx_rfbi_sysc, | |
922 | }; | |
923 | ||
924 | /* dss_rfbi */ | |
d63bd74f BC |
925 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
926 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 927 | { .dma_req = -1 } |
d63bd74f BC |
928 | }; |
929 | ||
3a23aafc TV |
930 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
931 | { .role = "ick", .clk = "dss_fck" }, | |
932 | }; | |
933 | ||
d63bd74f BC |
934 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
935 | .name = "dss_rfbi", | |
936 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 937 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 938 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 939 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
940 | .prcm = { |
941 | .omap4 = { | |
d0f0631d | 942 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 943 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
944 | }, |
945 | }, | |
3a23aafc TV |
946 | .opt_clks = dss_rfbi_opt_clks, |
947 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
948 | }; |
949 | ||
950 | /* | |
951 | * 'venc' class | |
952 | * video encoder | |
953 | */ | |
954 | ||
955 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
956 | .name = "venc", | |
957 | }; | |
958 | ||
959 | /* dss_venc */ | |
d63bd74f BC |
960 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
961 | .name = "dss_venc", | |
962 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 963 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 964 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
965 | .prcm = { |
966 | .omap4 = { | |
d0f0631d | 967 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 968 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
969 | }, |
970 | }, | |
d63bd74f BC |
971 | }; |
972 | ||
42b9e387 PW |
973 | /* |
974 | * 'elm' class | |
975 | * bch error location module | |
976 | */ | |
977 | ||
978 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
979 | .rev_offs = 0x0000, | |
980 | .sysc_offs = 0x0010, | |
981 | .syss_offs = 0x0014, | |
982 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
983 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
984 | SYSS_HAS_RESET_STATUS), | |
985 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
986 | .sysc_fields = &omap_hwmod_sysc_type1, | |
987 | }; | |
988 | ||
989 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
990 | .name = "elm", | |
991 | .sysc = &omap44xx_elm_sysc, | |
992 | }; | |
993 | ||
994 | /* elm */ | |
995 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | |
996 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | |
997 | { .irq = -1 } | |
998 | }; | |
999 | ||
1000 | static struct omap_hwmod omap44xx_elm_hwmod = { | |
1001 | .name = "elm", | |
1002 | .class = &omap44xx_elm_hwmod_class, | |
1003 | .clkdm_name = "l4_per_clkdm", | |
1004 | .mpu_irqs = omap44xx_elm_irqs, | |
1005 | .prcm = { | |
1006 | .omap4 = { | |
1007 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
1008 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
1009 | }, | |
1010 | }, | |
1011 | }; | |
1012 | ||
bf30f950 PW |
1013 | /* |
1014 | * 'emif' class | |
1015 | * external memory interface no1 | |
1016 | */ | |
1017 | ||
1018 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
1019 | .rev_offs = 0x0000, | |
1020 | }; | |
1021 | ||
1022 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
1023 | .name = "emif", | |
1024 | .sysc = &omap44xx_emif_sysc, | |
1025 | }; | |
1026 | ||
1027 | /* emif1 */ | |
1028 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | |
1029 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | |
1030 | { .irq = -1 } | |
1031 | }; | |
1032 | ||
1033 | static struct omap_hwmod omap44xx_emif1_hwmod = { | |
1034 | .name = "emif1", | |
1035 | .class = &omap44xx_emif_hwmod_class, | |
1036 | .clkdm_name = "l3_emif_clkdm", | |
1037 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1038 | .mpu_irqs = omap44xx_emif1_irqs, | |
1039 | .main_clk = "ddrphy_ck", | |
1040 | .prcm = { | |
1041 | .omap4 = { | |
1042 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
1043 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
1044 | .modulemode = MODULEMODE_HWCTRL, | |
1045 | }, | |
1046 | }, | |
1047 | }; | |
1048 | ||
1049 | /* emif2 */ | |
1050 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | |
1051 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | |
1052 | { .irq = -1 } | |
1053 | }; | |
1054 | ||
1055 | static struct omap_hwmod omap44xx_emif2_hwmod = { | |
1056 | .name = "emif2", | |
1057 | .class = &omap44xx_emif_hwmod_class, | |
1058 | .clkdm_name = "l3_emif_clkdm", | |
1059 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1060 | .mpu_irqs = omap44xx_emif2_irqs, | |
1061 | .main_clk = "ddrphy_ck", | |
1062 | .prcm = { | |
1063 | .omap4 = { | |
1064 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
1065 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
1066 | .modulemode = MODULEMODE_HWCTRL, | |
1067 | }, | |
1068 | }, | |
1069 | }; | |
1070 | ||
b050f688 ML |
1071 | /* |
1072 | * 'fdif' class | |
1073 | * face detection hw accelerator module | |
1074 | */ | |
1075 | ||
1076 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
1077 | .rev_offs = 0x0000, | |
1078 | .sysc_offs = 0x0010, | |
1079 | /* | |
1080 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
1081 | * accessing sysconfig again. | |
1082 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1083 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1084 | * | |
1085 | * TODO: Indicate errata when available. | |
1086 | */ | |
1087 | .srst_udelay = 2, | |
1088 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
1089 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1090 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1091 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1092 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1093 | }; | |
1094 | ||
1095 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1096 | .name = "fdif", | |
1097 | .sysc = &omap44xx_fdif_sysc, | |
1098 | }; | |
1099 | ||
1100 | /* fdif */ | |
1101 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
1102 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
1103 | { .irq = -1 } | |
1104 | }; | |
1105 | ||
1106 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
1107 | .name = "fdif", | |
1108 | .class = &omap44xx_fdif_hwmod_class, | |
1109 | .clkdm_name = "iss_clkdm", | |
1110 | .mpu_irqs = omap44xx_fdif_irqs, | |
1111 | .main_clk = "fdif_fck", | |
1112 | .prcm = { | |
1113 | .omap4 = { | |
1114 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1115 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1116 | .modulemode = MODULEMODE_SWCTRL, | |
1117 | }, | |
1118 | }, | |
1119 | }; | |
1120 | ||
3b54baad BC |
1121 | /* |
1122 | * 'gpio' class | |
1123 | * general purpose io module | |
1124 | */ | |
1125 | ||
1126 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1127 | .rev_offs = 0x0000, | |
f776471f | 1128 | .sysc_offs = 0x0010, |
3b54baad | 1129 | .syss_offs = 0x0114, |
0cfe8751 BC |
1130 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1131 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1132 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1133 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1134 | SIDLE_SMART_WKUP), | |
f776471f BC |
1135 | .sysc_fields = &omap_hwmod_sysc_type1, |
1136 | }; | |
1137 | ||
3b54baad | 1138 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1139 | .name = "gpio", |
1140 | .sysc = &omap44xx_gpio_sysc, | |
1141 | .rev = 2, | |
f776471f BC |
1142 | }; |
1143 | ||
3b54baad BC |
1144 | /* gpio dev_attr */ |
1145 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1146 | .bank_width = 32, |
1147 | .dbck_flag = true, | |
f776471f BC |
1148 | }; |
1149 | ||
3b54baad | 1150 | /* gpio1 */ |
3b54baad BC |
1151 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1152 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1153 | { .irq = -1 } |
f776471f BC |
1154 | }; |
1155 | ||
3b54baad | 1156 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1157 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1158 | }; |
1159 | ||
1160 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1161 | .name = "gpio1", | |
1162 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1163 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1164 | .mpu_irqs = omap44xx_gpio1_irqs, |
17b7e7d3 | 1165 | .main_clk = "l4_wkup_clk_mux_ck", |
f776471f BC |
1166 | .prcm = { |
1167 | .omap4 = { | |
d0f0631d | 1168 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1169 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1170 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1171 | }, |
1172 | }, | |
3b54baad BC |
1173 | .opt_clks = gpio1_opt_clks, |
1174 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1175 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1176 | }; |
1177 | ||
3b54baad | 1178 | /* gpio2 */ |
3b54baad BC |
1179 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1180 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1181 | { .irq = -1 } |
f776471f BC |
1182 | }; |
1183 | ||
3b54baad | 1184 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1185 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1186 | }; |
1187 | ||
1188 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1189 | .name = "gpio2", | |
1190 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1191 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1192 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1193 | .mpu_irqs = omap44xx_gpio2_irqs, |
17b7e7d3 | 1194 | .main_clk = "l4_div_ck", |
f776471f BC |
1195 | .prcm = { |
1196 | .omap4 = { | |
d0f0631d | 1197 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1198 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1199 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1200 | }, |
1201 | }, | |
3b54baad BC |
1202 | .opt_clks = gpio2_opt_clks, |
1203 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1204 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1205 | }; |
1206 | ||
3b54baad | 1207 | /* gpio3 */ |
3b54baad BC |
1208 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1209 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1210 | { .irq = -1 } |
f776471f BC |
1211 | }; |
1212 | ||
3b54baad | 1213 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1214 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1215 | }; |
1216 | ||
1217 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1218 | .name = "gpio3", | |
1219 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1220 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1221 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1222 | .mpu_irqs = omap44xx_gpio3_irqs, |
17b7e7d3 | 1223 | .main_clk = "l4_div_ck", |
f776471f BC |
1224 | .prcm = { |
1225 | .omap4 = { | |
d0f0631d | 1226 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1227 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1228 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1229 | }, |
1230 | }, | |
3b54baad BC |
1231 | .opt_clks = gpio3_opt_clks, |
1232 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1233 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1234 | }; |
1235 | ||
3b54baad | 1236 | /* gpio4 */ |
3b54baad BC |
1237 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1238 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1239 | { .irq = -1 } |
f776471f BC |
1240 | }; |
1241 | ||
3b54baad | 1242 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1243 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1244 | }; |
1245 | ||
1246 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1247 | .name = "gpio4", | |
1248 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1249 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1250 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1251 | .mpu_irqs = omap44xx_gpio4_irqs, |
17b7e7d3 | 1252 | .main_clk = "l4_div_ck", |
f776471f BC |
1253 | .prcm = { |
1254 | .omap4 = { | |
d0f0631d | 1255 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1256 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1257 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1258 | }, |
1259 | }, | |
3b54baad BC |
1260 | .opt_clks = gpio4_opt_clks, |
1261 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1262 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1263 | }; |
1264 | ||
3b54baad | 1265 | /* gpio5 */ |
3b54baad BC |
1266 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1267 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1268 | { .irq = -1 } |
55d2cb08 BC |
1269 | }; |
1270 | ||
844a3b63 PW |
1271 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1272 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1273 | }; |
1274 | ||
3b54baad BC |
1275 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1276 | .name = "gpio5", | |
1277 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1278 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1279 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1280 | .mpu_irqs = omap44xx_gpio5_irqs, |
17b7e7d3 | 1281 | .main_clk = "l4_div_ck", |
55d2cb08 BC |
1282 | .prcm = { |
1283 | .omap4 = { | |
d0f0631d | 1284 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1285 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1286 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1287 | }, |
1288 | }, | |
3b54baad BC |
1289 | .opt_clks = gpio5_opt_clks, |
1290 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1291 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1292 | }; |
1293 | ||
3b54baad | 1294 | /* gpio6 */ |
3b54baad BC |
1295 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1296 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1297 | { .irq = -1 } |
92b18d1c BC |
1298 | }; |
1299 | ||
3b54baad | 1300 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1301 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1302 | }; |
1303 | ||
3b54baad BC |
1304 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1305 | .name = "gpio6", | |
1306 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1307 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1308 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1309 | .mpu_irqs = omap44xx_gpio6_irqs, |
17b7e7d3 | 1310 | .main_clk = "l4_div_ck", |
3b54baad BC |
1311 | .prcm = { |
1312 | .omap4 = { | |
d0f0631d | 1313 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1314 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1315 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1316 | }, |
db12ba53 | 1317 | }, |
3b54baad BC |
1318 | .opt_clks = gpio6_opt_clks, |
1319 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1320 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1321 | }; |
1322 | ||
eb42b5d3 BC |
1323 | /* |
1324 | * 'gpmc' class | |
1325 | * general purpose memory controller | |
1326 | */ | |
1327 | ||
1328 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1329 | .rev_offs = 0x0000, | |
1330 | .sysc_offs = 0x0010, | |
1331 | .syss_offs = 0x0014, | |
1332 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1333 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1334 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1335 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1336 | }; | |
1337 | ||
1338 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1339 | .name = "gpmc", | |
1340 | .sysc = &omap44xx_gpmc_sysc, | |
1341 | }; | |
1342 | ||
1343 | /* gpmc */ | |
1344 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1345 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1346 | { .irq = -1 } | |
1347 | }; | |
1348 | ||
1349 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1350 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1351 | { .dma_req = -1 } | |
1352 | }; | |
1353 | ||
1354 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1355 | .name = "gpmc", | |
1356 | .class = &omap44xx_gpmc_hwmod_class, | |
1357 | .clkdm_name = "l3_2_clkdm", | |
49484a60 AM |
1358 | /* |
1359 | * XXX HWMOD_INIT_NO_RESET should not be needed for this IP | |
1360 | * block. It is not being added due to any known bugs with | |
1361 | * resetting the GPMC IP block, but rather because any timings | |
1362 | * set by the bootloader are not being correctly programmed by | |
1363 | * the kernel from the board file or DT data. | |
1364 | * HWMOD_INIT_NO_RESET should be removed ASAP. | |
1365 | */ | |
eb42b5d3 BC |
1366 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
1367 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1368 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1369 | .prcm = { | |
1370 | .omap4 = { | |
1371 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1372 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1373 | .modulemode = MODULEMODE_HWCTRL, | |
1374 | }, | |
1375 | }, | |
1376 | }; | |
1377 | ||
9def390e PW |
1378 | /* |
1379 | * 'gpu' class | |
1380 | * 2d/3d graphics accelerator | |
1381 | */ | |
1382 | ||
1383 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1384 | .rev_offs = 0x1fc00, | |
1385 | .sysc_offs = 0x1fc10, | |
1386 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1387 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1388 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1389 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1390 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1391 | }; | |
1392 | ||
1393 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1394 | .name = "gpu", | |
1395 | .sysc = &omap44xx_gpu_sysc, | |
1396 | }; | |
1397 | ||
1398 | /* gpu */ | |
1399 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | |
1400 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | |
1401 | { .irq = -1 } | |
1402 | }; | |
1403 | ||
1404 | static struct omap_hwmod omap44xx_gpu_hwmod = { | |
1405 | .name = "gpu", | |
1406 | .class = &omap44xx_gpu_hwmod_class, | |
1407 | .clkdm_name = "l3_gfx_clkdm", | |
1408 | .mpu_irqs = omap44xx_gpu_irqs, | |
ee877acd | 1409 | .main_clk = "sgx_clk_mux", |
9def390e PW |
1410 | .prcm = { |
1411 | .omap4 = { | |
1412 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1413 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1414 | .modulemode = MODULEMODE_SWCTRL, | |
1415 | }, | |
1416 | }, | |
1417 | }; | |
1418 | ||
a091c08e PW |
1419 | /* |
1420 | * 'hdq1w' class | |
1421 | * hdq / 1-wire serial interface controller | |
1422 | */ | |
1423 | ||
1424 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1425 | .rev_offs = 0x0000, | |
1426 | .sysc_offs = 0x0014, | |
1427 | .syss_offs = 0x0018, | |
1428 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1429 | SYSS_HAS_RESET_STATUS), | |
1430 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1431 | }; | |
1432 | ||
1433 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1434 | .name = "hdq1w", | |
1435 | .sysc = &omap44xx_hdq1w_sysc, | |
1436 | }; | |
1437 | ||
1438 | /* hdq1w */ | |
1439 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1440 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1441 | { .irq = -1 } | |
1442 | }; | |
1443 | ||
1444 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1445 | .name = "hdq1w", | |
1446 | .class = &omap44xx_hdq1w_hwmod_class, | |
1447 | .clkdm_name = "l4_per_clkdm", | |
1448 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1449 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
17b7e7d3 | 1450 | .main_clk = "func_12m_fclk", |
a091c08e PW |
1451 | .prcm = { |
1452 | .omap4 = { | |
1453 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1454 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1455 | .modulemode = MODULEMODE_SWCTRL, | |
1456 | }, | |
1457 | }, | |
1458 | }; | |
1459 | ||
407a6888 BC |
1460 | /* |
1461 | * 'hsi' class | |
1462 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1463 | * serial if) | |
1464 | */ | |
1465 | ||
1466 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1467 | .rev_offs = 0x0000, | |
1468 | .sysc_offs = 0x0010, | |
1469 | .syss_offs = 0x0014, | |
1470 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1471 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1472 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1473 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1474 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1475 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1476 | .sysc_fields = &omap_hwmod_sysc_type1, |
1477 | }; | |
1478 | ||
1479 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1480 | .name = "hsi", | |
1481 | .sysc = &omap44xx_hsi_sysc, | |
1482 | }; | |
1483 | ||
1484 | /* hsi */ | |
1485 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1486 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1487 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1488 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1489 | { .irq = -1 } |
407a6888 BC |
1490 | }; |
1491 | ||
407a6888 BC |
1492 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1493 | .name = "hsi", | |
1494 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1495 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1496 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1497 | .main_clk = "hsi_fck", |
00fe610b | 1498 | .prcm = { |
407a6888 | 1499 | .omap4 = { |
d0f0631d | 1500 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1501 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1502 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1503 | }, |
1504 | }, | |
407a6888 BC |
1505 | }; |
1506 | ||
3b54baad BC |
1507 | /* |
1508 | * 'i2c' class | |
1509 | * multimaster high-speed i2c controller | |
1510 | */ | |
db12ba53 | 1511 | |
3b54baad BC |
1512 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1513 | .sysc_offs = 0x0010, | |
1514 | .syss_offs = 0x0090, | |
1515 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1516 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1517 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1518 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1519 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1520 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1521 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1522 | }; |
1523 | ||
3b54baad | 1524 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1525 | .name = "i2c", |
1526 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1527 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1528 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1529 | }; |
1530 | ||
4d4441a6 | 1531 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
972deb4f | 1532 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
4d4441a6 AG |
1533 | }; |
1534 | ||
3b54baad | 1535 | /* i2c1 */ |
3b54baad BC |
1536 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1537 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1538 | { .irq = -1 } |
db12ba53 BC |
1539 | }; |
1540 | ||
3b54baad BC |
1541 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1542 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1543 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1544 | { .dma_req = -1 } |
db12ba53 BC |
1545 | }; |
1546 | ||
3b54baad BC |
1547 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1548 | .name = "i2c1", | |
1549 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1550 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1551 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1552 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1553 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
17b7e7d3 | 1554 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1555 | .prcm = { |
1556 | .omap4 = { | |
d0f0631d | 1557 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1558 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1559 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1560 | }, |
1561 | }, | |
4d4441a6 | 1562 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1563 | }; |
1564 | ||
3b54baad | 1565 | /* i2c2 */ |
3b54baad BC |
1566 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1567 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1568 | { .irq = -1 } |
92b18d1c BC |
1569 | }; |
1570 | ||
3b54baad BC |
1571 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1572 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1573 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1574 | { .dma_req = -1 } |
3b54baad BC |
1575 | }; |
1576 | ||
3b54baad BC |
1577 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1578 | .name = "i2c2", | |
1579 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1580 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1581 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1582 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1583 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
17b7e7d3 | 1584 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1585 | .prcm = { |
1586 | .omap4 = { | |
d0f0631d | 1587 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1588 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1589 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1590 | }, |
1591 | }, | |
4d4441a6 | 1592 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1593 | }; |
1594 | ||
3b54baad | 1595 | /* i2c3 */ |
3b54baad BC |
1596 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1597 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1598 | { .irq = -1 } |
db12ba53 BC |
1599 | }; |
1600 | ||
3b54baad BC |
1601 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1602 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1603 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1604 | { .dma_req = -1 } |
92b18d1c BC |
1605 | }; |
1606 | ||
3b54baad BC |
1607 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1608 | .name = "i2c3", | |
1609 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1610 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1611 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1612 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1613 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
17b7e7d3 | 1614 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1615 | .prcm = { |
1616 | .omap4 = { | |
d0f0631d | 1617 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1618 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1619 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1620 | }, |
1621 | }, | |
4d4441a6 | 1622 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1623 | }; |
1624 | ||
3b54baad | 1625 | /* i2c4 */ |
3b54baad BC |
1626 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1627 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1628 | { .irq = -1 } |
db12ba53 BC |
1629 | }; |
1630 | ||
3b54baad BC |
1631 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1632 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1633 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1634 | { .dma_req = -1 } |
db12ba53 BC |
1635 | }; |
1636 | ||
3b54baad BC |
1637 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1638 | .name = "i2c4", | |
1639 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1640 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1641 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1642 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1643 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
17b7e7d3 | 1644 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1645 | .prcm = { |
1646 | .omap4 = { | |
d0f0631d | 1647 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1648 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1649 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1650 | }, |
1651 | }, | |
4d4441a6 | 1652 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1653 | }; |
1654 | ||
407a6888 BC |
1655 | /* |
1656 | * 'ipu' class | |
1657 | * imaging processor unit | |
1658 | */ | |
1659 | ||
1660 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1661 | .name = "ipu", | |
1662 | }; | |
1663 | ||
1664 | /* ipu */ | |
1665 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1666 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1667 | { .irq = -1 } |
407a6888 BC |
1668 | }; |
1669 | ||
f2f5736c | 1670 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1671 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1672 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1673 | }; |
1674 | ||
407a6888 BC |
1675 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1676 | .name = "ipu", | |
1677 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1678 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1679 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1680 | .rst_lines = omap44xx_ipu_resets, |
1681 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
298ea44f | 1682 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1683 | .prcm = { |
407a6888 | 1684 | .omap4 = { |
d0f0631d | 1685 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1686 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1687 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1688 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1689 | }, |
1690 | }, | |
407a6888 BC |
1691 | }; |
1692 | ||
1693 | /* | |
1694 | * 'iss' class | |
1695 | * external images sensor pixel data processor | |
1696 | */ | |
1697 | ||
1698 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1699 | .rev_offs = 0x0000, | |
1700 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1701 | /* |
1702 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1703 | * accessing sysconfig again. | |
1704 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1705 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1706 | * | |
1707 | * TODO: Indicate errata when available. | |
1708 | */ | |
1709 | .srst_udelay = 2, | |
407a6888 BC |
1710 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1711 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1712 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1713 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1714 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1715 | .sysc_fields = &omap_hwmod_sysc_type2, |
1716 | }; | |
1717 | ||
1718 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1719 | .name = "iss", | |
1720 | .sysc = &omap44xx_iss_sysc, | |
1721 | }; | |
1722 | ||
1723 | /* iss */ | |
1724 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1725 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1726 | { .irq = -1 } |
407a6888 BC |
1727 | }; |
1728 | ||
1729 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1730 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1731 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1732 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1733 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1734 | { .dma_req = -1 } |
407a6888 BC |
1735 | }; |
1736 | ||
407a6888 BC |
1737 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1738 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1739 | }; | |
1740 | ||
1741 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1742 | .name = "iss", | |
1743 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1744 | .clkdm_name = "iss_clkdm", |
407a6888 | 1745 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1746 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
17b7e7d3 | 1747 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1748 | .prcm = { |
407a6888 | 1749 | .omap4 = { |
d0f0631d | 1750 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1751 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1752 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1753 | }, |
1754 | }, | |
1755 | .opt_clks = iss_opt_clks, | |
1756 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1757 | }; |
1758 | ||
8f25bdc5 BC |
1759 | /* |
1760 | * 'iva' class | |
1761 | * multi-standard video encoder/decoder hardware accelerator | |
1762 | */ | |
1763 | ||
1764 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1765 | .name = "iva", |
8f25bdc5 BC |
1766 | }; |
1767 | ||
1768 | /* iva */ | |
1769 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1770 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1771 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1772 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1773 | { .irq = -1 } |
8f25bdc5 BC |
1774 | }; |
1775 | ||
1776 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1777 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1778 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1779 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1780 | }; |
1781 | ||
8f25bdc5 BC |
1782 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1783 | .name = "iva", | |
1784 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1785 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1786 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1787 | .rst_lines = omap44xx_iva_resets, |
1788 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
17b7e7d3 | 1789 | .main_clk = "dpll_iva_m5x2_ck", |
8f25bdc5 BC |
1790 | .prcm = { |
1791 | .omap4 = { | |
d0f0631d | 1792 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1793 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1794 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1795 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1796 | }, |
1797 | }, | |
8f25bdc5 BC |
1798 | }; |
1799 | ||
407a6888 BC |
1800 | /* |
1801 | * 'kbd' class | |
1802 | * keyboard controller | |
1803 | */ | |
1804 | ||
1805 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1806 | .rev_offs = 0x0000, | |
1807 | .sysc_offs = 0x0010, | |
1808 | .syss_offs = 0x0014, | |
1809 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1810 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1811 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1812 | SYSS_HAS_RESET_STATUS), | |
1813 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1814 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1815 | }; | |
1816 | ||
1817 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1818 | .name = "kbd", | |
1819 | .sysc = &omap44xx_kbd_sysc, | |
1820 | }; | |
1821 | ||
1822 | /* kbd */ | |
407a6888 BC |
1823 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1824 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1825 | { .irq = -1 } |
407a6888 BC |
1826 | }; |
1827 | ||
407a6888 BC |
1828 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1829 | .name = "kbd", | |
1830 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1831 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1832 | .mpu_irqs = omap44xx_kbd_irqs, |
17b7e7d3 | 1833 | .main_clk = "sys_32k_ck", |
00fe610b | 1834 | .prcm = { |
407a6888 | 1835 | .omap4 = { |
d0f0631d | 1836 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1837 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1838 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1839 | }, |
1840 | }, | |
407a6888 BC |
1841 | }; |
1842 | ||
ec5df927 BC |
1843 | /* |
1844 | * 'mailbox' class | |
1845 | * mailbox module allowing communication between the on-chip processors using a | |
1846 | * queued mailbox-interrupt mechanism. | |
1847 | */ | |
1848 | ||
1849 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1850 | .rev_offs = 0x0000, | |
1851 | .sysc_offs = 0x0010, | |
1852 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1853 | SYSC_HAS_SOFTRESET), | |
1854 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1855 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1856 | }; | |
1857 | ||
1858 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1859 | .name = "mailbox", | |
1860 | .sysc = &omap44xx_mailbox_sysc, | |
1861 | }; | |
1862 | ||
1863 | /* mailbox */ | |
ec5df927 BC |
1864 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1865 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1866 | { .irq = -1 } |
ec5df927 BC |
1867 | }; |
1868 | ||
ec5df927 BC |
1869 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1870 | .name = "mailbox", | |
1871 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1872 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1873 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1874 | .prcm = { |
ec5df927 | 1875 | .omap4 = { |
d0f0631d | 1876 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1877 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1878 | }, |
1879 | }, | |
ec5df927 BC |
1880 | }; |
1881 | ||
896d4e98 BC |
1882 | /* |
1883 | * 'mcasp' class | |
1884 | * multi-channel audio serial port controller | |
1885 | */ | |
1886 | ||
1887 | /* The IP is not compliant to type1 / type2 scheme */ | |
1888 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1889 | .sidle_shift = 0, | |
1890 | }; | |
1891 | ||
1892 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1893 | .sysc_offs = 0x0004, | |
1894 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1895 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1896 | SIDLE_SMART_WKUP), | |
1897 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1898 | }; | |
1899 | ||
1900 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1901 | .name = "mcasp", | |
1902 | .sysc = &omap44xx_mcasp_sysc, | |
1903 | }; | |
1904 | ||
1905 | /* mcasp */ | |
1906 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | |
1907 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | |
1908 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | |
1909 | { .irq = -1 } | |
1910 | }; | |
1911 | ||
1912 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | |
1913 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | |
1914 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | |
1915 | { .dma_req = -1 } | |
1916 | }; | |
1917 | ||
1918 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | |
1919 | .name = "mcasp", | |
1920 | .class = &omap44xx_mcasp_hwmod_class, | |
1921 | .clkdm_name = "abe_clkdm", | |
1922 | .mpu_irqs = omap44xx_mcasp_irqs, | |
1923 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | |
ee877acd | 1924 | .main_clk = "func_mcasp_abe_gfclk", |
896d4e98 BC |
1925 | .prcm = { |
1926 | .omap4 = { | |
1927 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1928 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1929 | .modulemode = MODULEMODE_SWCTRL, | |
1930 | }, | |
1931 | }, | |
1932 | }; | |
1933 | ||
4ddff493 BC |
1934 | /* |
1935 | * 'mcbsp' class | |
1936 | * multi channel buffered serial port controller | |
1937 | */ | |
1938 | ||
1939 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1940 | .sysc_offs = 0x008c, | |
1941 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1942 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1943 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1944 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1945 | }; | |
1946 | ||
1947 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1948 | .name = "mcbsp", | |
1949 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1950 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1951 | }; |
1952 | ||
1953 | /* mcbsp1 */ | |
4ddff493 | 1954 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
437e8970 | 1955 | { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1956 | { .irq = -1 } |
4ddff493 BC |
1957 | }; |
1958 | ||
1959 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1960 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1961 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1962 | { .dma_req = -1 } |
4ddff493 BC |
1963 | }; |
1964 | ||
503d0ea2 PW |
1965 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1966 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1967 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1968 | }; |
1969 | ||
4ddff493 BC |
1970 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1971 | .name = "mcbsp1", | |
1972 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1973 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1974 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1975 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
ee877acd | 1976 | .main_clk = "func_mcbsp1_gfclk", |
4ddff493 BC |
1977 | .prcm = { |
1978 | .omap4 = { | |
d0f0631d | 1979 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1980 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1981 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1982 | }, |
1983 | }, | |
503d0ea2 PW |
1984 | .opt_clks = mcbsp1_opt_clks, |
1985 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1986 | }; |
1987 | ||
1988 | /* mcbsp2 */ | |
4ddff493 | 1989 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
437e8970 | 1990 | { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1991 | { .irq = -1 } |
4ddff493 BC |
1992 | }; |
1993 | ||
1994 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1995 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1996 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1997 | { .dma_req = -1 } |
4ddff493 BC |
1998 | }; |
1999 | ||
844a3b63 PW |
2000 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
2001 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2002 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
2003 | }; |
2004 | ||
4ddff493 BC |
2005 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
2006 | .name = "mcbsp2", | |
2007 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2008 | .clkdm_name = "abe_clkdm", |
4ddff493 | 2009 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 2010 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
ee877acd | 2011 | .main_clk = "func_mcbsp2_gfclk", |
4ddff493 BC |
2012 | .prcm = { |
2013 | .omap4 = { | |
d0f0631d | 2014 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 2015 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 2016 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2017 | }, |
2018 | }, | |
503d0ea2 PW |
2019 | .opt_clks = mcbsp2_opt_clks, |
2020 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
2021 | }; |
2022 | ||
2023 | /* mcbsp3 */ | |
4ddff493 | 2024 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
437e8970 | 2025 | { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 2026 | { .irq = -1 } |
4ddff493 BC |
2027 | }; |
2028 | ||
2029 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
2030 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
2031 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2032 | { .dma_req = -1 } |
4ddff493 BC |
2033 | }; |
2034 | ||
503d0ea2 PW |
2035 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
2036 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2037 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
2038 | }; |
2039 | ||
4ddff493 BC |
2040 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
2041 | .name = "mcbsp3", | |
2042 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2043 | .clkdm_name = "abe_clkdm", |
4ddff493 | 2044 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 2045 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
ee877acd | 2046 | .main_clk = "func_mcbsp3_gfclk", |
4ddff493 BC |
2047 | .prcm = { |
2048 | .omap4 = { | |
d0f0631d | 2049 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 2050 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 2051 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2052 | }, |
2053 | }, | |
503d0ea2 PW |
2054 | .opt_clks = mcbsp3_opt_clks, |
2055 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
2056 | }; |
2057 | ||
2058 | /* mcbsp4 */ | |
4ddff493 | 2059 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
437e8970 | 2060 | { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 2061 | { .irq = -1 } |
4ddff493 BC |
2062 | }; |
2063 | ||
2064 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
2065 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
2066 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2067 | { .dma_req = -1 } |
4ddff493 BC |
2068 | }; |
2069 | ||
503d0ea2 PW |
2070 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
2071 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2072 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
2073 | }; |
2074 | ||
4ddff493 BC |
2075 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
2076 | .name = "mcbsp4", | |
2077 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2078 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 2079 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 2080 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
ee877acd | 2081 | .main_clk = "per_mcbsp4_gfclk", |
4ddff493 BC |
2082 | .prcm = { |
2083 | .omap4 = { | |
d0f0631d | 2084 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 2085 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 2086 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2087 | }, |
2088 | }, | |
503d0ea2 PW |
2089 | .opt_clks = mcbsp4_opt_clks, |
2090 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
2091 | }; |
2092 | ||
407a6888 BC |
2093 | /* |
2094 | * 'mcpdm' class | |
2095 | * multi channel pdm controller (proprietary interface with phoenix power | |
2096 | * ic) | |
2097 | */ | |
2098 | ||
2099 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
2100 | .rev_offs = 0x0000, | |
2101 | .sysc_offs = 0x0010, | |
2102 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2103 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2104 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2105 | SIDLE_SMART_WKUP), | |
2106 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2107 | }; | |
2108 | ||
2109 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
2110 | .name = "mcpdm", | |
2111 | .sysc = &omap44xx_mcpdm_sysc, | |
2112 | }; | |
2113 | ||
2114 | /* mcpdm */ | |
407a6888 BC |
2115 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
2116 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2117 | { .irq = -1 } |
407a6888 BC |
2118 | }; |
2119 | ||
2120 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
2121 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
2122 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2123 | { .dma_req = -1 } |
407a6888 BC |
2124 | }; |
2125 | ||
407a6888 BC |
2126 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
2127 | .name = "mcpdm", | |
2128 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 2129 | .clkdm_name = "abe_clkdm", |
bc05244e PW |
2130 | /* |
2131 | * It's suspected that the McPDM requires an off-chip main | |
2132 | * functional clock, controlled via I2C. This IP block is | |
2133 | * currently reset very early during boot, before I2C is | |
2134 | * available, so it doesn't seem that we have any choice in | |
2135 | * the kernel other than to avoid resetting it. | |
12d82e4b PU |
2136 | * |
2137 | * Also, McPDM needs to be configured to NO_IDLE mode when it | |
2138 | * is in used otherwise vital clocks will be gated which | |
2139 | * results 'slow motion' audio playback. | |
bc05244e | 2140 | */ |
12d82e4b | 2141 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, |
407a6888 | 2142 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 2143 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
17b7e7d3 | 2144 | .main_clk = "pad_clks_ck", |
00fe610b | 2145 | .prcm = { |
407a6888 | 2146 | .omap4 = { |
d0f0631d | 2147 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 2148 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 2149 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2150 | }, |
2151 | }, | |
407a6888 BC |
2152 | }; |
2153 | ||
9bcbd7f0 BC |
2154 | /* |
2155 | * 'mcspi' class | |
2156 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2157 | * bus | |
2158 | */ | |
2159 | ||
2160 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
2161 | .rev_offs = 0x0000, | |
2162 | .sysc_offs = 0x0010, | |
2163 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2164 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2165 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2166 | SIDLE_SMART_WKUP), | |
2167 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2168 | }; | |
2169 | ||
2170 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
2171 | .name = "mcspi", | |
2172 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 2173 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
2174 | }; |
2175 | ||
2176 | /* mcspi1 */ | |
9bcbd7f0 BC |
2177 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
2178 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2179 | { .irq = -1 } |
9bcbd7f0 BC |
2180 | }; |
2181 | ||
2182 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
2183 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
2184 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
2185 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
2186 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
2187 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
2188 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
2189 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
2190 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2191 | { .dma_req = -1 } |
9bcbd7f0 BC |
2192 | }; |
2193 | ||
905a74d9 BC |
2194 | /* mcspi1 dev_attr */ |
2195 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
2196 | .num_chipselect = 4, | |
2197 | }; | |
2198 | ||
9bcbd7f0 BC |
2199 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
2200 | .name = "mcspi1", | |
2201 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2202 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2203 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 2204 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
17b7e7d3 | 2205 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
2206 | .prcm = { |
2207 | .omap4 = { | |
d0f0631d | 2208 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 2209 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 2210 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2211 | }, |
2212 | }, | |
905a74d9 | 2213 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
2214 | }; |
2215 | ||
2216 | /* mcspi2 */ | |
9bcbd7f0 BC |
2217 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
2218 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2219 | { .irq = -1 } |
9bcbd7f0 BC |
2220 | }; |
2221 | ||
2222 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
2223 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
2224 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
2225 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
2226 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2227 | { .dma_req = -1 } |
9bcbd7f0 BC |
2228 | }; |
2229 | ||
905a74d9 BC |
2230 | /* mcspi2 dev_attr */ |
2231 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
2232 | .num_chipselect = 2, | |
2233 | }; | |
2234 | ||
9bcbd7f0 BC |
2235 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
2236 | .name = "mcspi2", | |
2237 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2238 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2239 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 2240 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
17b7e7d3 | 2241 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
2242 | .prcm = { |
2243 | .omap4 = { | |
d0f0631d | 2244 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 2245 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 2246 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2247 | }, |
2248 | }, | |
905a74d9 | 2249 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
2250 | }; |
2251 | ||
2252 | /* mcspi3 */ | |
9bcbd7f0 BC |
2253 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
2254 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2255 | { .irq = -1 } |
9bcbd7f0 BC |
2256 | }; |
2257 | ||
2258 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
2259 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
2260 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
2261 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
2262 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2263 | { .dma_req = -1 } |
9bcbd7f0 BC |
2264 | }; |
2265 | ||
905a74d9 BC |
2266 | /* mcspi3 dev_attr */ |
2267 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
2268 | .num_chipselect = 2, | |
2269 | }; | |
2270 | ||
9bcbd7f0 BC |
2271 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
2272 | .name = "mcspi3", | |
2273 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2274 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2275 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 2276 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
17b7e7d3 | 2277 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
2278 | .prcm = { |
2279 | .omap4 = { | |
d0f0631d | 2280 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 2281 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 2282 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2283 | }, |
2284 | }, | |
905a74d9 | 2285 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2286 | }; |
2287 | ||
2288 | /* mcspi4 */ | |
9bcbd7f0 BC |
2289 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
2290 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2291 | { .irq = -1 } |
9bcbd7f0 BC |
2292 | }; |
2293 | ||
2294 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
2295 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2296 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2297 | { .dma_req = -1 } |
9bcbd7f0 BC |
2298 | }; |
2299 | ||
905a74d9 BC |
2300 | /* mcspi4 dev_attr */ |
2301 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2302 | .num_chipselect = 1, | |
2303 | }; | |
2304 | ||
9bcbd7f0 BC |
2305 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2306 | .name = "mcspi4", | |
2307 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2308 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2309 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 2310 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
17b7e7d3 | 2311 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
2312 | .prcm = { |
2313 | .omap4 = { | |
d0f0631d | 2314 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2315 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2316 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2317 | }, |
2318 | }, | |
905a74d9 | 2319 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2320 | }; |
2321 | ||
407a6888 BC |
2322 | /* |
2323 | * 'mmc' class | |
2324 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2325 | */ | |
2326 | ||
2327 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2328 | .rev_offs = 0x0000, | |
2329 | .sysc_offs = 0x0010, | |
2330 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2331 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2332 | SYSC_HAS_SOFTRESET), | |
2333 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2334 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2335 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2336 | .sysc_fields = &omap_hwmod_sysc_type2, |
2337 | }; | |
2338 | ||
2339 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2340 | .name = "mmc", | |
2341 | .sysc = &omap44xx_mmc_sysc, | |
2342 | }; | |
2343 | ||
2344 | /* mmc1 */ | |
2345 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
2346 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2347 | { .irq = -1 } |
407a6888 BC |
2348 | }; |
2349 | ||
2350 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
2351 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2352 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2353 | { .dma_req = -1 } |
407a6888 BC |
2354 | }; |
2355 | ||
6ab8946f KK |
2356 | /* mmc1 dev_attr */ |
2357 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
2358 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2359 | }; | |
2360 | ||
407a6888 BC |
2361 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2362 | .name = "mmc1", | |
2363 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2364 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2365 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 2366 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
ee877acd | 2367 | .main_clk = "hsmmc1_fclk", |
00fe610b | 2368 | .prcm = { |
407a6888 | 2369 | .omap4 = { |
d0f0631d | 2370 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2371 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2372 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2373 | }, |
2374 | }, | |
6ab8946f | 2375 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2376 | }; |
2377 | ||
2378 | /* mmc2 */ | |
2379 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2380 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2381 | { .irq = -1 } |
407a6888 BC |
2382 | }; |
2383 | ||
2384 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2385 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2386 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2387 | { .dma_req = -1 } |
407a6888 BC |
2388 | }; |
2389 | ||
407a6888 BC |
2390 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2391 | .name = "mmc2", | |
2392 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2393 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2394 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2395 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
ee877acd | 2396 | .main_clk = "hsmmc2_fclk", |
00fe610b | 2397 | .prcm = { |
407a6888 | 2398 | .omap4 = { |
d0f0631d | 2399 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2400 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2401 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2402 | }, |
2403 | }, | |
407a6888 BC |
2404 | }; |
2405 | ||
2406 | /* mmc3 */ | |
407a6888 BC |
2407 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2408 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2409 | { .irq = -1 } |
407a6888 BC |
2410 | }; |
2411 | ||
2412 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2413 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2414 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2415 | { .dma_req = -1 } |
407a6888 BC |
2416 | }; |
2417 | ||
407a6888 BC |
2418 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2419 | .name = "mmc3", | |
2420 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2421 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2422 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2423 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
17b7e7d3 | 2424 | .main_clk = "func_48m_fclk", |
00fe610b | 2425 | .prcm = { |
407a6888 | 2426 | .omap4 = { |
d0f0631d | 2427 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2428 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2429 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2430 | }, |
2431 | }, | |
407a6888 BC |
2432 | }; |
2433 | ||
2434 | /* mmc4 */ | |
407a6888 BC |
2435 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2436 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2437 | { .irq = -1 } |
407a6888 BC |
2438 | }; |
2439 | ||
2440 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2441 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2442 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2443 | { .dma_req = -1 } |
407a6888 BC |
2444 | }; |
2445 | ||
407a6888 BC |
2446 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2447 | .name = "mmc4", | |
2448 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2449 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2450 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2451 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
17b7e7d3 | 2452 | .main_clk = "func_48m_fclk", |
00fe610b | 2453 | .prcm = { |
407a6888 | 2454 | .omap4 = { |
d0f0631d | 2455 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2456 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2457 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2458 | }, |
2459 | }, | |
407a6888 BC |
2460 | }; |
2461 | ||
2462 | /* mmc5 */ | |
407a6888 BC |
2463 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2464 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2465 | { .irq = -1 } |
407a6888 BC |
2466 | }; |
2467 | ||
2468 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2469 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2470 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2471 | { .dma_req = -1 } |
407a6888 BC |
2472 | }; |
2473 | ||
407a6888 BC |
2474 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2475 | .name = "mmc5", | |
2476 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2477 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2478 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2479 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
17b7e7d3 | 2480 | .main_clk = "func_48m_fclk", |
00fe610b | 2481 | .prcm = { |
407a6888 | 2482 | .omap4 = { |
d0f0631d | 2483 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2484 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2485 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2486 | }, |
2487 | }, | |
407a6888 BC |
2488 | }; |
2489 | ||
230844db ORL |
2490 | /* |
2491 | * 'mmu' class | |
2492 | * The memory management unit performs virtual to physical address translation | |
2493 | * for its requestors. | |
2494 | */ | |
2495 | ||
2496 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2497 | .rev_offs = 0x000, | |
2498 | .sysc_offs = 0x010, | |
2499 | .syss_offs = 0x014, | |
2500 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2501 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2502 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2503 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2504 | }; | |
2505 | ||
2506 | static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { | |
2507 | .name = "mmu", | |
2508 | .sysc = &mmu_sysc, | |
2509 | }; | |
2510 | ||
2511 | /* mmu ipu */ | |
2512 | ||
2513 | static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { | |
2514 | .da_start = 0x0, | |
2515 | .da_end = 0xfffff000, | |
2516 | .nr_tlb_entries = 32, | |
2517 | }; | |
2518 | ||
2519 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; | |
2520 | static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { | |
2521 | { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, | |
2522 | { .irq = -1 } | |
2523 | }; | |
2524 | ||
2525 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { | |
2526 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2527 | }; | |
2528 | ||
2529 | static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { | |
2530 | { | |
2531 | .pa_start = 0x55082000, | |
2532 | .pa_end = 0x550820ff, | |
2533 | .flags = ADDR_TYPE_RT, | |
2534 | }, | |
2535 | { } | |
2536 | }; | |
2537 | ||
2538 | /* l3_main_2 -> mmu_ipu */ | |
2539 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { | |
2540 | .master = &omap44xx_l3_main_2_hwmod, | |
2541 | .slave = &omap44xx_mmu_ipu_hwmod, | |
2542 | .clk = "l3_div_ck", | |
2543 | .addr = omap44xx_mmu_ipu_addrs, | |
2544 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2545 | }; | |
2546 | ||
2547 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |
2548 | .name = "mmu_ipu", | |
2549 | .class = &omap44xx_mmu_hwmod_class, | |
2550 | .clkdm_name = "ducati_clkdm", | |
2551 | .mpu_irqs = omap44xx_mmu_ipu_irqs, | |
2552 | .rst_lines = omap44xx_mmu_ipu_resets, | |
2553 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | |
2554 | .main_clk = "ducati_clk_mux_ck", | |
2555 | .prcm = { | |
2556 | .omap4 = { | |
2557 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, | |
2558 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, | |
2559 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, | |
2560 | .modulemode = MODULEMODE_HWCTRL, | |
2561 | }, | |
2562 | }, | |
2563 | .dev_attr = &mmu_ipu_dev_attr, | |
2564 | }; | |
2565 | ||
2566 | /* mmu dsp */ | |
2567 | ||
2568 | static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { | |
2569 | .da_start = 0x0, | |
2570 | .da_end = 0xfffff000, | |
2571 | .nr_tlb_entries = 32, | |
2572 | }; | |
2573 | ||
2574 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; | |
2575 | static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { | |
2576 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
2577 | { .irq = -1 } | |
2578 | }; | |
2579 | ||
2580 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { | |
2581 | { .name = "mmu_cache", .rst_shift = 1 }, | |
2582 | }; | |
2583 | ||
2584 | static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { | |
2585 | { | |
2586 | .pa_start = 0x4a066000, | |
2587 | .pa_end = 0x4a0660ff, | |
2588 | .flags = ADDR_TYPE_RT, | |
2589 | }, | |
2590 | { } | |
2591 | }; | |
2592 | ||
2593 | /* l4_cfg -> dsp */ | |
2594 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { | |
2595 | .master = &omap44xx_l4_cfg_hwmod, | |
2596 | .slave = &omap44xx_mmu_dsp_hwmod, | |
2597 | .clk = "l4_div_ck", | |
2598 | .addr = omap44xx_mmu_dsp_addrs, | |
2599 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2600 | }; | |
2601 | ||
2602 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |
2603 | .name = "mmu_dsp", | |
2604 | .class = &omap44xx_mmu_hwmod_class, | |
2605 | .clkdm_name = "tesla_clkdm", | |
2606 | .mpu_irqs = omap44xx_mmu_dsp_irqs, | |
2607 | .rst_lines = omap44xx_mmu_dsp_resets, | |
2608 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | |
2609 | .main_clk = "dpll_iva_m4x2_ck", | |
2610 | .prcm = { | |
2611 | .omap4 = { | |
2612 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, | |
2613 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, | |
2614 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, | |
2615 | .modulemode = MODULEMODE_HWCTRL, | |
2616 | }, | |
2617 | }, | |
2618 | .dev_attr = &mmu_dsp_dev_attr, | |
2619 | }; | |
2620 | ||
3b54baad BC |
2621 | /* |
2622 | * 'mpu' class | |
2623 | * mpu sub-system | |
2624 | */ | |
2625 | ||
2626 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2627 | .name = "mpu", |
db12ba53 BC |
2628 | }; |
2629 | ||
3b54baad BC |
2630 | /* mpu */ |
2631 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
76a5d9bf JH |
2632 | { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START }, |
2633 | { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START }, | |
3b54baad BC |
2634 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, |
2635 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2636 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2637 | { .irq = -1 } |
db12ba53 BC |
2638 | }; |
2639 | ||
3b54baad BC |
2640 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2641 | .name = "mpu", | |
2642 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2643 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2644 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2645 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2646 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2647 | .prcm = { |
2648 | .omap4 = { | |
d0f0631d | 2649 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2650 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2651 | }, |
2652 | }, | |
db12ba53 BC |
2653 | }; |
2654 | ||
e17f18c0 PW |
2655 | /* |
2656 | * 'ocmc_ram' class | |
2657 | * top-level core on-chip ram | |
2658 | */ | |
2659 | ||
2660 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2661 | .name = "ocmc_ram", | |
2662 | }; | |
2663 | ||
2664 | /* ocmc_ram */ | |
2665 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2666 | .name = "ocmc_ram", | |
2667 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2668 | .clkdm_name = "l3_2_clkdm", | |
2669 | .prcm = { | |
2670 | .omap4 = { | |
2671 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2672 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2673 | }, | |
2674 | }, | |
2675 | }; | |
2676 | ||
0c668875 BC |
2677 | /* |
2678 | * 'ocp2scp' class | |
2679 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2680 | * protocol | |
2681 | */ | |
2682 | ||
33c976ec BC |
2683 | static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { |
2684 | .rev_offs = 0x0000, | |
2685 | .sysc_offs = 0x0010, | |
2686 | .syss_offs = 0x0014, | |
2687 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2688 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2689 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2690 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2691 | }; | |
2692 | ||
0c668875 BC |
2693 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { |
2694 | .name = "ocp2scp", | |
33c976ec | 2695 | .sysc = &omap44xx_ocp2scp_sysc, |
0c668875 BC |
2696 | }; |
2697 | ||
637874dd KVA |
2698 | /* ocp2scp dev_attr */ |
2699 | static struct resource omap44xx_usb_phy_and_pll_addrs[] = { | |
2700 | { | |
2701 | .name = "usb_phy", | |
2702 | .start = 0x4a0ad080, | |
2703 | .end = 0x4a0ae000, | |
2704 | .flags = IORESOURCE_MEM, | |
2705 | }, | |
637874dd KVA |
2706 | { } |
2707 | }; | |
2708 | ||
2709 | static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = { | |
2710 | { | |
2711 | .drv_name = "omap-usb2", | |
2712 | .res = omap44xx_usb_phy_and_pll_addrs, | |
2713 | }, | |
2714 | { } | |
2715 | }; | |
2716 | ||
92702df3 PW |
2717 | static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { |
2718 | { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" }, | |
2719 | }; | |
2720 | ||
0c668875 | 2721 | /* ocp2scp_usb_phy */ |
0c668875 BC |
2722 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
2723 | .name = "ocp2scp_usb_phy", | |
2724 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2725 | .clkdm_name = "l3_init_clkdm", | |
17b7e7d3 | 2726 | .main_clk = "func_48m_fclk", |
0c668875 BC |
2727 | .prcm = { |
2728 | .omap4 = { | |
2729 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2730 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2731 | .modulemode = MODULEMODE_HWCTRL, | |
2732 | }, | |
2733 | }, | |
637874dd | 2734 | .dev_attr = ocp2scp_dev_attr, |
92702df3 PW |
2735 | .opt_clks = ocp2scp_usb_phy_opt_clks, |
2736 | .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), | |
0c668875 BC |
2737 | }; |
2738 | ||
794b480a PW |
2739 | /* |
2740 | * 'prcm' class | |
2741 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2742 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2743 | */ | |
2744 | ||
2745 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2746 | .name = "prcm", | |
2747 | }; | |
2748 | ||
2749 | /* prcm_mpu */ | |
2750 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2751 | .name = "prcm_mpu", | |
2752 | .class = &omap44xx_prcm_hwmod_class, | |
2753 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 2754 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2755 | .prcm = { |
2756 | .omap4 = { | |
2757 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2758 | }, | |
2759 | }, | |
794b480a PW |
2760 | }; |
2761 | ||
2762 | /* cm_core_aon */ | |
2763 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2764 | .name = "cm_core_aon", | |
2765 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2766 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2767 | .prcm = { |
2768 | .omap4 = { | |
2769 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2770 | }, | |
2771 | }, | |
794b480a PW |
2772 | }; |
2773 | ||
2774 | /* cm_core */ | |
2775 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2776 | .name = "cm_core", | |
2777 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2778 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2779 | .prcm = { |
2780 | .omap4 = { | |
2781 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2782 | }, | |
2783 | }, | |
794b480a PW |
2784 | }; |
2785 | ||
2786 | /* prm */ | |
2787 | static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { | |
2788 | { .irq = 11 + OMAP44XX_IRQ_GIC_START }, | |
2789 | { .irq = -1 } | |
2790 | }; | |
2791 | ||
2792 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |
2793 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2794 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2795 | }; | |
2796 | ||
2797 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2798 | .name = "prm", | |
2799 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2800 | .mpu_irqs = omap44xx_prm_irqs, |
2801 | .rst_lines = omap44xx_prm_resets, | |
2802 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2803 | }; | |
2804 | ||
2805 | /* | |
2806 | * 'scrm' class | |
2807 | * system clock and reset manager | |
2808 | */ | |
2809 | ||
2810 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2811 | .name = "scrm", | |
2812 | }; | |
2813 | ||
2814 | /* scrm */ | |
2815 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2816 | .name = "scrm", | |
2817 | .class = &omap44xx_scrm_hwmod_class, | |
2818 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
2819 | .prcm = { |
2820 | .omap4 = { | |
2821 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2822 | }, | |
2823 | }, | |
794b480a PW |
2824 | }; |
2825 | ||
42b9e387 PW |
2826 | /* |
2827 | * 'sl2if' class | |
2828 | * shared level 2 memory interface | |
2829 | */ | |
2830 | ||
2831 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2832 | .name = "sl2if", | |
2833 | }; | |
2834 | ||
2835 | /* sl2if */ | |
2836 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2837 | .name = "sl2if", | |
2838 | .class = &omap44xx_sl2if_hwmod_class, | |
2839 | .clkdm_name = "ivahd_clkdm", | |
2840 | .prcm = { | |
2841 | .omap4 = { | |
2842 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2843 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2844 | .modulemode = MODULEMODE_HWCTRL, | |
2845 | }, | |
2846 | }, | |
2847 | }; | |
2848 | ||
1e3b5e59 BC |
2849 | /* |
2850 | * 'slimbus' class | |
2851 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2852 | * the device and external components | |
2853 | */ | |
2854 | ||
2855 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2856 | .rev_offs = 0x0000, | |
2857 | .sysc_offs = 0x0010, | |
2858 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2859 | SYSC_HAS_SOFTRESET), | |
2860 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2861 | SIDLE_SMART_WKUP), | |
2862 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2863 | }; | |
2864 | ||
2865 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2866 | .name = "slimbus", | |
2867 | .sysc = &omap44xx_slimbus_sysc, | |
2868 | }; | |
2869 | ||
2870 | /* slimbus1 */ | |
2871 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | |
2872 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | |
2873 | { .irq = -1 } | |
2874 | }; | |
2875 | ||
2876 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | |
2877 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | |
2878 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | |
2879 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | |
2880 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | |
2881 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | |
2882 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | |
2883 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | |
2884 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | |
2885 | { .dma_req = -1 } | |
2886 | }; | |
2887 | ||
2888 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | |
2889 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2890 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2891 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2892 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2893 | }; | |
2894 | ||
2895 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2896 | .name = "slimbus1", | |
2897 | .class = &omap44xx_slimbus_hwmod_class, | |
2898 | .clkdm_name = "abe_clkdm", | |
2899 | .mpu_irqs = omap44xx_slimbus1_irqs, | |
2900 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | |
2901 | .prcm = { | |
2902 | .omap4 = { | |
2903 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2904 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2905 | .modulemode = MODULEMODE_SWCTRL, | |
2906 | }, | |
2907 | }, | |
2908 | .opt_clks = slimbus1_opt_clks, | |
2909 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2910 | }; | |
2911 | ||
2912 | /* slimbus2 */ | |
2913 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | |
2914 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | |
2915 | { .irq = -1 } | |
2916 | }; | |
2917 | ||
2918 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | |
2919 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | |
2920 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | |
2921 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | |
2922 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | |
2923 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | |
2924 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | |
2925 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | |
2926 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | |
2927 | { .dma_req = -1 } | |
2928 | }; | |
2929 | ||
2930 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | |
2931 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2932 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2933 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2934 | }; | |
2935 | ||
2936 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2937 | .name = "slimbus2", | |
2938 | .class = &omap44xx_slimbus_hwmod_class, | |
2939 | .clkdm_name = "l4_per_clkdm", | |
2940 | .mpu_irqs = omap44xx_slimbus2_irqs, | |
2941 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | |
2942 | .prcm = { | |
2943 | .omap4 = { | |
2944 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2945 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2946 | .modulemode = MODULEMODE_SWCTRL, | |
2947 | }, | |
2948 | }, | |
2949 | .opt_clks = slimbus2_opt_clks, | |
2950 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2951 | }; | |
2952 | ||
1f6a717f BC |
2953 | /* |
2954 | * 'smartreflex' class | |
2955 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2956 | * performance error) | |
2957 | */ | |
2958 | ||
2959 | /* The IP is not compliant to type1 / type2 scheme */ | |
2960 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2961 | .sidle_shift = 24, | |
2962 | .enwkup_shift = 26, | |
2963 | }; | |
2964 | ||
2965 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2966 | .sysc_offs = 0x0038, | |
2967 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2968 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2969 | SIDLE_SMART_WKUP), | |
2970 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2971 | }; | |
2972 | ||
2973 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2974 | .name = "smartreflex", |
2975 | .sysc = &omap44xx_smartreflex_sysc, | |
2976 | .rev = 2, | |
1f6a717f BC |
2977 | }; |
2978 | ||
2979 | /* smartreflex_core */ | |
cea6b942 SG |
2980 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2981 | .sensor_voltdm_name = "core", | |
2982 | }; | |
2983 | ||
1f6a717f BC |
2984 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2985 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2986 | { .irq = -1 } |
1f6a717f BC |
2987 | }; |
2988 | ||
1f6a717f BC |
2989 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2990 | .name = "smartreflex_core", | |
2991 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2992 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2993 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2994 | |
1f6a717f | 2995 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2996 | .prcm = { |
2997 | .omap4 = { | |
d0f0631d | 2998 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2999 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 3000 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
3001 | }, |
3002 | }, | |
cea6b942 | 3003 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
3004 | }; |
3005 | ||
3006 | /* smartreflex_iva */ | |
cea6b942 SG |
3007 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
3008 | .sensor_voltdm_name = "iva", | |
3009 | }; | |
3010 | ||
1f6a717f BC |
3011 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
3012 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3013 | { .irq = -1 } |
1f6a717f BC |
3014 | }; |
3015 | ||
1f6a717f BC |
3016 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
3017 | .name = "smartreflex_iva", | |
3018 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 3019 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 3020 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 3021 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
3022 | .prcm = { |
3023 | .omap4 = { | |
d0f0631d | 3024 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 3025 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 3026 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
3027 | }, |
3028 | }, | |
cea6b942 | 3029 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
3030 | }; |
3031 | ||
3032 | /* smartreflex_mpu */ | |
cea6b942 SG |
3033 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
3034 | .sensor_voltdm_name = "mpu", | |
3035 | }; | |
3036 | ||
1f6a717f BC |
3037 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
3038 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3039 | { .irq = -1 } |
1f6a717f BC |
3040 | }; |
3041 | ||
1f6a717f BC |
3042 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
3043 | .name = "smartreflex_mpu", | |
3044 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 3045 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 3046 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 3047 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
3048 | .prcm = { |
3049 | .omap4 = { | |
d0f0631d | 3050 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 3051 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 3052 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
3053 | }, |
3054 | }, | |
cea6b942 | 3055 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
3056 | }; |
3057 | ||
d11c217f BC |
3058 | /* |
3059 | * 'spinlock' class | |
3060 | * spinlock provides hardware assistance for synchronizing the processes | |
3061 | * running on multiple processors | |
3062 | */ | |
3063 | ||
3064 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
3065 | .rev_offs = 0x0000, | |
3066 | .sysc_offs = 0x0010, | |
3067 | .syss_offs = 0x0014, | |
3068 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
3069 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
3070 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3071 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3072 | SIDLE_SMART_WKUP), | |
3073 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3074 | }; | |
3075 | ||
3076 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
3077 | .name = "spinlock", | |
3078 | .sysc = &omap44xx_spinlock_sysc, | |
3079 | }; | |
3080 | ||
3081 | /* spinlock */ | |
d11c217f BC |
3082 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
3083 | .name = "spinlock", | |
3084 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 3085 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
3086 | .prcm = { |
3087 | .omap4 = { | |
d0f0631d | 3088 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 3089 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
3090 | }, |
3091 | }, | |
d11c217f BC |
3092 | }; |
3093 | ||
35d1a66a BC |
3094 | /* |
3095 | * 'timer' class | |
3096 | * general purpose timer module with accurate 1ms tick | |
3097 | * This class contains several variants: ['timer_1ms', 'timer'] | |
3098 | */ | |
3099 | ||
3100 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
3101 | .rev_offs = 0x0000, | |
3102 | .sysc_offs = 0x0010, | |
3103 | .syss_offs = 0x0014, | |
3104 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
3105 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
3106 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
3107 | SYSS_HAS_RESET_STATUS), | |
3108 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
10759e82 | 3109 | .clockact = CLOCKACT_TEST_ICLK, |
35d1a66a BC |
3110 | .sysc_fields = &omap_hwmod_sysc_type1, |
3111 | }; | |
3112 | ||
3113 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
3114 | .name = "timer", | |
3115 | .sysc = &omap44xx_timer_1ms_sysc, | |
3116 | }; | |
3117 | ||
3118 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
3119 | .rev_offs = 0x0000, | |
3120 | .sysc_offs = 0x0010, | |
3121 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3122 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3123 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3124 | SIDLE_SMART_WKUP), | |
3125 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3126 | }; | |
3127 | ||
3128 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
3129 | .name = "timer", | |
3130 | .sysc = &omap44xx_timer_sysc, | |
3131 | }; | |
3132 | ||
c345c8b0 TKD |
3133 | /* always-on timers dev attribute */ |
3134 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
3135 | .timer_capability = OMAP_TIMER_ALWON, | |
3136 | }; | |
3137 | ||
3138 | /* pwm timers dev attribute */ | |
3139 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
3140 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
3141 | }; | |
3142 | ||
5c3e4ec4 JH |
3143 | /* timers with DSP interrupt dev attribute */ |
3144 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
3145 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
3146 | }; | |
3147 | ||
3148 | /* pwm timers with DSP interrupt dev attribute */ | |
3149 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
3150 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
3151 | }; | |
3152 | ||
35d1a66a | 3153 | /* timer1 */ |
35d1a66a BC |
3154 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
3155 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3156 | { .irq = -1 } |
35d1a66a BC |
3157 | }; |
3158 | ||
35d1a66a BC |
3159 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
3160 | .name = "timer1", | |
3161 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3162 | .clkdm_name = "l4_wkup_clkdm", |
10759e82 | 3163 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
35d1a66a | 3164 | .mpu_irqs = omap44xx_timer1_irqs, |
ee877acd | 3165 | .main_clk = "dmt1_clk_mux", |
35d1a66a BC |
3166 | .prcm = { |
3167 | .omap4 = { | |
d0f0631d | 3168 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 3169 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 3170 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3171 | }, |
3172 | }, | |
c345c8b0 | 3173 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
3174 | }; |
3175 | ||
3176 | /* timer2 */ | |
35d1a66a BC |
3177 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
3178 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3179 | { .irq = -1 } |
35d1a66a BC |
3180 | }; |
3181 | ||
35d1a66a BC |
3182 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
3183 | .name = "timer2", | |
3184 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3185 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 3186 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
35d1a66a | 3187 | .mpu_irqs = omap44xx_timer2_irqs, |
ee877acd | 3188 | .main_clk = "cm2_dm2_mux", |
35d1a66a BC |
3189 | .prcm = { |
3190 | .omap4 = { | |
d0f0631d | 3191 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 3192 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 3193 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3194 | }, |
3195 | }, | |
35d1a66a BC |
3196 | }; |
3197 | ||
3198 | /* timer3 */ | |
35d1a66a BC |
3199 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
3200 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3201 | { .irq = -1 } |
35d1a66a BC |
3202 | }; |
3203 | ||
35d1a66a BC |
3204 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
3205 | .name = "timer3", | |
3206 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3207 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3208 | .mpu_irqs = omap44xx_timer3_irqs, |
ee877acd | 3209 | .main_clk = "cm2_dm3_mux", |
35d1a66a BC |
3210 | .prcm = { |
3211 | .omap4 = { | |
d0f0631d | 3212 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 3213 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 3214 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3215 | }, |
3216 | }, | |
35d1a66a BC |
3217 | }; |
3218 | ||
3219 | /* timer4 */ | |
35d1a66a BC |
3220 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
3221 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3222 | { .irq = -1 } |
35d1a66a BC |
3223 | }; |
3224 | ||
35d1a66a BC |
3225 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
3226 | .name = "timer4", | |
3227 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3228 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3229 | .mpu_irqs = omap44xx_timer4_irqs, |
ee877acd | 3230 | .main_clk = "cm2_dm4_mux", |
35d1a66a BC |
3231 | .prcm = { |
3232 | .omap4 = { | |
d0f0631d | 3233 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 3234 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 3235 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3236 | }, |
3237 | }, | |
35d1a66a BC |
3238 | }; |
3239 | ||
3240 | /* timer5 */ | |
35d1a66a BC |
3241 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
3242 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3243 | { .irq = -1 } |
35d1a66a BC |
3244 | }; |
3245 | ||
35d1a66a BC |
3246 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
3247 | .name = "timer5", | |
3248 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3249 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3250 | .mpu_irqs = omap44xx_timer5_irqs, |
ee877acd | 3251 | .main_clk = "timer5_sync_mux", |
35d1a66a BC |
3252 | .prcm = { |
3253 | .omap4 = { | |
d0f0631d | 3254 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 3255 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 3256 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3257 | }, |
3258 | }, | |
5c3e4ec4 | 3259 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
3260 | }; |
3261 | ||
3262 | /* timer6 */ | |
35d1a66a BC |
3263 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
3264 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3265 | { .irq = -1 } |
35d1a66a BC |
3266 | }; |
3267 | ||
35d1a66a BC |
3268 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
3269 | .name = "timer6", | |
3270 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3271 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3272 | .mpu_irqs = omap44xx_timer6_irqs, |
ee877acd | 3273 | .main_clk = "timer6_sync_mux", |
35d1a66a BC |
3274 | .prcm = { |
3275 | .omap4 = { | |
d0f0631d | 3276 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 3277 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 3278 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3279 | }, |
3280 | }, | |
5c3e4ec4 | 3281 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
3282 | }; |
3283 | ||
3284 | /* timer7 */ | |
35d1a66a BC |
3285 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
3286 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3287 | { .irq = -1 } |
35d1a66a BC |
3288 | }; |
3289 | ||
35d1a66a BC |
3290 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
3291 | .name = "timer7", | |
3292 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3293 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3294 | .mpu_irqs = omap44xx_timer7_irqs, |
ee877acd | 3295 | .main_clk = "timer7_sync_mux", |
35d1a66a BC |
3296 | .prcm = { |
3297 | .omap4 = { | |
d0f0631d | 3298 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 3299 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 3300 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3301 | }, |
3302 | }, | |
5c3e4ec4 | 3303 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
3304 | }; |
3305 | ||
3306 | /* timer8 */ | |
35d1a66a BC |
3307 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
3308 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3309 | { .irq = -1 } |
35d1a66a BC |
3310 | }; |
3311 | ||
35d1a66a BC |
3312 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
3313 | .name = "timer8", | |
3314 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3315 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3316 | .mpu_irqs = omap44xx_timer8_irqs, |
ee877acd | 3317 | .main_clk = "timer8_sync_mux", |
35d1a66a BC |
3318 | .prcm = { |
3319 | .omap4 = { | |
d0f0631d | 3320 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 3321 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 3322 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3323 | }, |
3324 | }, | |
5c3e4ec4 | 3325 | .dev_attr = &capability_dsp_pwm_dev_attr, |
35d1a66a BC |
3326 | }; |
3327 | ||
3328 | /* timer9 */ | |
35d1a66a BC |
3329 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
3330 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3331 | { .irq = -1 } |
35d1a66a BC |
3332 | }; |
3333 | ||
35d1a66a BC |
3334 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
3335 | .name = "timer9", | |
3336 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3337 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3338 | .mpu_irqs = omap44xx_timer9_irqs, |
ee877acd | 3339 | .main_clk = "cm2_dm9_mux", |
35d1a66a BC |
3340 | .prcm = { |
3341 | .omap4 = { | |
d0f0631d | 3342 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 3343 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 3344 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3345 | }, |
3346 | }, | |
c345c8b0 | 3347 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3348 | }; |
3349 | ||
3350 | /* timer10 */ | |
35d1a66a BC |
3351 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
3352 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3353 | { .irq = -1 } |
35d1a66a BC |
3354 | }; |
3355 | ||
35d1a66a BC |
3356 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
3357 | .name = "timer10", | |
3358 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3359 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 3360 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
35d1a66a | 3361 | .mpu_irqs = omap44xx_timer10_irqs, |
ee877acd | 3362 | .main_clk = "cm2_dm10_mux", |
35d1a66a BC |
3363 | .prcm = { |
3364 | .omap4 = { | |
d0f0631d | 3365 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 3366 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 3367 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3368 | }, |
3369 | }, | |
c345c8b0 | 3370 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3371 | }; |
3372 | ||
3373 | /* timer11 */ | |
35d1a66a BC |
3374 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
3375 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3376 | { .irq = -1 } |
35d1a66a BC |
3377 | }; |
3378 | ||
35d1a66a BC |
3379 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
3380 | .name = "timer11", | |
3381 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3382 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3383 | .mpu_irqs = omap44xx_timer11_irqs, |
ee877acd | 3384 | .main_clk = "cm2_dm11_mux", |
35d1a66a BC |
3385 | .prcm = { |
3386 | .omap4 = { | |
d0f0631d | 3387 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 3388 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 3389 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3390 | }, |
3391 | }, | |
c345c8b0 | 3392 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3393 | }; |
3394 | ||
9780a9cf | 3395 | /* |
3b54baad BC |
3396 | * 'uart' class |
3397 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
3398 | */ |
3399 | ||
3b54baad BC |
3400 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
3401 | .rev_offs = 0x0050, | |
3402 | .sysc_offs = 0x0054, | |
3403 | .syss_offs = 0x0058, | |
3404 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
3405 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
3406 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
3407 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3408 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
3409 | .sysc_fields = &omap_hwmod_sysc_type1, |
3410 | }; | |
3411 | ||
3b54baad | 3412 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
3413 | .name = "uart", |
3414 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
3415 | }; |
3416 | ||
3b54baad | 3417 | /* uart1 */ |
3b54baad BC |
3418 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
3419 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3420 | { .irq = -1 } |
9780a9cf BC |
3421 | }; |
3422 | ||
3b54baad BC |
3423 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
3424 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
3425 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3426 | { .dma_req = -1 } |
9780a9cf BC |
3427 | }; |
3428 | ||
3b54baad BC |
3429 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
3430 | .name = "uart1", | |
3431 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3432 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3433 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 3434 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
17b7e7d3 | 3435 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
3436 | .prcm = { |
3437 | .omap4 = { | |
d0f0631d | 3438 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 3439 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 3440 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3441 | }, |
3442 | }, | |
9780a9cf BC |
3443 | }; |
3444 | ||
3b54baad | 3445 | /* uart2 */ |
3b54baad BC |
3446 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
3447 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3448 | { .irq = -1 } |
9780a9cf BC |
3449 | }; |
3450 | ||
3b54baad BC |
3451 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
3452 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
3453 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3454 | { .dma_req = -1 } |
3b54baad BC |
3455 | }; |
3456 | ||
3b54baad BC |
3457 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
3458 | .name = "uart2", | |
3459 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3460 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3461 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 3462 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
17b7e7d3 | 3463 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
3464 | .prcm = { |
3465 | .omap4 = { | |
d0f0631d | 3466 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 3467 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 3468 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3469 | }, |
3470 | }, | |
9780a9cf BC |
3471 | }; |
3472 | ||
3b54baad | 3473 | /* uart3 */ |
3b54baad BC |
3474 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
3475 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3476 | { .irq = -1 } |
9780a9cf BC |
3477 | }; |
3478 | ||
3b54baad BC |
3479 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
3480 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
3481 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3482 | { .dma_req = -1 } |
3b54baad BC |
3483 | }; |
3484 | ||
3b54baad BC |
3485 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
3486 | .name = "uart3", | |
3487 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3488 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 3489 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3490 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 3491 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
17b7e7d3 | 3492 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
3493 | .prcm = { |
3494 | .omap4 = { | |
d0f0631d | 3495 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 3496 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 3497 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3498 | }, |
3499 | }, | |
9780a9cf BC |
3500 | }; |
3501 | ||
3b54baad | 3502 | /* uart4 */ |
3b54baad BC |
3503 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
3504 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3505 | { .irq = -1 } |
9780a9cf BC |
3506 | }; |
3507 | ||
3b54baad BC |
3508 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
3509 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
3510 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3511 | { .dma_req = -1 } |
3b54baad BC |
3512 | }; |
3513 | ||
3b54baad BC |
3514 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
3515 | .name = "uart4", | |
3516 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3517 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3518 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 3519 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
17b7e7d3 | 3520 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
3521 | .prcm = { |
3522 | .omap4 = { | |
d0f0631d | 3523 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 3524 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 3525 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3526 | }, |
3527 | }, | |
9780a9cf BC |
3528 | }; |
3529 | ||
0c668875 BC |
3530 | /* |
3531 | * 'usb_host_fs' class | |
3532 | * full-speed usb host controller | |
3533 | */ | |
3534 | ||
3535 | /* The IP is not compliant to type1 / type2 scheme */ | |
3536 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
3537 | .midle_shift = 4, | |
3538 | .sidle_shift = 2, | |
3539 | .srst_shift = 1, | |
3540 | }; | |
3541 | ||
3542 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
3543 | .rev_offs = 0x0000, | |
3544 | .sysc_offs = 0x0210, | |
3545 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3546 | SYSC_HAS_SOFTRESET), | |
3547 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3548 | SIDLE_SMART_WKUP), | |
3549 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
3550 | }; | |
3551 | ||
3552 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
3553 | .name = "usb_host_fs", | |
3554 | .sysc = &omap44xx_usb_host_fs_sysc, | |
3555 | }; | |
3556 | ||
3557 | /* usb_host_fs */ | |
3558 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | |
3559 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | |
3560 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | |
3561 | { .irq = -1 } | |
3562 | }; | |
3563 | ||
3564 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | |
3565 | .name = "usb_host_fs", | |
3566 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
3567 | .clkdm_name = "l3_init_clkdm", | |
3568 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | |
3569 | .main_clk = "usb_host_fs_fck", | |
3570 | .prcm = { | |
3571 | .omap4 = { | |
3572 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
3573 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
3574 | .modulemode = MODULEMODE_SWCTRL, | |
3575 | }, | |
3576 | }, | |
3577 | }; | |
3578 | ||
5844c4ea | 3579 | /* |
844a3b63 PW |
3580 | * 'usb_host_hs' class |
3581 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3582 | */ |
3583 | ||
844a3b63 PW |
3584 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3585 | .rev_offs = 0x0000, | |
3586 | .sysc_offs = 0x0010, | |
3587 | .syss_offs = 0x0014, | |
3588 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3589 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
3590 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3591 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3592 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3593 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3594 | }; |
3595 | ||
844a3b63 PW |
3596 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3597 | .name = "usb_host_hs", | |
3598 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3599 | }; |
3600 | ||
844a3b63 PW |
3601 | /* usb_host_hs */ |
3602 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
3603 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
3604 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3605 | { .irq = -1 } |
5844c4ea BC |
3606 | }; |
3607 | ||
844a3b63 PW |
3608 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3609 | .name = "usb_host_hs", | |
3610 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3611 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3612 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3613 | .prcm = { |
3614 | .omap4 = { | |
844a3b63 PW |
3615 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3616 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3617 | .modulemode = MODULEMODE_SWCTRL, | |
3618 | }, | |
3619 | }, | |
3620 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
3621 | ||
3622 | /* | |
3623 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3624 | * id: i660 | |
3625 | * | |
3626 | * Description: | |
3627 | * In the following configuration : | |
3628 | * - USBHOST module is set to smart-idle mode | |
3629 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3630 | * happens when the system is going to a low power mode : all ports | |
3631 | * have been suspended, the master part of the USBHOST module has | |
3632 | * entered the standby state, and SW has cut the functional clocks) | |
3633 | * - an USBHOST interrupt occurs before the module is able to answer | |
3634 | * idle_ack, typically a remote wakeup IRQ. | |
3635 | * Then the USB HOST module will enter a deadlock situation where it | |
3636 | * is no more accessible nor functional. | |
3637 | * | |
3638 | * Workaround: | |
3639 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3640 | */ | |
3641 | ||
3642 | /* | |
3643 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3644 | * Id: i571 | |
3645 | * | |
3646 | * Description: | |
3647 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3648 | * ready to enter the standby state (i.e. all ports are suspended and | |
3649 | * all attached devices are in suspend mode), then it can wrongly assert | |
3650 | * the Mstandby signal too early while there are still some residual OCP | |
3651 | * transactions ongoing. If this condition occurs, the internal state | |
3652 | * machine may go to an undefined state and the USB link may be stuck | |
3653 | * upon the next resume. | |
3654 | * | |
3655 | * Workaround: | |
3656 | * Don't use smart standby; use only force standby, | |
3657 | * hence HWMOD_SWSUP_MSTANDBY | |
3658 | */ | |
3659 | ||
3660 | /* | |
3661 | * During system boot; If the hwmod framework resets the module | |
3662 | * the module will have smart idle settings; which can lead to deadlock | |
3663 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3664 | * Use HWMOD_INIT_NO_RESET. | |
3665 | */ | |
3666 | ||
3667 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3668 | HWMOD_INIT_NO_RESET, | |
3669 | }; | |
3670 | ||
3671 | /* | |
3672 | * 'usb_otg_hs' class | |
3673 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3674 | */ | |
3675 | ||
3676 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3677 | .rev_offs = 0x0400, | |
3678 | .sysc_offs = 0x0404, | |
3679 | .syss_offs = 0x0408, | |
3680 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3681 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3682 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3683 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3684 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3685 | MSTANDBY_SMART), | |
3686 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3687 | }; | |
3688 | ||
3689 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3690 | .name = "usb_otg_hs", | |
3691 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3692 | }; | |
3693 | ||
3694 | /* usb_otg_hs */ | |
3695 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
3696 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
3697 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
3698 | { .irq = -1 } | |
3699 | }; | |
3700 | ||
3701 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
3702 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3703 | }; | |
3704 | ||
3705 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3706 | .name = "usb_otg_hs", | |
3707 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3708 | .clkdm_name = "l3_init_clkdm", | |
3709 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
3710 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
3711 | .main_clk = "usb_otg_hs_ick", | |
3712 | .prcm = { | |
3713 | .omap4 = { | |
3714 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3715 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3716 | .modulemode = MODULEMODE_HWCTRL, | |
3717 | }, | |
3718 | }, | |
3719 | .opt_clks = usb_otg_hs_opt_clks, | |
3720 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3721 | }; | |
3722 | ||
3723 | /* | |
3724 | * 'usb_tll_hs' class | |
3725 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3726 | */ | |
3727 | ||
3728 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3729 | .rev_offs = 0x0000, | |
3730 | .sysc_offs = 0x0010, | |
3731 | .syss_offs = 0x0014, | |
3732 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3733 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3734 | SYSC_HAS_AUTOIDLE), | |
3735 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3736 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3737 | }; | |
3738 | ||
3739 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3740 | .name = "usb_tll_hs", | |
3741 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3742 | }; | |
3743 | ||
3744 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
3745 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
3746 | { .irq = -1 } | |
3747 | }; | |
3748 | ||
3749 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
3750 | .name = "usb_tll_hs", | |
3751 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3752 | .clkdm_name = "l3_init_clkdm", | |
3753 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
3754 | .main_clk = "usb_tll_hs_ick", | |
3755 | .prcm = { | |
3756 | .omap4 = { | |
3757 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3758 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3759 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3760 | }, |
3761 | }, | |
5844c4ea BC |
3762 | }; |
3763 | ||
3b54baad BC |
3764 | /* |
3765 | * 'wd_timer' class | |
3766 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3767 | * overflow condition | |
3768 | */ | |
3769 | ||
3770 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3771 | .rev_offs = 0x0000, | |
3772 | .sysc_offs = 0x0010, | |
3773 | .syss_offs = 0x0014, | |
3774 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3775 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3776 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3777 | SIDLE_SMART_WKUP), | |
3b54baad | 3778 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3779 | }; |
3780 | ||
3b54baad BC |
3781 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3782 | .name = "wd_timer", | |
3783 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3784 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 3785 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
3786 | }; |
3787 | ||
3788 | /* wd_timer2 */ | |
3b54baad BC |
3789 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
3790 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3791 | { .irq = -1 } |
3b54baad BC |
3792 | }; |
3793 | ||
3b54baad BC |
3794 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3795 | .name = "wd_timer2", | |
3796 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3797 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 3798 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
17b7e7d3 | 3799 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3800 | .prcm = { |
3801 | .omap4 = { | |
d0f0631d | 3802 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3803 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3804 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3805 | }, |
3806 | }, | |
9780a9cf BC |
3807 | }; |
3808 | ||
3b54baad | 3809 | /* wd_timer3 */ |
3b54baad BC |
3810 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
3811 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3812 | { .irq = -1 } |
9780a9cf BC |
3813 | }; |
3814 | ||
3b54baad BC |
3815 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3816 | .name = "wd_timer3", | |
3817 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3818 | .clkdm_name = "abe_clkdm", |
3b54baad | 3819 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
17b7e7d3 | 3820 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3821 | .prcm = { |
3822 | .omap4 = { | |
d0f0631d | 3823 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3824 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3825 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3826 | }, |
3827 | }, | |
9780a9cf | 3828 | }; |
531ce0d5 | 3829 | |
844a3b63 | 3830 | |
af88fa9a | 3831 | /* |
844a3b63 | 3832 | * interfaces |
af88fa9a | 3833 | */ |
af88fa9a | 3834 | |
42b9e387 PW |
3835 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { |
3836 | { | |
3837 | .pa_start = 0x4a204000, | |
3838 | .pa_end = 0x4a2040ff, | |
3839 | .flags = ADDR_TYPE_RT | |
3840 | }, | |
3841 | { } | |
3842 | }; | |
3843 | ||
3844 | /* c2c -> c2c_target_fw */ | |
3845 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | |
3846 | .master = &omap44xx_c2c_hwmod, | |
3847 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3848 | .clk = "div_core_ck", | |
3849 | .addr = omap44xx_c2c_target_fw_addrs, | |
3850 | .user = OCP_USER_MPU, | |
3851 | }; | |
3852 | ||
3853 | /* l4_cfg -> c2c_target_fw */ | |
3854 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | |
3855 | .master = &omap44xx_l4_cfg_hwmod, | |
3856 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3857 | .clk = "l4_div_ck", | |
3858 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3859 | }; | |
3860 | ||
844a3b63 PW |
3861 | /* l3_main_1 -> dmm */ |
3862 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3863 | .master = &omap44xx_l3_main_1_hwmod, | |
3864 | .slave = &omap44xx_dmm_hwmod, | |
3865 | .clk = "l3_div_ck", | |
3866 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3867 | }; |
3868 | ||
844a3b63 | 3869 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 3870 | { |
844a3b63 PW |
3871 | .pa_start = 0x4e000000, |
3872 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
3873 | .flags = ADDR_TYPE_RT |
3874 | }, | |
844a3b63 | 3875 | { } |
af88fa9a BC |
3876 | }; |
3877 | ||
844a3b63 PW |
3878 | /* mpu -> dmm */ |
3879 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3880 | .master = &omap44xx_mpu_hwmod, | |
3881 | .slave = &omap44xx_dmm_hwmod, | |
3882 | .clk = "l3_div_ck", | |
3883 | .addr = omap44xx_dmm_addrs, | |
3884 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3885 | }; |
3886 | ||
42b9e387 PW |
3887 | /* c2c -> emif_fw */ |
3888 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | |
3889 | .master = &omap44xx_c2c_hwmod, | |
3890 | .slave = &omap44xx_emif_fw_hwmod, | |
3891 | .clk = "div_core_ck", | |
3892 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3893 | }; | |
3894 | ||
844a3b63 PW |
3895 | /* dmm -> emif_fw */ |
3896 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3897 | .master = &omap44xx_dmm_hwmod, | |
3898 | .slave = &omap44xx_emif_fw_hwmod, | |
3899 | .clk = "l3_div_ck", | |
3900 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3901 | }; | |
3902 | ||
3903 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3904 | { | |
3905 | .pa_start = 0x4a20c000, | |
3906 | .pa_end = 0x4a20c0ff, | |
3907 | .flags = ADDR_TYPE_RT | |
3908 | }, | |
3909 | { } | |
3910 | }; | |
3911 | ||
3912 | /* l4_cfg -> emif_fw */ | |
3913 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3914 | .master = &omap44xx_l4_cfg_hwmod, | |
3915 | .slave = &omap44xx_emif_fw_hwmod, | |
3916 | .clk = "l4_div_ck", | |
3917 | .addr = omap44xx_emif_fw_addrs, | |
3918 | .user = OCP_USER_MPU, | |
3919 | }; | |
3920 | ||
3921 | /* iva -> l3_instr */ | |
3922 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3923 | .master = &omap44xx_iva_hwmod, | |
3924 | .slave = &omap44xx_l3_instr_hwmod, | |
3925 | .clk = "l3_div_ck", | |
3926 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3927 | }; | |
3928 | ||
3929 | /* l3_main_3 -> l3_instr */ | |
3930 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3931 | .master = &omap44xx_l3_main_3_hwmod, | |
3932 | .slave = &omap44xx_l3_instr_hwmod, | |
3933 | .clk = "l3_div_ck", | |
3934 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3935 | }; | |
3936 | ||
9a817bc8 BC |
3937 | /* ocp_wp_noc -> l3_instr */ |
3938 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3939 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3940 | .slave = &omap44xx_l3_instr_hwmod, | |
3941 | .clk = "l3_div_ck", | |
3942 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3943 | }; | |
3944 | ||
844a3b63 PW |
3945 | /* dsp -> l3_main_1 */ |
3946 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3947 | .master = &omap44xx_dsp_hwmod, | |
3948 | .slave = &omap44xx_l3_main_1_hwmod, | |
3949 | .clk = "l3_div_ck", | |
3950 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3951 | }; | |
3952 | ||
3953 | /* dss -> l3_main_1 */ | |
3954 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3955 | .master = &omap44xx_dss_hwmod, | |
3956 | .slave = &omap44xx_l3_main_1_hwmod, | |
3957 | .clk = "l3_div_ck", | |
3958 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3959 | }; | |
3960 | ||
3961 | /* l3_main_2 -> l3_main_1 */ | |
3962 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3963 | .master = &omap44xx_l3_main_2_hwmod, | |
3964 | .slave = &omap44xx_l3_main_1_hwmod, | |
3965 | .clk = "l3_div_ck", | |
3966 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3967 | }; | |
3968 | ||
3969 | /* l4_cfg -> l3_main_1 */ | |
3970 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3971 | .master = &omap44xx_l4_cfg_hwmod, | |
3972 | .slave = &omap44xx_l3_main_1_hwmod, | |
3973 | .clk = "l4_div_ck", | |
3974 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3975 | }; | |
3976 | ||
3977 | /* mmc1 -> l3_main_1 */ | |
3978 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3979 | .master = &omap44xx_mmc1_hwmod, | |
3980 | .slave = &omap44xx_l3_main_1_hwmod, | |
3981 | .clk = "l3_div_ck", | |
3982 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3983 | }; | |
3984 | ||
3985 | /* mmc2 -> l3_main_1 */ | |
3986 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3987 | .master = &omap44xx_mmc2_hwmod, | |
3988 | .slave = &omap44xx_l3_main_1_hwmod, | |
3989 | .clk = "l3_div_ck", | |
3990 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3991 | }; | |
3992 | ||
3993 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3994 | { | |
3995 | .pa_start = 0x44000000, | |
3996 | .pa_end = 0x44000fff, | |
3997 | .flags = ADDR_TYPE_RT | |
3998 | }, | |
3999 | { } | |
4000 | }; | |
4001 | ||
4002 | /* mpu -> l3_main_1 */ | |
4003 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
4004 | .master = &omap44xx_mpu_hwmod, | |
4005 | .slave = &omap44xx_l3_main_1_hwmod, | |
4006 | .clk = "l3_div_ck", | |
4007 | .addr = omap44xx_l3_main_1_addrs, | |
4008 | .user = OCP_USER_MPU, | |
4009 | }; | |
4010 | ||
42b9e387 PW |
4011 | /* c2c_target_fw -> l3_main_2 */ |
4012 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | |
4013 | .master = &omap44xx_c2c_target_fw_hwmod, | |
4014 | .slave = &omap44xx_l3_main_2_hwmod, | |
4015 | .clk = "l3_div_ck", | |
4016 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4017 | }; | |
4018 | ||
96566043 BC |
4019 | /* debugss -> l3_main_2 */ |
4020 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
4021 | .master = &omap44xx_debugss_hwmod, | |
4022 | .slave = &omap44xx_l3_main_2_hwmod, | |
4023 | .clk = "dbgclk_mux_ck", | |
4024 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4025 | }; | |
4026 | ||
844a3b63 PW |
4027 | /* dma_system -> l3_main_2 */ |
4028 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
4029 | .master = &omap44xx_dma_system_hwmod, | |
4030 | .slave = &omap44xx_l3_main_2_hwmod, | |
4031 | .clk = "l3_div_ck", | |
4032 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4033 | }; | |
4034 | ||
b050f688 ML |
4035 | /* fdif -> l3_main_2 */ |
4036 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
4037 | .master = &omap44xx_fdif_hwmod, | |
4038 | .slave = &omap44xx_l3_main_2_hwmod, | |
4039 | .clk = "l3_div_ck", | |
4040 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4041 | }; | |
4042 | ||
9def390e PW |
4043 | /* gpu -> l3_main_2 */ |
4044 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
4045 | .master = &omap44xx_gpu_hwmod, | |
4046 | .slave = &omap44xx_l3_main_2_hwmod, | |
4047 | .clk = "l3_div_ck", | |
4048 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4049 | }; | |
4050 | ||
844a3b63 PW |
4051 | /* hsi -> l3_main_2 */ |
4052 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
4053 | .master = &omap44xx_hsi_hwmod, | |
4054 | .slave = &omap44xx_l3_main_2_hwmod, | |
4055 | .clk = "l3_div_ck", | |
4056 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4057 | }; | |
4058 | ||
4059 | /* ipu -> l3_main_2 */ | |
4060 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
4061 | .master = &omap44xx_ipu_hwmod, | |
4062 | .slave = &omap44xx_l3_main_2_hwmod, | |
4063 | .clk = "l3_div_ck", | |
4064 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4065 | }; | |
4066 | ||
4067 | /* iss -> l3_main_2 */ | |
4068 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
4069 | .master = &omap44xx_iss_hwmod, | |
4070 | .slave = &omap44xx_l3_main_2_hwmod, | |
4071 | .clk = "l3_div_ck", | |
4072 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4073 | }; | |
4074 | ||
4075 | /* iva -> l3_main_2 */ | |
4076 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
4077 | .master = &omap44xx_iva_hwmod, | |
4078 | .slave = &omap44xx_l3_main_2_hwmod, | |
4079 | .clk = "l3_div_ck", | |
4080 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4081 | }; | |
4082 | ||
4083 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
4084 | { | |
4085 | .pa_start = 0x44800000, | |
4086 | .pa_end = 0x44801fff, | |
4087 | .flags = ADDR_TYPE_RT | |
4088 | }, | |
4089 | { } | |
4090 | }; | |
4091 | ||
4092 | /* l3_main_1 -> l3_main_2 */ | |
4093 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
4094 | .master = &omap44xx_l3_main_1_hwmod, | |
4095 | .slave = &omap44xx_l3_main_2_hwmod, | |
4096 | .clk = "l3_div_ck", | |
4097 | .addr = omap44xx_l3_main_2_addrs, | |
4098 | .user = OCP_USER_MPU, | |
4099 | }; | |
4100 | ||
4101 | /* l4_cfg -> l3_main_2 */ | |
4102 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
4103 | .master = &omap44xx_l4_cfg_hwmod, | |
4104 | .slave = &omap44xx_l3_main_2_hwmod, | |
4105 | .clk = "l4_div_ck", | |
4106 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4107 | }; | |
4108 | ||
0c668875 | 4109 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 4110 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
4111 | .master = &omap44xx_usb_host_fs_hwmod, |
4112 | .slave = &omap44xx_l3_main_2_hwmod, | |
4113 | .clk = "l3_div_ck", | |
4114 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4115 | }; | |
4116 | ||
844a3b63 PW |
4117 | /* usb_host_hs -> l3_main_2 */ |
4118 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
4119 | .master = &omap44xx_usb_host_hs_hwmod, | |
4120 | .slave = &omap44xx_l3_main_2_hwmod, | |
4121 | .clk = "l3_div_ck", | |
4122 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4123 | }; | |
4124 | ||
4125 | /* usb_otg_hs -> l3_main_2 */ | |
4126 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
4127 | .master = &omap44xx_usb_otg_hs_hwmod, | |
4128 | .slave = &omap44xx_l3_main_2_hwmod, | |
4129 | .clk = "l3_div_ck", | |
4130 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4131 | }; | |
4132 | ||
4133 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
4134 | { | |
4135 | .pa_start = 0x45000000, | |
4136 | .pa_end = 0x45000fff, | |
4137 | .flags = ADDR_TYPE_RT | |
4138 | }, | |
4139 | { } | |
4140 | }; | |
4141 | ||
4142 | /* l3_main_1 -> l3_main_3 */ | |
4143 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
4144 | .master = &omap44xx_l3_main_1_hwmod, | |
4145 | .slave = &omap44xx_l3_main_3_hwmod, | |
4146 | .clk = "l3_div_ck", | |
4147 | .addr = omap44xx_l3_main_3_addrs, | |
4148 | .user = OCP_USER_MPU, | |
4149 | }; | |
4150 | ||
4151 | /* l3_main_2 -> l3_main_3 */ | |
4152 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
4153 | .master = &omap44xx_l3_main_2_hwmod, | |
4154 | .slave = &omap44xx_l3_main_3_hwmod, | |
4155 | .clk = "l3_div_ck", | |
4156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4157 | }; | |
4158 | ||
4159 | /* l4_cfg -> l3_main_3 */ | |
4160 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
4161 | .master = &omap44xx_l4_cfg_hwmod, | |
4162 | .slave = &omap44xx_l3_main_3_hwmod, | |
4163 | .clk = "l4_div_ck", | |
4164 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4165 | }; | |
4166 | ||
4167 | /* aess -> l4_abe */ | |
b0a70cc8 | 4168 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
4169 | .master = &omap44xx_aess_hwmod, |
4170 | .slave = &omap44xx_l4_abe_hwmod, | |
4171 | .clk = "ocp_abe_iclk", | |
4172 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4173 | }; | |
4174 | ||
4175 | /* dsp -> l4_abe */ | |
4176 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
4177 | .master = &omap44xx_dsp_hwmod, | |
4178 | .slave = &omap44xx_l4_abe_hwmod, | |
4179 | .clk = "ocp_abe_iclk", | |
4180 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4181 | }; | |
4182 | ||
4183 | /* l3_main_1 -> l4_abe */ | |
4184 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
4185 | .master = &omap44xx_l3_main_1_hwmod, | |
4186 | .slave = &omap44xx_l4_abe_hwmod, | |
4187 | .clk = "l3_div_ck", | |
4188 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4189 | }; | |
4190 | ||
4191 | /* mpu -> l4_abe */ | |
4192 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
4193 | .master = &omap44xx_mpu_hwmod, | |
4194 | .slave = &omap44xx_l4_abe_hwmod, | |
4195 | .clk = "ocp_abe_iclk", | |
4196 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4197 | }; | |
4198 | ||
4199 | /* l3_main_1 -> l4_cfg */ | |
4200 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
4201 | .master = &omap44xx_l3_main_1_hwmod, | |
4202 | .slave = &omap44xx_l4_cfg_hwmod, | |
4203 | .clk = "l3_div_ck", | |
4204 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4205 | }; | |
4206 | ||
4207 | /* l3_main_2 -> l4_per */ | |
4208 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
4209 | .master = &omap44xx_l3_main_2_hwmod, | |
4210 | .slave = &omap44xx_l4_per_hwmod, | |
4211 | .clk = "l3_div_ck", | |
4212 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4213 | }; | |
4214 | ||
4215 | /* l4_cfg -> l4_wkup */ | |
4216 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
4217 | .master = &omap44xx_l4_cfg_hwmod, | |
4218 | .slave = &omap44xx_l4_wkup_hwmod, | |
4219 | .clk = "l4_div_ck", | |
4220 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4221 | }; | |
4222 | ||
4223 | /* mpu -> mpu_private */ | |
4224 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
4225 | .master = &omap44xx_mpu_hwmod, | |
4226 | .slave = &omap44xx_mpu_private_hwmod, | |
4227 | .clk = "l3_div_ck", | |
4228 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4229 | }; | |
4230 | ||
9a817bc8 BC |
4231 | static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { |
4232 | { | |
4233 | .pa_start = 0x4a102000, | |
4234 | .pa_end = 0x4a10207f, | |
4235 | .flags = ADDR_TYPE_RT | |
4236 | }, | |
4237 | { } | |
4238 | }; | |
4239 | ||
4240 | /* l4_cfg -> ocp_wp_noc */ | |
4241 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
4242 | .master = &omap44xx_l4_cfg_hwmod, | |
4243 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
4244 | .clk = "l4_div_ck", | |
4245 | .addr = omap44xx_ocp_wp_noc_addrs, | |
4246 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4247 | }; | |
4248 | ||
844a3b63 PW |
4249 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
4250 | { | |
9f0c5996 SG |
4251 | .name = "dmem", |
4252 | .pa_start = 0x40180000, | |
4253 | .pa_end = 0x4018ffff | |
4254 | }, | |
4255 | { | |
4256 | .name = "cmem", | |
4257 | .pa_start = 0x401a0000, | |
4258 | .pa_end = 0x401a1fff | |
4259 | }, | |
4260 | { | |
4261 | .name = "smem", | |
4262 | .pa_start = 0x401c0000, | |
4263 | .pa_end = 0x401c5fff | |
4264 | }, | |
4265 | { | |
4266 | .name = "pmem", | |
4267 | .pa_start = 0x401e0000, | |
4268 | .pa_end = 0x401e1fff | |
4269 | }, | |
4270 | { | |
4271 | .name = "mpu", | |
844a3b63 PW |
4272 | .pa_start = 0x401f1000, |
4273 | .pa_end = 0x401f13ff, | |
4274 | .flags = ADDR_TYPE_RT | |
4275 | }, | |
4276 | { } | |
4277 | }; | |
4278 | ||
4279 | /* l4_abe -> aess */ | |
b0a70cc8 | 4280 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
4281 | .master = &omap44xx_l4_abe_hwmod, |
4282 | .slave = &omap44xx_aess_hwmod, | |
4283 | .clk = "ocp_abe_iclk", | |
4284 | .addr = omap44xx_aess_addrs, | |
4285 | .user = OCP_USER_MPU, | |
4286 | }; | |
4287 | ||
4288 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
4289 | { | |
9f0c5996 SG |
4290 | .name = "dmem_dma", |
4291 | .pa_start = 0x49080000, | |
4292 | .pa_end = 0x4908ffff | |
4293 | }, | |
4294 | { | |
4295 | .name = "cmem_dma", | |
4296 | .pa_start = 0x490a0000, | |
4297 | .pa_end = 0x490a1fff | |
4298 | }, | |
4299 | { | |
4300 | .name = "smem_dma", | |
4301 | .pa_start = 0x490c0000, | |
4302 | .pa_end = 0x490c5fff | |
4303 | }, | |
4304 | { | |
4305 | .name = "pmem_dma", | |
4306 | .pa_start = 0x490e0000, | |
4307 | .pa_end = 0x490e1fff | |
4308 | }, | |
4309 | { | |
4310 | .name = "dma", | |
844a3b63 PW |
4311 | .pa_start = 0x490f1000, |
4312 | .pa_end = 0x490f13ff, | |
4313 | .flags = ADDR_TYPE_RT | |
4314 | }, | |
4315 | { } | |
4316 | }; | |
4317 | ||
4318 | /* l4_abe -> aess (dma) */ | |
b0a70cc8 | 4319 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
4320 | .master = &omap44xx_l4_abe_hwmod, |
4321 | .slave = &omap44xx_aess_hwmod, | |
4322 | .clk = "ocp_abe_iclk", | |
4323 | .addr = omap44xx_aess_dma_addrs, | |
4324 | .user = OCP_USER_SDMA, | |
4325 | }; | |
4326 | ||
42b9e387 PW |
4327 | /* l3_main_2 -> c2c */ |
4328 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
4329 | .master = &omap44xx_l3_main_2_hwmod, | |
4330 | .slave = &omap44xx_c2c_hwmod, | |
4331 | .clk = "l3_div_ck", | |
4332 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4333 | }; | |
4334 | ||
844a3b63 PW |
4335 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
4336 | { | |
4337 | .pa_start = 0x4a304000, | |
4338 | .pa_end = 0x4a30401f, | |
4339 | .flags = ADDR_TYPE_RT | |
4340 | }, | |
4341 | { } | |
4342 | }; | |
4343 | ||
4344 | /* l4_wkup -> counter_32k */ | |
4345 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
4346 | .master = &omap44xx_l4_wkup_hwmod, | |
4347 | .slave = &omap44xx_counter_32k_hwmod, | |
4348 | .clk = "l4_wkup_clk_mux_ck", | |
4349 | .addr = omap44xx_counter_32k_addrs, | |
4350 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4351 | }; | |
4352 | ||
a0b5d813 PW |
4353 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
4354 | { | |
4355 | .pa_start = 0x4a002000, | |
4356 | .pa_end = 0x4a0027ff, | |
4357 | .flags = ADDR_TYPE_RT | |
4358 | }, | |
4359 | { } | |
4360 | }; | |
4361 | ||
4362 | /* l4_cfg -> ctrl_module_core */ | |
4363 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
4364 | .master = &omap44xx_l4_cfg_hwmod, | |
4365 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
4366 | .clk = "l4_div_ck", | |
4367 | .addr = omap44xx_ctrl_module_core_addrs, | |
4368 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4369 | }; | |
4370 | ||
4371 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
4372 | { | |
4373 | .pa_start = 0x4a100000, | |
4374 | .pa_end = 0x4a1007ff, | |
4375 | .flags = ADDR_TYPE_RT | |
4376 | }, | |
4377 | { } | |
4378 | }; | |
4379 | ||
4380 | /* l4_cfg -> ctrl_module_pad_core */ | |
4381 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
4382 | .master = &omap44xx_l4_cfg_hwmod, | |
4383 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
4384 | .clk = "l4_div_ck", | |
4385 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
4386 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4387 | }; | |
4388 | ||
4389 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
4390 | { | |
4391 | .pa_start = 0x4a30c000, | |
4392 | .pa_end = 0x4a30c7ff, | |
4393 | .flags = ADDR_TYPE_RT | |
4394 | }, | |
4395 | { } | |
4396 | }; | |
4397 | ||
4398 | /* l4_wkup -> ctrl_module_wkup */ | |
4399 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
4400 | .master = &omap44xx_l4_wkup_hwmod, | |
4401 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
4402 | .clk = "l4_wkup_clk_mux_ck", | |
4403 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
4404 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4405 | }; | |
4406 | ||
4407 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
4408 | { | |
4409 | .pa_start = 0x4a31e000, | |
4410 | .pa_end = 0x4a31e7ff, | |
4411 | .flags = ADDR_TYPE_RT | |
4412 | }, | |
4413 | { } | |
4414 | }; | |
4415 | ||
4416 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
4417 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
4418 | .master = &omap44xx_l4_wkup_hwmod, | |
4419 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
4420 | .clk = "l4_wkup_clk_mux_ck", | |
4421 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
4422 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4423 | }; | |
4424 | ||
96566043 BC |
4425 | static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { |
4426 | { | |
4427 | .pa_start = 0x54160000, | |
4428 | .pa_end = 0x54167fff, | |
4429 | .flags = ADDR_TYPE_RT | |
4430 | }, | |
4431 | { } | |
4432 | }; | |
4433 | ||
4434 | /* l3_instr -> debugss */ | |
4435 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
4436 | .master = &omap44xx_l3_instr_hwmod, | |
4437 | .slave = &omap44xx_debugss_hwmod, | |
4438 | .clk = "l3_div_ck", | |
4439 | .addr = omap44xx_debugss_addrs, | |
4440 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4441 | }; | |
4442 | ||
844a3b63 PW |
4443 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
4444 | { | |
4445 | .pa_start = 0x4a056000, | |
4446 | .pa_end = 0x4a056fff, | |
4447 | .flags = ADDR_TYPE_RT | |
4448 | }, | |
4449 | { } | |
4450 | }; | |
4451 | ||
4452 | /* l4_cfg -> dma_system */ | |
4453 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
4454 | .master = &omap44xx_l4_cfg_hwmod, | |
4455 | .slave = &omap44xx_dma_system_hwmod, | |
4456 | .clk = "l4_div_ck", | |
4457 | .addr = omap44xx_dma_system_addrs, | |
4458 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4459 | }; | |
4460 | ||
4461 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
4462 | { | |
4463 | .name = "mpu", | |
4464 | .pa_start = 0x4012e000, | |
4465 | .pa_end = 0x4012e07f, | |
4466 | .flags = ADDR_TYPE_RT | |
4467 | }, | |
4468 | { } | |
4469 | }; | |
4470 | ||
4471 | /* l4_abe -> dmic */ | |
4472 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
4473 | .master = &omap44xx_l4_abe_hwmod, | |
4474 | .slave = &omap44xx_dmic_hwmod, | |
4475 | .clk = "ocp_abe_iclk", | |
4476 | .addr = omap44xx_dmic_addrs, | |
4477 | .user = OCP_USER_MPU, | |
4478 | }; | |
4479 | ||
4480 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
4481 | { | |
4482 | .name = "dma", | |
4483 | .pa_start = 0x4902e000, | |
4484 | .pa_end = 0x4902e07f, | |
4485 | .flags = ADDR_TYPE_RT | |
4486 | }, | |
4487 | { } | |
4488 | }; | |
4489 | ||
4490 | /* l4_abe -> dmic (dma) */ | |
4491 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
4492 | .master = &omap44xx_l4_abe_hwmod, | |
4493 | .slave = &omap44xx_dmic_hwmod, | |
4494 | .clk = "ocp_abe_iclk", | |
4495 | .addr = omap44xx_dmic_dma_addrs, | |
4496 | .user = OCP_USER_SDMA, | |
4497 | }; | |
4498 | ||
4499 | /* dsp -> iva */ | |
4500 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
4501 | .master = &omap44xx_dsp_hwmod, | |
4502 | .slave = &omap44xx_iva_hwmod, | |
4503 | .clk = "dpll_iva_m5x2_ck", | |
4504 | .user = OCP_USER_DSP, | |
4505 | }; | |
4506 | ||
42b9e387 | 4507 | /* dsp -> sl2if */ |
b360124e | 4508 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
42b9e387 PW |
4509 | .master = &omap44xx_dsp_hwmod, |
4510 | .slave = &omap44xx_sl2if_hwmod, | |
4511 | .clk = "dpll_iva_m5x2_ck", | |
4512 | .user = OCP_USER_DSP, | |
4513 | }; | |
4514 | ||
844a3b63 PW |
4515 | /* l4_cfg -> dsp */ |
4516 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
4517 | .master = &omap44xx_l4_cfg_hwmod, | |
4518 | .slave = &omap44xx_dsp_hwmod, | |
4519 | .clk = "l4_div_ck", | |
4520 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4521 | }; | |
4522 | ||
4523 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
4524 | { | |
4525 | .pa_start = 0x58000000, | |
4526 | .pa_end = 0x5800007f, | |
4527 | .flags = ADDR_TYPE_RT | |
4528 | }, | |
4529 | { } | |
4530 | }; | |
4531 | ||
4532 | /* l3_main_2 -> dss */ | |
4533 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
4534 | .master = &omap44xx_l3_main_2_hwmod, | |
4535 | .slave = &omap44xx_dss_hwmod, | |
4536 | .clk = "dss_fck", | |
4537 | .addr = omap44xx_dss_dma_addrs, | |
4538 | .user = OCP_USER_SDMA, | |
4539 | }; | |
4540 | ||
4541 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
4542 | { | |
4543 | .pa_start = 0x48040000, | |
4544 | .pa_end = 0x4804007f, | |
4545 | .flags = ADDR_TYPE_RT | |
4546 | }, | |
4547 | { } | |
4548 | }; | |
4549 | ||
4550 | /* l4_per -> dss */ | |
4551 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
4552 | .master = &omap44xx_l4_per_hwmod, | |
4553 | .slave = &omap44xx_dss_hwmod, | |
4554 | .clk = "l4_div_ck", | |
4555 | .addr = omap44xx_dss_addrs, | |
4556 | .user = OCP_USER_MPU, | |
4557 | }; | |
4558 | ||
4559 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
4560 | { | |
4561 | .pa_start = 0x58001000, | |
4562 | .pa_end = 0x58001fff, | |
4563 | .flags = ADDR_TYPE_RT | |
4564 | }, | |
4565 | { } | |
4566 | }; | |
4567 | ||
4568 | /* l3_main_2 -> dss_dispc */ | |
4569 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
4570 | .master = &omap44xx_l3_main_2_hwmod, | |
4571 | .slave = &omap44xx_dss_dispc_hwmod, | |
4572 | .clk = "dss_fck", | |
4573 | .addr = omap44xx_dss_dispc_dma_addrs, | |
4574 | .user = OCP_USER_SDMA, | |
4575 | }; | |
4576 | ||
4577 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
4578 | { | |
4579 | .pa_start = 0x48041000, | |
4580 | .pa_end = 0x48041fff, | |
4581 | .flags = ADDR_TYPE_RT | |
4582 | }, | |
4583 | { } | |
4584 | }; | |
4585 | ||
4586 | /* l4_per -> dss_dispc */ | |
4587 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
4588 | .master = &omap44xx_l4_per_hwmod, | |
4589 | .slave = &omap44xx_dss_dispc_hwmod, | |
4590 | .clk = "l4_div_ck", | |
4591 | .addr = omap44xx_dss_dispc_addrs, | |
4592 | .user = OCP_USER_MPU, | |
4593 | }; | |
4594 | ||
4595 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
4596 | { | |
4597 | .pa_start = 0x58004000, | |
4598 | .pa_end = 0x580041ff, | |
4599 | .flags = ADDR_TYPE_RT | |
4600 | }, | |
4601 | { } | |
4602 | }; | |
4603 | ||
4604 | /* l3_main_2 -> dss_dsi1 */ | |
4605 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
4606 | .master = &omap44xx_l3_main_2_hwmod, | |
4607 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4608 | .clk = "dss_fck", | |
4609 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
4610 | .user = OCP_USER_SDMA, | |
4611 | }; | |
4612 | ||
4613 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
4614 | { | |
4615 | .pa_start = 0x48044000, | |
4616 | .pa_end = 0x480441ff, | |
4617 | .flags = ADDR_TYPE_RT | |
4618 | }, | |
4619 | { } | |
4620 | }; | |
4621 | ||
4622 | /* l4_per -> dss_dsi1 */ | |
4623 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
4624 | .master = &omap44xx_l4_per_hwmod, | |
4625 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4626 | .clk = "l4_div_ck", | |
4627 | .addr = omap44xx_dss_dsi1_addrs, | |
4628 | .user = OCP_USER_MPU, | |
4629 | }; | |
4630 | ||
4631 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
4632 | { | |
4633 | .pa_start = 0x58005000, | |
4634 | .pa_end = 0x580051ff, | |
4635 | .flags = ADDR_TYPE_RT | |
4636 | }, | |
4637 | { } | |
4638 | }; | |
4639 | ||
4640 | /* l3_main_2 -> dss_dsi2 */ | |
4641 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
4642 | .master = &omap44xx_l3_main_2_hwmod, | |
4643 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4644 | .clk = "dss_fck", | |
4645 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
4646 | .user = OCP_USER_SDMA, | |
4647 | }; | |
4648 | ||
4649 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
4650 | { | |
4651 | .pa_start = 0x48045000, | |
4652 | .pa_end = 0x480451ff, | |
4653 | .flags = ADDR_TYPE_RT | |
4654 | }, | |
4655 | { } | |
4656 | }; | |
4657 | ||
4658 | /* l4_per -> dss_dsi2 */ | |
4659 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
4660 | .master = &omap44xx_l4_per_hwmod, | |
4661 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4662 | .clk = "l4_div_ck", | |
4663 | .addr = omap44xx_dss_dsi2_addrs, | |
4664 | .user = OCP_USER_MPU, | |
4665 | }; | |
4666 | ||
4667 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
4668 | { | |
4669 | .pa_start = 0x58006000, | |
4670 | .pa_end = 0x58006fff, | |
4671 | .flags = ADDR_TYPE_RT | |
4672 | }, | |
4673 | { } | |
4674 | }; | |
4675 | ||
4676 | /* l3_main_2 -> dss_hdmi */ | |
4677 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
4678 | .master = &omap44xx_l3_main_2_hwmod, | |
4679 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4680 | .clk = "dss_fck", | |
4681 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
4682 | .user = OCP_USER_SDMA, | |
4683 | }; | |
4684 | ||
4685 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
4686 | { | |
4687 | .pa_start = 0x48046000, | |
4688 | .pa_end = 0x48046fff, | |
4689 | .flags = ADDR_TYPE_RT | |
4690 | }, | |
4691 | { } | |
4692 | }; | |
4693 | ||
4694 | /* l4_per -> dss_hdmi */ | |
4695 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
4696 | .master = &omap44xx_l4_per_hwmod, | |
4697 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4698 | .clk = "l4_div_ck", | |
4699 | .addr = omap44xx_dss_hdmi_addrs, | |
4700 | .user = OCP_USER_MPU, | |
4701 | }; | |
4702 | ||
4703 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
4704 | { | |
4705 | .pa_start = 0x58002000, | |
4706 | .pa_end = 0x580020ff, | |
4707 | .flags = ADDR_TYPE_RT | |
4708 | }, | |
4709 | { } | |
4710 | }; | |
4711 | ||
4712 | /* l3_main_2 -> dss_rfbi */ | |
4713 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
4714 | .master = &omap44xx_l3_main_2_hwmod, | |
4715 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4716 | .clk = "dss_fck", | |
4717 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
4718 | .user = OCP_USER_SDMA, | |
4719 | }; | |
4720 | ||
4721 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
4722 | { | |
4723 | .pa_start = 0x48042000, | |
4724 | .pa_end = 0x480420ff, | |
4725 | .flags = ADDR_TYPE_RT | |
4726 | }, | |
4727 | { } | |
4728 | }; | |
4729 | ||
4730 | /* l4_per -> dss_rfbi */ | |
4731 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
4732 | .master = &omap44xx_l4_per_hwmod, | |
4733 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4734 | .clk = "l4_div_ck", | |
4735 | .addr = omap44xx_dss_rfbi_addrs, | |
4736 | .user = OCP_USER_MPU, | |
4737 | }; | |
4738 | ||
4739 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
4740 | { | |
4741 | .pa_start = 0x58003000, | |
4742 | .pa_end = 0x580030ff, | |
4743 | .flags = ADDR_TYPE_RT | |
4744 | }, | |
4745 | { } | |
4746 | }; | |
4747 | ||
4748 | /* l3_main_2 -> dss_venc */ | |
4749 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
4750 | .master = &omap44xx_l3_main_2_hwmod, | |
4751 | .slave = &omap44xx_dss_venc_hwmod, | |
4752 | .clk = "dss_fck", | |
4753 | .addr = omap44xx_dss_venc_dma_addrs, | |
4754 | .user = OCP_USER_SDMA, | |
4755 | }; | |
4756 | ||
4757 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
4758 | { | |
4759 | .pa_start = 0x48043000, | |
4760 | .pa_end = 0x480430ff, | |
4761 | .flags = ADDR_TYPE_RT | |
4762 | }, | |
4763 | { } | |
4764 | }; | |
4765 | ||
4766 | /* l4_per -> dss_venc */ | |
4767 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
4768 | .master = &omap44xx_l4_per_hwmod, | |
4769 | .slave = &omap44xx_dss_venc_hwmod, | |
4770 | .clk = "l4_div_ck", | |
4771 | .addr = omap44xx_dss_venc_addrs, | |
4772 | .user = OCP_USER_MPU, | |
4773 | }; | |
4774 | ||
42b9e387 PW |
4775 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
4776 | { | |
4777 | .pa_start = 0x48078000, | |
4778 | .pa_end = 0x48078fff, | |
4779 | .flags = ADDR_TYPE_RT | |
4780 | }, | |
4781 | { } | |
4782 | }; | |
4783 | ||
4784 | /* l4_per -> elm */ | |
4785 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
4786 | .master = &omap44xx_l4_per_hwmod, | |
4787 | .slave = &omap44xx_elm_hwmod, | |
4788 | .clk = "l4_div_ck", | |
4789 | .addr = omap44xx_elm_addrs, | |
4790 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4791 | }; | |
4792 | ||
bf30f950 PW |
4793 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
4794 | { | |
4795 | .pa_start = 0x4c000000, | |
4796 | .pa_end = 0x4c0000ff, | |
4797 | .flags = ADDR_TYPE_RT | |
4798 | }, | |
4799 | { } | |
4800 | }; | |
4801 | ||
4802 | /* emif_fw -> emif1 */ | |
4803 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | |
4804 | .master = &omap44xx_emif_fw_hwmod, | |
4805 | .slave = &omap44xx_emif1_hwmod, | |
4806 | .clk = "l3_div_ck", | |
4807 | .addr = omap44xx_emif1_addrs, | |
4808 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4809 | }; | |
4810 | ||
4811 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | |
4812 | { | |
4813 | .pa_start = 0x4d000000, | |
4814 | .pa_end = 0x4d0000ff, | |
4815 | .flags = ADDR_TYPE_RT | |
4816 | }, | |
4817 | { } | |
4818 | }; | |
4819 | ||
4820 | /* emif_fw -> emif2 */ | |
4821 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | |
4822 | .master = &omap44xx_emif_fw_hwmod, | |
4823 | .slave = &omap44xx_emif2_hwmod, | |
4824 | .clk = "l3_div_ck", | |
4825 | .addr = omap44xx_emif2_addrs, | |
4826 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4827 | }; | |
4828 | ||
b050f688 ML |
4829 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
4830 | { | |
4831 | .pa_start = 0x4a10a000, | |
4832 | .pa_end = 0x4a10a1ff, | |
4833 | .flags = ADDR_TYPE_RT | |
4834 | }, | |
4835 | { } | |
4836 | }; | |
4837 | ||
4838 | /* l4_cfg -> fdif */ | |
4839 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4840 | .master = &omap44xx_l4_cfg_hwmod, | |
4841 | .slave = &omap44xx_fdif_hwmod, | |
4842 | .clk = "l4_div_ck", | |
4843 | .addr = omap44xx_fdif_addrs, | |
4844 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4845 | }; | |
4846 | ||
844a3b63 PW |
4847 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
4848 | { | |
4849 | .pa_start = 0x4a310000, | |
4850 | .pa_end = 0x4a3101ff, | |
4851 | .flags = ADDR_TYPE_RT | |
4852 | }, | |
4853 | { } | |
4854 | }; | |
4855 | ||
4856 | /* l4_wkup -> gpio1 */ | |
4857 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4858 | .master = &omap44xx_l4_wkup_hwmod, | |
4859 | .slave = &omap44xx_gpio1_hwmod, | |
4860 | .clk = "l4_wkup_clk_mux_ck", | |
4861 | .addr = omap44xx_gpio1_addrs, | |
4862 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4863 | }; | |
4864 | ||
4865 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
4866 | { | |
4867 | .pa_start = 0x48055000, | |
4868 | .pa_end = 0x480551ff, | |
4869 | .flags = ADDR_TYPE_RT | |
4870 | }, | |
4871 | { } | |
4872 | }; | |
4873 | ||
4874 | /* l4_per -> gpio2 */ | |
4875 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4876 | .master = &omap44xx_l4_per_hwmod, | |
4877 | .slave = &omap44xx_gpio2_hwmod, | |
4878 | .clk = "l4_div_ck", | |
4879 | .addr = omap44xx_gpio2_addrs, | |
4880 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4881 | }; | |
4882 | ||
4883 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
4884 | { | |
4885 | .pa_start = 0x48057000, | |
4886 | .pa_end = 0x480571ff, | |
4887 | .flags = ADDR_TYPE_RT | |
4888 | }, | |
4889 | { } | |
4890 | }; | |
4891 | ||
4892 | /* l4_per -> gpio3 */ | |
4893 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4894 | .master = &omap44xx_l4_per_hwmod, | |
4895 | .slave = &omap44xx_gpio3_hwmod, | |
4896 | .clk = "l4_div_ck", | |
4897 | .addr = omap44xx_gpio3_addrs, | |
4898 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4899 | }; | |
4900 | ||
4901 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
4902 | { | |
4903 | .pa_start = 0x48059000, | |
4904 | .pa_end = 0x480591ff, | |
4905 | .flags = ADDR_TYPE_RT | |
4906 | }, | |
4907 | { } | |
4908 | }; | |
4909 | ||
4910 | /* l4_per -> gpio4 */ | |
4911 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4912 | .master = &omap44xx_l4_per_hwmod, | |
4913 | .slave = &omap44xx_gpio4_hwmod, | |
4914 | .clk = "l4_div_ck", | |
4915 | .addr = omap44xx_gpio4_addrs, | |
4916 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4917 | }; | |
4918 | ||
4919 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
4920 | { | |
4921 | .pa_start = 0x4805b000, | |
4922 | .pa_end = 0x4805b1ff, | |
4923 | .flags = ADDR_TYPE_RT | |
4924 | }, | |
4925 | { } | |
4926 | }; | |
4927 | ||
4928 | /* l4_per -> gpio5 */ | |
4929 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4930 | .master = &omap44xx_l4_per_hwmod, | |
4931 | .slave = &omap44xx_gpio5_hwmod, | |
4932 | .clk = "l4_div_ck", | |
4933 | .addr = omap44xx_gpio5_addrs, | |
4934 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4935 | }; | |
4936 | ||
4937 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
4938 | { | |
4939 | .pa_start = 0x4805d000, | |
4940 | .pa_end = 0x4805d1ff, | |
4941 | .flags = ADDR_TYPE_RT | |
4942 | }, | |
4943 | { } | |
4944 | }; | |
4945 | ||
4946 | /* l4_per -> gpio6 */ | |
4947 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4948 | .master = &omap44xx_l4_per_hwmod, | |
4949 | .slave = &omap44xx_gpio6_hwmod, | |
4950 | .clk = "l4_div_ck", | |
4951 | .addr = omap44xx_gpio6_addrs, | |
4952 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4953 | }; | |
4954 | ||
eb42b5d3 BC |
4955 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
4956 | { | |
4957 | .pa_start = 0x50000000, | |
4958 | .pa_end = 0x500003ff, | |
4959 | .flags = ADDR_TYPE_RT | |
4960 | }, | |
4961 | { } | |
4962 | }; | |
4963 | ||
4964 | /* l3_main_2 -> gpmc */ | |
4965 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4966 | .master = &omap44xx_l3_main_2_hwmod, | |
4967 | .slave = &omap44xx_gpmc_hwmod, | |
4968 | .clk = "l3_div_ck", | |
4969 | .addr = omap44xx_gpmc_addrs, | |
4970 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4971 | }; | |
4972 | ||
9def390e PW |
4973 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4974 | { | |
4975 | .pa_start = 0x56000000, | |
4976 | .pa_end = 0x5600ffff, | |
4977 | .flags = ADDR_TYPE_RT | |
4978 | }, | |
4979 | { } | |
4980 | }; | |
4981 | ||
4982 | /* l3_main_2 -> gpu */ | |
4983 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4984 | .master = &omap44xx_l3_main_2_hwmod, | |
4985 | .slave = &omap44xx_gpu_hwmod, | |
4986 | .clk = "l3_div_ck", | |
4987 | .addr = omap44xx_gpu_addrs, | |
4988 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4989 | }; | |
4990 | ||
a091c08e PW |
4991 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4992 | { | |
4993 | .pa_start = 0x480b2000, | |
4994 | .pa_end = 0x480b201f, | |
4995 | .flags = ADDR_TYPE_RT | |
4996 | }, | |
4997 | { } | |
4998 | }; | |
4999 | ||
5000 | /* l4_per -> hdq1w */ | |
5001 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
5002 | .master = &omap44xx_l4_per_hwmod, | |
5003 | .slave = &omap44xx_hdq1w_hwmod, | |
5004 | .clk = "l4_div_ck", | |
5005 | .addr = omap44xx_hdq1w_addrs, | |
5006 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5007 | }; | |
5008 | ||
844a3b63 PW |
5009 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
5010 | { | |
5011 | .pa_start = 0x4a058000, | |
5012 | .pa_end = 0x4a05bfff, | |
5013 | .flags = ADDR_TYPE_RT | |
5014 | }, | |
5015 | { } | |
5016 | }; | |
5017 | ||
5018 | /* l4_cfg -> hsi */ | |
5019 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
5020 | .master = &omap44xx_l4_cfg_hwmod, | |
5021 | .slave = &omap44xx_hsi_hwmod, | |
5022 | .clk = "l4_div_ck", | |
5023 | .addr = omap44xx_hsi_addrs, | |
5024 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5025 | }; | |
5026 | ||
5027 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
5028 | { | |
5029 | .pa_start = 0x48070000, | |
5030 | .pa_end = 0x480700ff, | |
5031 | .flags = ADDR_TYPE_RT | |
5032 | }, | |
5033 | { } | |
5034 | }; | |
5035 | ||
5036 | /* l4_per -> i2c1 */ | |
5037 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
5038 | .master = &omap44xx_l4_per_hwmod, | |
5039 | .slave = &omap44xx_i2c1_hwmod, | |
5040 | .clk = "l4_div_ck", | |
5041 | .addr = omap44xx_i2c1_addrs, | |
5042 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5043 | }; | |
5044 | ||
5045 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
5046 | { | |
5047 | .pa_start = 0x48072000, | |
5048 | .pa_end = 0x480720ff, | |
5049 | .flags = ADDR_TYPE_RT | |
5050 | }, | |
5051 | { } | |
5052 | }; | |
5053 | ||
5054 | /* l4_per -> i2c2 */ | |
5055 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
5056 | .master = &omap44xx_l4_per_hwmod, | |
5057 | .slave = &omap44xx_i2c2_hwmod, | |
5058 | .clk = "l4_div_ck", | |
5059 | .addr = omap44xx_i2c2_addrs, | |
5060 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5061 | }; | |
5062 | ||
5063 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
5064 | { | |
5065 | .pa_start = 0x48060000, | |
5066 | .pa_end = 0x480600ff, | |
5067 | .flags = ADDR_TYPE_RT | |
5068 | }, | |
5069 | { } | |
5070 | }; | |
5071 | ||
5072 | /* l4_per -> i2c3 */ | |
5073 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
5074 | .master = &omap44xx_l4_per_hwmod, | |
5075 | .slave = &omap44xx_i2c3_hwmod, | |
5076 | .clk = "l4_div_ck", | |
5077 | .addr = omap44xx_i2c3_addrs, | |
5078 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5079 | }; | |
5080 | ||
5081 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
5082 | { | |
5083 | .pa_start = 0x48350000, | |
5084 | .pa_end = 0x483500ff, | |
5085 | .flags = ADDR_TYPE_RT | |
5086 | }, | |
5087 | { } | |
5088 | }; | |
5089 | ||
5090 | /* l4_per -> i2c4 */ | |
5091 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
5092 | .master = &omap44xx_l4_per_hwmod, | |
5093 | .slave = &omap44xx_i2c4_hwmod, | |
5094 | .clk = "l4_div_ck", | |
5095 | .addr = omap44xx_i2c4_addrs, | |
5096 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5097 | }; | |
5098 | ||
5099 | /* l3_main_2 -> ipu */ | |
5100 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
5101 | .master = &omap44xx_l3_main_2_hwmod, | |
5102 | .slave = &omap44xx_ipu_hwmod, | |
5103 | .clk = "l3_div_ck", | |
5104 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5105 | }; | |
5106 | ||
5107 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
5108 | { | |
5109 | .pa_start = 0x52000000, | |
5110 | .pa_end = 0x520000ff, | |
5111 | .flags = ADDR_TYPE_RT | |
5112 | }, | |
5113 | { } | |
5114 | }; | |
5115 | ||
5116 | /* l3_main_2 -> iss */ | |
5117 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
5118 | .master = &omap44xx_l3_main_2_hwmod, | |
5119 | .slave = &omap44xx_iss_hwmod, | |
5120 | .clk = "l3_div_ck", | |
5121 | .addr = omap44xx_iss_addrs, | |
5122 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5123 | }; | |
5124 | ||
42b9e387 | 5125 | /* iva -> sl2if */ |
b360124e | 5126 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
42b9e387 PW |
5127 | .master = &omap44xx_iva_hwmod, |
5128 | .slave = &omap44xx_sl2if_hwmod, | |
5129 | .clk = "dpll_iva_m5x2_ck", | |
5130 | .user = OCP_USER_IVA, | |
5131 | }; | |
5132 | ||
844a3b63 PW |
5133 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
5134 | { | |
5135 | .pa_start = 0x5a000000, | |
5136 | .pa_end = 0x5a07ffff, | |
5137 | .flags = ADDR_TYPE_RT | |
5138 | }, | |
5139 | { } | |
5140 | }; | |
5141 | ||
5142 | /* l3_main_2 -> iva */ | |
5143 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
5144 | .master = &omap44xx_l3_main_2_hwmod, | |
5145 | .slave = &omap44xx_iva_hwmod, | |
5146 | .clk = "l3_div_ck", | |
5147 | .addr = omap44xx_iva_addrs, | |
5148 | .user = OCP_USER_MPU, | |
5149 | }; | |
5150 | ||
5151 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
5152 | { | |
5153 | .pa_start = 0x4a31c000, | |
5154 | .pa_end = 0x4a31c07f, | |
5155 | .flags = ADDR_TYPE_RT | |
5156 | }, | |
5157 | { } | |
5158 | }; | |
5159 | ||
5160 | /* l4_wkup -> kbd */ | |
5161 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
5162 | .master = &omap44xx_l4_wkup_hwmod, | |
5163 | .slave = &omap44xx_kbd_hwmod, | |
5164 | .clk = "l4_wkup_clk_mux_ck", | |
5165 | .addr = omap44xx_kbd_addrs, | |
5166 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5167 | }; | |
5168 | ||
5169 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
5170 | { | |
5171 | .pa_start = 0x4a0f4000, | |
5172 | .pa_end = 0x4a0f41ff, | |
5173 | .flags = ADDR_TYPE_RT | |
5174 | }, | |
5175 | { } | |
5176 | }; | |
5177 | ||
5178 | /* l4_cfg -> mailbox */ | |
5179 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
5180 | .master = &omap44xx_l4_cfg_hwmod, | |
5181 | .slave = &omap44xx_mailbox_hwmod, | |
5182 | .clk = "l4_div_ck", | |
5183 | .addr = omap44xx_mailbox_addrs, | |
5184 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5185 | }; | |
5186 | ||
896d4e98 BC |
5187 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
5188 | { | |
5189 | .pa_start = 0x40128000, | |
5190 | .pa_end = 0x401283ff, | |
5191 | .flags = ADDR_TYPE_RT | |
5192 | }, | |
5193 | { } | |
5194 | }; | |
5195 | ||
5196 | /* l4_abe -> mcasp */ | |
5197 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
5198 | .master = &omap44xx_l4_abe_hwmod, | |
5199 | .slave = &omap44xx_mcasp_hwmod, | |
5200 | .clk = "ocp_abe_iclk", | |
5201 | .addr = omap44xx_mcasp_addrs, | |
5202 | .user = OCP_USER_MPU, | |
5203 | }; | |
5204 | ||
5205 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
5206 | { | |
5207 | .pa_start = 0x49028000, | |
5208 | .pa_end = 0x490283ff, | |
5209 | .flags = ADDR_TYPE_RT | |
5210 | }, | |
5211 | { } | |
5212 | }; | |
5213 | ||
5214 | /* l4_abe -> mcasp (dma) */ | |
5215 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
5216 | .master = &omap44xx_l4_abe_hwmod, | |
5217 | .slave = &omap44xx_mcasp_hwmod, | |
5218 | .clk = "ocp_abe_iclk", | |
5219 | .addr = omap44xx_mcasp_dma_addrs, | |
5220 | .user = OCP_USER_SDMA, | |
5221 | }; | |
5222 | ||
844a3b63 PW |
5223 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
5224 | { | |
5225 | .name = "mpu", | |
5226 | .pa_start = 0x40122000, | |
5227 | .pa_end = 0x401220ff, | |
5228 | .flags = ADDR_TYPE_RT | |
5229 | }, | |
5230 | { } | |
5231 | }; | |
5232 | ||
5233 | /* l4_abe -> mcbsp1 */ | |
5234 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
5235 | .master = &omap44xx_l4_abe_hwmod, | |
5236 | .slave = &omap44xx_mcbsp1_hwmod, | |
5237 | .clk = "ocp_abe_iclk", | |
5238 | .addr = omap44xx_mcbsp1_addrs, | |
5239 | .user = OCP_USER_MPU, | |
5240 | }; | |
5241 | ||
5242 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
5243 | { | |
5244 | .name = "dma", | |
5245 | .pa_start = 0x49022000, | |
5246 | .pa_end = 0x490220ff, | |
5247 | .flags = ADDR_TYPE_RT | |
5248 | }, | |
5249 | { } | |
5250 | }; | |
5251 | ||
5252 | /* l4_abe -> mcbsp1 (dma) */ | |
5253 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
5254 | .master = &omap44xx_l4_abe_hwmod, | |
5255 | .slave = &omap44xx_mcbsp1_hwmod, | |
5256 | .clk = "ocp_abe_iclk", | |
5257 | .addr = omap44xx_mcbsp1_dma_addrs, | |
5258 | .user = OCP_USER_SDMA, | |
5259 | }; | |
5260 | ||
5261 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
5262 | { | |
5263 | .name = "mpu", | |
5264 | .pa_start = 0x40124000, | |
5265 | .pa_end = 0x401240ff, | |
5266 | .flags = ADDR_TYPE_RT | |
5267 | }, | |
5268 | { } | |
5269 | }; | |
5270 | ||
5271 | /* l4_abe -> mcbsp2 */ | |
5272 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
5273 | .master = &omap44xx_l4_abe_hwmod, | |
5274 | .slave = &omap44xx_mcbsp2_hwmod, | |
5275 | .clk = "ocp_abe_iclk", | |
5276 | .addr = omap44xx_mcbsp2_addrs, | |
5277 | .user = OCP_USER_MPU, | |
5278 | }; | |
5279 | ||
5280 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
5281 | { | |
5282 | .name = "dma", | |
5283 | .pa_start = 0x49024000, | |
5284 | .pa_end = 0x490240ff, | |
5285 | .flags = ADDR_TYPE_RT | |
5286 | }, | |
5287 | { } | |
5288 | }; | |
5289 | ||
5290 | /* l4_abe -> mcbsp2 (dma) */ | |
5291 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
5292 | .master = &omap44xx_l4_abe_hwmod, | |
5293 | .slave = &omap44xx_mcbsp2_hwmod, | |
5294 | .clk = "ocp_abe_iclk", | |
5295 | .addr = omap44xx_mcbsp2_dma_addrs, | |
5296 | .user = OCP_USER_SDMA, | |
5297 | }; | |
5298 | ||
5299 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
5300 | { | |
5301 | .name = "mpu", | |
5302 | .pa_start = 0x40126000, | |
5303 | .pa_end = 0x401260ff, | |
5304 | .flags = ADDR_TYPE_RT | |
5305 | }, | |
5306 | { } | |
5307 | }; | |
5308 | ||
5309 | /* l4_abe -> mcbsp3 */ | |
5310 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
5311 | .master = &omap44xx_l4_abe_hwmod, | |
5312 | .slave = &omap44xx_mcbsp3_hwmod, | |
5313 | .clk = "ocp_abe_iclk", | |
5314 | .addr = omap44xx_mcbsp3_addrs, | |
5315 | .user = OCP_USER_MPU, | |
5316 | }; | |
5317 | ||
5318 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
5319 | { | |
5320 | .name = "dma", | |
5321 | .pa_start = 0x49026000, | |
5322 | .pa_end = 0x490260ff, | |
5323 | .flags = ADDR_TYPE_RT | |
5324 | }, | |
5325 | { } | |
5326 | }; | |
5327 | ||
5328 | /* l4_abe -> mcbsp3 (dma) */ | |
5329 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
5330 | .master = &omap44xx_l4_abe_hwmod, | |
5331 | .slave = &omap44xx_mcbsp3_hwmod, | |
5332 | .clk = "ocp_abe_iclk", | |
5333 | .addr = omap44xx_mcbsp3_dma_addrs, | |
5334 | .user = OCP_USER_SDMA, | |
5335 | }; | |
5336 | ||
5337 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
5338 | { | |
5339 | .pa_start = 0x48096000, | |
5340 | .pa_end = 0x480960ff, | |
5341 | .flags = ADDR_TYPE_RT | |
5342 | }, | |
5343 | { } | |
5344 | }; | |
5345 | ||
5346 | /* l4_per -> mcbsp4 */ | |
5347 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
5348 | .master = &omap44xx_l4_per_hwmod, | |
5349 | .slave = &omap44xx_mcbsp4_hwmod, | |
5350 | .clk = "l4_div_ck", | |
5351 | .addr = omap44xx_mcbsp4_addrs, | |
5352 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5353 | }; | |
5354 | ||
5355 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
5356 | { | |
acd08ecd | 5357 | .name = "mpu", |
844a3b63 PW |
5358 | .pa_start = 0x40132000, |
5359 | .pa_end = 0x4013207f, | |
5360 | .flags = ADDR_TYPE_RT | |
5361 | }, | |
5362 | { } | |
5363 | }; | |
5364 | ||
5365 | /* l4_abe -> mcpdm */ | |
5366 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
5367 | .master = &omap44xx_l4_abe_hwmod, | |
5368 | .slave = &omap44xx_mcpdm_hwmod, | |
5369 | .clk = "ocp_abe_iclk", | |
5370 | .addr = omap44xx_mcpdm_addrs, | |
5371 | .user = OCP_USER_MPU, | |
5372 | }; | |
5373 | ||
5374 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
5375 | { | |
acd08ecd | 5376 | .name = "dma", |
844a3b63 PW |
5377 | .pa_start = 0x49032000, |
5378 | .pa_end = 0x4903207f, | |
5379 | .flags = ADDR_TYPE_RT | |
5380 | }, | |
5381 | { } | |
5382 | }; | |
5383 | ||
5384 | /* l4_abe -> mcpdm (dma) */ | |
5385 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
5386 | .master = &omap44xx_l4_abe_hwmod, | |
5387 | .slave = &omap44xx_mcpdm_hwmod, | |
5388 | .clk = "ocp_abe_iclk", | |
5389 | .addr = omap44xx_mcpdm_dma_addrs, | |
5390 | .user = OCP_USER_SDMA, | |
5391 | }; | |
5392 | ||
5393 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
5394 | { | |
5395 | .pa_start = 0x48098000, | |
5396 | .pa_end = 0x480981ff, | |
5397 | .flags = ADDR_TYPE_RT | |
5398 | }, | |
5399 | { } | |
5400 | }; | |
5401 | ||
5402 | /* l4_per -> mcspi1 */ | |
5403 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
5404 | .master = &omap44xx_l4_per_hwmod, | |
5405 | .slave = &omap44xx_mcspi1_hwmod, | |
5406 | .clk = "l4_div_ck", | |
5407 | .addr = omap44xx_mcspi1_addrs, | |
5408 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5409 | }; | |
5410 | ||
5411 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
5412 | { | |
5413 | .pa_start = 0x4809a000, | |
5414 | .pa_end = 0x4809a1ff, | |
5415 | .flags = ADDR_TYPE_RT | |
5416 | }, | |
5417 | { } | |
5418 | }; | |
5419 | ||
5420 | /* l4_per -> mcspi2 */ | |
5421 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
5422 | .master = &omap44xx_l4_per_hwmod, | |
5423 | .slave = &omap44xx_mcspi2_hwmod, | |
5424 | .clk = "l4_div_ck", | |
5425 | .addr = omap44xx_mcspi2_addrs, | |
5426 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5427 | }; | |
5428 | ||
5429 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
5430 | { | |
5431 | .pa_start = 0x480b8000, | |
5432 | .pa_end = 0x480b81ff, | |
5433 | .flags = ADDR_TYPE_RT | |
5434 | }, | |
5435 | { } | |
5436 | }; | |
5437 | ||
5438 | /* l4_per -> mcspi3 */ | |
5439 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
5440 | .master = &omap44xx_l4_per_hwmod, | |
5441 | .slave = &omap44xx_mcspi3_hwmod, | |
5442 | .clk = "l4_div_ck", | |
5443 | .addr = omap44xx_mcspi3_addrs, | |
5444 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5445 | }; | |
5446 | ||
5447 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
5448 | { | |
5449 | .pa_start = 0x480ba000, | |
5450 | .pa_end = 0x480ba1ff, | |
5451 | .flags = ADDR_TYPE_RT | |
5452 | }, | |
5453 | { } | |
5454 | }; | |
5455 | ||
5456 | /* l4_per -> mcspi4 */ | |
5457 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
5458 | .master = &omap44xx_l4_per_hwmod, | |
5459 | .slave = &omap44xx_mcspi4_hwmod, | |
5460 | .clk = "l4_div_ck", | |
5461 | .addr = omap44xx_mcspi4_addrs, | |
5462 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5463 | }; | |
5464 | ||
5465 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
5466 | { | |
5467 | .pa_start = 0x4809c000, | |
5468 | .pa_end = 0x4809c3ff, | |
5469 | .flags = ADDR_TYPE_RT | |
5470 | }, | |
5471 | { } | |
5472 | }; | |
5473 | ||
5474 | /* l4_per -> mmc1 */ | |
5475 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
5476 | .master = &omap44xx_l4_per_hwmod, | |
5477 | .slave = &omap44xx_mmc1_hwmod, | |
5478 | .clk = "l4_div_ck", | |
5479 | .addr = omap44xx_mmc1_addrs, | |
5480 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5481 | }; | |
5482 | ||
5483 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
5484 | { | |
5485 | .pa_start = 0x480b4000, | |
5486 | .pa_end = 0x480b43ff, | |
5487 | .flags = ADDR_TYPE_RT | |
5488 | }, | |
5489 | { } | |
5490 | }; | |
5491 | ||
5492 | /* l4_per -> mmc2 */ | |
5493 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
5494 | .master = &omap44xx_l4_per_hwmod, | |
5495 | .slave = &omap44xx_mmc2_hwmod, | |
5496 | .clk = "l4_div_ck", | |
5497 | .addr = omap44xx_mmc2_addrs, | |
5498 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5499 | }; | |
5500 | ||
5501 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
5502 | { | |
5503 | .pa_start = 0x480ad000, | |
5504 | .pa_end = 0x480ad3ff, | |
5505 | .flags = ADDR_TYPE_RT | |
5506 | }, | |
5507 | { } | |
5508 | }; | |
5509 | ||
5510 | /* l4_per -> mmc3 */ | |
5511 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
5512 | .master = &omap44xx_l4_per_hwmod, | |
5513 | .slave = &omap44xx_mmc3_hwmod, | |
5514 | .clk = "l4_div_ck", | |
5515 | .addr = omap44xx_mmc3_addrs, | |
5516 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5517 | }; | |
5518 | ||
5519 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
5520 | { | |
5521 | .pa_start = 0x480d1000, | |
5522 | .pa_end = 0x480d13ff, | |
5523 | .flags = ADDR_TYPE_RT | |
5524 | }, | |
5525 | { } | |
5526 | }; | |
5527 | ||
5528 | /* l4_per -> mmc4 */ | |
5529 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
5530 | .master = &omap44xx_l4_per_hwmod, | |
5531 | .slave = &omap44xx_mmc4_hwmod, | |
5532 | .clk = "l4_div_ck", | |
5533 | .addr = omap44xx_mmc4_addrs, | |
5534 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5535 | }; | |
5536 | ||
5537 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
5538 | { | |
5539 | .pa_start = 0x480d5000, | |
5540 | .pa_end = 0x480d53ff, | |
5541 | .flags = ADDR_TYPE_RT | |
5542 | }, | |
5543 | { } | |
5544 | }; | |
5545 | ||
5546 | /* l4_per -> mmc5 */ | |
5547 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
5548 | .master = &omap44xx_l4_per_hwmod, | |
5549 | .slave = &omap44xx_mmc5_hwmod, | |
5550 | .clk = "l4_div_ck", | |
5551 | .addr = omap44xx_mmc5_addrs, | |
5552 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5553 | }; | |
5554 | ||
e17f18c0 PW |
5555 | /* l3_main_2 -> ocmc_ram */ |
5556 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
5557 | .master = &omap44xx_l3_main_2_hwmod, | |
5558 | .slave = &omap44xx_ocmc_ram_hwmod, | |
5559 | .clk = "l3_div_ck", | |
5560 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5561 | }; | |
5562 | ||
33c976ec BC |
5563 | static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = { |
5564 | { | |
5565 | .pa_start = 0x4a0ad000, | |
5566 | .pa_end = 0x4a0ad01f, | |
5567 | .flags = ADDR_TYPE_RT | |
5568 | }, | |
5569 | { } | |
5570 | }; | |
5571 | ||
0c668875 BC |
5572 | /* l4_cfg -> ocp2scp_usb_phy */ |
5573 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
5574 | .master = &omap44xx_l4_cfg_hwmod, | |
5575 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
5576 | .clk = "l4_div_ck", | |
33c976ec | 5577 | .addr = omap44xx_ocp2scp_usb_phy_addrs, |
0c668875 BC |
5578 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5579 | }; | |
5580 | ||
794b480a PW |
5581 | static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { |
5582 | { | |
5583 | .pa_start = 0x48243000, | |
5584 | .pa_end = 0x48243fff, | |
5585 | .flags = ADDR_TYPE_RT | |
5586 | }, | |
5587 | { } | |
5588 | }; | |
5589 | ||
5590 | /* mpu_private -> prcm_mpu */ | |
5591 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
5592 | .master = &omap44xx_mpu_private_hwmod, | |
5593 | .slave = &omap44xx_prcm_mpu_hwmod, | |
5594 | .clk = "l3_div_ck", | |
5595 | .addr = omap44xx_prcm_mpu_addrs, | |
5596 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5597 | }; | |
5598 | ||
5599 | static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { | |
5600 | { | |
5601 | .pa_start = 0x4a004000, | |
5602 | .pa_end = 0x4a004fff, | |
5603 | .flags = ADDR_TYPE_RT | |
5604 | }, | |
5605 | { } | |
5606 | }; | |
5607 | ||
5608 | /* l4_wkup -> cm_core_aon */ | |
5609 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
5610 | .master = &omap44xx_l4_wkup_hwmod, | |
5611 | .slave = &omap44xx_cm_core_aon_hwmod, | |
5612 | .clk = "l4_wkup_clk_mux_ck", | |
5613 | .addr = omap44xx_cm_core_aon_addrs, | |
5614 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5615 | }; | |
5616 | ||
5617 | static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { | |
5618 | { | |
5619 | .pa_start = 0x4a008000, | |
5620 | .pa_end = 0x4a009fff, | |
5621 | .flags = ADDR_TYPE_RT | |
5622 | }, | |
5623 | { } | |
5624 | }; | |
5625 | ||
5626 | /* l4_cfg -> cm_core */ | |
5627 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
5628 | .master = &omap44xx_l4_cfg_hwmod, | |
5629 | .slave = &omap44xx_cm_core_hwmod, | |
5630 | .clk = "l4_div_ck", | |
5631 | .addr = omap44xx_cm_core_addrs, | |
5632 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5633 | }; | |
5634 | ||
5635 | static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { | |
5636 | { | |
5637 | .pa_start = 0x4a306000, | |
5638 | .pa_end = 0x4a307fff, | |
5639 | .flags = ADDR_TYPE_RT | |
5640 | }, | |
5641 | { } | |
5642 | }; | |
5643 | ||
5644 | /* l4_wkup -> prm */ | |
5645 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
5646 | .master = &omap44xx_l4_wkup_hwmod, | |
5647 | .slave = &omap44xx_prm_hwmod, | |
5648 | .clk = "l4_wkup_clk_mux_ck", | |
5649 | .addr = omap44xx_prm_addrs, | |
5650 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5651 | }; | |
5652 | ||
5653 | static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { | |
5654 | { | |
5655 | .pa_start = 0x4a30a000, | |
5656 | .pa_end = 0x4a30a7ff, | |
5657 | .flags = ADDR_TYPE_RT | |
5658 | }, | |
5659 | { } | |
5660 | }; | |
5661 | ||
5662 | /* l4_wkup -> scrm */ | |
5663 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
5664 | .master = &omap44xx_l4_wkup_hwmod, | |
5665 | .slave = &omap44xx_scrm_hwmod, | |
5666 | .clk = "l4_wkup_clk_mux_ck", | |
5667 | .addr = omap44xx_scrm_addrs, | |
5668 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5669 | }; | |
5670 | ||
42b9e387 | 5671 | /* l3_main_2 -> sl2if */ |
b360124e | 5672 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
5673 | .master = &omap44xx_l3_main_2_hwmod, |
5674 | .slave = &omap44xx_sl2if_hwmod, | |
5675 | .clk = "l3_div_ck", | |
5676 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5677 | }; | |
5678 | ||
1e3b5e59 BC |
5679 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
5680 | { | |
5681 | .pa_start = 0x4012c000, | |
5682 | .pa_end = 0x4012c3ff, | |
5683 | .flags = ADDR_TYPE_RT | |
5684 | }, | |
5685 | { } | |
5686 | }; | |
5687 | ||
5688 | /* l4_abe -> slimbus1 */ | |
5689 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
5690 | .master = &omap44xx_l4_abe_hwmod, | |
5691 | .slave = &omap44xx_slimbus1_hwmod, | |
5692 | .clk = "ocp_abe_iclk", | |
5693 | .addr = omap44xx_slimbus1_addrs, | |
5694 | .user = OCP_USER_MPU, | |
5695 | }; | |
5696 | ||
5697 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
5698 | { | |
5699 | .pa_start = 0x4902c000, | |
5700 | .pa_end = 0x4902c3ff, | |
5701 | .flags = ADDR_TYPE_RT | |
5702 | }, | |
5703 | { } | |
5704 | }; | |
5705 | ||
5706 | /* l4_abe -> slimbus1 (dma) */ | |
5707 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
5708 | .master = &omap44xx_l4_abe_hwmod, | |
5709 | .slave = &omap44xx_slimbus1_hwmod, | |
5710 | .clk = "ocp_abe_iclk", | |
5711 | .addr = omap44xx_slimbus1_dma_addrs, | |
5712 | .user = OCP_USER_SDMA, | |
5713 | }; | |
5714 | ||
5715 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
5716 | { | |
5717 | .pa_start = 0x48076000, | |
5718 | .pa_end = 0x480763ff, | |
5719 | .flags = ADDR_TYPE_RT | |
5720 | }, | |
5721 | { } | |
5722 | }; | |
5723 | ||
5724 | /* l4_per -> slimbus2 */ | |
5725 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
5726 | .master = &omap44xx_l4_per_hwmod, | |
5727 | .slave = &omap44xx_slimbus2_hwmod, | |
5728 | .clk = "l4_div_ck", | |
5729 | .addr = omap44xx_slimbus2_addrs, | |
5730 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5731 | }; | |
5732 | ||
844a3b63 PW |
5733 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
5734 | { | |
5735 | .pa_start = 0x4a0dd000, | |
5736 | .pa_end = 0x4a0dd03f, | |
5737 | .flags = ADDR_TYPE_RT | |
5738 | }, | |
5739 | { } | |
5740 | }; | |
5741 | ||
5742 | /* l4_cfg -> smartreflex_core */ | |
5743 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
5744 | .master = &omap44xx_l4_cfg_hwmod, | |
5745 | .slave = &omap44xx_smartreflex_core_hwmod, | |
5746 | .clk = "l4_div_ck", | |
5747 | .addr = omap44xx_smartreflex_core_addrs, | |
5748 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5749 | }; | |
5750 | ||
5751 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
5752 | { | |
5753 | .pa_start = 0x4a0db000, | |
5754 | .pa_end = 0x4a0db03f, | |
5755 | .flags = ADDR_TYPE_RT | |
5756 | }, | |
5757 | { } | |
5758 | }; | |
5759 | ||
5760 | /* l4_cfg -> smartreflex_iva */ | |
5761 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
5762 | .master = &omap44xx_l4_cfg_hwmod, | |
5763 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
5764 | .clk = "l4_div_ck", | |
5765 | .addr = omap44xx_smartreflex_iva_addrs, | |
5766 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5767 | }; | |
5768 | ||
5769 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
5770 | { | |
5771 | .pa_start = 0x4a0d9000, | |
5772 | .pa_end = 0x4a0d903f, | |
5773 | .flags = ADDR_TYPE_RT | |
5774 | }, | |
5775 | { } | |
5776 | }; | |
5777 | ||
5778 | /* l4_cfg -> smartreflex_mpu */ | |
5779 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
5780 | .master = &omap44xx_l4_cfg_hwmod, | |
5781 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
5782 | .clk = "l4_div_ck", | |
5783 | .addr = omap44xx_smartreflex_mpu_addrs, | |
5784 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5785 | }; | |
5786 | ||
5787 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
5788 | { | |
5789 | .pa_start = 0x4a0f6000, | |
5790 | .pa_end = 0x4a0f6fff, | |
5791 | .flags = ADDR_TYPE_RT | |
5792 | }, | |
5793 | { } | |
5794 | }; | |
5795 | ||
5796 | /* l4_cfg -> spinlock */ | |
5797 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
5798 | .master = &omap44xx_l4_cfg_hwmod, | |
5799 | .slave = &omap44xx_spinlock_hwmod, | |
5800 | .clk = "l4_div_ck", | |
5801 | .addr = omap44xx_spinlock_addrs, | |
5802 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5803 | }; | |
5804 | ||
5805 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
5806 | { | |
5807 | .pa_start = 0x4a318000, | |
5808 | .pa_end = 0x4a31807f, | |
5809 | .flags = ADDR_TYPE_RT | |
5810 | }, | |
5811 | { } | |
5812 | }; | |
5813 | ||
5814 | /* l4_wkup -> timer1 */ | |
5815 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
5816 | .master = &omap44xx_l4_wkup_hwmod, | |
5817 | .slave = &omap44xx_timer1_hwmod, | |
5818 | .clk = "l4_wkup_clk_mux_ck", | |
5819 | .addr = omap44xx_timer1_addrs, | |
5820 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5821 | }; | |
5822 | ||
5823 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
5824 | { | |
5825 | .pa_start = 0x48032000, | |
5826 | .pa_end = 0x4803207f, | |
5827 | .flags = ADDR_TYPE_RT | |
5828 | }, | |
5829 | { } | |
5830 | }; | |
5831 | ||
5832 | /* l4_per -> timer2 */ | |
5833 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
5834 | .master = &omap44xx_l4_per_hwmod, | |
5835 | .slave = &omap44xx_timer2_hwmod, | |
5836 | .clk = "l4_div_ck", | |
5837 | .addr = omap44xx_timer2_addrs, | |
5838 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5839 | }; | |
5840 | ||
5841 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
5842 | { | |
5843 | .pa_start = 0x48034000, | |
5844 | .pa_end = 0x4803407f, | |
5845 | .flags = ADDR_TYPE_RT | |
5846 | }, | |
5847 | { } | |
5848 | }; | |
5849 | ||
5850 | /* l4_per -> timer3 */ | |
5851 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
5852 | .master = &omap44xx_l4_per_hwmod, | |
5853 | .slave = &omap44xx_timer3_hwmod, | |
5854 | .clk = "l4_div_ck", | |
5855 | .addr = omap44xx_timer3_addrs, | |
5856 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5857 | }; | |
5858 | ||
5859 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
5860 | { | |
5861 | .pa_start = 0x48036000, | |
5862 | .pa_end = 0x4803607f, | |
5863 | .flags = ADDR_TYPE_RT | |
5864 | }, | |
5865 | { } | |
5866 | }; | |
5867 | ||
5868 | /* l4_per -> timer4 */ | |
5869 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
5870 | .master = &omap44xx_l4_per_hwmod, | |
5871 | .slave = &omap44xx_timer4_hwmod, | |
5872 | .clk = "l4_div_ck", | |
5873 | .addr = omap44xx_timer4_addrs, | |
5874 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5875 | }; | |
5876 | ||
5877 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
5878 | { | |
5879 | .pa_start = 0x40138000, | |
5880 | .pa_end = 0x4013807f, | |
5881 | .flags = ADDR_TYPE_RT | |
5882 | }, | |
5883 | { } | |
5884 | }; | |
5885 | ||
5886 | /* l4_abe -> timer5 */ | |
5887 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
5888 | .master = &omap44xx_l4_abe_hwmod, | |
5889 | .slave = &omap44xx_timer5_hwmod, | |
5890 | .clk = "ocp_abe_iclk", | |
5891 | .addr = omap44xx_timer5_addrs, | |
5892 | .user = OCP_USER_MPU, | |
5893 | }; | |
5894 | ||
5895 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
5896 | { | |
5897 | .pa_start = 0x49038000, | |
5898 | .pa_end = 0x4903807f, | |
5899 | .flags = ADDR_TYPE_RT | |
5900 | }, | |
5901 | { } | |
5902 | }; | |
5903 | ||
5904 | /* l4_abe -> timer5 (dma) */ | |
5905 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
5906 | .master = &omap44xx_l4_abe_hwmod, | |
5907 | .slave = &omap44xx_timer5_hwmod, | |
5908 | .clk = "ocp_abe_iclk", | |
5909 | .addr = omap44xx_timer5_dma_addrs, | |
5910 | .user = OCP_USER_SDMA, | |
5911 | }; | |
5912 | ||
5913 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
5914 | { | |
5915 | .pa_start = 0x4013a000, | |
5916 | .pa_end = 0x4013a07f, | |
5917 | .flags = ADDR_TYPE_RT | |
5918 | }, | |
5919 | { } | |
5920 | }; | |
5921 | ||
5922 | /* l4_abe -> timer6 */ | |
5923 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
5924 | .master = &omap44xx_l4_abe_hwmod, | |
5925 | .slave = &omap44xx_timer6_hwmod, | |
5926 | .clk = "ocp_abe_iclk", | |
5927 | .addr = omap44xx_timer6_addrs, | |
5928 | .user = OCP_USER_MPU, | |
5929 | }; | |
5930 | ||
5931 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
5932 | { | |
5933 | .pa_start = 0x4903a000, | |
5934 | .pa_end = 0x4903a07f, | |
5935 | .flags = ADDR_TYPE_RT | |
5936 | }, | |
5937 | { } | |
5938 | }; | |
5939 | ||
5940 | /* l4_abe -> timer6 (dma) */ | |
5941 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
5942 | .master = &omap44xx_l4_abe_hwmod, | |
5943 | .slave = &omap44xx_timer6_hwmod, | |
5944 | .clk = "ocp_abe_iclk", | |
5945 | .addr = omap44xx_timer6_dma_addrs, | |
5946 | .user = OCP_USER_SDMA, | |
5947 | }; | |
5948 | ||
5949 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
5950 | { | |
5951 | .pa_start = 0x4013c000, | |
5952 | .pa_end = 0x4013c07f, | |
5953 | .flags = ADDR_TYPE_RT | |
5954 | }, | |
5955 | { } | |
5956 | }; | |
5957 | ||
5958 | /* l4_abe -> timer7 */ | |
5959 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
5960 | .master = &omap44xx_l4_abe_hwmod, | |
5961 | .slave = &omap44xx_timer7_hwmod, | |
5962 | .clk = "ocp_abe_iclk", | |
5963 | .addr = omap44xx_timer7_addrs, | |
5964 | .user = OCP_USER_MPU, | |
5965 | }; | |
5966 | ||
5967 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
5968 | { | |
5969 | .pa_start = 0x4903c000, | |
5970 | .pa_end = 0x4903c07f, | |
5971 | .flags = ADDR_TYPE_RT | |
5972 | }, | |
5973 | { } | |
5974 | }; | |
5975 | ||
5976 | /* l4_abe -> timer7 (dma) */ | |
5977 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
5978 | .master = &omap44xx_l4_abe_hwmod, | |
5979 | .slave = &omap44xx_timer7_hwmod, | |
5980 | .clk = "ocp_abe_iclk", | |
5981 | .addr = omap44xx_timer7_dma_addrs, | |
5982 | .user = OCP_USER_SDMA, | |
5983 | }; | |
5984 | ||
5985 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
5986 | { | |
5987 | .pa_start = 0x4013e000, | |
5988 | .pa_end = 0x4013e07f, | |
5989 | .flags = ADDR_TYPE_RT | |
5990 | }, | |
5991 | { } | |
5992 | }; | |
5993 | ||
5994 | /* l4_abe -> timer8 */ | |
5995 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
5996 | .master = &omap44xx_l4_abe_hwmod, | |
5997 | .slave = &omap44xx_timer8_hwmod, | |
5998 | .clk = "ocp_abe_iclk", | |
5999 | .addr = omap44xx_timer8_addrs, | |
6000 | .user = OCP_USER_MPU, | |
6001 | }; | |
6002 | ||
6003 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
6004 | { | |
6005 | .pa_start = 0x4903e000, | |
6006 | .pa_end = 0x4903e07f, | |
6007 | .flags = ADDR_TYPE_RT | |
6008 | }, | |
6009 | { } | |
6010 | }; | |
6011 | ||
6012 | /* l4_abe -> timer8 (dma) */ | |
6013 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
6014 | .master = &omap44xx_l4_abe_hwmod, | |
6015 | .slave = &omap44xx_timer8_hwmod, | |
6016 | .clk = "ocp_abe_iclk", | |
6017 | .addr = omap44xx_timer8_dma_addrs, | |
6018 | .user = OCP_USER_SDMA, | |
6019 | }; | |
6020 | ||
6021 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
6022 | { | |
6023 | .pa_start = 0x4803e000, | |
6024 | .pa_end = 0x4803e07f, | |
6025 | .flags = ADDR_TYPE_RT | |
6026 | }, | |
6027 | { } | |
6028 | }; | |
6029 | ||
6030 | /* l4_per -> timer9 */ | |
6031 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
6032 | .master = &omap44xx_l4_per_hwmod, | |
6033 | .slave = &omap44xx_timer9_hwmod, | |
6034 | .clk = "l4_div_ck", | |
6035 | .addr = omap44xx_timer9_addrs, | |
6036 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6037 | }; | |
6038 | ||
6039 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
6040 | { | |
6041 | .pa_start = 0x48086000, | |
6042 | .pa_end = 0x4808607f, | |
6043 | .flags = ADDR_TYPE_RT | |
6044 | }, | |
6045 | { } | |
6046 | }; | |
6047 | ||
6048 | /* l4_per -> timer10 */ | |
6049 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
6050 | .master = &omap44xx_l4_per_hwmod, | |
6051 | .slave = &omap44xx_timer10_hwmod, | |
6052 | .clk = "l4_div_ck", | |
6053 | .addr = omap44xx_timer10_addrs, | |
6054 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6055 | }; | |
6056 | ||
6057 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
6058 | { | |
6059 | .pa_start = 0x48088000, | |
6060 | .pa_end = 0x4808807f, | |
6061 | .flags = ADDR_TYPE_RT | |
6062 | }, | |
6063 | { } | |
6064 | }; | |
6065 | ||
6066 | /* l4_per -> timer11 */ | |
6067 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
6068 | .master = &omap44xx_l4_per_hwmod, | |
6069 | .slave = &omap44xx_timer11_hwmod, | |
6070 | .clk = "l4_div_ck", | |
6071 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
6072 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
6073 | }; | |
6074 | ||
844a3b63 PW |
6075 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
6076 | { | |
6077 | .pa_start = 0x4806a000, | |
6078 | .pa_end = 0x4806a0ff, | |
6079 | .flags = ADDR_TYPE_RT | |
af88fa9a | 6080 | }, |
844a3b63 PW |
6081 | { } |
6082 | }; | |
af88fa9a | 6083 | |
844a3b63 PW |
6084 | /* l4_per -> uart1 */ |
6085 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
6086 | .master = &omap44xx_l4_per_hwmod, | |
6087 | .slave = &omap44xx_uart1_hwmod, | |
6088 | .clk = "l4_div_ck", | |
6089 | .addr = omap44xx_uart1_addrs, | |
6090 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6091 | }; | |
af88fa9a | 6092 | |
844a3b63 PW |
6093 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
6094 | { | |
6095 | .pa_start = 0x4806c000, | |
6096 | .pa_end = 0x4806c0ff, | |
6097 | .flags = ADDR_TYPE_RT | |
6098 | }, | |
6099 | { } | |
6100 | }; | |
af88fa9a | 6101 | |
844a3b63 PW |
6102 | /* l4_per -> uart2 */ |
6103 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
6104 | .master = &omap44xx_l4_per_hwmod, | |
6105 | .slave = &omap44xx_uart2_hwmod, | |
6106 | .clk = "l4_div_ck", | |
6107 | .addr = omap44xx_uart2_addrs, | |
6108 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6109 | }; | |
af88fa9a | 6110 | |
844a3b63 PW |
6111 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
6112 | { | |
6113 | .pa_start = 0x48020000, | |
6114 | .pa_end = 0x480200ff, | |
6115 | .flags = ADDR_TYPE_RT | |
6116 | }, | |
6117 | { } | |
af88fa9a BC |
6118 | }; |
6119 | ||
844a3b63 PW |
6120 | /* l4_per -> uart3 */ |
6121 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
6122 | .master = &omap44xx_l4_per_hwmod, | |
6123 | .slave = &omap44xx_uart3_hwmod, | |
6124 | .clk = "l4_div_ck", | |
6125 | .addr = omap44xx_uart3_addrs, | |
6126 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
6127 | }; |
6128 | ||
844a3b63 PW |
6129 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
6130 | { | |
6131 | .pa_start = 0x4806e000, | |
6132 | .pa_end = 0x4806e0ff, | |
6133 | .flags = ADDR_TYPE_RT | |
6134 | }, | |
6135 | { } | |
af88fa9a BC |
6136 | }; |
6137 | ||
844a3b63 PW |
6138 | /* l4_per -> uart4 */ |
6139 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
6140 | .master = &omap44xx_l4_per_hwmod, | |
6141 | .slave = &omap44xx_uart4_hwmod, | |
6142 | .clk = "l4_div_ck", | |
6143 | .addr = omap44xx_uart4_addrs, | |
6144 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6145 | }; | |
6146 | ||
0c668875 BC |
6147 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { |
6148 | { | |
6149 | .pa_start = 0x4a0a9000, | |
6150 | .pa_end = 0x4a0a93ff, | |
6151 | .flags = ADDR_TYPE_RT | |
6152 | }, | |
6153 | { } | |
6154 | }; | |
6155 | ||
6156 | /* l4_cfg -> usb_host_fs */ | |
b0a70cc8 | 6157 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
6158 | .master = &omap44xx_l4_cfg_hwmod, |
6159 | .slave = &omap44xx_usb_host_fs_hwmod, | |
6160 | .clk = "l4_div_ck", | |
6161 | .addr = omap44xx_usb_host_fs_addrs, | |
6162 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6163 | }; | |
6164 | ||
844a3b63 PW |
6165 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
6166 | { | |
6167 | .name = "uhh", | |
6168 | .pa_start = 0x4a064000, | |
6169 | .pa_end = 0x4a0647ff, | |
6170 | .flags = ADDR_TYPE_RT | |
6171 | }, | |
6172 | { | |
6173 | .name = "ohci", | |
6174 | .pa_start = 0x4a064800, | |
6175 | .pa_end = 0x4a064bff, | |
6176 | }, | |
6177 | { | |
6178 | .name = "ehci", | |
6179 | .pa_start = 0x4a064c00, | |
6180 | .pa_end = 0x4a064fff, | |
6181 | }, | |
6182 | {} | |
6183 | }; | |
6184 | ||
6185 | /* l4_cfg -> usb_host_hs */ | |
6186 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
6187 | .master = &omap44xx_l4_cfg_hwmod, | |
6188 | .slave = &omap44xx_usb_host_hs_hwmod, | |
6189 | .clk = "l4_div_ck", | |
6190 | .addr = omap44xx_usb_host_hs_addrs, | |
6191 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6192 | }; | |
6193 | ||
6194 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
6195 | { | |
6196 | .pa_start = 0x4a0ab000, | |
33c976ec | 6197 | .pa_end = 0x4a0ab7ff, |
844a3b63 PW |
6198 | .flags = ADDR_TYPE_RT |
6199 | }, | |
6200 | { } | |
6201 | }; | |
6202 | ||
6203 | /* l4_cfg -> usb_otg_hs */ | |
6204 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
6205 | .master = &omap44xx_l4_cfg_hwmod, | |
6206 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
6207 | .clk = "l4_div_ck", | |
6208 | .addr = omap44xx_usb_otg_hs_addrs, | |
6209 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
6210 | }; |
6211 | ||
6212 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
6213 | { | |
6214 | .name = "tll", | |
6215 | .pa_start = 0x4a062000, | |
6216 | .pa_end = 0x4a063fff, | |
6217 | .flags = ADDR_TYPE_RT | |
6218 | }, | |
6219 | {} | |
6220 | }; | |
6221 | ||
844a3b63 | 6222 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
6223 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
6224 | .master = &omap44xx_l4_cfg_hwmod, | |
6225 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
6226 | .clk = "l4_div_ck", | |
6227 | .addr = omap44xx_usb_tll_hs_addrs, | |
6228 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6229 | }; | |
6230 | ||
844a3b63 PW |
6231 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
6232 | { | |
6233 | .pa_start = 0x4a314000, | |
6234 | .pa_end = 0x4a31407f, | |
6235 | .flags = ADDR_TYPE_RT | |
af88fa9a | 6236 | }, |
844a3b63 PW |
6237 | { } |
6238 | }; | |
6239 | ||
6240 | /* l4_wkup -> wd_timer2 */ | |
6241 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
6242 | .master = &omap44xx_l4_wkup_hwmod, | |
6243 | .slave = &omap44xx_wd_timer2_hwmod, | |
6244 | .clk = "l4_wkup_clk_mux_ck", | |
6245 | .addr = omap44xx_wd_timer2_addrs, | |
6246 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6247 | }; | |
6248 | ||
6249 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
6250 | { | |
6251 | .pa_start = 0x40130000, | |
6252 | .pa_end = 0x4013007f, | |
6253 | .flags = ADDR_TYPE_RT | |
6254 | }, | |
6255 | { } | |
6256 | }; | |
6257 | ||
6258 | /* l4_abe -> wd_timer3 */ | |
6259 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
6260 | .master = &omap44xx_l4_abe_hwmod, | |
6261 | .slave = &omap44xx_wd_timer3_hwmod, | |
6262 | .clk = "ocp_abe_iclk", | |
6263 | .addr = omap44xx_wd_timer3_addrs, | |
6264 | .user = OCP_USER_MPU, | |
6265 | }; | |
6266 | ||
6267 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
6268 | { | |
6269 | .pa_start = 0x49030000, | |
6270 | .pa_end = 0x4903007f, | |
6271 | .flags = ADDR_TYPE_RT | |
6272 | }, | |
6273 | { } | |
6274 | }; | |
6275 | ||
6276 | /* l4_abe -> wd_timer3 (dma) */ | |
6277 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
6278 | .master = &omap44xx_l4_abe_hwmod, | |
6279 | .slave = &omap44xx_wd_timer3_hwmod, | |
6280 | .clk = "ocp_abe_iclk", | |
6281 | .addr = omap44xx_wd_timer3_dma_addrs, | |
6282 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
6283 | }; |
6284 | ||
0a78c5c5 | 6285 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
42b9e387 PW |
6286 | &omap44xx_c2c__c2c_target_fw, |
6287 | &omap44xx_l4_cfg__c2c_target_fw, | |
0a78c5c5 PW |
6288 | &omap44xx_l3_main_1__dmm, |
6289 | &omap44xx_mpu__dmm, | |
42b9e387 | 6290 | &omap44xx_c2c__emif_fw, |
0a78c5c5 PW |
6291 | &omap44xx_dmm__emif_fw, |
6292 | &omap44xx_l4_cfg__emif_fw, | |
6293 | &omap44xx_iva__l3_instr, | |
6294 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 6295 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
6296 | &omap44xx_dsp__l3_main_1, |
6297 | &omap44xx_dss__l3_main_1, | |
6298 | &omap44xx_l3_main_2__l3_main_1, | |
6299 | &omap44xx_l4_cfg__l3_main_1, | |
6300 | &omap44xx_mmc1__l3_main_1, | |
6301 | &omap44xx_mmc2__l3_main_1, | |
6302 | &omap44xx_mpu__l3_main_1, | |
42b9e387 | 6303 | &omap44xx_c2c_target_fw__l3_main_2, |
96566043 | 6304 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 6305 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 6306 | &omap44xx_fdif__l3_main_2, |
9def390e | 6307 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
6308 | &omap44xx_hsi__l3_main_2, |
6309 | &omap44xx_ipu__l3_main_2, | |
6310 | &omap44xx_iss__l3_main_2, | |
6311 | &omap44xx_iva__l3_main_2, | |
6312 | &omap44xx_l3_main_1__l3_main_2, | |
6313 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 6314 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
6315 | &omap44xx_usb_host_hs__l3_main_2, |
6316 | &omap44xx_usb_otg_hs__l3_main_2, | |
6317 | &omap44xx_l3_main_1__l3_main_3, | |
6318 | &omap44xx_l3_main_2__l3_main_3, | |
6319 | &omap44xx_l4_cfg__l3_main_3, | |
5cebb23c | 6320 | &omap44xx_aess__l4_abe, |
0a78c5c5 PW |
6321 | &omap44xx_dsp__l4_abe, |
6322 | &omap44xx_l3_main_1__l4_abe, | |
6323 | &omap44xx_mpu__l4_abe, | |
6324 | &omap44xx_l3_main_1__l4_cfg, | |
6325 | &omap44xx_l3_main_2__l4_per, | |
6326 | &omap44xx_l4_cfg__l4_wkup, | |
6327 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 6328 | &omap44xx_l4_cfg__ocp_wp_noc, |
5cebb23c SG |
6329 | &omap44xx_l4_abe__aess, |
6330 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 6331 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 6332 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
6333 | &omap44xx_l4_cfg__ctrl_module_core, |
6334 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
6335 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
6336 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 6337 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
6338 | &omap44xx_l4_cfg__dma_system, |
6339 | &omap44xx_l4_abe__dmic, | |
6340 | &omap44xx_l4_abe__dmic_dma, | |
6341 | &omap44xx_dsp__iva, | |
b360124e | 6342 | /* &omap44xx_dsp__sl2if, */ |
0a78c5c5 PW |
6343 | &omap44xx_l4_cfg__dsp, |
6344 | &omap44xx_l3_main_2__dss, | |
6345 | &omap44xx_l4_per__dss, | |
6346 | &omap44xx_l3_main_2__dss_dispc, | |
6347 | &omap44xx_l4_per__dss_dispc, | |
6348 | &omap44xx_l3_main_2__dss_dsi1, | |
6349 | &omap44xx_l4_per__dss_dsi1, | |
6350 | &omap44xx_l3_main_2__dss_dsi2, | |
6351 | &omap44xx_l4_per__dss_dsi2, | |
6352 | &omap44xx_l3_main_2__dss_hdmi, | |
6353 | &omap44xx_l4_per__dss_hdmi, | |
6354 | &omap44xx_l3_main_2__dss_rfbi, | |
6355 | &omap44xx_l4_per__dss_rfbi, | |
6356 | &omap44xx_l3_main_2__dss_venc, | |
6357 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 6358 | &omap44xx_l4_per__elm, |
bf30f950 PW |
6359 | &omap44xx_emif_fw__emif1, |
6360 | &omap44xx_emif_fw__emif2, | |
b050f688 | 6361 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
6362 | &omap44xx_l4_wkup__gpio1, |
6363 | &omap44xx_l4_per__gpio2, | |
6364 | &omap44xx_l4_per__gpio3, | |
6365 | &omap44xx_l4_per__gpio4, | |
6366 | &omap44xx_l4_per__gpio5, | |
6367 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 6368 | &omap44xx_l3_main_2__gpmc, |
9def390e | 6369 | &omap44xx_l3_main_2__gpu, |
a091c08e | 6370 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
6371 | &omap44xx_l4_cfg__hsi, |
6372 | &omap44xx_l4_per__i2c1, | |
6373 | &omap44xx_l4_per__i2c2, | |
6374 | &omap44xx_l4_per__i2c3, | |
6375 | &omap44xx_l4_per__i2c4, | |
6376 | &omap44xx_l3_main_2__ipu, | |
6377 | &omap44xx_l3_main_2__iss, | |
b360124e | 6378 | /* &omap44xx_iva__sl2if, */ |
0a78c5c5 PW |
6379 | &omap44xx_l3_main_2__iva, |
6380 | &omap44xx_l4_wkup__kbd, | |
6381 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
6382 | &omap44xx_l4_abe__mcasp, |
6383 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 PW |
6384 | &omap44xx_l4_abe__mcbsp1, |
6385 | &omap44xx_l4_abe__mcbsp1_dma, | |
6386 | &omap44xx_l4_abe__mcbsp2, | |
6387 | &omap44xx_l4_abe__mcbsp2_dma, | |
6388 | &omap44xx_l4_abe__mcbsp3, | |
6389 | &omap44xx_l4_abe__mcbsp3_dma, | |
6390 | &omap44xx_l4_per__mcbsp4, | |
6391 | &omap44xx_l4_abe__mcpdm, | |
6392 | &omap44xx_l4_abe__mcpdm_dma, | |
6393 | &omap44xx_l4_per__mcspi1, | |
6394 | &omap44xx_l4_per__mcspi2, | |
6395 | &omap44xx_l4_per__mcspi3, | |
6396 | &omap44xx_l4_per__mcspi4, | |
6397 | &omap44xx_l4_per__mmc1, | |
6398 | &omap44xx_l4_per__mmc2, | |
6399 | &omap44xx_l4_per__mmc3, | |
6400 | &omap44xx_l4_per__mmc4, | |
6401 | &omap44xx_l4_per__mmc5, | |
230844db ORL |
6402 | &omap44xx_l3_main_2__mmu_ipu, |
6403 | &omap44xx_l4_cfg__mmu_dsp, | |
e17f18c0 | 6404 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 6405 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
6406 | &omap44xx_mpu_private__prcm_mpu, |
6407 | &omap44xx_l4_wkup__cm_core_aon, | |
6408 | &omap44xx_l4_cfg__cm_core, | |
6409 | &omap44xx_l4_wkup__prm, | |
6410 | &omap44xx_l4_wkup__scrm, | |
b360124e | 6411 | /* &omap44xx_l3_main_2__sl2if, */ |
1e3b5e59 BC |
6412 | &omap44xx_l4_abe__slimbus1, |
6413 | &omap44xx_l4_abe__slimbus1_dma, | |
6414 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
6415 | &omap44xx_l4_cfg__smartreflex_core, |
6416 | &omap44xx_l4_cfg__smartreflex_iva, | |
6417 | &omap44xx_l4_cfg__smartreflex_mpu, | |
6418 | &omap44xx_l4_cfg__spinlock, | |
6419 | &omap44xx_l4_wkup__timer1, | |
6420 | &omap44xx_l4_per__timer2, | |
6421 | &omap44xx_l4_per__timer3, | |
6422 | &omap44xx_l4_per__timer4, | |
6423 | &omap44xx_l4_abe__timer5, | |
6424 | &omap44xx_l4_abe__timer5_dma, | |
6425 | &omap44xx_l4_abe__timer6, | |
6426 | &omap44xx_l4_abe__timer6_dma, | |
6427 | &omap44xx_l4_abe__timer7, | |
6428 | &omap44xx_l4_abe__timer7_dma, | |
6429 | &omap44xx_l4_abe__timer8, | |
6430 | &omap44xx_l4_abe__timer8_dma, | |
6431 | &omap44xx_l4_per__timer9, | |
6432 | &omap44xx_l4_per__timer10, | |
6433 | &omap44xx_l4_per__timer11, | |
6434 | &omap44xx_l4_per__uart1, | |
6435 | &omap44xx_l4_per__uart2, | |
6436 | &omap44xx_l4_per__uart3, | |
6437 | &omap44xx_l4_per__uart4, | |
b0a70cc8 | 6438 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
6439 | &omap44xx_l4_cfg__usb_host_hs, |
6440 | &omap44xx_l4_cfg__usb_otg_hs, | |
6441 | &omap44xx_l4_cfg__usb_tll_hs, | |
6442 | &omap44xx_l4_wkup__wd_timer2, | |
6443 | &omap44xx_l4_abe__wd_timer3, | |
6444 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
6445 | NULL, |
6446 | }; | |
6447 | ||
6448 | int __init omap44xx_hwmod_init(void) | |
6449 | { | |
9ebfd285 | 6450 | omap_hwmod_init(); |
0a78c5c5 | 6451 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
6452 | } |
6453 |