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OMAP4: hwmod data: Add timer
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
CommitLineData
55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
9780a9cf 25#include <plat/gpio.h>
531ce0d5 26#include <plat/dma.h>
55d2cb08
BC		 27
28#include "omap_hwmod_common_data.h"
29
d198b514
PW		 30#include "cm1_44xx.h"
31#include "cm2_44xx.h"
32#include "prm44xx.h"
55d2cb08 33#include "prm-regbits-44xx.h"
ff2516fb 34#include "wd_timer.h"
55d2cb08
BC		 35
36/* Base offset for all OMAP4 interrupts external to MPUSS */
37#define OMAP44XX_IRQ_GIC_START 32
38
39/* Base offset for all OMAP4 dma requests */
40#define OMAP44XX_DMA_REQ_START 1
41
42/* Backward references (IPs with Bus Master capability) */
531ce0d5 43static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 44static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 45static struct omap_hwmod omap44xx_dsp_hwmod;
55d2cb08 46static struct omap_hwmod omap44xx_emif_fw_hwmod;
8f25bdc5 47static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 48static struct omap_hwmod omap44xx_l3_instr_hwmod;
49static struct omap_hwmod omap44xx_l3_main_1_hwmod;
50static struct omap_hwmod omap44xx_l3_main_2_hwmod;
51static struct omap_hwmod omap44xx_l3_main_3_hwmod;
52static struct omap_hwmod omap44xx_l4_abe_hwmod;
53static struct omap_hwmod omap44xx_l4_cfg_hwmod;
54static struct omap_hwmod omap44xx_l4_per_hwmod;
55static struct omap_hwmod omap44xx_l4_wkup_hwmod;
56static struct omap_hwmod omap44xx_mpu_hwmod;
57static struct omap_hwmod omap44xx_mpu_private_hwmod;
58
59/*
60 * Interconnects omap_hwmod structures
61 * hwmods that compose the global OMAP interconnect
62 */
63
64/*
65 * 'dmm' class
66 * instance(s): dmm
67 */
68static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 69 .name = "dmm",
55d2cb08
BC		 70};
71
72/* dmm interface data */
73/* l3_main_1 -> dmm */
74static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
75 .master = &omap44xx_l3_main_1_hwmod,
76 .slave = &omap44xx_dmm_hwmod,
77 .clk = "l3_div_ck",
659fa822
BC		 78 .user = OCP_USER_SDMA,
79};
80
81static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
82 {
83 .pa_start = 0x4e000000,
84 .pa_end = 0x4e0007ff,
85 .flags = ADDR_TYPE_RT
86 },
55d2cb08
BC		 87};
88
89/* mpu -> dmm */
90static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
91 .master = &omap44xx_mpu_hwmod,
92 .slave = &omap44xx_dmm_hwmod,
93 .clk = "l3_div_ck",
659fa822
BC		 94 .addr = omap44xx_dmm_addrs,
95 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
96 .user = OCP_USER_MPU,
55d2cb08
BC		 97};
98
99/* dmm slave ports */
100static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
101 &omap44xx_l3_main_1__dmm,
102 &omap44xx_mpu__dmm,
103};
104
105static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
106 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
107};
108
109static struct omap_hwmod omap44xx_dmm_hwmod = {
110 .name = "dmm",
111 .class = &omap44xx_dmm_hwmod_class,
112 .slaves = omap44xx_dmm_slaves,
113 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
114 .mpu_irqs = omap44xx_dmm_irqs,
115 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
117};
118
119/*
120 * 'emif_fw' class
121 * instance(s): emif_fw
122 */
123static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 124 .name = "emif_fw",
55d2cb08
BC		 125};
126
127/* emif_fw interface data */
128/* dmm -> emif_fw */
129static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
130 .master = &omap44xx_dmm_hwmod,
131 .slave = &omap44xx_emif_fw_hwmod,
132 .clk = "l3_div_ck",
133 .user = OCP_USER_MPU | OCP_USER_SDMA,
134};
135
659fa822
BC		 136static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
137 {
138 .pa_start = 0x4a20c000,
139 .pa_end = 0x4a20c0ff,
140 .flags = ADDR_TYPE_RT
141 },
142};
143
55d2cb08
BC		 144/* l4_cfg -> emif_fw */
145static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
146 .master = &omap44xx_l4_cfg_hwmod,
147 .slave = &omap44xx_emif_fw_hwmod,
148 .clk = "l4_div_ck",
659fa822
BC		 149 .addr = omap44xx_emif_fw_addrs,
150 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
151 .user = OCP_USER_MPU,
55d2cb08
BC		 152};
153
154/* emif_fw slave ports */
155static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
156 &omap44xx_dmm__emif_fw,
157 &omap44xx_l4_cfg__emif_fw,
158};
159
160static struct omap_hwmod omap44xx_emif_fw_hwmod = {
161 .name = "emif_fw",
162 .class = &omap44xx_emif_fw_hwmod_class,
163 .slaves = omap44xx_emif_fw_slaves,
164 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
166};
167
168/*
169 * 'l3' class
170 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
171 */
172static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 173 .name = "l3",
55d2cb08
BC		 174};
175
176/* l3_instr interface data */
8f25bdc5
BC		 177/* iva -> l3_instr */
178static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
179 .master = &omap44xx_iva_hwmod,
180 .slave = &omap44xx_l3_instr_hwmod,
181 .clk = "l3_div_ck",
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183};
184
55d2cb08
BC		 185/* l3_main_3 -> l3_instr */
186static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
187 .master = &omap44xx_l3_main_3_hwmod,
188 .slave = &omap44xx_l3_instr_hwmod,
189 .clk = "l3_div_ck",
190 .user = OCP_USER_MPU | OCP_USER_SDMA,
191};
192
193/* l3_instr slave ports */
194static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 195 &omap44xx_iva__l3_instr,
55d2cb08
BC		 196 &omap44xx_l3_main_3__l3_instr,
197};
198
199static struct omap_hwmod omap44xx_l3_instr_hwmod = {
200 .name = "l3_instr",
201 .class = &omap44xx_l3_hwmod_class,
202 .slaves = omap44xx_l3_instr_slaves,
203 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
204 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
205};
206
3b54baad 207/* l3_main_1 interface data */
8f25bdc5
BC		 208/* dsp -> l3_main_1 */
209static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
210 .master = &omap44xx_dsp_hwmod,
211 .slave = &omap44xx_l3_main_1_hwmod,
212 .clk = "l3_div_ck",
213 .user = OCP_USER_MPU | OCP_USER_SDMA,
214};
215
55d2cb08
BC		 216/* l3_main_2 -> l3_main_1 */
217static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
218 .master = &omap44xx_l3_main_2_hwmod,
219 .slave = &omap44xx_l3_main_1_hwmod,
220 .clk = "l3_div_ck",
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
222};
223
224/* l4_cfg -> l3_main_1 */
225static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
226 .master = &omap44xx_l4_cfg_hwmod,
227 .slave = &omap44xx_l3_main_1_hwmod,
228 .clk = "l4_div_ck",
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230};
231
232/* mpu -> l3_main_1 */
233static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
234 .master = &omap44xx_mpu_hwmod,
235 .slave = &omap44xx_l3_main_1_hwmod,
236 .clk = "l3_div_ck",
237 .user = OCP_USER_MPU | OCP_USER_SDMA,
238};
239
240/* l3_main_1 slave ports */
241static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 242 &omap44xx_dsp__l3_main_1,
55d2cb08
BC		 243 &omap44xx_l3_main_2__l3_main_1,
244 &omap44xx_l4_cfg__l3_main_1,
245 &omap44xx_mpu__l3_main_1,
246};
247
248static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
249 .name = "l3_main_1",
250 .class = &omap44xx_l3_hwmod_class,
251 .slaves = omap44xx_l3_main_1_slaves,
252 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
254};
255
256/* l3_main_2 interface data */
d7cf5f33
BC		 257/* dma_system -> l3_main_2 */
258static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
259 .master = &omap44xx_dma_system_hwmod,
260 .slave = &omap44xx_l3_main_2_hwmod,
261 .clk = "l3_div_ck",
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263};
264
8f25bdc5
BC		 265/* iva -> l3_main_2 */
266static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
267 .master = &omap44xx_iva_hwmod,
268 .slave = &omap44xx_l3_main_2_hwmod,
269 .clk = "l3_div_ck",
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
271};
272
55d2cb08
BC		 273/* l3_main_1 -> l3_main_2 */
274static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
275 .master = &omap44xx_l3_main_1_hwmod,
276 .slave = &omap44xx_l3_main_2_hwmod,
277 .clk = "l3_div_ck",
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
279};
280
281/* l4_cfg -> l3_main_2 */
282static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
283 .master = &omap44xx_l4_cfg_hwmod,
284 .slave = &omap44xx_l3_main_2_hwmod,
285 .clk = "l4_div_ck",
286 .user = OCP_USER_MPU | OCP_USER_SDMA,
287};
288
289/* l3_main_2 slave ports */
290static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 291 &omap44xx_dma_system__l3_main_2,
8f25bdc5 292 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 293 &omap44xx_l3_main_1__l3_main_2,
294 &omap44xx_l4_cfg__l3_main_2,
295};
296
297static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
298 .name = "l3_main_2",
299 .class = &omap44xx_l3_hwmod_class,
300 .slaves = omap44xx_l3_main_2_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
303};
304
305/* l3_main_3 interface data */
306/* l3_main_1 -> l3_main_3 */
307static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
308 .master = &omap44xx_l3_main_1_hwmod,
309 .slave = &omap44xx_l3_main_3_hwmod,
310 .clk = "l3_div_ck",
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
312};
313
314/* l3_main_2 -> l3_main_3 */
315static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
316 .master = &omap44xx_l3_main_2_hwmod,
317 .slave = &omap44xx_l3_main_3_hwmod,
318 .clk = "l3_div_ck",
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
320};
321
322/* l4_cfg -> l3_main_3 */
323static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
324 .master = &omap44xx_l4_cfg_hwmod,
325 .slave = &omap44xx_l3_main_3_hwmod,
326 .clk = "l4_div_ck",
327 .user = OCP_USER_MPU | OCP_USER_SDMA,
328};
329
330/* l3_main_3 slave ports */
331static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
332 &omap44xx_l3_main_1__l3_main_3,
333 &omap44xx_l3_main_2__l3_main_3,
334 &omap44xx_l4_cfg__l3_main_3,
335};
336
337static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
338 .name = "l3_main_3",
339 .class = &omap44xx_l3_hwmod_class,
340 .slaves = omap44xx_l3_main_3_slaves,
341 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
342 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
343};
344
345/*
346 * 'l4' class
347 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
348 */
349static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 350 .name = "l4",
55d2cb08
BC		 351};
352
353/* l4_abe interface data */
8f25bdc5
BC		 354/* dsp -> l4_abe */
355static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
356 .master = &omap44xx_dsp_hwmod,
357 .slave = &omap44xx_l4_abe_hwmod,
358 .clk = "ocp_abe_iclk",
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
360};
361
55d2cb08
BC		 362/* l3_main_1 -> l4_abe */
363static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
364 .master = &omap44xx_l3_main_1_hwmod,
365 .slave = &omap44xx_l4_abe_hwmod,
366 .clk = "l3_div_ck",
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
368};
369
370/* mpu -> l4_abe */
371static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
372 .master = &omap44xx_mpu_hwmod,
373 .slave = &omap44xx_l4_abe_hwmod,
374 .clk = "ocp_abe_iclk",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
376};
377
378/* l4_abe slave ports */
379static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
8f25bdc5 380 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 381 &omap44xx_l3_main_1__l4_abe,
382 &omap44xx_mpu__l4_abe,
383};
384
385static struct omap_hwmod omap44xx_l4_abe_hwmod = {
386 .name = "l4_abe",
387 .class = &omap44xx_l4_hwmod_class,
388 .slaves = omap44xx_l4_abe_slaves,
389 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
390 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
391};
392
393/* l4_cfg interface data */
394/* l3_main_1 -> l4_cfg */
395static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
396 .master = &omap44xx_l3_main_1_hwmod,
397 .slave = &omap44xx_l4_cfg_hwmod,
398 .clk = "l3_div_ck",
399 .user = OCP_USER_MPU | OCP_USER_SDMA,
400};
401
402/* l4_cfg slave ports */
403static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
404 &omap44xx_l3_main_1__l4_cfg,
405};
406
407static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
408 .name = "l4_cfg",
409 .class = &omap44xx_l4_hwmod_class,
410 .slaves = omap44xx_l4_cfg_slaves,
411 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
413};
414
415/* l4_per interface data */
416/* l3_main_2 -> l4_per */
417static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
418 .master = &omap44xx_l3_main_2_hwmod,
419 .slave = &omap44xx_l4_per_hwmod,
420 .clk = "l3_div_ck",
421 .user = OCP_USER_MPU | OCP_USER_SDMA,
422};
423
424/* l4_per slave ports */
425static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
426 &omap44xx_l3_main_2__l4_per,
427};
428
429static struct omap_hwmod omap44xx_l4_per_hwmod = {
430 .name = "l4_per",
431 .class = &omap44xx_l4_hwmod_class,
432 .slaves = omap44xx_l4_per_slaves,
433 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
435};
436
437/* l4_wkup interface data */
438/* l4_cfg -> l4_wkup */
439static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
440 .master = &omap44xx_l4_cfg_hwmod,
441 .slave = &omap44xx_l4_wkup_hwmod,
442 .clk = "l4_div_ck",
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
444};
445
446/* l4_wkup slave ports */
447static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
448 &omap44xx_l4_cfg__l4_wkup,
449};
450
451static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
452 .name = "l4_wkup",
453 .class = &omap44xx_l4_hwmod_class,
454 .slaves = omap44xx_l4_wkup_slaves,
455 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
457};
458
f776471f 459/*
3b54baad
BC		 460 * 'mpu_bus' class
461 * instance(s): mpu_private
f776471f 462 */
3b54baad 463static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 464 .name = "mpu_bus",
3b54baad 465};
f776471f 466
3b54baad
BC		 467/* mpu_private interface data */
468/* mpu -> mpu_private */
469static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
470 .master = &omap44xx_mpu_hwmod,
471 .slave = &omap44xx_mpu_private_hwmod,
472 .clk = "l3_div_ck",
473 .user = OCP_USER_MPU | OCP_USER_SDMA,
474};
475
476/* mpu_private slave ports */
477static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
478 &omap44xx_mpu__mpu_private,
479};
480
481static struct omap_hwmod omap44xx_mpu_private_hwmod = {
482 .name = "mpu_private",
483 .class = &omap44xx_mpu_bus_hwmod_class,
484 .slaves = omap44xx_mpu_private_slaves,
485 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
486 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
487};
488
489/*
490 * Modules omap_hwmod structures
491 *
492 * The following IPs are excluded for the moment because:
493 * - They do not need an explicit SW control using omap_hwmod API.
494 * - They still need to be validated with the driver
495 * properly adapted to omap_hwmod / omap_device
496 *
497 * aess
498 * bandgap
499 * c2c
500 * c2c_target_fw
501 * cm_core
502 * cm_core_aon
503 * counter_32k
504 * ctrl_module_core
505 * ctrl_module_pad_core
506 * ctrl_module_pad_wkup
507 * ctrl_module_wkup
508 * debugss
3b54baad 509 * dmic
3b54baad
BC		 510 * dss
511 * dss_dispc
512 * dss_dsi1
513 * dss_dsi2
514 * dss_hdmi
515 * dss_rfbi
516 * dss_venc
517 * efuse_ctrl_cust
518 * efuse_ctrl_std
519 * elm
520 * emif1
521 * emif2
522 * fdif
523 * gpmc
524 * gpu
525 * hdq1w
526 * hsi
527 * ipu
528 * iss
3b54baad
BC		 529 * kbd
530 * mailbox
531 * mcasp
532 * mcbsp1
533 * mcbsp2
534 * mcbsp3
535 * mcbsp4
536 * mcpdm
3b54baad
BC		 537 * mmc1
538 * mmc2
539 * mmc3
540 * mmc4
541 * mmc5
542 * mpu_c0
543 * mpu_c1
544 * ocmc_ram
545 * ocp2scp_usb_phy
546 * ocp_wp_noc
547 * prcm
548 * prcm_mpu
549 * prm
550 * scrm
551 * sl2if
552 * slimbus1
553 * slimbus2
3b54baad
BC		 554 * usb_host_fs
555 * usb_host_hs
556 * usb_otg_hs
557 * usb_phy_cm
558 * usb_tll_hs
559 * usim
560 */
561
d7cf5f33
BC		 562/*
563 * 'dma' class
564 * dma controller for data exchange between memory to memory (i.e. internal or
565 * external memory) and gp peripherals to memory or memory to gp peripherals
566 */
567
568static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
569 .rev_offs = 0x0000,
570 .sysc_offs = 0x002c,
571 .syss_offs = 0x0028,
572 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
573 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
574 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
575 SYSS_HAS_RESET_STATUS),
576 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
577 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
578 .sysc_fields = &omap_hwmod_sysc_type1,
579};
580
581static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
582 .name = "dma",
583 .sysc = &omap44xx_dma_sysc,
584};
585
586/* dma dev_attr */
587static struct omap_dma_dev_attr dma_dev_attr = {
588 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
589 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
590 .lch_count = 32,
591};
592
593/* dma_system */
594static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
595 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
596 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
597 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
598 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
599};
600
601/* dma_system master ports */
602static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
603 &omap44xx_dma_system__l3_main_2,
604};
605
606static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
607 {
608 .pa_start = 0x4a056000,
609 .pa_end = 0x4a0560ff,
610 .flags = ADDR_TYPE_RT
611 },
612};
613
614/* l4_cfg -> dma_system */
615static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
616 .master = &omap44xx_l4_cfg_hwmod,
617 .slave = &omap44xx_dma_system_hwmod,
618 .clk = "l4_div_ck",
619 .addr = omap44xx_dma_system_addrs,
620 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
621 .user = OCP_USER_MPU | OCP_USER_SDMA,
622};
623
624/* dma_system slave ports */
625static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
626 &omap44xx_l4_cfg__dma_system,
627};
628
629static struct omap_hwmod omap44xx_dma_system_hwmod = {
630 .name = "dma_system",
631 .class = &omap44xx_dma_hwmod_class,
632 .mpu_irqs = omap44xx_dma_system_irqs,
633 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
634 .main_clk = "l3_div_ck",
635 .prcm = {
636 .omap4 = {
637 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
638 },
639 },
640 .dev_attr = &dma_dev_attr,
641 .slaves = omap44xx_dma_system_slaves,
642 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
643 .masters = omap44xx_dma_system_masters,
644 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
645 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
646};
647
8f25bdc5
BC		 648/*
649 * 'dsp' class
650 * dsp sub-system
651 */
652
653static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 654 .name = "dsp",
8f25bdc5
BC		 655};
656
657/* dsp */
658static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
659 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
660};
661
662static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
663 { .name = "mmu_cache", .rst_shift = 1 },
664};
665
666static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
667 { .name = "dsp", .rst_shift = 0 },
668};
669
670/* dsp -> iva */
671static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
672 .master = &omap44xx_dsp_hwmod,
673 .slave = &omap44xx_iva_hwmod,
674 .clk = "dpll_iva_m5x2_ck",
675};
676
677/* dsp master ports */
678static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
679 &omap44xx_dsp__l3_main_1,
680 &omap44xx_dsp__l4_abe,
681 &omap44xx_dsp__iva,
682};
683
684/* l4_cfg -> dsp */
685static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
686 .master = &omap44xx_l4_cfg_hwmod,
687 .slave = &omap44xx_dsp_hwmod,
688 .clk = "l4_div_ck",
689 .user = OCP_USER_MPU | OCP_USER_SDMA,
690};
691
692/* dsp slave ports */
693static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
694 &omap44xx_l4_cfg__dsp,
695};
696
697/* Pseudo hwmod for reset control purpose only */
698static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
699 .name = "dsp_c0",
700 .class = &omap44xx_dsp_hwmod_class,
701 .flags = HWMOD_INIT_NO_RESET,
702 .rst_lines = omap44xx_dsp_c0_resets,
703 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
704 .prcm = {
705 .omap4 = {
706 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
707 },
708 },
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
710};
711
712static struct omap_hwmod omap44xx_dsp_hwmod = {
713 .name = "dsp",
714 .class = &omap44xx_dsp_hwmod_class,
715 .mpu_irqs = omap44xx_dsp_irqs,
716 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
717 .rst_lines = omap44xx_dsp_resets,
718 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
719 .main_clk = "dsp_fck",
720 .prcm = {
721 .omap4 = {
722 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
723 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
724 },
725 },
726 .slaves = omap44xx_dsp_slaves,
727 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
728 .masters = omap44xx_dsp_masters,
729 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
730 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
731};
732
3b54baad
BC		 733/*
734 * 'gpio' class
735 * general purpose io module
736 */
737
738static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
739 .rev_offs = 0x0000,
f776471f 740 .sysc_offs = 0x0010,
3b54baad 741 .syss_offs = 0x0114,
0cfe8751
BC		 742 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
743 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
744 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 745 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
746 SIDLE_SMART_WKUP),
f776471f
BC		 747 .sysc_fields = &omap_hwmod_sysc_type1,
748};
749
3b54baad 750static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 751 .name = "gpio",
752 .sysc = &omap44xx_gpio_sysc,
753 .rev = 2,
f776471f
BC		 754};
755
3b54baad
BC		 756/* gpio dev_attr */
757static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 758 .bank_width = 32,
759 .dbck_flag = true,
f776471f
BC		 760};
761
3b54baad
BC		 762/* gpio1 */
763static struct omap_hwmod omap44xx_gpio1_hwmod;
764static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
765 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 766};
767
3b54baad 768static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 769 {
3b54baad
BC		 770 .pa_start = 0x4a310000,
771 .pa_end = 0x4a3101ff,
f776471f
BC		 772 .flags = ADDR_TYPE_RT
773 },
774};
775
3b54baad
BC		 776/* l4_wkup -> gpio1 */
777static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
778 .master = &omap44xx_l4_wkup_hwmod,
779 .slave = &omap44xx_gpio1_hwmod,
b399bca8 780 .clk = "l4_wkup_clk_mux_ck",
3b54baad
BC		 781 .addr = omap44xx_gpio1_addrs,
782 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
f776471f
BC		 783 .user = OCP_USER_MPU | OCP_USER_SDMA,
784};
785
3b54baad
BC		 786/* gpio1 slave ports */
787static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
788 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 789};
790
3b54baad 791static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 792 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 793};
794
795static struct omap_hwmod omap44xx_gpio1_hwmod = {
796 .name = "gpio1",
797 .class = &omap44xx_gpio_hwmod_class,
798 .mpu_irqs = omap44xx_gpio1_irqs,
799 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
800 .main_clk = "gpio1_ick",
f776471f
BC		 801 .prcm = {
802 .omap4 = {
3b54baad 803 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
f776471f
BC		 804 },
805 },
3b54baad
BC		 806 .opt_clks = gpio1_opt_clks,
807 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
808 .dev_attr = &gpio_dev_attr,
809 .slaves = omap44xx_gpio1_slaves,
810 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 811 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
812};
813
3b54baad
BC		 814/* gpio2 */
815static struct omap_hwmod omap44xx_gpio2_hwmod;
816static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
817 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 818};
819
3b54baad 820static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 821 {
3b54baad
BC		 822 .pa_start = 0x48055000,
823 .pa_end = 0x480551ff,
f776471f
BC		 824 .flags = ADDR_TYPE_RT
825 },
826};
827
3b54baad
BC		 828/* l4_per -> gpio2 */
829static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 830 .master = &omap44xx_l4_per_hwmod,
3b54baad 831 .slave = &omap44xx_gpio2_hwmod,
b399bca8 832 .clk = "l4_div_ck",
3b54baad
BC		 833 .addr = omap44xx_gpio2_addrs,
834 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
f776471f
BC		 835 .user = OCP_USER_MPU | OCP_USER_SDMA,
836};
837
3b54baad
BC		 838/* gpio2 slave ports */
839static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
840 &omap44xx_l4_per__gpio2,
f776471f
BC		 841};
842
3b54baad 843static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 844 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 845};
846
847static struct omap_hwmod omap44xx_gpio2_hwmod = {
848 .name = "gpio2",
849 .class = &omap44xx_gpio_hwmod_class,
b399bca8 850 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 851 .mpu_irqs = omap44xx_gpio2_irqs,
852 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
853 .main_clk = "gpio2_ick",
f776471f
BC		 854 .prcm = {
855 .omap4 = {
3b54baad 856 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
f776471f
BC		 857 },
858 },
3b54baad
BC		 859 .opt_clks = gpio2_opt_clks,
860 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
861 .dev_attr = &gpio_dev_attr,
862 .slaves = omap44xx_gpio2_slaves,
863 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 864 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
865};
866
3b54baad
BC		 867/* gpio3 */
868static struct omap_hwmod omap44xx_gpio3_hwmod;
869static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
870 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 871};
872
3b54baad 873static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 874 {
3b54baad
BC		 875 .pa_start = 0x48057000,
876 .pa_end = 0x480571ff,
f776471f
BC		 877 .flags = ADDR_TYPE_RT
878 },
879};
880
3b54baad
BC		 881/* l4_per -> gpio3 */
882static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 883 .master = &omap44xx_l4_per_hwmod,
3b54baad 884 .slave = &omap44xx_gpio3_hwmod,
b399bca8 885 .clk = "l4_div_ck",
3b54baad
BC		 886 .addr = omap44xx_gpio3_addrs,
887 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
f776471f
BC		 888 .user = OCP_USER_MPU | OCP_USER_SDMA,
889};
890
3b54baad
BC		 891/* gpio3 slave ports */
892static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
893 &omap44xx_l4_per__gpio3,
f776471f
BC		 894};
895
3b54baad 896static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 897 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 898};
899
900static struct omap_hwmod omap44xx_gpio3_hwmod = {
901 .name = "gpio3",
902 .class = &omap44xx_gpio_hwmod_class,
b399bca8 903 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 904 .mpu_irqs = omap44xx_gpio3_irqs,
905 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
906 .main_clk = "gpio3_ick",
f776471f
BC		 907 .prcm = {
908 .omap4 = {
3b54baad 909 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
f776471f
BC		 910 },
911 },
3b54baad
BC		 912 .opt_clks = gpio3_opt_clks,
913 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
914 .dev_attr = &gpio_dev_attr,
915 .slaves = omap44xx_gpio3_slaves,
916 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 917 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
918};
919
3b54baad
BC		 920/* gpio4 */
921static struct omap_hwmod omap44xx_gpio4_hwmod;
922static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
923 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 924};
925
3b54baad 926static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 927 {
3b54baad
BC		 928 .pa_start = 0x48059000,
929 .pa_end = 0x480591ff,
f776471f
BC		 930 .flags = ADDR_TYPE_RT
931 },
932};
933
3b54baad
BC		 934/* l4_per -> gpio4 */
935static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 936 .master = &omap44xx_l4_per_hwmod,
3b54baad 937 .slave = &omap44xx_gpio4_hwmod,
b399bca8 938 .clk = "l4_div_ck",
3b54baad
BC		 939 .addr = omap44xx_gpio4_addrs,
940 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
f776471f
BC		 941 .user = OCP_USER_MPU | OCP_USER_SDMA,
942};
943
3b54baad
BC		 944/* gpio4 slave ports */
945static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
946 &omap44xx_l4_per__gpio4,
f776471f
BC		 947};
948
3b54baad 949static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 950 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 951};
952
953static struct omap_hwmod omap44xx_gpio4_hwmod = {
954 .name = "gpio4",
955 .class = &omap44xx_gpio_hwmod_class,
b399bca8 956 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 957 .mpu_irqs = omap44xx_gpio4_irqs,
958 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
959 .main_clk = "gpio4_ick",
f776471f
BC		 960 .prcm = {
961 .omap4 = {
3b54baad 962 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
f776471f
BC		 963 },
964 },
3b54baad
BC		 965 .opt_clks = gpio4_opt_clks,
966 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
967 .dev_attr = &gpio_dev_attr,
968 .slaves = omap44xx_gpio4_slaves,
969 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 970 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
971};
972
3b54baad
BC		 973/* gpio5 */
974static struct omap_hwmod omap44xx_gpio5_hwmod;
975static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
976 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
55d2cb08
BC		 977};
978
3b54baad
BC		 979static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
980 {
981 .pa_start = 0x4805b000,
982 .pa_end = 0x4805b1ff,
983 .flags = ADDR_TYPE_RT
984 },
55d2cb08
BC		 985};
986
3b54baad
BC		 987/* l4_per -> gpio5 */
988static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
989 .master = &omap44xx_l4_per_hwmod,
990 .slave = &omap44xx_gpio5_hwmod,
b399bca8 991 .clk = "l4_div_ck",
3b54baad
BC		 992 .addr = omap44xx_gpio5_addrs,
993 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
994 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 995};
996
3b54baad
BC		 997/* gpio5 slave ports */
998static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
999 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 1000};
1001
3b54baad 1002static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 1003 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 1004};
1005
3b54baad
BC		 1006static struct omap_hwmod omap44xx_gpio5_hwmod = {
1007 .name = "gpio5",
1008 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1009 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1010 .mpu_irqs = omap44xx_gpio5_irqs,
1011 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1012 .main_clk = "gpio5_ick",
55d2cb08
BC		 1013 .prcm = {
1014 .omap4 = {
3b54baad 1015 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
55d2cb08
BC		 1016 },
1017 },
3b54baad
BC		 1018 .opt_clks = gpio5_opt_clks,
1019 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1020 .dev_attr = &gpio_dev_attr,
1021 .slaves = omap44xx_gpio5_slaves,
1022 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 1023 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1024};
1025
3b54baad
BC		 1026/* gpio6 */
1027static struct omap_hwmod omap44xx_gpio6_hwmod;
1028static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1029 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 1030};
1031
3b54baad 1032static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 1033 {
3b54baad
BC		 1034 .pa_start = 0x4805d000,
1035 .pa_end = 0x4805d1ff,
92b18d1c
BC		 1036 .flags = ADDR_TYPE_RT
1037 },
1038};
1039
3b54baad
BC		 1040/* l4_per -> gpio6 */
1041static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1042 .master = &omap44xx_l4_per_hwmod,
1043 .slave = &omap44xx_gpio6_hwmod,
b399bca8 1044 .clk = "l4_div_ck",
3b54baad
BC		 1045 .addr = omap44xx_gpio6_addrs,
1046 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
1047 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 1048};
1049
3b54baad
BC		 1050/* gpio6 slave ports */
1051static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1052 &omap44xx_l4_per__gpio6,
db12ba53
BC		 1053};
1054
3b54baad 1055static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 1056 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 1057};
1058
3b54baad
BC		 1059static struct omap_hwmod omap44xx_gpio6_hwmod = {
1060 .name = "gpio6",
1061 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1062 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1063 .mpu_irqs = omap44xx_gpio6_irqs,
1064 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
1065 .main_clk = "gpio6_ick",
1066 .prcm = {
1067 .omap4 = {
1068 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1069 },
db12ba53 1070 },
3b54baad
BC		 1071 .opt_clks = gpio6_opt_clks,
1072 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1073 .dev_attr = &gpio_dev_attr,
1074 .slaves = omap44xx_gpio6_slaves,
1075 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1076 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 1077};
1078
3b54baad
BC		 1079/*
1080 * 'i2c' class
1081 * multimaster high-speed i2c controller
1082 */
db12ba53 1083
3b54baad
BC		 1084static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1085 .sysc_offs = 0x0010,
1086 .syss_offs = 0x0090,
1087 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1088 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 1089 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1090 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091 SIDLE_SMART_WKUP),
3b54baad 1092 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 1093};
1094
3b54baad 1095static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 1096 .name = "i2c",
1097 .sysc = &omap44xx_i2c_sysc,
db12ba53
BC		 1098};
1099
3b54baad
BC		 1100/* i2c1 */
1101static struct omap_hwmod omap44xx_i2c1_hwmod;
1102static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1103 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 1104};
1105
3b54baad
BC		 1106static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1107 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1108 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 1109};
1110
3b54baad 1111static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 1112 {
3b54baad
BC		 1113 .pa_start = 0x48070000,
1114 .pa_end = 0x480700ff,
db12ba53
BC		 1115 .flags = ADDR_TYPE_RT
1116 },
1117};
1118
3b54baad
BC		 1119/* l4_per -> i2c1 */
1120static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1121 .master = &omap44xx_l4_per_hwmod,
1122 .slave = &omap44xx_i2c1_hwmod,
1123 .clk = "l4_div_ck",
1124 .addr = omap44xx_i2c1_addrs,
1125 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
92b18d1c
BC		 1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1127};
1128
3b54baad
BC		 1129/* i2c1 slave ports */
1130static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1131 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 1132};
1133
3b54baad
BC		 1134static struct omap_hwmod omap44xx_i2c1_hwmod = {
1135 .name = "i2c1",
1136 .class = &omap44xx_i2c_hwmod_class,
1137 .flags = HWMOD_INIT_NO_RESET,
1138 .mpu_irqs = omap44xx_i2c1_irqs,
1139 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
1140 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1141 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1142 .main_clk = "i2c1_fck",
92b18d1c
BC		 1143 .prcm = {
1144 .omap4 = {
3b54baad 1145 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
92b18d1c
BC		 1146 },
1147 },
3b54baad
BC		 1148 .slaves = omap44xx_i2c1_slaves,
1149 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
92b18d1c
BC		 1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1151};
1152
3b54baad
BC		 1153/* i2c2 */
1154static struct omap_hwmod omap44xx_i2c2_hwmod;
1155static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1156 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 1157};
1158
3b54baad
BC		 1159static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1160 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1161 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1162};
1163
1164static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 1165 {
3b54baad
BC		 1166 .pa_start = 0x48072000,
1167 .pa_end = 0x480720ff,
92b18d1c
BC		 1168 .flags = ADDR_TYPE_RT
1169 },
1170};
1171
3b54baad
BC		 1172/* l4_per -> i2c2 */
1173static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 1174 .master = &omap44xx_l4_per_hwmod,
3b54baad 1175 .slave = &omap44xx_i2c2_hwmod,
db12ba53 1176 .clk = "l4_div_ck",
3b54baad
BC		 1177 .addr = omap44xx_i2c2_addrs,
1178 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
db12ba53
BC		 1179 .user = OCP_USER_MPU | OCP_USER_SDMA,
1180};
1181
3b54baad
BC		 1182/* i2c2 slave ports */
1183static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1184 &omap44xx_l4_per__i2c2,
db12ba53
BC		 1185};
1186
3b54baad
BC		 1187static struct omap_hwmod omap44xx_i2c2_hwmod = {
1188 .name = "i2c2",
1189 .class = &omap44xx_i2c_hwmod_class,
1190 .flags = HWMOD_INIT_NO_RESET,
1191 .mpu_irqs = omap44xx_i2c2_irqs,
1192 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
1193 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1194 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1195 .main_clk = "i2c2_fck",
db12ba53
BC		 1196 .prcm = {
1197 .omap4 = {
3b54baad 1198 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
db12ba53
BC		 1199 },
1200 },
3b54baad
BC		 1201 .slaves = omap44xx_i2c2_slaves,
1202 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
db12ba53
BC		 1203 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1204};
1205
3b54baad
BC		 1206/* i2c3 */
1207static struct omap_hwmod omap44xx_i2c3_hwmod;
1208static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1209 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 1210};
1211
3b54baad
BC		 1212static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1213 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1214 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
92b18d1c
BC		 1215};
1216
3b54baad 1217static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 1218 {
3b54baad
BC		 1219 .pa_start = 0x48060000,
1220 .pa_end = 0x480600ff,
92b18d1c
BC		 1221 .flags = ADDR_TYPE_RT
1222 },
1223};
1224
3b54baad
BC		 1225/* l4_per -> i2c3 */
1226static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 1227 .master = &omap44xx_l4_per_hwmod,
3b54baad 1228 .slave = &omap44xx_i2c3_hwmod,
db12ba53 1229 .clk = "l4_div_ck",
3b54baad
BC		 1230 .addr = omap44xx_i2c3_addrs,
1231 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
db12ba53
BC		 1232 .user = OCP_USER_MPU | OCP_USER_SDMA,
1233};
1234
3b54baad
BC		 1235/* i2c3 slave ports */
1236static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1237 &omap44xx_l4_per__i2c3,
db12ba53
BC		 1238};
1239
3b54baad
BC		 1240static struct omap_hwmod omap44xx_i2c3_hwmod = {
1241 .name = "i2c3",
1242 .class = &omap44xx_i2c_hwmod_class,
1243 .flags = HWMOD_INIT_NO_RESET,
1244 .mpu_irqs = omap44xx_i2c3_irqs,
1245 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
1246 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1247 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1248 .main_clk = "i2c3_fck",
db12ba53
BC		 1249 .prcm = {
1250 .omap4 = {
3b54baad 1251 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
db12ba53
BC		 1252 },
1253 },
3b54baad
BC		 1254 .slaves = omap44xx_i2c3_slaves,
1255 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
db12ba53
BC		 1256 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1257};
1258
3b54baad
BC		 1259/* i2c4 */
1260static struct omap_hwmod omap44xx_i2c4_hwmod;
1261static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1262 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 1263};
1264
3b54baad
BC		 1265static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1266 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1267 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 1268};
1269
3b54baad 1270static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 1271 {
3b54baad
BC		 1272 .pa_start = 0x48350000,
1273 .pa_end = 0x483500ff,
db12ba53
BC		 1274 .flags = ADDR_TYPE_RT
1275 },
1276};
1277
3b54baad
BC		 1278/* l4_per -> i2c4 */
1279static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1280 .master = &omap44xx_l4_per_hwmod,
1281 .slave = &omap44xx_i2c4_hwmod,
1282 .clk = "l4_div_ck",
1283 .addr = omap44xx_i2c4_addrs,
1284 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
1285 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 1286};
1287
3b54baad
BC		 1288/* i2c4 slave ports */
1289static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1290 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 1291};
1292
3b54baad
BC		 1293static struct omap_hwmod omap44xx_i2c4_hwmod = {
1294 .name = "i2c4",
1295 .class = &omap44xx_i2c_hwmod_class,
1296 .flags = HWMOD_INIT_NO_RESET,
1297 .mpu_irqs = omap44xx_i2c4_irqs,
1298 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
1299 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1300 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1301 .main_clk = "i2c4_fck",
92b18d1c
BC		 1302 .prcm = {
1303 .omap4 = {
3b54baad 1304 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
92b18d1c
BC		 1305 },
1306 },
3b54baad
BC		 1307 .slaves = omap44xx_i2c4_slaves,
1308 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
92b18d1c
BC		 1309 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1310};
1311
8f25bdc5
BC		 1312/*
1313 * 'iva' class
1314 * multi-standard video encoder/decoder hardware accelerator
1315 */
1316
1317static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 1318 .name = "iva",
8f25bdc5
BC		 1319};
1320
1321/* iva */
1322static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1323 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1324 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1325 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1326};
1327
1328static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1329 { .name = "logic", .rst_shift = 2 },
1330};
1331
1332static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1333 { .name = "seq0", .rst_shift = 0 },
1334};
1335
1336static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1337 { .name = "seq1", .rst_shift = 1 },
1338};
1339
1340/* iva master ports */
1341static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1342 &omap44xx_iva__l3_main_2,
1343 &omap44xx_iva__l3_instr,
1344};
1345
1346static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1347 {
1348 .pa_start = 0x5a000000,
1349 .pa_end = 0x5a07ffff,
1350 .flags = ADDR_TYPE_RT
1351 },
1352};
1353
1354/* l3_main_2 -> iva */
1355static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1356 .master = &omap44xx_l3_main_2_hwmod,
1357 .slave = &omap44xx_iva_hwmod,
1358 .clk = "l3_div_ck",
1359 .addr = omap44xx_iva_addrs,
1360 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
1361 .user = OCP_USER_MPU,
1362};
1363
1364/* iva slave ports */
1365static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1366 &omap44xx_dsp__iva,
1367 &omap44xx_l3_main_2__iva,
1368};
1369
1370/* Pseudo hwmod for reset control purpose only */
1371static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1372 .name = "iva_seq0",
1373 .class = &omap44xx_iva_hwmod_class,
1374 .flags = HWMOD_INIT_NO_RESET,
1375 .rst_lines = omap44xx_iva_seq0_resets,
1376 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1377 .prcm = {
1378 .omap4 = {
1379 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1380 },
1381 },
1382 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1383};
1384
1385/* Pseudo hwmod for reset control purpose only */
1386static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1387 .name = "iva_seq1",
1388 .class = &omap44xx_iva_hwmod_class,
1389 .flags = HWMOD_INIT_NO_RESET,
1390 .rst_lines = omap44xx_iva_seq1_resets,
1391 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1392 .prcm = {
1393 .omap4 = {
1394 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1395 },
1396 },
1397 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1398};
1399
1400static struct omap_hwmod omap44xx_iva_hwmod = {
1401 .name = "iva",
1402 .class = &omap44xx_iva_hwmod_class,
1403 .mpu_irqs = omap44xx_iva_irqs,
1404 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
1405 .rst_lines = omap44xx_iva_resets,
1406 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1407 .main_clk = "iva_fck",
1408 .prcm = {
1409 .omap4 = {
1410 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1411 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1412 },
1413 },
1414 .slaves = omap44xx_iva_slaves,
1415 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
1416 .masters = omap44xx_iva_masters,
1417 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
1418 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1419};
1420
9bcbd7f0
BC		 1421/*
1422 * 'mcspi' class
1423 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1424 * bus
1425 */
1426
1427static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1428 .rev_offs = 0x0000,
1429 .sysc_offs = 0x0010,
1430 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1431 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1433 SIDLE_SMART_WKUP),
1434 .sysc_fields = &omap_hwmod_sysc_type2,
1435};
1436
1437static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1438 .name = "mcspi",
1439 .sysc = &omap44xx_mcspi_sysc,
1440};
1441
1442/* mcspi1 */
1443static struct omap_hwmod omap44xx_mcspi1_hwmod;
1444static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
1445 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
1446};
1447
1448static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1449 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1450 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1451 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1452 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1453 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1454 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1455 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1456 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1457};
1458
1459static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
1460 {
1461 .pa_start = 0x48098000,
1462 .pa_end = 0x480981ff,
1463 .flags = ADDR_TYPE_RT
1464 },
1465};
1466
1467/* l4_per -> mcspi1 */
1468static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
1469 .master = &omap44xx_l4_per_hwmod,
1470 .slave = &omap44xx_mcspi1_hwmod,
1471 .clk = "l4_div_ck",
1472 .addr = omap44xx_mcspi1_addrs,
1473 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
1474 .user = OCP_USER_MPU | OCP_USER_SDMA,
1475};
1476
1477/* mcspi1 slave ports */
1478static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
1479 &omap44xx_l4_per__mcspi1,
1480};
1481
1482static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1483 .name = "mcspi1",
1484 .class = &omap44xx_mcspi_hwmod_class,
1485 .mpu_irqs = omap44xx_mcspi1_irqs,
1486 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
1487 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1488 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
1489 .main_clk = "mcspi1_fck",
1490 .prcm = {
1491 .omap4 = {
1492 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1493 },
1494 },
1495 .slaves = omap44xx_mcspi1_slaves,
1496 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
1497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1498};
1499
1500/* mcspi2 */
1501static struct omap_hwmod omap44xx_mcspi2_hwmod;
1502static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
1503 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
1504};
1505
1506static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1507 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1508 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1509 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1510 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1511};
1512
1513static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
1514 {
1515 .pa_start = 0x4809a000,
1516 .pa_end = 0x4809a1ff,
1517 .flags = ADDR_TYPE_RT
1518 },
1519};
1520
1521/* l4_per -> mcspi2 */
1522static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
1523 .master = &omap44xx_l4_per_hwmod,
1524 .slave = &omap44xx_mcspi2_hwmod,
1525 .clk = "l4_div_ck",
1526 .addr = omap44xx_mcspi2_addrs,
1527 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
1528 .user = OCP_USER_MPU | OCP_USER_SDMA,
1529};
1530
1531/* mcspi2 slave ports */
1532static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
1533 &omap44xx_l4_per__mcspi2,
1534};
1535
1536static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1537 .name = "mcspi2",
1538 .class = &omap44xx_mcspi_hwmod_class,
1539 .mpu_irqs = omap44xx_mcspi2_irqs,
1540 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
1541 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1542 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
1543 .main_clk = "mcspi2_fck",
1544 .prcm = {
1545 .omap4 = {
1546 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1547 },
1548 },
1549 .slaves = omap44xx_mcspi2_slaves,
1550 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
1551 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1552};
1553
1554/* mcspi3 */
1555static struct omap_hwmod omap44xx_mcspi3_hwmod;
1556static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
1557 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
1558};
1559
1560static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1561 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1562 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1563 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1564 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1565};
1566
1567static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
1568 {
1569 .pa_start = 0x480b8000,
1570 .pa_end = 0x480b81ff,
1571 .flags = ADDR_TYPE_RT
1572 },
1573};
1574
1575/* l4_per -> mcspi3 */
1576static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
1577 .master = &omap44xx_l4_per_hwmod,
1578 .slave = &omap44xx_mcspi3_hwmod,
1579 .clk = "l4_div_ck",
1580 .addr = omap44xx_mcspi3_addrs,
1581 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
1582 .user = OCP_USER_MPU | OCP_USER_SDMA,
1583};
1584
1585/* mcspi3 slave ports */
1586static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
1587 &omap44xx_l4_per__mcspi3,
1588};
1589
1590static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1591 .name = "mcspi3",
1592 .class = &omap44xx_mcspi_hwmod_class,
1593 .mpu_irqs = omap44xx_mcspi3_irqs,
1594 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
1595 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1596 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
1597 .main_clk = "mcspi3_fck",
1598 .prcm = {
1599 .omap4 = {
1600 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1601 },
1602 },
1603 .slaves = omap44xx_mcspi3_slaves,
1604 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
1605 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1606};
1607
1608/* mcspi4 */
1609static struct omap_hwmod omap44xx_mcspi4_hwmod;
1610static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
1611 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
1612};
1613
1614static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1615 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1616 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1617};
1618
1619static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
1620 {
1621 .pa_start = 0x480ba000,
1622 .pa_end = 0x480ba1ff,
1623 .flags = ADDR_TYPE_RT
1624 },
1625};
1626
1627/* l4_per -> mcspi4 */
1628static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
1629 .master = &omap44xx_l4_per_hwmod,
1630 .slave = &omap44xx_mcspi4_hwmod,
1631 .clk = "l4_div_ck",
1632 .addr = omap44xx_mcspi4_addrs,
1633 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
1634 .user = OCP_USER_MPU | OCP_USER_SDMA,
1635};
1636
1637/* mcspi4 slave ports */
1638static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
1639 &omap44xx_l4_per__mcspi4,
1640};
1641
1642static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1643 .name = "mcspi4",
1644 .class = &omap44xx_mcspi_hwmod_class,
1645 .mpu_irqs = omap44xx_mcspi4_irqs,
1646 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
1647 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1648 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
1649 .main_clk = "mcspi4_fck",
1650 .prcm = {
1651 .omap4 = {
1652 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1653 },
1654 },
1655 .slaves = omap44xx_mcspi4_slaves,
1656 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
1657 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1658};
1659
3b54baad
BC		 1660/*
1661 * 'mpu' class
1662 * mpu sub-system
1663 */
1664
1665static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 1666 .name = "mpu",
db12ba53
BC		 1667};
1668
3b54baad
BC		 1669/* mpu */
1670static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
1671 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
1672 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
1673 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 1674};
1675
3b54baad
BC		 1676/* mpu master ports */
1677static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
1678 &omap44xx_mpu__l3_main_1,
1679 &omap44xx_mpu__l4_abe,
1680 &omap44xx_mpu__dmm,
1681};
1682
1683static struct omap_hwmod omap44xx_mpu_hwmod = {
1684 .name = "mpu",
1685 .class = &omap44xx_mpu_hwmod_class,
1686 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1687 .mpu_irqs = omap44xx_mpu_irqs,
1688 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
1689 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 1690 .prcm = {
1691 .omap4 = {
3b54baad 1692 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
db12ba53
BC		 1693 },
1694 },
3b54baad
BC		 1695 .masters = omap44xx_mpu_masters,
1696 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 1697 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1698};
1699
1f6a717f
BC		 1700/*
1701 * 'smartreflex' class
1702 * smartreflex module (monitor silicon performance and outputs a measure of
1703 * performance error)
1704 */
1705
1706/* The IP is not compliant to type1 / type2 scheme */
1707static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1708 .sidle_shift = 24,
1709 .enwkup_shift = 26,
1710};
1711
1712static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1713 .sysc_offs = 0x0038,
1714 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1715 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1716 SIDLE_SMART_WKUP),
1717 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1718};
1719
1720static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 1721 .name = "smartreflex",
1722 .sysc = &omap44xx_smartreflex_sysc,
1723 .rev = 2,
1f6a717f
BC		 1724};
1725
1726/* smartreflex_core */
1727static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
1728static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
1729 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
1730};
1731
1732static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
1733 {
1734 .pa_start = 0x4a0dd000,
1735 .pa_end = 0x4a0dd03f,
1736 .flags = ADDR_TYPE_RT
1737 },
1738};
1739
1740/* l4_cfg -> smartreflex_core */
1741static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
1742 .master = &omap44xx_l4_cfg_hwmod,
1743 .slave = &omap44xx_smartreflex_core_hwmod,
1744 .clk = "l4_div_ck",
1745 .addr = omap44xx_smartreflex_core_addrs,
1746 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
1747 .user = OCP_USER_MPU | OCP_USER_SDMA,
1748};
1749
1750/* smartreflex_core slave ports */
1751static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
1752 &omap44xx_l4_cfg__smartreflex_core,
1753};
1754
1755static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1756 .name = "smartreflex_core",
1757 .class = &omap44xx_smartreflex_hwmod_class,
1758 .mpu_irqs = omap44xx_smartreflex_core_irqs,
1759 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
1760 .main_clk = "smartreflex_core_fck",
1761 .vdd_name = "core",
1762 .prcm = {
1763 .omap4 = {
1764 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1765 },
1766 },
1767 .slaves = omap44xx_smartreflex_core_slaves,
1768 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
1769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1770};
1771
1772/* smartreflex_iva */
1773static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
1774static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
1775 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
1776};
1777
1778static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
1779 {
1780 .pa_start = 0x4a0db000,
1781 .pa_end = 0x4a0db03f,
1782 .flags = ADDR_TYPE_RT
1783 },
1784};
1785
1786/* l4_cfg -> smartreflex_iva */
1787static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
1788 .master = &omap44xx_l4_cfg_hwmod,
1789 .slave = &omap44xx_smartreflex_iva_hwmod,
1790 .clk = "l4_div_ck",
1791 .addr = omap44xx_smartreflex_iva_addrs,
1792 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
1793 .user = OCP_USER_MPU | OCP_USER_SDMA,
1794};
1795
1796/* smartreflex_iva slave ports */
1797static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
1798 &omap44xx_l4_cfg__smartreflex_iva,
1799};
1800
1801static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1802 .name = "smartreflex_iva",
1803 .class = &omap44xx_smartreflex_hwmod_class,
1804 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1805 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
1806 .main_clk = "smartreflex_iva_fck",
1807 .vdd_name = "iva",
1808 .prcm = {
1809 .omap4 = {
1810 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1811 },
1812 },
1813 .slaves = omap44xx_smartreflex_iva_slaves,
1814 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
1815 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1816};
1817
1818/* smartreflex_mpu */
1819static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
1820static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
1821 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
1822};
1823
1824static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
1825 {
1826 .pa_start = 0x4a0d9000,
1827 .pa_end = 0x4a0d903f,
1828 .flags = ADDR_TYPE_RT
1829 },
1830};
1831
1832/* l4_cfg -> smartreflex_mpu */
1833static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
1834 .master = &omap44xx_l4_cfg_hwmod,
1835 .slave = &omap44xx_smartreflex_mpu_hwmod,
1836 .clk = "l4_div_ck",
1837 .addr = omap44xx_smartreflex_mpu_addrs,
1838 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
1839 .user = OCP_USER_MPU | OCP_USER_SDMA,
1840};
1841
1842/* smartreflex_mpu slave ports */
1843static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
1844 &omap44xx_l4_cfg__smartreflex_mpu,
1845};
1846
1847static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1848 .name = "smartreflex_mpu",
1849 .class = &omap44xx_smartreflex_hwmod_class,
1850 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1851 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
1852 .main_clk = "smartreflex_mpu_fck",
1853 .vdd_name = "mpu",
1854 .prcm = {
1855 .omap4 = {
1856 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1857 },
1858 },
1859 .slaves = omap44xx_smartreflex_mpu_slaves,
1860 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
1861 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1862};
1863
d11c217f
BC		 1864/*
1865 * 'spinlock' class
1866 * spinlock provides hardware assistance for synchronizing the processes
1867 * running on multiple processors
1868 */
1869
1870static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
1871 .rev_offs = 0x0000,
1872 .sysc_offs = 0x0010,
1873 .syss_offs = 0x0014,
1874 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1875 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1876 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1877 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1878 SIDLE_SMART_WKUP),
1879 .sysc_fields = &omap_hwmod_sysc_type1,
1880};
1881
1882static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
1883 .name = "spinlock",
1884 .sysc = &omap44xx_spinlock_sysc,
1885};
1886
1887/* spinlock */
1888static struct omap_hwmod omap44xx_spinlock_hwmod;
1889static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
1890 {
1891 .pa_start = 0x4a0f6000,
1892 .pa_end = 0x4a0f6fff,
1893 .flags = ADDR_TYPE_RT
1894 },
1895};
1896
1897/* l4_cfg -> spinlock */
1898static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
1899 .master = &omap44xx_l4_cfg_hwmod,
1900 .slave = &omap44xx_spinlock_hwmod,
1901 .clk = "l4_div_ck",
1902 .addr = omap44xx_spinlock_addrs,
1903 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* spinlock slave ports */
1908static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
1909 &omap44xx_l4_cfg__spinlock,
1910};
1911
1912static struct omap_hwmod omap44xx_spinlock_hwmod = {
1913 .name = "spinlock",
1914 .class = &omap44xx_spinlock_hwmod_class,
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
1918 },
1919 },
1920 .slaves = omap44xx_spinlock_slaves,
1921 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
1922 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1923};
1924
35d1a66a
BC		 1925/*
1926 * 'timer' class
1927 * general purpose timer module with accurate 1ms tick
1928 * This class contains several variants: ['timer_1ms', 'timer']
1929 */
1930
1931static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
1932 .rev_offs = 0x0000,
1933 .sysc_offs = 0x0010,
1934 .syss_offs = 0x0014,
1935 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1936 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1937 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1938 SYSS_HAS_RESET_STATUS),
1939 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1940 .sysc_fields = &omap_hwmod_sysc_type1,
1941};
1942
1943static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
1944 .name = "timer",
1945 .sysc = &omap44xx_timer_1ms_sysc,
1946};
1947
1948static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
1949 .rev_offs = 0x0000,
1950 .sysc_offs = 0x0010,
1951 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1952 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1953 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1954 SIDLE_SMART_WKUP),
1955 .sysc_fields = &omap_hwmod_sysc_type2,
1956};
1957
1958static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
1959 .name = "timer",
1960 .sysc = &omap44xx_timer_sysc,
1961};
1962
1963/* timer1 */
1964static struct omap_hwmod omap44xx_timer1_hwmod;
1965static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
1966 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
1967};
1968
1969static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
1970 {
1971 .pa_start = 0x4a318000,
1972 .pa_end = 0x4a31807f,
1973 .flags = ADDR_TYPE_RT
1974 },
1975};
1976
1977/* l4_wkup -> timer1 */
1978static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
1979 .master = &omap44xx_l4_wkup_hwmod,
1980 .slave = &omap44xx_timer1_hwmod,
1981 .clk = "l4_wkup_clk_mux_ck",
1982 .addr = omap44xx_timer1_addrs,
1983 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985};
1986
1987/* timer1 slave ports */
1988static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
1989 &omap44xx_l4_wkup__timer1,
1990};
1991
1992static struct omap_hwmod omap44xx_timer1_hwmod = {
1993 .name = "timer1",
1994 .class = &omap44xx_timer_1ms_hwmod_class,
1995 .mpu_irqs = omap44xx_timer1_irqs,
1996 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
1997 .main_clk = "timer1_fck",
1998 .prcm = {
1999 .omap4 = {
2000 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2001 },
2002 },
2003 .slaves = omap44xx_timer1_slaves,
2004 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
2005 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2006};
2007
2008/* timer2 */
2009static struct omap_hwmod omap44xx_timer2_hwmod;
2010static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2011 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2012};
2013
2014static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
2015 {
2016 .pa_start = 0x48032000,
2017 .pa_end = 0x4803207f,
2018 .flags = ADDR_TYPE_RT
2019 },
2020};
2021
2022/* l4_per -> timer2 */
2023static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
2024 .master = &omap44xx_l4_per_hwmod,
2025 .slave = &omap44xx_timer2_hwmod,
2026 .clk = "l4_div_ck",
2027 .addr = omap44xx_timer2_addrs,
2028 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
2029 .user = OCP_USER_MPU | OCP_USER_SDMA,
2030};
2031
2032/* timer2 slave ports */
2033static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
2034 &omap44xx_l4_per__timer2,
2035};
2036
2037static struct omap_hwmod omap44xx_timer2_hwmod = {
2038 .name = "timer2",
2039 .class = &omap44xx_timer_1ms_hwmod_class,
2040 .mpu_irqs = omap44xx_timer2_irqs,
2041 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
2042 .main_clk = "timer2_fck",
2043 .prcm = {
2044 .omap4 = {
2045 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2046 },
2047 },
2048 .slaves = omap44xx_timer2_slaves,
2049 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
2050 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2051};
2052
2053/* timer3 */
2054static struct omap_hwmod omap44xx_timer3_hwmod;
2055static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2056 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2057};
2058
2059static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
2060 {
2061 .pa_start = 0x48034000,
2062 .pa_end = 0x4803407f,
2063 .flags = ADDR_TYPE_RT
2064 },
2065};
2066
2067/* l4_per -> timer3 */
2068static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
2069 .master = &omap44xx_l4_per_hwmod,
2070 .slave = &omap44xx_timer3_hwmod,
2071 .clk = "l4_div_ck",
2072 .addr = omap44xx_timer3_addrs,
2073 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
2074 .user = OCP_USER_MPU | OCP_USER_SDMA,
2075};
2076
2077/* timer3 slave ports */
2078static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
2079 &omap44xx_l4_per__timer3,
2080};
2081
2082static struct omap_hwmod omap44xx_timer3_hwmod = {
2083 .name = "timer3",
2084 .class = &omap44xx_timer_hwmod_class,
2085 .mpu_irqs = omap44xx_timer3_irqs,
2086 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
2087 .main_clk = "timer3_fck",
2088 .prcm = {
2089 .omap4 = {
2090 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2091 },
2092 },
2093 .slaves = omap44xx_timer3_slaves,
2094 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
2095 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2096};
2097
2098/* timer4 */
2099static struct omap_hwmod omap44xx_timer4_hwmod;
2100static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2101 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2102};
2103
2104static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
2105 {
2106 .pa_start = 0x48036000,
2107 .pa_end = 0x4803607f,
2108 .flags = ADDR_TYPE_RT
2109 },
2110};
2111
2112/* l4_per -> timer4 */
2113static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
2114 .master = &omap44xx_l4_per_hwmod,
2115 .slave = &omap44xx_timer4_hwmod,
2116 .clk = "l4_div_ck",
2117 .addr = omap44xx_timer4_addrs,
2118 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
2119 .user = OCP_USER_MPU | OCP_USER_SDMA,
2120};
2121
2122/* timer4 slave ports */
2123static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
2124 &omap44xx_l4_per__timer4,
2125};
2126
2127static struct omap_hwmod omap44xx_timer4_hwmod = {
2128 .name = "timer4",
2129 .class = &omap44xx_timer_hwmod_class,
2130 .mpu_irqs = omap44xx_timer4_irqs,
2131 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
2132 .main_clk = "timer4_fck",
2133 .prcm = {
2134 .omap4 = {
2135 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2136 },
2137 },
2138 .slaves = omap44xx_timer4_slaves,
2139 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
2140 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2141};
2142
2143/* timer5 */
2144static struct omap_hwmod omap44xx_timer5_hwmod;
2145static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2146 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2147};
2148
2149static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
2150 {
2151 .pa_start = 0x40138000,
2152 .pa_end = 0x4013807f,
2153 .flags = ADDR_TYPE_RT
2154 },
2155};
2156
2157/* l4_abe -> timer5 */
2158static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
2159 .master = &omap44xx_l4_abe_hwmod,
2160 .slave = &omap44xx_timer5_hwmod,
2161 .clk = "ocp_abe_iclk",
2162 .addr = omap44xx_timer5_addrs,
2163 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
2164 .user = OCP_USER_MPU,
2165};
2166
2167static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
2168 {
2169 .pa_start = 0x49038000,
2170 .pa_end = 0x4903807f,
2171 .flags = ADDR_TYPE_RT
2172 },
2173};
2174
2175/* l4_abe -> timer5 (dma) */
2176static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
2177 .master = &omap44xx_l4_abe_hwmod,
2178 .slave = &omap44xx_timer5_hwmod,
2179 .clk = "ocp_abe_iclk",
2180 .addr = omap44xx_timer5_dma_addrs,
2181 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
2182 .user = OCP_USER_SDMA,
2183};
2184
2185/* timer5 slave ports */
2186static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
2187 &omap44xx_l4_abe__timer5,
2188 &omap44xx_l4_abe__timer5_dma,
2189};
2190
2191static struct omap_hwmod omap44xx_timer5_hwmod = {
2192 .name = "timer5",
2193 .class = &omap44xx_timer_hwmod_class,
2194 .mpu_irqs = omap44xx_timer5_irqs,
2195 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
2196 .main_clk = "timer5_fck",
2197 .prcm = {
2198 .omap4 = {
2199 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2200 },
2201 },
2202 .slaves = omap44xx_timer5_slaves,
2203 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
2204 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2205};
2206
2207/* timer6 */
2208static struct omap_hwmod omap44xx_timer6_hwmod;
2209static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
2210 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
2211};
2212
2213static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
2214 {
2215 .pa_start = 0x4013a000,
2216 .pa_end = 0x4013a07f,
2217 .flags = ADDR_TYPE_RT
2218 },
2219};
2220
2221/* l4_abe -> timer6 */
2222static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
2223 .master = &omap44xx_l4_abe_hwmod,
2224 .slave = &omap44xx_timer6_hwmod,
2225 .clk = "ocp_abe_iclk",
2226 .addr = omap44xx_timer6_addrs,
2227 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
2228 .user = OCP_USER_MPU,
2229};
2230
2231static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
2232 {
2233 .pa_start = 0x4903a000,
2234 .pa_end = 0x4903a07f,
2235 .flags = ADDR_TYPE_RT
2236 },
2237};
2238
2239/* l4_abe -> timer6 (dma) */
2240static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
2241 .master = &omap44xx_l4_abe_hwmod,
2242 .slave = &omap44xx_timer6_hwmod,
2243 .clk = "ocp_abe_iclk",
2244 .addr = omap44xx_timer6_dma_addrs,
2245 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
2246 .user = OCP_USER_SDMA,
2247};
2248
2249/* timer6 slave ports */
2250static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
2251 &omap44xx_l4_abe__timer6,
2252 &omap44xx_l4_abe__timer6_dma,
2253};
2254
2255static struct omap_hwmod omap44xx_timer6_hwmod = {
2256 .name = "timer6",
2257 .class = &omap44xx_timer_hwmod_class,
2258 .mpu_irqs = omap44xx_timer6_irqs,
2259 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
2260 .main_clk = "timer6_fck",
2261 .prcm = {
2262 .omap4 = {
2263 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2264 },
2265 },
2266 .slaves = omap44xx_timer6_slaves,
2267 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
2268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2269};
2270
2271/* timer7 */
2272static struct omap_hwmod omap44xx_timer7_hwmod;
2273static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
2274 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
2275};
2276
2277static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
2278 {
2279 .pa_start = 0x4013c000,
2280 .pa_end = 0x4013c07f,
2281 .flags = ADDR_TYPE_RT
2282 },
2283};
2284
2285/* l4_abe -> timer7 */
2286static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
2287 .master = &omap44xx_l4_abe_hwmod,
2288 .slave = &omap44xx_timer7_hwmod,
2289 .clk = "ocp_abe_iclk",
2290 .addr = omap44xx_timer7_addrs,
2291 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
2292 .user = OCP_USER_MPU,
2293};
2294
2295static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
2296 {
2297 .pa_start = 0x4903c000,
2298 .pa_end = 0x4903c07f,
2299 .flags = ADDR_TYPE_RT
2300 },
2301};
2302
2303/* l4_abe -> timer7 (dma) */
2304static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
2305 .master = &omap44xx_l4_abe_hwmod,
2306 .slave = &omap44xx_timer7_hwmod,
2307 .clk = "ocp_abe_iclk",
2308 .addr = omap44xx_timer7_dma_addrs,
2309 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
2310 .user = OCP_USER_SDMA,
2311};
2312
2313/* timer7 slave ports */
2314static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
2315 &omap44xx_l4_abe__timer7,
2316 &omap44xx_l4_abe__timer7_dma,
2317};
2318
2319static struct omap_hwmod omap44xx_timer7_hwmod = {
2320 .name = "timer7",
2321 .class = &omap44xx_timer_hwmod_class,
2322 .mpu_irqs = omap44xx_timer7_irqs,
2323 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
2324 .main_clk = "timer7_fck",
2325 .prcm = {
2326 .omap4 = {
2327 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2328 },
2329 },
2330 .slaves = omap44xx_timer7_slaves,
2331 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
2332 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2333};
2334
2335/* timer8 */
2336static struct omap_hwmod omap44xx_timer8_hwmod;
2337static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
2338 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
2339};
2340
2341static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
2342 {
2343 .pa_start = 0x4013e000,
2344 .pa_end = 0x4013e07f,
2345 .flags = ADDR_TYPE_RT
2346 },
2347};
2348
2349/* l4_abe -> timer8 */
2350static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
2351 .master = &omap44xx_l4_abe_hwmod,
2352 .slave = &omap44xx_timer8_hwmod,
2353 .clk = "ocp_abe_iclk",
2354 .addr = omap44xx_timer8_addrs,
2355 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
2356 .user = OCP_USER_MPU,
2357};
2358
2359static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
2360 {
2361 .pa_start = 0x4903e000,
2362 .pa_end = 0x4903e07f,
2363 .flags = ADDR_TYPE_RT
2364 },
2365};
2366
2367/* l4_abe -> timer8 (dma) */
2368static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
2369 .master = &omap44xx_l4_abe_hwmod,
2370 .slave = &omap44xx_timer8_hwmod,
2371 .clk = "ocp_abe_iclk",
2372 .addr = omap44xx_timer8_dma_addrs,
2373 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
2374 .user = OCP_USER_SDMA,
2375};
2376
2377/* timer8 slave ports */
2378static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
2379 &omap44xx_l4_abe__timer8,
2380 &omap44xx_l4_abe__timer8_dma,
2381};
2382
2383static struct omap_hwmod omap44xx_timer8_hwmod = {
2384 .name = "timer8",
2385 .class = &omap44xx_timer_hwmod_class,
2386 .mpu_irqs = omap44xx_timer8_irqs,
2387 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
2388 .main_clk = "timer8_fck",
2389 .prcm = {
2390 .omap4 = {
2391 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2392 },
2393 },
2394 .slaves = omap44xx_timer8_slaves,
2395 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
2396 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2397};
2398
2399/* timer9 */
2400static struct omap_hwmod omap44xx_timer9_hwmod;
2401static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
2402 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
2403};
2404
2405static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
2406 {
2407 .pa_start = 0x4803e000,
2408 .pa_end = 0x4803e07f,
2409 .flags = ADDR_TYPE_RT
2410 },
2411};
2412
2413/* l4_per -> timer9 */
2414static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
2415 .master = &omap44xx_l4_per_hwmod,
2416 .slave = &omap44xx_timer9_hwmod,
2417 .clk = "l4_div_ck",
2418 .addr = omap44xx_timer9_addrs,
2419 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
2420 .user = OCP_USER_MPU | OCP_USER_SDMA,
2421};
2422
2423/* timer9 slave ports */
2424static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
2425 &omap44xx_l4_per__timer9,
2426};
2427
2428static struct omap_hwmod omap44xx_timer9_hwmod = {
2429 .name = "timer9",
2430 .class = &omap44xx_timer_hwmod_class,
2431 .mpu_irqs = omap44xx_timer9_irqs,
2432 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
2433 .main_clk = "timer9_fck",
2434 .prcm = {
2435 .omap4 = {
2436 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2437 },
2438 },
2439 .slaves = omap44xx_timer9_slaves,
2440 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
2441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2442};
2443
2444/* timer10 */
2445static struct omap_hwmod omap44xx_timer10_hwmod;
2446static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
2447 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
2448};
2449
2450static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
2451 {
2452 .pa_start = 0x48086000,
2453 .pa_end = 0x4808607f,
2454 .flags = ADDR_TYPE_RT
2455 },
2456};
2457
2458/* l4_per -> timer10 */
2459static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
2460 .master = &omap44xx_l4_per_hwmod,
2461 .slave = &omap44xx_timer10_hwmod,
2462 .clk = "l4_div_ck",
2463 .addr = omap44xx_timer10_addrs,
2464 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
2465 .user = OCP_USER_MPU | OCP_USER_SDMA,
2466};
2467
2468/* timer10 slave ports */
2469static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
2470 &omap44xx_l4_per__timer10,
2471};
2472
2473static struct omap_hwmod omap44xx_timer10_hwmod = {
2474 .name = "timer10",
2475 .class = &omap44xx_timer_1ms_hwmod_class,
2476 .mpu_irqs = omap44xx_timer10_irqs,
2477 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
2478 .main_clk = "timer10_fck",
2479 .prcm = {
2480 .omap4 = {
2481 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2482 },
2483 },
2484 .slaves = omap44xx_timer10_slaves,
2485 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
2486 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2487};
2488
2489/* timer11 */
2490static struct omap_hwmod omap44xx_timer11_hwmod;
2491static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
2492 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
2493};
2494
2495static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
2496 {
2497 .pa_start = 0x48088000,
2498 .pa_end = 0x4808807f,
2499 .flags = ADDR_TYPE_RT
2500 },
2501};
2502
2503/* l4_per -> timer11 */
2504static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
2505 .master = &omap44xx_l4_per_hwmod,
2506 .slave = &omap44xx_timer11_hwmod,
2507 .clk = "l4_div_ck",
2508 .addr = omap44xx_timer11_addrs,
2509 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
2510 .user = OCP_USER_MPU | OCP_USER_SDMA,
2511};
2512
2513/* timer11 slave ports */
2514static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
2515 &omap44xx_l4_per__timer11,
2516};
2517
2518static struct omap_hwmod omap44xx_timer11_hwmod = {
2519 .name = "timer11",
2520 .class = &omap44xx_timer_hwmod_class,
2521 .mpu_irqs = omap44xx_timer11_irqs,
2522 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
2523 .main_clk = "timer11_fck",
2524 .prcm = {
2525 .omap4 = {
2526 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2527 },
2528 },
2529 .slaves = omap44xx_timer11_slaves,
2530 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
2531 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2532};
2533
9780a9cf 2534/*
3b54baad
BC		 2535 * 'uart' class
2536 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 2537 */
2538
3b54baad
BC		 2539static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2540 .rev_offs = 0x0050,
2541 .sysc_offs = 0x0054,
2542 .syss_offs = 0x0058,
2543 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 2544 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2545 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2546 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2547 SIDLE_SMART_WKUP),
9780a9cf
BC		 2548 .sysc_fields = &omap_hwmod_sysc_type1,
2549};
2550
3b54baad 2551static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 2552 .name = "uart",
2553 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 2554};
2555
3b54baad
BC		 2556/* uart1 */
2557static struct omap_hwmod omap44xx_uart1_hwmod;
2558static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
2559 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 2560};
2561
3b54baad
BC		 2562static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
2563 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
2564 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
9780a9cf
BC		 2565};
2566
3b54baad 2567static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 2568 {
3b54baad
BC		 2569 .pa_start = 0x4806a000,
2570 .pa_end = 0x4806a0ff,
9780a9cf
BC		 2571 .flags = ADDR_TYPE_RT
2572 },
2573};
2574
3b54baad
BC		 2575/* l4_per -> uart1 */
2576static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
2577 .master = &omap44xx_l4_per_hwmod,
2578 .slave = &omap44xx_uart1_hwmod,
2579 .clk = "l4_div_ck",
2580 .addr = omap44xx_uart1_addrs,
2581 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
9780a9cf
BC		 2582 .user = OCP_USER_MPU | OCP_USER_SDMA,
2583};
2584
3b54baad
BC		 2585/* uart1 slave ports */
2586static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
2587 &omap44xx_l4_per__uart1,
9780a9cf
BC		 2588};
2589
3b54baad
BC		 2590static struct omap_hwmod omap44xx_uart1_hwmod = {
2591 .name = "uart1",
2592 .class = &omap44xx_uart_hwmod_class,
2593 .mpu_irqs = omap44xx_uart1_irqs,
2594 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
2595 .sdma_reqs = omap44xx_uart1_sdma_reqs,
2596 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
2597 .main_clk = "uart1_fck",
9780a9cf
BC		 2598 .prcm = {
2599 .omap4 = {
3b54baad 2600 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
9780a9cf
BC		 2601 },
2602 },
3b54baad
BC		 2603 .slaves = omap44xx_uart1_slaves,
2604 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 2605 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2606};
2607
3b54baad
BC		 2608/* uart2 */
2609static struct omap_hwmod omap44xx_uart2_hwmod;
2610static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
2611 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 2612};
2613
3b54baad
BC		 2614static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
2615 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
2616 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
2617};
2618
2619static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 2620 {
3b54baad
BC		 2621 .pa_start = 0x4806c000,
2622 .pa_end = 0x4806c0ff,
9780a9cf
BC		 2623 .flags = ADDR_TYPE_RT
2624 },
2625};
2626
3b54baad
BC		 2627/* l4_per -> uart2 */
2628static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 2629 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 2630 .slave = &omap44xx_uart2_hwmod,
2631 .clk = "l4_div_ck",
2632 .addr = omap44xx_uart2_addrs,
2633 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
9780a9cf
BC		 2634 .user = OCP_USER_MPU | OCP_USER_SDMA,
2635};
2636
3b54baad
BC		 2637/* uart2 slave ports */
2638static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
2639 &omap44xx_l4_per__uart2,
9780a9cf
BC		 2640};
2641
3b54baad
BC		 2642static struct omap_hwmod omap44xx_uart2_hwmod = {
2643 .name = "uart2",
2644 .class = &omap44xx_uart_hwmod_class,
2645 .mpu_irqs = omap44xx_uart2_irqs,
2646 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
2647 .sdma_reqs = omap44xx_uart2_sdma_reqs,
2648 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
2649 .main_clk = "uart2_fck",
9780a9cf
BC		 2650 .prcm = {
2651 .omap4 = {
3b54baad 2652 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
9780a9cf
BC		 2653 },
2654 },
3b54baad
BC		 2655 .slaves = omap44xx_uart2_slaves,
2656 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 2657 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2658};
2659
3b54baad
BC		 2660/* uart3 */
2661static struct omap_hwmod omap44xx_uart3_hwmod;
2662static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
2663 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 2664};
2665
3b54baad
BC		 2666static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
2667 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
2668 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
2669};
2670
2671static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 2672 {
3b54baad
BC		 2673 .pa_start = 0x48020000,
2674 .pa_end = 0x480200ff,
9780a9cf
BC		 2675 .flags = ADDR_TYPE_RT
2676 },
2677};
2678
3b54baad
BC		 2679/* l4_per -> uart3 */
2680static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 2681 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 2682 .slave = &omap44xx_uart3_hwmod,
2683 .clk = "l4_div_ck",
2684 .addr = omap44xx_uart3_addrs,
2685 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
9780a9cf
BC		 2686 .user = OCP_USER_MPU | OCP_USER_SDMA,
2687};
2688
3b54baad
BC		 2689/* uart3 slave ports */
2690static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
2691 &omap44xx_l4_per__uart3,
2692};
2693
2694static struct omap_hwmod omap44xx_uart3_hwmod = {
2695 .name = "uart3",
2696 .class = &omap44xx_uart_hwmod_class,
2697 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
2698 .mpu_irqs = omap44xx_uart3_irqs,
2699 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
2700 .sdma_reqs = omap44xx_uart3_sdma_reqs,
2701 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
2702 .main_clk = "uart3_fck",
9780a9cf
BC		 2703 .prcm = {
2704 .omap4 = {
3b54baad 2705 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
9780a9cf
BC		 2706 },
2707 },
3b54baad
BC		 2708 .slaves = omap44xx_uart3_slaves,
2709 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 2710 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2711};
2712
3b54baad
BC		 2713/* uart4 */
2714static struct omap_hwmod omap44xx_uart4_hwmod;
2715static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
2716 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 2717};
2718
3b54baad
BC		 2719static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
2720 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
2721 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
2722};
2723
2724static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 2725 {
3b54baad
BC		 2726 .pa_start = 0x4806e000,
2727 .pa_end = 0x4806e0ff,
9780a9cf
BC		 2728 .flags = ADDR_TYPE_RT
2729 },
2730};
2731
3b54baad
BC		 2732/* l4_per -> uart4 */
2733static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 2734 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 2735 .slave = &omap44xx_uart4_hwmod,
2736 .clk = "l4_div_ck",
2737 .addr = omap44xx_uart4_addrs,
2738 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
9780a9cf
BC		 2739 .user = OCP_USER_MPU | OCP_USER_SDMA,
2740};
2741
3b54baad
BC		 2742/* uart4 slave ports */
2743static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
2744 &omap44xx_l4_per__uart4,
9780a9cf
BC		 2745};
2746
3b54baad
BC		 2747static struct omap_hwmod omap44xx_uart4_hwmod = {
2748 .name = "uart4",
2749 .class = &omap44xx_uart_hwmod_class,
2750 .mpu_irqs = omap44xx_uart4_irqs,
2751 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
2752 .sdma_reqs = omap44xx_uart4_sdma_reqs,
2753 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
2754 .main_clk = "uart4_fck",
9780a9cf
BC		 2755 .prcm = {
2756 .omap4 = {
3b54baad 2757 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
9780a9cf
BC		 2758 },
2759 },
3b54baad
BC		 2760 .slaves = omap44xx_uart4_slaves,
2761 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 2762 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2763};
2764
3b54baad
BC		 2765/*
2766 * 'wd_timer' class
2767 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
2768 * overflow condition
2769 */
2770
2771static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
2772 .rev_offs = 0x0000,
2773 .sysc_offs = 0x0010,
2774 .syss_offs = 0x0014,
2775 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 2776 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2777 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2778 SIDLE_SMART_WKUP),
3b54baad 2779 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 2780};
2781
3b54baad
BC		 2782static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
2783 .name = "wd_timer",
2784 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 2785 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 2786};
2787
2788/* wd_timer2 */
2789static struct omap_hwmod omap44xx_wd_timer2_hwmod;
2790static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
2791 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
2792};
2793
2794static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 2795 {
3b54baad
BC		 2796 .pa_start = 0x4a314000,
2797 .pa_end = 0x4a31407f,
9780a9cf
BC		 2798 .flags = ADDR_TYPE_RT
2799 },
2800};
2801
3b54baad
BC		 2802/* l4_wkup -> wd_timer2 */
2803static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
2804 .master = &omap44xx_l4_wkup_hwmod,
2805 .slave = &omap44xx_wd_timer2_hwmod,
2806 .clk = "l4_wkup_clk_mux_ck",
2807 .addr = omap44xx_wd_timer2_addrs,
2808 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
9780a9cf
BC		 2809 .user = OCP_USER_MPU | OCP_USER_SDMA,
2810};
2811
3b54baad
BC		 2812/* wd_timer2 slave ports */
2813static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
2814 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 2815};
2816
3b54baad
BC		 2817static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
2818 .name = "wd_timer2",
2819 .class = &omap44xx_wd_timer_hwmod_class,
2820 .mpu_irqs = omap44xx_wd_timer2_irqs,
2821 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
2822 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 2823 .prcm = {
2824 .omap4 = {
3b54baad 2825 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
9780a9cf
BC		 2826 },
2827 },
3b54baad
BC		 2828 .slaves = omap44xx_wd_timer2_slaves,
2829 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 2830 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2831};
2832
3b54baad
BC		 2833/* wd_timer3 */
2834static struct omap_hwmod omap44xx_wd_timer3_hwmod;
2835static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
2836 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 2837};
2838
3b54baad 2839static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 2840 {
3b54baad
BC		 2841 .pa_start = 0x40130000,
2842 .pa_end = 0x4013007f,
9780a9cf
BC		 2843 .flags = ADDR_TYPE_RT
2844 },
2845};
2846
3b54baad
BC		 2847/* l4_abe -> wd_timer3 */
2848static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
2849 .master = &omap44xx_l4_abe_hwmod,
2850 .slave = &omap44xx_wd_timer3_hwmod,
2851 .clk = "ocp_abe_iclk",
2852 .addr = omap44xx_wd_timer3_addrs,
2853 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
2854 .user = OCP_USER_MPU,
9780a9cf
BC		 2855};
2856
3b54baad
BC		 2857static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
2858 {
2859 .pa_start = 0x49030000,
2860 .pa_end = 0x4903007f,
2861 .flags = ADDR_TYPE_RT
2862 },
9780a9cf
BC		 2863};
2864
3b54baad
BC		 2865/* l4_abe -> wd_timer3 (dma) */
2866static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
2867 .master = &omap44xx_l4_abe_hwmod,
2868 .slave = &omap44xx_wd_timer3_hwmod,
2869 .clk = "ocp_abe_iclk",
2870 .addr = omap44xx_wd_timer3_dma_addrs,
2871 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
2872 .user = OCP_USER_SDMA,
9780a9cf
BC		 2873};
2874
3b54baad
BC		 2875/* wd_timer3 slave ports */
2876static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
2877 &omap44xx_l4_abe__wd_timer3,
2878 &omap44xx_l4_abe__wd_timer3_dma,
2879};
2880
2881static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
2882 .name = "wd_timer3",
2883 .class = &omap44xx_wd_timer_hwmod_class,
2884 .mpu_irqs = omap44xx_wd_timer3_irqs,
2885 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
2886 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 2887 .prcm = {
2888 .omap4 = {
3b54baad 2889 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
9780a9cf
BC		 2890 },
2891 },
3b54baad
BC		 2892 .slaves = omap44xx_wd_timer3_slaves,
2893 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 2894 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2895};
531ce0d5 2896
55d2cb08 2897static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 2898
55d2cb08
BC		 2899 /* dmm class */
2900 &omap44xx_dmm_hwmod,
3b54baad 2901
55d2cb08
BC		 2902 /* emif_fw class */
2903 &omap44xx_emif_fw_hwmod,
3b54baad 2904
55d2cb08
BC		 2905 /* l3 class */
2906 &omap44xx_l3_instr_hwmod,
2907 &omap44xx_l3_main_1_hwmod,
2908 &omap44xx_l3_main_2_hwmod,
2909 &omap44xx_l3_main_3_hwmod,
3b54baad 2910
55d2cb08
BC		 2911 /* l4 class */
2912 &omap44xx_l4_abe_hwmod,
2913 &omap44xx_l4_cfg_hwmod,
2914 &omap44xx_l4_per_hwmod,
2915 &omap44xx_l4_wkup_hwmod,
531ce0d5 2916
55d2cb08
BC		 2917 /* mpu_bus class */
2918 &omap44xx_mpu_private_hwmod,
2919
d7cf5f33
BC		 2920 /* dma class */
2921 &omap44xx_dma_system_hwmod,
2922
8f25bdc5
BC		 2923 /* dsp class */
2924 &omap44xx_dsp_hwmod,
2925 &omap44xx_dsp_c0_hwmod,
2926
9780a9cf
BC		 2927 /* gpio class */
2928 &omap44xx_gpio1_hwmod,
2929 &omap44xx_gpio2_hwmod,
2930 &omap44xx_gpio3_hwmod,
2931 &omap44xx_gpio4_hwmod,
2932 &omap44xx_gpio5_hwmod,
2933 &omap44xx_gpio6_hwmod,
2934
3b54baad
BC		 2935 /* i2c class */
2936 &omap44xx_i2c1_hwmod,
2937 &omap44xx_i2c2_hwmod,
2938 &omap44xx_i2c3_hwmod,
2939 &omap44xx_i2c4_hwmod,
2940
8f25bdc5
BC		 2941 /* iva class */
2942 &omap44xx_iva_hwmod,
2943 &omap44xx_iva_seq0_hwmod,
2944 &omap44xx_iva_seq1_hwmod,
2945
9bcbd7f0
BC		 2946 /* mcspi class */
2947 &omap44xx_mcspi1_hwmod,
2948 &omap44xx_mcspi2_hwmod,
2949 &omap44xx_mcspi3_hwmod,
2950 &omap44xx_mcspi4_hwmod,
2951
55d2cb08
BC		 2952 /* mpu class */
2953 &omap44xx_mpu_hwmod,
db12ba53 2954
1f6a717f
BC		 2955 /* smartreflex class */
2956 &omap44xx_smartreflex_core_hwmod,
2957 &omap44xx_smartreflex_iva_hwmod,
2958 &omap44xx_smartreflex_mpu_hwmod,
2959
d11c217f
BC		 2960 /* spinlock class */
2961 &omap44xx_spinlock_hwmod,
2962
35d1a66a
BC		 2963 /* timer class */
2964 &omap44xx_timer1_hwmod,
2965 &omap44xx_timer2_hwmod,
2966 &omap44xx_timer3_hwmod,
2967 &omap44xx_timer4_hwmod,
2968 &omap44xx_timer5_hwmod,
2969 &omap44xx_timer6_hwmod,
2970 &omap44xx_timer7_hwmod,
2971 &omap44xx_timer8_hwmod,
2972 &omap44xx_timer9_hwmod,
2973 &omap44xx_timer10_hwmod,
2974 &omap44xx_timer11_hwmod,
2975
db12ba53
BC		 2976 /* uart class */
2977 &omap44xx_uart1_hwmod,
2978 &omap44xx_uart2_hwmod,
2979 &omap44xx_uart3_hwmod,
2980 &omap44xx_uart4_hwmod,
3b54baad
BC		 2981
2982 /* wd_timer class */
2983 &omap44xx_wd_timer2_hwmod,
2984 &omap44xx_wd_timer3_hwmod,
2985
55d2cb08
BC		 2986 NULL,
2987};
2988
2989int __init omap44xx_hwmod_init(void)
2990{
2991 return omap_hwmod_init(omap44xx_hwmods);
2992}
2993
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