]>
Commit | Line | Data |
---|---|---|
55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
9780a9cf | 25 | #include <plat/gpio.h> |
531ce0d5 | 26 | #include <plat/dma.h> |
55d2cb08 BC |
27 | |
28 | #include "omap_hwmod_common_data.h" | |
29 | ||
d198b514 PW |
30 | #include "cm1_44xx.h" |
31 | #include "cm2_44xx.h" | |
32 | #include "prm44xx.h" | |
55d2cb08 | 33 | #include "prm-regbits-44xx.h" |
ff2516fb | 34 | #include "wd_timer.h" |
55d2cb08 BC |
35 | |
36 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
37 | #define OMAP44XX_IRQ_GIC_START 32 | |
38 | ||
39 | /* Base offset for all OMAP4 dma requests */ | |
40 | #define OMAP44XX_DMA_REQ_START 1 | |
41 | ||
42 | /* Backward references (IPs with Bus Master capability) */ | |
531ce0d5 | 43 | static struct omap_hwmod omap44xx_dma_system_hwmod; |
55d2cb08 BC |
44 | static struct omap_hwmod omap44xx_dmm_hwmod; |
45 | static struct omap_hwmod omap44xx_emif_fw_hwmod; | |
46 | static struct omap_hwmod omap44xx_l3_instr_hwmod; | |
47 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; | |
48 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; | |
49 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; | |
50 | static struct omap_hwmod omap44xx_l4_abe_hwmod; | |
51 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; | |
52 | static struct omap_hwmod omap44xx_l4_per_hwmod; | |
53 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; | |
54 | static struct omap_hwmod omap44xx_mpu_hwmod; | |
55 | static struct omap_hwmod omap44xx_mpu_private_hwmod; | |
56 | ||
57 | /* | |
58 | * Interconnects omap_hwmod structures | |
59 | * hwmods that compose the global OMAP interconnect | |
60 | */ | |
61 | ||
62 | /* | |
63 | * 'dmm' class | |
64 | * instance(s): dmm | |
65 | */ | |
66 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
67 | .name = "dmm", | |
68 | }; | |
69 | ||
70 | /* dmm interface data */ | |
71 | /* l3_main_1 -> dmm */ | |
72 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
73 | .master = &omap44xx_l3_main_1_hwmod, | |
74 | .slave = &omap44xx_dmm_hwmod, | |
75 | .clk = "l3_div_ck", | |
76 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
77 | }; | |
78 | ||
79 | /* mpu -> dmm */ | |
80 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
81 | .master = &omap44xx_mpu_hwmod, | |
82 | .slave = &omap44xx_dmm_hwmod, | |
83 | .clk = "l3_div_ck", | |
84 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
85 | }; | |
86 | ||
87 | /* dmm slave ports */ | |
88 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { | |
89 | &omap44xx_l3_main_1__dmm, | |
90 | &omap44xx_mpu__dmm, | |
91 | }; | |
92 | ||
93 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
94 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
95 | }; | |
96 | ||
97 | static struct omap_hwmod omap44xx_dmm_hwmod = { | |
98 | .name = "dmm", | |
99 | .class = &omap44xx_dmm_hwmod_class, | |
100 | .slaves = omap44xx_dmm_slaves, | |
101 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | |
102 | .mpu_irqs = omap44xx_dmm_irqs, | |
103 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), | |
104 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
105 | }; | |
106 | ||
107 | /* | |
108 | * 'emif_fw' class | |
109 | * instance(s): emif_fw | |
110 | */ | |
111 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
112 | .name = "emif_fw", | |
113 | }; | |
114 | ||
115 | /* emif_fw interface data */ | |
116 | /* dmm -> emif_fw */ | |
117 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
118 | .master = &omap44xx_dmm_hwmod, | |
119 | .slave = &omap44xx_emif_fw_hwmod, | |
120 | .clk = "l3_div_ck", | |
121 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
122 | }; | |
123 | ||
124 | /* l4_cfg -> emif_fw */ | |
125 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
126 | .master = &omap44xx_l4_cfg_hwmod, | |
127 | .slave = &omap44xx_emif_fw_hwmod, | |
128 | .clk = "l4_div_ck", | |
129 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
130 | }; | |
131 | ||
132 | /* emif_fw slave ports */ | |
133 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { | |
134 | &omap44xx_dmm__emif_fw, | |
135 | &omap44xx_l4_cfg__emif_fw, | |
136 | }; | |
137 | ||
138 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |
139 | .name = "emif_fw", | |
140 | .class = &omap44xx_emif_fw_hwmod_class, | |
141 | .slaves = omap44xx_emif_fw_slaves, | |
142 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), | |
143 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
144 | }; | |
145 | ||
146 | /* | |
147 | * 'l3' class | |
148 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
149 | */ | |
150 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
151 | .name = "l3", | |
152 | }; | |
153 | ||
154 | /* l3_instr interface data */ | |
155 | /* l3_main_3 -> l3_instr */ | |
156 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
157 | .master = &omap44xx_l3_main_3_hwmod, | |
158 | .slave = &omap44xx_l3_instr_hwmod, | |
159 | .clk = "l3_div_ck", | |
160 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
161 | }; | |
162 | ||
163 | /* l3_instr slave ports */ | |
164 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { | |
165 | &omap44xx_l3_main_3__l3_instr, | |
166 | }; | |
167 | ||
168 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |
169 | .name = "l3_instr", | |
170 | .class = &omap44xx_l3_hwmod_class, | |
171 | .slaves = omap44xx_l3_instr_slaves, | |
172 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), | |
173 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
174 | }; | |
175 | ||
3b54baad | 176 | /* l3_main_1 interface data */ |
55d2cb08 BC |
177 | /* l3_main_2 -> l3_main_1 */ |
178 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
179 | .master = &omap44xx_l3_main_2_hwmod, | |
180 | .slave = &omap44xx_l3_main_1_hwmod, | |
181 | .clk = "l3_div_ck", | |
182 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
183 | }; | |
184 | ||
185 | /* l4_cfg -> l3_main_1 */ | |
186 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
187 | .master = &omap44xx_l4_cfg_hwmod, | |
188 | .slave = &omap44xx_l3_main_1_hwmod, | |
189 | .clk = "l4_div_ck", | |
190 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
191 | }; | |
192 | ||
193 | /* mpu -> l3_main_1 */ | |
194 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
195 | .master = &omap44xx_mpu_hwmod, | |
196 | .slave = &omap44xx_l3_main_1_hwmod, | |
197 | .clk = "l3_div_ck", | |
198 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
199 | }; | |
200 | ||
201 | /* l3_main_1 slave ports */ | |
202 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { | |
203 | &omap44xx_l3_main_2__l3_main_1, | |
204 | &omap44xx_l4_cfg__l3_main_1, | |
205 | &omap44xx_mpu__l3_main_1, | |
206 | }; | |
207 | ||
208 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |
209 | .name = "l3_main_1", | |
210 | .class = &omap44xx_l3_hwmod_class, | |
211 | .slaves = omap44xx_l3_main_1_slaves, | |
212 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | |
213 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
214 | }; | |
215 | ||
216 | /* l3_main_2 interface data */ | |
217 | /* l3_main_1 -> l3_main_2 */ | |
218 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
219 | .master = &omap44xx_l3_main_1_hwmod, | |
220 | .slave = &omap44xx_l3_main_2_hwmod, | |
221 | .clk = "l3_div_ck", | |
222 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
223 | }; | |
224 | ||
531ce0d5 BC |
225 | /* dma_system -> l3_main_2 */ |
226 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
227 | .master = &omap44xx_dma_system_hwmod, | |
228 | .slave = &omap44xx_l3_main_2_hwmod, | |
229 | .clk = "l3_div_ck", | |
230 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
231 | }; | |
232 | ||
55d2cb08 BC |
233 | /* l4_cfg -> l3_main_2 */ |
234 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
235 | .master = &omap44xx_l4_cfg_hwmod, | |
236 | .slave = &omap44xx_l3_main_2_hwmod, | |
237 | .clk = "l4_div_ck", | |
238 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
239 | }; | |
240 | ||
241 | /* l3_main_2 slave ports */ | |
242 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { | |
531ce0d5 | 243 | &omap44xx_dma_system__l3_main_2, |
55d2cb08 BC |
244 | &omap44xx_l3_main_1__l3_main_2, |
245 | &omap44xx_l4_cfg__l3_main_2, | |
246 | }; | |
247 | ||
248 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { | |
249 | .name = "l3_main_2", | |
250 | .class = &omap44xx_l3_hwmod_class, | |
251 | .slaves = omap44xx_l3_main_2_slaves, | |
252 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), | |
253 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
254 | }; | |
255 | ||
256 | /* l3_main_3 interface data */ | |
257 | /* l3_main_1 -> l3_main_3 */ | |
258 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
259 | .master = &omap44xx_l3_main_1_hwmod, | |
260 | .slave = &omap44xx_l3_main_3_hwmod, | |
261 | .clk = "l3_div_ck", | |
262 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
263 | }; | |
264 | ||
265 | /* l3_main_2 -> l3_main_3 */ | |
266 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
267 | .master = &omap44xx_l3_main_2_hwmod, | |
268 | .slave = &omap44xx_l3_main_3_hwmod, | |
269 | .clk = "l3_div_ck", | |
270 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
271 | }; | |
272 | ||
273 | /* l4_cfg -> l3_main_3 */ | |
274 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
275 | .master = &omap44xx_l4_cfg_hwmod, | |
276 | .slave = &omap44xx_l3_main_3_hwmod, | |
277 | .clk = "l4_div_ck", | |
278 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
279 | }; | |
280 | ||
281 | /* l3_main_3 slave ports */ | |
282 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { | |
283 | &omap44xx_l3_main_1__l3_main_3, | |
284 | &omap44xx_l3_main_2__l3_main_3, | |
285 | &omap44xx_l4_cfg__l3_main_3, | |
286 | }; | |
287 | ||
288 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |
289 | .name = "l3_main_3", | |
290 | .class = &omap44xx_l3_hwmod_class, | |
291 | .slaves = omap44xx_l3_main_3_slaves, | |
292 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), | |
293 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
294 | }; | |
295 | ||
296 | /* | |
297 | * 'l4' class | |
298 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
299 | */ | |
300 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
301 | .name = "l4", | |
302 | }; | |
303 | ||
304 | /* l4_abe interface data */ | |
305 | /* l3_main_1 -> l4_abe */ | |
306 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
307 | .master = &omap44xx_l3_main_1_hwmod, | |
308 | .slave = &omap44xx_l4_abe_hwmod, | |
309 | .clk = "l3_div_ck", | |
310 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
311 | }; | |
312 | ||
313 | /* mpu -> l4_abe */ | |
314 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
315 | .master = &omap44xx_mpu_hwmod, | |
316 | .slave = &omap44xx_l4_abe_hwmod, | |
317 | .clk = "ocp_abe_iclk", | |
318 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
319 | }; | |
320 | ||
321 | /* l4_abe slave ports */ | |
322 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { | |
323 | &omap44xx_l3_main_1__l4_abe, | |
324 | &omap44xx_mpu__l4_abe, | |
325 | }; | |
326 | ||
327 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { | |
328 | .name = "l4_abe", | |
329 | .class = &omap44xx_l4_hwmod_class, | |
330 | .slaves = omap44xx_l4_abe_slaves, | |
331 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), | |
332 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
333 | }; | |
334 | ||
335 | /* l4_cfg interface data */ | |
336 | /* l3_main_1 -> l4_cfg */ | |
337 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
338 | .master = &omap44xx_l3_main_1_hwmod, | |
339 | .slave = &omap44xx_l4_cfg_hwmod, | |
340 | .clk = "l3_div_ck", | |
341 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
342 | }; | |
343 | ||
344 | /* l4_cfg slave ports */ | |
345 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { | |
346 | &omap44xx_l3_main_1__l4_cfg, | |
347 | }; | |
348 | ||
349 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { | |
350 | .name = "l4_cfg", | |
351 | .class = &omap44xx_l4_hwmod_class, | |
352 | .slaves = omap44xx_l4_cfg_slaves, | |
353 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), | |
354 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
355 | }; | |
356 | ||
357 | /* l4_per interface data */ | |
358 | /* l3_main_2 -> l4_per */ | |
359 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
360 | .master = &omap44xx_l3_main_2_hwmod, | |
361 | .slave = &omap44xx_l4_per_hwmod, | |
362 | .clk = "l3_div_ck", | |
363 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
364 | }; | |
365 | ||
366 | /* l4_per slave ports */ | |
367 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { | |
368 | &omap44xx_l3_main_2__l4_per, | |
369 | }; | |
370 | ||
371 | static struct omap_hwmod omap44xx_l4_per_hwmod = { | |
372 | .name = "l4_per", | |
373 | .class = &omap44xx_l4_hwmod_class, | |
374 | .slaves = omap44xx_l4_per_slaves, | |
375 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), | |
376 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
377 | }; | |
378 | ||
379 | /* l4_wkup interface data */ | |
380 | /* l4_cfg -> l4_wkup */ | |
381 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
382 | .master = &omap44xx_l4_cfg_hwmod, | |
383 | .slave = &omap44xx_l4_wkup_hwmod, | |
384 | .clk = "l4_div_ck", | |
385 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
386 | }; | |
387 | ||
388 | /* l4_wkup slave ports */ | |
389 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { | |
390 | &omap44xx_l4_cfg__l4_wkup, | |
391 | }; | |
392 | ||
393 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |
394 | .name = "l4_wkup", | |
395 | .class = &omap44xx_l4_hwmod_class, | |
396 | .slaves = omap44xx_l4_wkup_slaves, | |
397 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), | |
398 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
399 | }; | |
400 | ||
f776471f | 401 | /* |
3b54baad BC |
402 | * 'mpu_bus' class |
403 | * instance(s): mpu_private | |
f776471f | 404 | */ |
3b54baad BC |
405 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
406 | .name = "mpu_bus", | |
407 | }; | |
f776471f | 408 | |
3b54baad BC |
409 | /* mpu_private interface data */ |
410 | /* mpu -> mpu_private */ | |
411 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
412 | .master = &omap44xx_mpu_hwmod, | |
413 | .slave = &omap44xx_mpu_private_hwmod, | |
414 | .clk = "l3_div_ck", | |
415 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
416 | }; | |
417 | ||
418 | /* mpu_private slave ports */ | |
419 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { | |
420 | &omap44xx_mpu__mpu_private, | |
421 | }; | |
422 | ||
423 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |
424 | .name = "mpu_private", | |
425 | .class = &omap44xx_mpu_bus_hwmod_class, | |
426 | .slaves = omap44xx_mpu_private_slaves, | |
427 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), | |
428 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
429 | }; | |
430 | ||
431 | /* | |
432 | * Modules omap_hwmod structures | |
433 | * | |
434 | * The following IPs are excluded for the moment because: | |
435 | * - They do not need an explicit SW control using omap_hwmod API. | |
436 | * - They still need to be validated with the driver | |
437 | * properly adapted to omap_hwmod / omap_device | |
438 | * | |
439 | * aess | |
440 | * bandgap | |
441 | * c2c | |
442 | * c2c_target_fw | |
443 | * cm_core | |
444 | * cm_core_aon | |
445 | * counter_32k | |
446 | * ctrl_module_core | |
447 | * ctrl_module_pad_core | |
448 | * ctrl_module_pad_wkup | |
449 | * ctrl_module_wkup | |
450 | * debugss | |
451 | * dma_system | |
452 | * dmic | |
453 | * dsp | |
454 | * dss | |
455 | * dss_dispc | |
456 | * dss_dsi1 | |
457 | * dss_dsi2 | |
458 | * dss_hdmi | |
459 | * dss_rfbi | |
460 | * dss_venc | |
461 | * efuse_ctrl_cust | |
462 | * efuse_ctrl_std | |
463 | * elm | |
464 | * emif1 | |
465 | * emif2 | |
466 | * fdif | |
467 | * gpmc | |
468 | * gpu | |
469 | * hdq1w | |
470 | * hsi | |
471 | * ipu | |
472 | * iss | |
473 | * iva | |
474 | * kbd | |
475 | * mailbox | |
476 | * mcasp | |
477 | * mcbsp1 | |
478 | * mcbsp2 | |
479 | * mcbsp3 | |
480 | * mcbsp4 | |
481 | * mcpdm | |
482 | * mcspi1 | |
483 | * mcspi2 | |
484 | * mcspi3 | |
485 | * mcspi4 | |
486 | * mmc1 | |
487 | * mmc2 | |
488 | * mmc3 | |
489 | * mmc4 | |
490 | * mmc5 | |
491 | * mpu_c0 | |
492 | * mpu_c1 | |
493 | * ocmc_ram | |
494 | * ocp2scp_usb_phy | |
495 | * ocp_wp_noc | |
496 | * prcm | |
497 | * prcm_mpu | |
498 | * prm | |
499 | * scrm | |
500 | * sl2if | |
501 | * slimbus1 | |
502 | * slimbus2 | |
503 | * smartreflex_core | |
504 | * smartreflex_iva | |
505 | * smartreflex_mpu | |
506 | * spinlock | |
507 | * timer1 | |
508 | * timer10 | |
509 | * timer11 | |
510 | * timer2 | |
511 | * timer3 | |
512 | * timer4 | |
513 | * timer5 | |
514 | * timer6 | |
515 | * timer7 | |
516 | * timer8 | |
517 | * timer9 | |
518 | * usb_host_fs | |
519 | * usb_host_hs | |
520 | * usb_otg_hs | |
521 | * usb_phy_cm | |
522 | * usb_tll_hs | |
523 | * usim | |
524 | */ | |
525 | ||
526 | /* | |
527 | * 'gpio' class | |
528 | * general purpose io module | |
529 | */ | |
530 | ||
531 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
532 | .rev_offs = 0x0000, | |
f776471f | 533 | .sysc_offs = 0x0010, |
3b54baad | 534 | .syss_offs = 0x0114, |
f776471f | 535 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
3b54baad | 536 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
f776471f BC |
537 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
538 | .sysc_fields = &omap_hwmod_sysc_type1, | |
539 | }; | |
540 | ||
3b54baad BC |
541 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
542 | .name = "gpio", | |
543 | .sysc = &omap44xx_gpio_sysc, | |
544 | .rev = 2, | |
f776471f BC |
545 | }; |
546 | ||
3b54baad BC |
547 | /* gpio dev_attr */ |
548 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
549 | .bank_width = 32, | |
550 | .dbck_flag = true, | |
f776471f BC |
551 | }; |
552 | ||
3b54baad BC |
553 | /* gpio1 */ |
554 | static struct omap_hwmod omap44xx_gpio1_hwmod; | |
555 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | |
556 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
557 | }; |
558 | ||
3b54baad | 559 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
f776471f | 560 | { |
3b54baad BC |
561 | .pa_start = 0x4a310000, |
562 | .pa_end = 0x4a3101ff, | |
f776471f BC |
563 | .flags = ADDR_TYPE_RT |
564 | }, | |
565 | }; | |
566 | ||
3b54baad BC |
567 | /* l4_wkup -> gpio1 */ |
568 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
569 | .master = &omap44xx_l4_wkup_hwmod, | |
570 | .slave = &omap44xx_gpio1_hwmod, | |
571 | .addr = omap44xx_gpio1_addrs, | |
572 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), | |
f776471f BC |
573 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
574 | }; | |
575 | ||
3b54baad BC |
576 | /* gpio1 slave ports */ |
577 | static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { | |
578 | &omap44xx_l4_wkup__gpio1, | |
f776471f BC |
579 | }; |
580 | ||
3b54baad BC |
581 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
582 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
583 | }; | |
584 | ||
585 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
586 | .name = "gpio1", | |
587 | .class = &omap44xx_gpio_hwmod_class, | |
588 | .mpu_irqs = omap44xx_gpio1_irqs, | |
589 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), | |
590 | .main_clk = "gpio1_ick", | |
f776471f BC |
591 | .prcm = { |
592 | .omap4 = { | |
3b54baad | 593 | .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
f776471f BC |
594 | }, |
595 | }, | |
3b54baad BC |
596 | .opt_clks = gpio1_opt_clks, |
597 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
598 | .dev_attr = &gpio_dev_attr, | |
599 | .slaves = omap44xx_gpio1_slaves, | |
600 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), | |
f776471f BC |
601 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
602 | }; | |
603 | ||
3b54baad BC |
604 | /* gpio2 */ |
605 | static struct omap_hwmod omap44xx_gpio2_hwmod; | |
606 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | |
607 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
608 | }; |
609 | ||
3b54baad | 610 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
f776471f | 611 | { |
3b54baad BC |
612 | .pa_start = 0x48055000, |
613 | .pa_end = 0x480551ff, | |
f776471f BC |
614 | .flags = ADDR_TYPE_RT |
615 | }, | |
616 | }; | |
617 | ||
3b54baad BC |
618 | /* l4_per -> gpio2 */ |
619 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
f776471f | 620 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
621 | .slave = &omap44xx_gpio2_hwmod, |
622 | .addr = omap44xx_gpio2_addrs, | |
623 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), | |
f776471f BC |
624 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
625 | }; | |
626 | ||
3b54baad BC |
627 | /* gpio2 slave ports */ |
628 | static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { | |
629 | &omap44xx_l4_per__gpio2, | |
f776471f BC |
630 | }; |
631 | ||
3b54baad BC |
632 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
633 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
634 | }; | |
635 | ||
636 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
637 | .name = "gpio2", | |
638 | .class = &omap44xx_gpio_hwmod_class, | |
639 | .mpu_irqs = omap44xx_gpio2_irqs, | |
640 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), | |
641 | .main_clk = "gpio2_ick", | |
f776471f BC |
642 | .prcm = { |
643 | .omap4 = { | |
3b54baad | 644 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
f776471f BC |
645 | }, |
646 | }, | |
3b54baad BC |
647 | .opt_clks = gpio2_opt_clks, |
648 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
649 | .dev_attr = &gpio_dev_attr, | |
650 | .slaves = omap44xx_gpio2_slaves, | |
651 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), | |
f776471f BC |
652 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
653 | }; | |
654 | ||
3b54baad BC |
655 | /* gpio3 */ |
656 | static struct omap_hwmod omap44xx_gpio3_hwmod; | |
657 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | |
658 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
659 | }; |
660 | ||
3b54baad | 661 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
f776471f | 662 | { |
3b54baad BC |
663 | .pa_start = 0x48057000, |
664 | .pa_end = 0x480571ff, | |
f776471f BC |
665 | .flags = ADDR_TYPE_RT |
666 | }, | |
667 | }; | |
668 | ||
3b54baad BC |
669 | /* l4_per -> gpio3 */ |
670 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
f776471f | 671 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
672 | .slave = &omap44xx_gpio3_hwmod, |
673 | .addr = omap44xx_gpio3_addrs, | |
674 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), | |
f776471f BC |
675 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
676 | }; | |
677 | ||
3b54baad BC |
678 | /* gpio3 slave ports */ |
679 | static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { | |
680 | &omap44xx_l4_per__gpio3, | |
f776471f BC |
681 | }; |
682 | ||
3b54baad BC |
683 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
684 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
685 | }; | |
686 | ||
687 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
688 | .name = "gpio3", | |
689 | .class = &omap44xx_gpio_hwmod_class, | |
690 | .mpu_irqs = omap44xx_gpio3_irqs, | |
691 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), | |
692 | .main_clk = "gpio3_ick", | |
f776471f BC |
693 | .prcm = { |
694 | .omap4 = { | |
3b54baad | 695 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
f776471f BC |
696 | }, |
697 | }, | |
3b54baad BC |
698 | .opt_clks = gpio3_opt_clks, |
699 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
700 | .dev_attr = &gpio_dev_attr, | |
701 | .slaves = omap44xx_gpio3_slaves, | |
702 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), | |
f776471f BC |
703 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
704 | }; | |
705 | ||
3b54baad BC |
706 | /* gpio4 */ |
707 | static struct omap_hwmod omap44xx_gpio4_hwmod; | |
708 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | |
709 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
710 | }; |
711 | ||
3b54baad | 712 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
f776471f | 713 | { |
3b54baad BC |
714 | .pa_start = 0x48059000, |
715 | .pa_end = 0x480591ff, | |
f776471f BC |
716 | .flags = ADDR_TYPE_RT |
717 | }, | |
718 | }; | |
719 | ||
3b54baad BC |
720 | /* l4_per -> gpio4 */ |
721 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
f776471f | 722 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
723 | .slave = &omap44xx_gpio4_hwmod, |
724 | .addr = omap44xx_gpio4_addrs, | |
725 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), | |
f776471f BC |
726 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
727 | }; | |
728 | ||
3b54baad BC |
729 | /* gpio4 slave ports */ |
730 | static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { | |
731 | &omap44xx_l4_per__gpio4, | |
f776471f BC |
732 | }; |
733 | ||
3b54baad BC |
734 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
735 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
736 | }; | |
737 | ||
738 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
739 | .name = "gpio4", | |
740 | .class = &omap44xx_gpio_hwmod_class, | |
741 | .mpu_irqs = omap44xx_gpio4_irqs, | |
742 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), | |
743 | .main_clk = "gpio4_ick", | |
f776471f BC |
744 | .prcm = { |
745 | .omap4 = { | |
3b54baad | 746 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
f776471f BC |
747 | }, |
748 | }, | |
3b54baad BC |
749 | .opt_clks = gpio4_opt_clks, |
750 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
751 | .dev_attr = &gpio_dev_attr, | |
752 | .slaves = omap44xx_gpio4_slaves, | |
753 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), | |
f776471f BC |
754 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
755 | }; | |
756 | ||
3b54baad BC |
757 | /* gpio5 */ |
758 | static struct omap_hwmod omap44xx_gpio5_hwmod; | |
759 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | |
760 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
55d2cb08 BC |
761 | }; |
762 | ||
3b54baad BC |
763 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
764 | { | |
765 | .pa_start = 0x4805b000, | |
766 | .pa_end = 0x4805b1ff, | |
767 | .flags = ADDR_TYPE_RT | |
768 | }, | |
55d2cb08 BC |
769 | }; |
770 | ||
3b54baad BC |
771 | /* l4_per -> gpio5 */ |
772 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
773 | .master = &omap44xx_l4_per_hwmod, | |
774 | .slave = &omap44xx_gpio5_hwmod, | |
775 | .addr = omap44xx_gpio5_addrs, | |
776 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), | |
777 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
55d2cb08 BC |
778 | }; |
779 | ||
3b54baad BC |
780 | /* gpio5 slave ports */ |
781 | static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { | |
782 | &omap44xx_l4_per__gpio5, | |
55d2cb08 BC |
783 | }; |
784 | ||
3b54baad BC |
785 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
786 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
55d2cb08 BC |
787 | }; |
788 | ||
3b54baad BC |
789 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
790 | .name = "gpio5", | |
791 | .class = &omap44xx_gpio_hwmod_class, | |
792 | .mpu_irqs = omap44xx_gpio5_irqs, | |
793 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), | |
794 | .main_clk = "gpio5_ick", | |
55d2cb08 BC |
795 | .prcm = { |
796 | .omap4 = { | |
3b54baad | 797 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
55d2cb08 BC |
798 | }, |
799 | }, | |
3b54baad BC |
800 | .opt_clks = gpio5_opt_clks, |
801 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
802 | .dev_attr = &gpio_dev_attr, | |
803 | .slaves = omap44xx_gpio5_slaves, | |
804 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), | |
55d2cb08 BC |
805 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
806 | }; | |
807 | ||
3b54baad BC |
808 | /* gpio6 */ |
809 | static struct omap_hwmod omap44xx_gpio6_hwmod; | |
810 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | |
811 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
92b18d1c BC |
812 | }; |
813 | ||
3b54baad | 814 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
92b18d1c | 815 | { |
3b54baad BC |
816 | .pa_start = 0x4805d000, |
817 | .pa_end = 0x4805d1ff, | |
92b18d1c BC |
818 | .flags = ADDR_TYPE_RT |
819 | }, | |
820 | }; | |
821 | ||
3b54baad BC |
822 | /* l4_per -> gpio6 */ |
823 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
824 | .master = &omap44xx_l4_per_hwmod, | |
825 | .slave = &omap44xx_gpio6_hwmod, | |
826 | .addr = omap44xx_gpio6_addrs, | |
827 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), | |
828 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
db12ba53 BC |
829 | }; |
830 | ||
3b54baad BC |
831 | /* gpio6 slave ports */ |
832 | static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { | |
833 | &omap44xx_l4_per__gpio6, | |
db12ba53 BC |
834 | }; |
835 | ||
3b54baad BC |
836 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
837 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
db12ba53 BC |
838 | }; |
839 | ||
3b54baad BC |
840 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
841 | .name = "gpio6", | |
842 | .class = &omap44xx_gpio_hwmod_class, | |
843 | .mpu_irqs = omap44xx_gpio6_irqs, | |
844 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), | |
845 | .main_clk = "gpio6_ick", | |
846 | .prcm = { | |
847 | .omap4 = { | |
848 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
849 | }, | |
db12ba53 | 850 | }, |
3b54baad BC |
851 | .opt_clks = gpio6_opt_clks, |
852 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
853 | .dev_attr = &gpio_dev_attr, | |
854 | .slaves = omap44xx_gpio6_slaves, | |
855 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), | |
856 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
db12ba53 BC |
857 | }; |
858 | ||
3b54baad BC |
859 | /* |
860 | * 'i2c' class | |
861 | * multimaster high-speed i2c controller | |
862 | */ | |
db12ba53 | 863 | |
3b54baad BC |
864 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
865 | .sysc_offs = 0x0010, | |
866 | .syss_offs = 0x0090, | |
867 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
868 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
869 | SYSC_HAS_SOFTRESET), | |
870 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
871 | .sysc_fields = &omap_hwmod_sysc_type1, | |
db12ba53 BC |
872 | }; |
873 | ||
3b54baad BC |
874 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
875 | .name = "i2c", | |
876 | .sysc = &omap44xx_i2c_sysc, | |
db12ba53 BC |
877 | }; |
878 | ||
3b54baad BC |
879 | /* i2c1 */ |
880 | static struct omap_hwmod omap44xx_i2c1_hwmod; | |
881 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | |
882 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
883 | }; |
884 | ||
3b54baad BC |
885 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
886 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
887 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
db12ba53 BC |
888 | }; |
889 | ||
3b54baad | 890 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
db12ba53 | 891 | { |
3b54baad BC |
892 | .pa_start = 0x48070000, |
893 | .pa_end = 0x480700ff, | |
db12ba53 BC |
894 | .flags = ADDR_TYPE_RT |
895 | }, | |
896 | }; | |
897 | ||
3b54baad BC |
898 | /* l4_per -> i2c1 */ |
899 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
900 | .master = &omap44xx_l4_per_hwmod, | |
901 | .slave = &omap44xx_i2c1_hwmod, | |
902 | .clk = "l4_div_ck", | |
903 | .addr = omap44xx_i2c1_addrs, | |
904 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), | |
92b18d1c BC |
905 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
906 | }; | |
907 | ||
3b54baad BC |
908 | /* i2c1 slave ports */ |
909 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | |
910 | &omap44xx_l4_per__i2c1, | |
92b18d1c BC |
911 | }; |
912 | ||
3b54baad BC |
913 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
914 | .name = "i2c1", | |
915 | .class = &omap44xx_i2c_hwmod_class, | |
916 | .flags = HWMOD_INIT_NO_RESET, | |
917 | .mpu_irqs = omap44xx_i2c1_irqs, | |
918 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), | |
919 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | |
920 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), | |
921 | .main_clk = "i2c1_fck", | |
92b18d1c BC |
922 | .prcm = { |
923 | .omap4 = { | |
3b54baad | 924 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
92b18d1c BC |
925 | }, |
926 | }, | |
3b54baad BC |
927 | .slaves = omap44xx_i2c1_slaves, |
928 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | |
92b18d1c BC |
929 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
930 | }; | |
931 | ||
3b54baad BC |
932 | /* i2c2 */ |
933 | static struct omap_hwmod omap44xx_i2c2_hwmod; | |
934 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | |
935 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
92b18d1c BC |
936 | }; |
937 | ||
3b54baad BC |
938 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
939 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
940 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
941 | }; | |
942 | ||
943 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
92b18d1c | 944 | { |
3b54baad BC |
945 | .pa_start = 0x48072000, |
946 | .pa_end = 0x480720ff, | |
92b18d1c BC |
947 | .flags = ADDR_TYPE_RT |
948 | }, | |
949 | }; | |
950 | ||
3b54baad BC |
951 | /* l4_per -> i2c2 */ |
952 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
db12ba53 | 953 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 954 | .slave = &omap44xx_i2c2_hwmod, |
db12ba53 | 955 | .clk = "l4_div_ck", |
3b54baad BC |
956 | .addr = omap44xx_i2c2_addrs, |
957 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), | |
db12ba53 BC |
958 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
959 | }; | |
960 | ||
3b54baad BC |
961 | /* i2c2 slave ports */ |
962 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | |
963 | &omap44xx_l4_per__i2c2, | |
db12ba53 BC |
964 | }; |
965 | ||
3b54baad BC |
966 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
967 | .name = "i2c2", | |
968 | .class = &omap44xx_i2c_hwmod_class, | |
969 | .flags = HWMOD_INIT_NO_RESET, | |
970 | .mpu_irqs = omap44xx_i2c2_irqs, | |
971 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), | |
972 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | |
973 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), | |
974 | .main_clk = "i2c2_fck", | |
db12ba53 BC |
975 | .prcm = { |
976 | .omap4 = { | |
3b54baad | 977 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
db12ba53 BC |
978 | }, |
979 | }, | |
3b54baad BC |
980 | .slaves = omap44xx_i2c2_slaves, |
981 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | |
db12ba53 BC |
982 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
983 | }; | |
984 | ||
3b54baad BC |
985 | /* i2c3 */ |
986 | static struct omap_hwmod omap44xx_i2c3_hwmod; | |
987 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | |
988 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
989 | }; |
990 | ||
3b54baad BC |
991 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
992 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
993 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
92b18d1c BC |
994 | }; |
995 | ||
3b54baad | 996 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
92b18d1c | 997 | { |
3b54baad BC |
998 | .pa_start = 0x48060000, |
999 | .pa_end = 0x480600ff, | |
92b18d1c BC |
1000 | .flags = ADDR_TYPE_RT |
1001 | }, | |
1002 | }; | |
1003 | ||
3b54baad BC |
1004 | /* l4_per -> i2c3 */ |
1005 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
db12ba53 | 1006 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1007 | .slave = &omap44xx_i2c3_hwmod, |
db12ba53 | 1008 | .clk = "l4_div_ck", |
3b54baad BC |
1009 | .addr = omap44xx_i2c3_addrs, |
1010 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), | |
db12ba53 BC |
1011 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1012 | }; | |
1013 | ||
3b54baad BC |
1014 | /* i2c3 slave ports */ |
1015 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | |
1016 | &omap44xx_l4_per__i2c3, | |
db12ba53 BC |
1017 | }; |
1018 | ||
3b54baad BC |
1019 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1020 | .name = "i2c3", | |
1021 | .class = &omap44xx_i2c_hwmod_class, | |
1022 | .flags = HWMOD_INIT_NO_RESET, | |
1023 | .mpu_irqs = omap44xx_i2c3_irqs, | |
1024 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), | |
1025 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | |
1026 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), | |
1027 | .main_clk = "i2c3_fck", | |
db12ba53 BC |
1028 | .prcm = { |
1029 | .omap4 = { | |
3b54baad | 1030 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
db12ba53 BC |
1031 | }, |
1032 | }, | |
3b54baad BC |
1033 | .slaves = omap44xx_i2c3_slaves, |
1034 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | |
db12ba53 BC |
1035 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1036 | }; | |
1037 | ||
3b54baad BC |
1038 | /* i2c4 */ |
1039 | static struct omap_hwmod omap44xx_i2c4_hwmod; | |
1040 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | |
1041 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1042 | }; |
1043 | ||
3b54baad BC |
1044 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1045 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1046 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
db12ba53 BC |
1047 | }; |
1048 | ||
3b54baad | 1049 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
db12ba53 | 1050 | { |
3b54baad BC |
1051 | .pa_start = 0x48350000, |
1052 | .pa_end = 0x483500ff, | |
db12ba53 BC |
1053 | .flags = ADDR_TYPE_RT |
1054 | }, | |
1055 | }; | |
1056 | ||
3b54baad BC |
1057 | /* l4_per -> i2c4 */ |
1058 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
1059 | .master = &omap44xx_l4_per_hwmod, | |
1060 | .slave = &omap44xx_i2c4_hwmod, | |
1061 | .clk = "l4_div_ck", | |
1062 | .addr = omap44xx_i2c4_addrs, | |
1063 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), | |
1064 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
92b18d1c BC |
1065 | }; |
1066 | ||
3b54baad BC |
1067 | /* i2c4 slave ports */ |
1068 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | |
1069 | &omap44xx_l4_per__i2c4, | |
92b18d1c BC |
1070 | }; |
1071 | ||
3b54baad BC |
1072 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1073 | .name = "i2c4", | |
1074 | .class = &omap44xx_i2c_hwmod_class, | |
1075 | .flags = HWMOD_INIT_NO_RESET, | |
1076 | .mpu_irqs = omap44xx_i2c4_irqs, | |
1077 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), | |
1078 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | |
1079 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), | |
1080 | .main_clk = "i2c4_fck", | |
92b18d1c BC |
1081 | .prcm = { |
1082 | .omap4 = { | |
3b54baad | 1083 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
92b18d1c BC |
1084 | }, |
1085 | }, | |
3b54baad BC |
1086 | .slaves = omap44xx_i2c4_slaves, |
1087 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | |
92b18d1c BC |
1088 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1089 | }; | |
1090 | ||
3b54baad BC |
1091 | /* |
1092 | * 'mpu' class | |
1093 | * mpu sub-system | |
1094 | */ | |
1095 | ||
1096 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
1097 | .name = "mpu", | |
db12ba53 BC |
1098 | }; |
1099 | ||
3b54baad BC |
1100 | /* mpu */ |
1101 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
1102 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
1103 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
1104 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1105 | }; |
1106 | ||
3b54baad BC |
1107 | /* mpu master ports */ |
1108 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { | |
1109 | &omap44xx_mpu__l3_main_1, | |
1110 | &omap44xx_mpu__l4_abe, | |
1111 | &omap44xx_mpu__dmm, | |
1112 | }; | |
1113 | ||
1114 | static struct omap_hwmod omap44xx_mpu_hwmod = { | |
1115 | .name = "mpu", | |
1116 | .class = &omap44xx_mpu_hwmod_class, | |
1117 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
1118 | .mpu_irqs = omap44xx_mpu_irqs, | |
1119 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), | |
1120 | .main_clk = "dpll_mpu_m2_ck", | |
db12ba53 BC |
1121 | .prcm = { |
1122 | .omap4 = { | |
3b54baad | 1123 | .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, |
db12ba53 BC |
1124 | }, |
1125 | }, | |
3b54baad BC |
1126 | .masters = omap44xx_mpu_masters, |
1127 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), | |
db12ba53 BC |
1128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1129 | }; | |
1130 | ||
9780a9cf | 1131 | /* |
3b54baad BC |
1132 | * 'uart' class |
1133 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
1134 | */ |
1135 | ||
3b54baad BC |
1136 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
1137 | .rev_offs = 0x0050, | |
1138 | .sysc_offs = 0x0054, | |
1139 | .syss_offs = 0x0058, | |
1140 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
1141 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
9780a9cf BC |
1142 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1143 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1144 | }; | |
1145 | ||
3b54baad BC |
1146 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
1147 | .name = "uart", | |
1148 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
1149 | }; |
1150 | ||
3b54baad BC |
1151 | /* uart1 */ |
1152 | static struct omap_hwmod omap44xx_uart1_hwmod; | |
1153 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | |
1154 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1155 | }; |
1156 | ||
3b54baad BC |
1157 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
1158 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
1159 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
9780a9cf BC |
1160 | }; |
1161 | ||
3b54baad | 1162 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
9780a9cf | 1163 | { |
3b54baad BC |
1164 | .pa_start = 0x4806a000, |
1165 | .pa_end = 0x4806a0ff, | |
9780a9cf BC |
1166 | .flags = ADDR_TYPE_RT |
1167 | }, | |
1168 | }; | |
1169 | ||
3b54baad BC |
1170 | /* l4_per -> uart1 */ |
1171 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
1172 | .master = &omap44xx_l4_per_hwmod, | |
1173 | .slave = &omap44xx_uart1_hwmod, | |
1174 | .clk = "l4_div_ck", | |
1175 | .addr = omap44xx_uart1_addrs, | |
1176 | .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), | |
9780a9cf BC |
1177 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1178 | }; | |
1179 | ||
3b54baad BC |
1180 | /* uart1 slave ports */ |
1181 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { | |
1182 | &omap44xx_l4_per__uart1, | |
9780a9cf BC |
1183 | }; |
1184 | ||
3b54baad BC |
1185 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
1186 | .name = "uart1", | |
1187 | .class = &omap44xx_uart_hwmod_class, | |
1188 | .mpu_irqs = omap44xx_uart1_irqs, | |
1189 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), | |
1190 | .sdma_reqs = omap44xx_uart1_sdma_reqs, | |
1191 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), | |
1192 | .main_clk = "uart1_fck", | |
9780a9cf BC |
1193 | .prcm = { |
1194 | .omap4 = { | |
3b54baad | 1195 | .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
9780a9cf BC |
1196 | }, |
1197 | }, | |
3b54baad BC |
1198 | .slaves = omap44xx_uart1_slaves, |
1199 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), | |
9780a9cf BC |
1200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1201 | }; | |
1202 | ||
3b54baad BC |
1203 | /* uart2 */ |
1204 | static struct omap_hwmod omap44xx_uart2_hwmod; | |
1205 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | |
1206 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1207 | }; |
1208 | ||
3b54baad BC |
1209 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
1210 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
1211 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
1212 | }; | |
1213 | ||
1214 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | |
9780a9cf | 1215 | { |
3b54baad BC |
1216 | .pa_start = 0x4806c000, |
1217 | .pa_end = 0x4806c0ff, | |
9780a9cf BC |
1218 | .flags = ADDR_TYPE_RT |
1219 | }, | |
1220 | }; | |
1221 | ||
3b54baad BC |
1222 | /* l4_per -> uart2 */ |
1223 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
9780a9cf | 1224 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
1225 | .slave = &omap44xx_uart2_hwmod, |
1226 | .clk = "l4_div_ck", | |
1227 | .addr = omap44xx_uart2_addrs, | |
1228 | .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), | |
9780a9cf BC |
1229 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1230 | }; | |
1231 | ||
3b54baad BC |
1232 | /* uart2 slave ports */ |
1233 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { | |
1234 | &omap44xx_l4_per__uart2, | |
9780a9cf BC |
1235 | }; |
1236 | ||
3b54baad BC |
1237 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
1238 | .name = "uart2", | |
1239 | .class = &omap44xx_uart_hwmod_class, | |
1240 | .mpu_irqs = omap44xx_uart2_irqs, | |
1241 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), | |
1242 | .sdma_reqs = omap44xx_uart2_sdma_reqs, | |
1243 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), | |
1244 | .main_clk = "uart2_fck", | |
9780a9cf BC |
1245 | .prcm = { |
1246 | .omap4 = { | |
3b54baad | 1247 | .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
9780a9cf BC |
1248 | }, |
1249 | }, | |
3b54baad BC |
1250 | .slaves = omap44xx_uart2_slaves, |
1251 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), | |
9780a9cf BC |
1252 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1253 | }; | |
1254 | ||
3b54baad BC |
1255 | /* uart3 */ |
1256 | static struct omap_hwmod omap44xx_uart3_hwmod; | |
1257 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | |
1258 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1259 | }; |
1260 | ||
3b54baad BC |
1261 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
1262 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
1263 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
1264 | }; | |
1265 | ||
1266 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | |
9780a9cf | 1267 | { |
3b54baad BC |
1268 | .pa_start = 0x48020000, |
1269 | .pa_end = 0x480200ff, | |
9780a9cf BC |
1270 | .flags = ADDR_TYPE_RT |
1271 | }, | |
1272 | }; | |
1273 | ||
3b54baad BC |
1274 | /* l4_per -> uart3 */ |
1275 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
9780a9cf | 1276 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
1277 | .slave = &omap44xx_uart3_hwmod, |
1278 | .clk = "l4_div_ck", | |
1279 | .addr = omap44xx_uart3_addrs, | |
1280 | .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), | |
9780a9cf BC |
1281 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1282 | }; | |
1283 | ||
3b54baad BC |
1284 | /* uart3 slave ports */ |
1285 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { | |
1286 | &omap44xx_l4_per__uart3, | |
1287 | }; | |
1288 | ||
1289 | static struct omap_hwmod omap44xx_uart3_hwmod = { | |
1290 | .name = "uart3", | |
1291 | .class = &omap44xx_uart_hwmod_class, | |
1292 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
1293 | .mpu_irqs = omap44xx_uart3_irqs, | |
1294 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), | |
1295 | .sdma_reqs = omap44xx_uart3_sdma_reqs, | |
1296 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), | |
1297 | .main_clk = "uart3_fck", | |
9780a9cf BC |
1298 | .prcm = { |
1299 | .omap4 = { | |
3b54baad | 1300 | .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
9780a9cf BC |
1301 | }, |
1302 | }, | |
3b54baad BC |
1303 | .slaves = omap44xx_uart3_slaves, |
1304 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), | |
9780a9cf BC |
1305 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1306 | }; | |
1307 | ||
3b54baad BC |
1308 | /* uart4 */ |
1309 | static struct omap_hwmod omap44xx_uart4_hwmod; | |
1310 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | |
1311 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1312 | }; |
1313 | ||
3b54baad BC |
1314 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
1315 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
1316 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
1317 | }; | |
1318 | ||
1319 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | |
9780a9cf | 1320 | { |
3b54baad BC |
1321 | .pa_start = 0x4806e000, |
1322 | .pa_end = 0x4806e0ff, | |
9780a9cf BC |
1323 | .flags = ADDR_TYPE_RT |
1324 | }, | |
1325 | }; | |
1326 | ||
3b54baad BC |
1327 | /* l4_per -> uart4 */ |
1328 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
9780a9cf | 1329 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
1330 | .slave = &omap44xx_uart4_hwmod, |
1331 | .clk = "l4_div_ck", | |
1332 | .addr = omap44xx_uart4_addrs, | |
1333 | .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), | |
9780a9cf BC |
1334 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1335 | }; | |
1336 | ||
3b54baad BC |
1337 | /* uart4 slave ports */ |
1338 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { | |
1339 | &omap44xx_l4_per__uart4, | |
9780a9cf BC |
1340 | }; |
1341 | ||
3b54baad BC |
1342 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
1343 | .name = "uart4", | |
1344 | .class = &omap44xx_uart_hwmod_class, | |
1345 | .mpu_irqs = omap44xx_uart4_irqs, | |
1346 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), | |
1347 | .sdma_reqs = omap44xx_uart4_sdma_reqs, | |
1348 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), | |
1349 | .main_clk = "uart4_fck", | |
9780a9cf BC |
1350 | .prcm = { |
1351 | .omap4 = { | |
3b54baad | 1352 | .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
9780a9cf BC |
1353 | }, |
1354 | }, | |
3b54baad BC |
1355 | .slaves = omap44xx_uart4_slaves, |
1356 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), | |
9780a9cf BC |
1357 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1358 | }; | |
1359 | ||
3b54baad BC |
1360 | /* |
1361 | * 'wd_timer' class | |
1362 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
1363 | * overflow condition | |
1364 | */ | |
1365 | ||
1366 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
1367 | .rev_offs = 0x0000, | |
1368 | .sysc_offs = 0x0010, | |
1369 | .syss_offs = 0x0014, | |
1370 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
1371 | SYSC_HAS_SOFTRESET), | |
1372 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1373 | .sysc_fields = &omap_hwmod_sysc_type1, | |
9780a9cf BC |
1374 | }; |
1375 | ||
3b54baad BC |
1376 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
1377 | .name = "wd_timer", | |
1378 | .sysc = &omap44xx_wd_timer_sysc, | |
1379 | .pre_shutdown = &omap2_wd_timer_disable | |
1380 | }; | |
1381 | ||
1382 | /* wd_timer2 */ | |
1383 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | |
1384 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | |
1385 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
1386 | }; | |
1387 | ||
1388 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | |
9780a9cf | 1389 | { |
3b54baad BC |
1390 | .pa_start = 0x4a314000, |
1391 | .pa_end = 0x4a31407f, | |
9780a9cf BC |
1392 | .flags = ADDR_TYPE_RT |
1393 | }, | |
1394 | }; | |
1395 | ||
3b54baad BC |
1396 | /* l4_wkup -> wd_timer2 */ |
1397 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
1398 | .master = &omap44xx_l4_wkup_hwmod, | |
1399 | .slave = &omap44xx_wd_timer2_hwmod, | |
1400 | .clk = "l4_wkup_clk_mux_ck", | |
1401 | .addr = omap44xx_wd_timer2_addrs, | |
1402 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), | |
9780a9cf BC |
1403 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1404 | }; | |
1405 | ||
3b54baad BC |
1406 | /* wd_timer2 slave ports */ |
1407 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | |
1408 | &omap44xx_l4_wkup__wd_timer2, | |
9780a9cf BC |
1409 | }; |
1410 | ||
3b54baad BC |
1411 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
1412 | .name = "wd_timer2", | |
1413 | .class = &omap44xx_wd_timer_hwmod_class, | |
1414 | .mpu_irqs = omap44xx_wd_timer2_irqs, | |
1415 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), | |
1416 | .main_clk = "wd_timer2_fck", | |
9780a9cf BC |
1417 | .prcm = { |
1418 | .omap4 = { | |
3b54baad | 1419 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
9780a9cf BC |
1420 | }, |
1421 | }, | |
3b54baad BC |
1422 | .slaves = omap44xx_wd_timer2_slaves, |
1423 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | |
9780a9cf BC |
1424 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1425 | }; | |
1426 | ||
3b54baad BC |
1427 | /* wd_timer3 */ |
1428 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | |
1429 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | |
1430 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1431 | }; |
1432 | ||
3b54baad | 1433 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
9780a9cf | 1434 | { |
3b54baad BC |
1435 | .pa_start = 0x40130000, |
1436 | .pa_end = 0x4013007f, | |
9780a9cf BC |
1437 | .flags = ADDR_TYPE_RT |
1438 | }, | |
1439 | }; | |
1440 | ||
3b54baad BC |
1441 | /* l4_abe -> wd_timer3 */ |
1442 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
1443 | .master = &omap44xx_l4_abe_hwmod, | |
1444 | .slave = &omap44xx_wd_timer3_hwmod, | |
1445 | .clk = "ocp_abe_iclk", | |
1446 | .addr = omap44xx_wd_timer3_addrs, | |
1447 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), | |
1448 | .user = OCP_USER_MPU, | |
9780a9cf BC |
1449 | }; |
1450 | ||
3b54baad BC |
1451 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
1452 | { | |
1453 | .pa_start = 0x49030000, | |
1454 | .pa_end = 0x4903007f, | |
1455 | .flags = ADDR_TYPE_RT | |
1456 | }, | |
9780a9cf BC |
1457 | }; |
1458 | ||
3b54baad BC |
1459 | /* l4_abe -> wd_timer3 (dma) */ |
1460 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
1461 | .master = &omap44xx_l4_abe_hwmod, | |
1462 | .slave = &omap44xx_wd_timer3_hwmod, | |
1463 | .clk = "ocp_abe_iclk", | |
1464 | .addr = omap44xx_wd_timer3_dma_addrs, | |
1465 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), | |
1466 | .user = OCP_USER_SDMA, | |
9780a9cf BC |
1467 | }; |
1468 | ||
3b54baad BC |
1469 | /* wd_timer3 slave ports */ |
1470 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | |
1471 | &omap44xx_l4_abe__wd_timer3, | |
1472 | &omap44xx_l4_abe__wd_timer3_dma, | |
1473 | }; | |
1474 | ||
1475 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |
1476 | .name = "wd_timer3", | |
1477 | .class = &omap44xx_wd_timer_hwmod_class, | |
1478 | .mpu_irqs = omap44xx_wd_timer3_irqs, | |
1479 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), | |
1480 | .main_clk = "wd_timer3_fck", | |
9780a9cf BC |
1481 | .prcm = { |
1482 | .omap4 = { | |
3b54baad | 1483 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
9780a9cf BC |
1484 | }, |
1485 | }, | |
3b54baad BC |
1486 | .slaves = omap44xx_wd_timer3_slaves, |
1487 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | |
9780a9cf BC |
1488 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1489 | }; | |
531ce0d5 | 1490 | |
3b54baad | 1491 | |
531ce0d5 BC |
1492 | /* |
1493 | * 'dma' class | |
1494 | * dma controller for data exchange between memory to memory (i.e. internal or | |
1495 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
1496 | */ | |
1497 | ||
1498 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
1499 | .rev_offs = 0x0000, | |
1500 | .sysc_offs = 0x002c, | |
1501 | .syss_offs = 0x0028, | |
1502 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1503 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1504 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1505 | SYSS_HAS_RESET_STATUS), | |
1506 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1507 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1508 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1509 | }; | |
1510 | ||
1511 | /* dma attributes */ | |
1512 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1513 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1514 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1515 | .lch_count = 32, | |
1516 | }; | |
1517 | ||
1518 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
1519 | .name = "dma", | |
1520 | .sysc = &omap44xx_dma_sysc, | |
1521 | }; | |
1522 | ||
1523 | /* dma_system */ | |
1524 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
1525 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
1526 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
1527 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
1528 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
1529 | }; | |
1530 | ||
1531 | /* dma_system master ports */ | |
1532 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { | |
1533 | &omap44xx_dma_system__l3_main_2, | |
1534 | }; | |
1535 | ||
1536 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
1537 | { | |
1538 | .pa_start = 0x4a056000, | |
1539 | .pa_end = 0x4a0560ff, | |
1540 | .flags = ADDR_TYPE_RT | |
1541 | }, | |
1542 | }; | |
1543 | ||
1544 | /* l4_cfg -> dma_system */ | |
1545 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
1546 | .master = &omap44xx_l4_cfg_hwmod, | |
1547 | .slave = &omap44xx_dma_system_hwmod, | |
1548 | .clk = "l4_div_ck", | |
1549 | .addr = omap44xx_dma_system_addrs, | |
1550 | .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs), | |
1551 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1552 | }; | |
1553 | ||
1554 | /* dma_system slave ports */ | |
1555 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { | |
1556 | &omap44xx_l4_cfg__dma_system, | |
1557 | }; | |
1558 | ||
1559 | static struct omap_hwmod omap44xx_dma_system_hwmod = { | |
1560 | .name = "dma_system", | |
1561 | .class = &omap44xx_dma_hwmod_class, | |
1562 | .mpu_irqs = omap44xx_dma_system_irqs, | |
1563 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs), | |
1564 | .main_clk = "l3_div_ck", | |
1565 | .prcm = { | |
1566 | .omap4 = { | |
1567 | .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL, | |
1568 | }, | |
1569 | }, | |
1570 | .slaves = omap44xx_dma_system_slaves, | |
1571 | .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), | |
1572 | .masters = omap44xx_dma_system_masters, | |
1573 | .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), | |
1574 | .dev_attr = &dma_dev_attr, | |
1575 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1576 | }; | |
1577 | ||
55d2cb08 BC |
1578 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
1579 | /* dmm class */ | |
1580 | &omap44xx_dmm_hwmod, | |
3b54baad | 1581 | |
55d2cb08 BC |
1582 | /* emif_fw class */ |
1583 | &omap44xx_emif_fw_hwmod, | |
3b54baad | 1584 | |
55d2cb08 BC |
1585 | /* l3 class */ |
1586 | &omap44xx_l3_instr_hwmod, | |
1587 | &omap44xx_l3_main_1_hwmod, | |
1588 | &omap44xx_l3_main_2_hwmod, | |
1589 | &omap44xx_l3_main_3_hwmod, | |
3b54baad | 1590 | |
55d2cb08 BC |
1591 | /* l4 class */ |
1592 | &omap44xx_l4_abe_hwmod, | |
1593 | &omap44xx_l4_cfg_hwmod, | |
1594 | &omap44xx_l4_per_hwmod, | |
1595 | &omap44xx_l4_wkup_hwmod, | |
531ce0d5 BC |
1596 | |
1597 | /* dma class */ | |
1598 | &omap44xx_dma_system_hwmod, | |
1599 | ||
55d2cb08 BC |
1600 | /* mpu_bus class */ |
1601 | &omap44xx_mpu_private_hwmod, | |
1602 | ||
9780a9cf BC |
1603 | /* gpio class */ |
1604 | &omap44xx_gpio1_hwmod, | |
1605 | &omap44xx_gpio2_hwmod, | |
1606 | &omap44xx_gpio3_hwmod, | |
1607 | &omap44xx_gpio4_hwmod, | |
1608 | &omap44xx_gpio5_hwmod, | |
1609 | &omap44xx_gpio6_hwmod, | |
1610 | ||
3b54baad BC |
1611 | /* i2c class */ |
1612 | &omap44xx_i2c1_hwmod, | |
1613 | &omap44xx_i2c2_hwmod, | |
1614 | &omap44xx_i2c3_hwmod, | |
1615 | &omap44xx_i2c4_hwmod, | |
1616 | ||
55d2cb08 BC |
1617 | /* mpu class */ |
1618 | &omap44xx_mpu_hwmod, | |
db12ba53 BC |
1619 | |
1620 | /* uart class */ | |
1621 | &omap44xx_uart1_hwmod, | |
1622 | &omap44xx_uart2_hwmod, | |
1623 | &omap44xx_uart3_hwmod, | |
1624 | &omap44xx_uart4_hwmod, | |
3b54baad BC |
1625 | |
1626 | /* wd_timer class */ | |
1627 | &omap44xx_wd_timer2_hwmod, | |
1628 | &omap44xx_wd_timer3_hwmod, | |
1629 | ||
55d2cb08 BC |
1630 | NULL, |
1631 | }; | |
1632 | ||
1633 | int __init omap44xx_hwmod_init(void) | |
1634 | { | |
1635 | return omap_hwmod_init(omap44xx_hwmods); | |
1636 | } | |
1637 |