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OMAP4: hwmod data: Add AESS, McPDM, bandgap, counter_32k, MMC, KBD, ISS & IPU
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
CommitLineData
55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
d63bd74f 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
55d2cb08
BC		 5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
9780a9cf 25#include <plat/gpio.h>
531ce0d5 26#include <plat/dma.h>
55d2cb08
BC		 27
28#include "omap_hwmod_common_data.h"
29
d198b514
PW		 30#include "cm1_44xx.h"
31#include "cm2_44xx.h"
32#include "prm44xx.h"
55d2cb08 33#include "prm-regbits-44xx.h"
ff2516fb 34#include "wd_timer.h"
55d2cb08
BC		 35
36/* Base offset for all OMAP4 interrupts external to MPUSS */
37#define OMAP44XX_IRQ_GIC_START 32
38
39/* Base offset for all OMAP4 dma requests */
40#define OMAP44XX_DMA_REQ_START 1
41
42/* Backward references (IPs with Bus Master capability) */
407a6888 43static struct omap_hwmod omap44xx_aess_hwmod;
531ce0d5 44static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 45static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 46static struct omap_hwmod omap44xx_dsp_hwmod;
d63bd74f 47static struct omap_hwmod omap44xx_dss_hwmod;
55d2cb08 48static struct omap_hwmod omap44xx_emif_fw_hwmod;
407a6888
BC		 49static struct omap_hwmod omap44xx_hsi_hwmod;
50static struct omap_hwmod omap44xx_ipu_hwmod;
51static struct omap_hwmod omap44xx_iss_hwmod;
8f25bdc5 52static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 53static struct omap_hwmod omap44xx_l3_instr_hwmod;
54static struct omap_hwmod omap44xx_l3_main_1_hwmod;
55static struct omap_hwmod omap44xx_l3_main_2_hwmod;
56static struct omap_hwmod omap44xx_l3_main_3_hwmod;
57static struct omap_hwmod omap44xx_l4_abe_hwmod;
58static struct omap_hwmod omap44xx_l4_cfg_hwmod;
59static struct omap_hwmod omap44xx_l4_per_hwmod;
60static struct omap_hwmod omap44xx_l4_wkup_hwmod;
407a6888
BC		 61static struct omap_hwmod omap44xx_mmc1_hwmod;
62static struct omap_hwmod omap44xx_mmc2_hwmod;
55d2cb08
BC		 63static struct omap_hwmod omap44xx_mpu_hwmod;
64static struct omap_hwmod omap44xx_mpu_private_hwmod;
65
66/*
67 * Interconnects omap_hwmod structures
68 * hwmods that compose the global OMAP interconnect
69 */
70
71/*
72 * 'dmm' class
73 * instance(s): dmm
74 */
75static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 76 .name = "dmm",
55d2cb08
BC		 77};
78
79/* dmm interface data */
80/* l3_main_1 -> dmm */
81static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
82 .master = &omap44xx_l3_main_1_hwmod,
83 .slave = &omap44xx_dmm_hwmod,
84 .clk = "l3_div_ck",
659fa822
BC		 85 .user = OCP_USER_SDMA,
86};
87
88static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
89 {
90 .pa_start = 0x4e000000,
91 .pa_end = 0x4e0007ff,
92 .flags = ADDR_TYPE_RT
93 },
55d2cb08
BC		 94};
95
96/* mpu -> dmm */
97static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
98 .master = &omap44xx_mpu_hwmod,
99 .slave = &omap44xx_dmm_hwmod,
100 .clk = "l3_div_ck",
659fa822
BC		 101 .addr = omap44xx_dmm_addrs,
102 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
103 .user = OCP_USER_MPU,
55d2cb08
BC		 104};
105
106/* dmm slave ports */
107static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
108 &omap44xx_l3_main_1__dmm,
109 &omap44xx_mpu__dmm,
110};
111
112static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
113 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
114};
115
116static struct omap_hwmod omap44xx_dmm_hwmod = {
117 .name = "dmm",
118 .class = &omap44xx_dmm_hwmod_class,
119 .slaves = omap44xx_dmm_slaves,
120 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
121 .mpu_irqs = omap44xx_dmm_irqs,
122 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
124};
125
126/*
127 * 'emif_fw' class
128 * instance(s): emif_fw
129 */
130static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 131 .name = "emif_fw",
55d2cb08
BC		 132};
133
134/* emif_fw interface data */
135/* dmm -> emif_fw */
136static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
137 .master = &omap44xx_dmm_hwmod,
138 .slave = &omap44xx_emif_fw_hwmod,
139 .clk = "l3_div_ck",
140 .user = OCP_USER_MPU | OCP_USER_SDMA,
141};
142
659fa822
BC		 143static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
144 {
145 .pa_start = 0x4a20c000,
146 .pa_end = 0x4a20c0ff,
147 .flags = ADDR_TYPE_RT
148 },
149};
150
55d2cb08
BC		 151/* l4_cfg -> emif_fw */
152static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
153 .master = &omap44xx_l4_cfg_hwmod,
154 .slave = &omap44xx_emif_fw_hwmod,
155 .clk = "l4_div_ck",
659fa822
BC		 156 .addr = omap44xx_emif_fw_addrs,
157 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
158 .user = OCP_USER_MPU,
55d2cb08
BC		 159};
160
161/* emif_fw slave ports */
162static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
163 &omap44xx_dmm__emif_fw,
164 &omap44xx_l4_cfg__emif_fw,
165};
166
167static struct omap_hwmod omap44xx_emif_fw_hwmod = {
168 .name = "emif_fw",
169 .class = &omap44xx_emif_fw_hwmod_class,
170 .slaves = omap44xx_emif_fw_slaves,
171 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
172 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
173};
174
175/*
176 * 'l3' class
177 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
178 */
179static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 180 .name = "l3",
55d2cb08
BC		 181};
182
183/* l3_instr interface data */
8f25bdc5
BC		 184/* iva -> l3_instr */
185static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
186 .master = &omap44xx_iva_hwmod,
187 .slave = &omap44xx_l3_instr_hwmod,
188 .clk = "l3_div_ck",
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
190};
191
55d2cb08
BC		 192/* l3_main_3 -> l3_instr */
193static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
194 .master = &omap44xx_l3_main_3_hwmod,
195 .slave = &omap44xx_l3_instr_hwmod,
196 .clk = "l3_div_ck",
197 .user = OCP_USER_MPU | OCP_USER_SDMA,
198};
199
200/* l3_instr slave ports */
201static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 202 &omap44xx_iva__l3_instr,
55d2cb08
BC		 203 &omap44xx_l3_main_3__l3_instr,
204};
205
206static struct omap_hwmod omap44xx_l3_instr_hwmod = {
207 .name = "l3_instr",
208 .class = &omap44xx_l3_hwmod_class,
209 .slaves = omap44xx_l3_instr_slaves,
210 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
211 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
212};
213
3b54baad 214/* l3_main_1 interface data */
8f25bdc5
BC		 215/* dsp -> l3_main_1 */
216static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
217 .master = &omap44xx_dsp_hwmod,
218 .slave = &omap44xx_l3_main_1_hwmod,
219 .clk = "l3_div_ck",
220 .user = OCP_USER_MPU | OCP_USER_SDMA,
221};
222
d63bd74f
BC		 223/* dss -> l3_main_1 */
224static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
225 .master = &omap44xx_dss_hwmod,
226 .slave = &omap44xx_l3_main_1_hwmod,
227 .clk = "l3_div_ck",
228 .user = OCP_USER_MPU | OCP_USER_SDMA,
229};
230
55d2cb08
BC		 231/* l3_main_2 -> l3_main_1 */
232static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
233 .master = &omap44xx_l3_main_2_hwmod,
234 .slave = &omap44xx_l3_main_1_hwmod,
235 .clk = "l3_div_ck",
236 .user = OCP_USER_MPU | OCP_USER_SDMA,
237};
238
239/* l4_cfg -> l3_main_1 */
240static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
241 .master = &omap44xx_l4_cfg_hwmod,
242 .slave = &omap44xx_l3_main_1_hwmod,
243 .clk = "l4_div_ck",
244 .user = OCP_USER_MPU | OCP_USER_SDMA,
245};
246
407a6888
BC		 247/* mmc1 -> l3_main_1 */
248static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
249 .master = &omap44xx_mmc1_hwmod,
250 .slave = &omap44xx_l3_main_1_hwmod,
251 .clk = "l3_div_ck",
252 .user = OCP_USER_MPU | OCP_USER_SDMA,
253};
254
255/* mmc2 -> l3_main_1 */
256static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
257 .master = &omap44xx_mmc2_hwmod,
258 .slave = &omap44xx_l3_main_1_hwmod,
259 .clk = "l3_div_ck",
260 .user = OCP_USER_MPU | OCP_USER_SDMA,
261};
262
55d2cb08
BC		 263/* mpu -> l3_main_1 */
264static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
265 .master = &omap44xx_mpu_hwmod,
266 .slave = &omap44xx_l3_main_1_hwmod,
267 .clk = "l3_div_ck",
268 .user = OCP_USER_MPU | OCP_USER_SDMA,
269};
270
271/* l3_main_1 slave ports */
272static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 273 &omap44xx_dsp__l3_main_1,
d63bd74f 274 &omap44xx_dss__l3_main_1,
55d2cb08
BC		 275 &omap44xx_l3_main_2__l3_main_1,
276 &omap44xx_l4_cfg__l3_main_1,
407a6888
BC		 277 &omap44xx_mmc1__l3_main_1,
278 &omap44xx_mmc2__l3_main_1,
55d2cb08
BC		 279 &omap44xx_mpu__l3_main_1,
280};
281
282static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
283 .name = "l3_main_1",
284 .class = &omap44xx_l3_hwmod_class,
285 .slaves = omap44xx_l3_main_1_slaves,
286 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
288};
289
290/* l3_main_2 interface data */
d7cf5f33
BC		 291/* dma_system -> l3_main_2 */
292static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
293 .master = &omap44xx_dma_system_hwmod,
294 .slave = &omap44xx_l3_main_2_hwmod,
295 .clk = "l3_div_ck",
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297};
298
407a6888
BC		 299/* hsi -> l3_main_2 */
300static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
301 .master = &omap44xx_hsi_hwmod,
302 .slave = &omap44xx_l3_main_2_hwmod,
303 .clk = "l3_div_ck",
304 .user = OCP_USER_MPU | OCP_USER_SDMA,
305};
306
307/* ipu -> l3_main_2 */
308static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
309 .master = &omap44xx_ipu_hwmod,
310 .slave = &omap44xx_l3_main_2_hwmod,
311 .clk = "l3_div_ck",
312 .user = OCP_USER_MPU | OCP_USER_SDMA,
313};
314
315/* iss -> l3_main_2 */
316static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
317 .master = &omap44xx_iss_hwmod,
318 .slave = &omap44xx_l3_main_2_hwmod,
319 .clk = "l3_div_ck",
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321};
322
8f25bdc5
BC		 323/* iva -> l3_main_2 */
324static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
325 .master = &omap44xx_iva_hwmod,
326 .slave = &omap44xx_l3_main_2_hwmod,
327 .clk = "l3_div_ck",
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
329};
330
55d2cb08
BC		 331/* l3_main_1 -> l3_main_2 */
332static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
333 .master = &omap44xx_l3_main_1_hwmod,
334 .slave = &omap44xx_l3_main_2_hwmod,
335 .clk = "l3_div_ck",
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337};
338
339/* l4_cfg -> l3_main_2 */
340static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
341 .master = &omap44xx_l4_cfg_hwmod,
342 .slave = &omap44xx_l3_main_2_hwmod,
343 .clk = "l4_div_ck",
344 .user = OCP_USER_MPU | OCP_USER_SDMA,
345};
346
347/* l3_main_2 slave ports */
348static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 349 &omap44xx_dma_system__l3_main_2,
407a6888
BC		 350 &omap44xx_hsi__l3_main_2,
351 &omap44xx_ipu__l3_main_2,
352 &omap44xx_iss__l3_main_2,
8f25bdc5 353 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 354 &omap44xx_l3_main_1__l3_main_2,
355 &omap44xx_l4_cfg__l3_main_2,
356};
357
358static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
359 .name = "l3_main_2",
360 .class = &omap44xx_l3_hwmod_class,
361 .slaves = omap44xx_l3_main_2_slaves,
362 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
363 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
364};
365
366/* l3_main_3 interface data */
367/* l3_main_1 -> l3_main_3 */
368static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
369 .master = &omap44xx_l3_main_1_hwmod,
370 .slave = &omap44xx_l3_main_3_hwmod,
371 .clk = "l3_div_ck",
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373};
374
375/* l3_main_2 -> l3_main_3 */
376static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
377 .master = &omap44xx_l3_main_2_hwmod,
378 .slave = &omap44xx_l3_main_3_hwmod,
379 .clk = "l3_div_ck",
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
381};
382
383/* l4_cfg -> l3_main_3 */
384static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
385 .master = &omap44xx_l4_cfg_hwmod,
386 .slave = &omap44xx_l3_main_3_hwmod,
387 .clk = "l4_div_ck",
388 .user = OCP_USER_MPU | OCP_USER_SDMA,
389};
390
391/* l3_main_3 slave ports */
392static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
393 &omap44xx_l3_main_1__l3_main_3,
394 &omap44xx_l3_main_2__l3_main_3,
395 &omap44xx_l4_cfg__l3_main_3,
396};
397
398static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
399 .name = "l3_main_3",
400 .class = &omap44xx_l3_hwmod_class,
401 .slaves = omap44xx_l3_main_3_slaves,
402 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
403 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
404};
405
406/*
407 * 'l4' class
408 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
409 */
410static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 411 .name = "l4",
55d2cb08
BC		 412};
413
414/* l4_abe interface data */
407a6888
BC		 415/* aess -> l4_abe */
416static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
417 .master = &omap44xx_aess_hwmod,
418 .slave = &omap44xx_l4_abe_hwmod,
419 .clk = "ocp_abe_iclk",
420 .user = OCP_USER_MPU | OCP_USER_SDMA,
421};
422
8f25bdc5
BC		 423/* dsp -> l4_abe */
424static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
425 .master = &omap44xx_dsp_hwmod,
426 .slave = &omap44xx_l4_abe_hwmod,
427 .clk = "ocp_abe_iclk",
428 .user = OCP_USER_MPU | OCP_USER_SDMA,
429};
430
55d2cb08
BC		 431/* l3_main_1 -> l4_abe */
432static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
433 .master = &omap44xx_l3_main_1_hwmod,
434 .slave = &omap44xx_l4_abe_hwmod,
435 .clk = "l3_div_ck",
436 .user = OCP_USER_MPU | OCP_USER_SDMA,
437};
438
439/* mpu -> l4_abe */
440static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
441 .master = &omap44xx_mpu_hwmod,
442 .slave = &omap44xx_l4_abe_hwmod,
443 .clk = "ocp_abe_iclk",
444 .user = OCP_USER_MPU | OCP_USER_SDMA,
445};
446
447/* l4_abe slave ports */
448static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
407a6888 449 &omap44xx_aess__l4_abe,
8f25bdc5 450 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 451 &omap44xx_l3_main_1__l4_abe,
452 &omap44xx_mpu__l4_abe,
453};
454
455static struct omap_hwmod omap44xx_l4_abe_hwmod = {
456 .name = "l4_abe",
457 .class = &omap44xx_l4_hwmod_class,
458 .slaves = omap44xx_l4_abe_slaves,
459 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
460 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
461};
462
463/* l4_cfg interface data */
464/* l3_main_1 -> l4_cfg */
465static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
466 .master = &omap44xx_l3_main_1_hwmod,
467 .slave = &omap44xx_l4_cfg_hwmod,
468 .clk = "l3_div_ck",
469 .user = OCP_USER_MPU | OCP_USER_SDMA,
470};
471
472/* l4_cfg slave ports */
473static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
474 &omap44xx_l3_main_1__l4_cfg,
475};
476
477static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
478 .name = "l4_cfg",
479 .class = &omap44xx_l4_hwmod_class,
480 .slaves = omap44xx_l4_cfg_slaves,
481 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
482 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
483};
484
485/* l4_per interface data */
486/* l3_main_2 -> l4_per */
487static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
488 .master = &omap44xx_l3_main_2_hwmod,
489 .slave = &omap44xx_l4_per_hwmod,
490 .clk = "l3_div_ck",
491 .user = OCP_USER_MPU | OCP_USER_SDMA,
492};
493
494/* l4_per slave ports */
495static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
496 &omap44xx_l3_main_2__l4_per,
497};
498
499static struct omap_hwmod omap44xx_l4_per_hwmod = {
500 .name = "l4_per",
501 .class = &omap44xx_l4_hwmod_class,
502 .slaves = omap44xx_l4_per_slaves,
503 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
504 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
505};
506
507/* l4_wkup interface data */
508/* l4_cfg -> l4_wkup */
509static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
510 .master = &omap44xx_l4_cfg_hwmod,
511 .slave = &omap44xx_l4_wkup_hwmod,
512 .clk = "l4_div_ck",
513 .user = OCP_USER_MPU | OCP_USER_SDMA,
514};
515
516/* l4_wkup slave ports */
517static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
518 &omap44xx_l4_cfg__l4_wkup,
519};
520
521static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
522 .name = "l4_wkup",
523 .class = &omap44xx_l4_hwmod_class,
524 .slaves = omap44xx_l4_wkup_slaves,
525 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
526 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
527};
528
f776471f 529/*
3b54baad
BC		 530 * 'mpu_bus' class
531 * instance(s): mpu_private
f776471f 532 */
3b54baad 533static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 534 .name = "mpu_bus",
3b54baad 535};
f776471f 536
3b54baad
BC		 537/* mpu_private interface data */
538/* mpu -> mpu_private */
539static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
540 .master = &omap44xx_mpu_hwmod,
541 .slave = &omap44xx_mpu_private_hwmod,
542 .clk = "l3_div_ck",
543 .user = OCP_USER_MPU | OCP_USER_SDMA,
544};
545
546/* mpu_private slave ports */
547static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
548 &omap44xx_mpu__mpu_private,
549};
550
551static struct omap_hwmod omap44xx_mpu_private_hwmod = {
552 .name = "mpu_private",
553 .class = &omap44xx_mpu_bus_hwmod_class,
554 .slaves = omap44xx_mpu_private_slaves,
555 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
557};
558
559/*
560 * Modules omap_hwmod structures
561 *
562 * The following IPs are excluded for the moment because:
563 * - They do not need an explicit SW control using omap_hwmod API.
564 * - They still need to be validated with the driver
565 * properly adapted to omap_hwmod / omap_device
566 *
3b54baad
BC		 567 * c2c
568 * c2c_target_fw
569 * cm_core
570 * cm_core_aon
3b54baad
BC		 571 * ctrl_module_core
572 * ctrl_module_pad_core
573 * ctrl_module_pad_wkup
574 * ctrl_module_wkup
575 * debugss
3b54baad
BC		 576 * efuse_ctrl_cust
577 * efuse_ctrl_std
578 * elm
579 * emif1
580 * emif2
581 * fdif
582 * gpmc
583 * gpu
584 * hdq1w
585 * hsi
3b54baad
BC		 586 * ocmc_ram
587 * ocp2scp_usb_phy
588 * ocp_wp_noc
3b54baad
BC		 589 * prcm_mpu
590 * prm
591 * scrm
592 * sl2if
593 * slimbus1
594 * slimbus2
3b54baad
BC		 595 * usb_host_fs
596 * usb_host_hs
597 * usb_otg_hs
598 * usb_phy_cm
599 * usb_tll_hs
600 * usim
601 */
602
407a6888
BC		 603/*
604 * 'aess' class
605 * audio engine sub system
606 */
607
608static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
609 .rev_offs = 0x0000,
610 .sysc_offs = 0x0010,
611 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
613 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
614 .sysc_fields = &omap_hwmod_sysc_type2,
615};
616
617static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
618 .name = "aess",
619 .sysc = &omap44xx_aess_sysc,
620};
621
622/* aess */
623static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
624 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
625};
626
627static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
628 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
629 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
630 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
631 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
632 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
633 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
634 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
635 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
636};
637
638/* aess master ports */
639static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
640 &omap44xx_aess__l4_abe,
641};
642
643static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
644 {
645 .pa_start = 0x401f1000,
646 .pa_end = 0x401f13ff,
647 .flags = ADDR_TYPE_RT
648 },
649};
650
651/* l4_abe -> aess */
652static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
653 .master = &omap44xx_l4_abe_hwmod,
654 .slave = &omap44xx_aess_hwmod,
655 .clk = "ocp_abe_iclk",
656 .addr = omap44xx_aess_addrs,
657 .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
658 .user = OCP_USER_MPU,
659};
660
661static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
662 {
663 .pa_start = 0x490f1000,
664 .pa_end = 0x490f13ff,
665 .flags = ADDR_TYPE_RT
666 },
667};
668
669/* l4_abe -> aess (dma) */
670static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
671 .master = &omap44xx_l4_abe_hwmod,
672 .slave = &omap44xx_aess_hwmod,
673 .clk = "ocp_abe_iclk",
674 .addr = omap44xx_aess_dma_addrs,
675 .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
676 .user = OCP_USER_SDMA,
677};
678
679/* aess slave ports */
680static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
681 &omap44xx_l4_abe__aess,
682 &omap44xx_l4_abe__aess_dma,
683};
684
685static struct omap_hwmod omap44xx_aess_hwmod = {
686 .name = "aess",
687 .class = &omap44xx_aess_hwmod_class,
688 .mpu_irqs = omap44xx_aess_irqs,
689 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
690 .sdma_reqs = omap44xx_aess_sdma_reqs,
691 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
692 .main_clk = "aess_fck",
693 .prcm = {
694 .omap4 = {
695 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
696 },
697 },
698 .slaves = omap44xx_aess_slaves,
699 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
700 .masters = omap44xx_aess_masters,
701 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
702 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
703};
704
705/*
706 * 'bandgap' class
707 * bangap reference for ldo regulators
708 */
709
710static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
711 .name = "bandgap",
712};
713
714/* bandgap */
715static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
716 { .role = "fclk", .clk = "bandgap_fclk" },
717};
718
719static struct omap_hwmod omap44xx_bandgap_hwmod = {
720 .name = "bandgap",
721 .class = &omap44xx_bandgap_hwmod_class,
722 .prcm = {
723 .omap4 = {
724 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
725 },
726 },
727 .opt_clks = bandgap_opt_clks,
728 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
729 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
730};
731
732/*
733 * 'counter' class
734 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
735 */
736
737static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
738 .rev_offs = 0x0000,
739 .sysc_offs = 0x0004,
740 .sysc_flags = SYSC_HAS_SIDLEMODE,
741 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
742 SIDLE_SMART_WKUP),
743 .sysc_fields = &omap_hwmod_sysc_type1,
744};
745
746static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
747 .name = "counter",
748 .sysc = &omap44xx_counter_sysc,
749};
750
751/* counter_32k */
752static struct omap_hwmod omap44xx_counter_32k_hwmod;
753static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
754 {
755 .pa_start = 0x4a304000,
756 .pa_end = 0x4a30401f,
757 .flags = ADDR_TYPE_RT
758 },
759};
760
761/* l4_wkup -> counter_32k */
762static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
763 .master = &omap44xx_l4_wkup_hwmod,
764 .slave = &omap44xx_counter_32k_hwmod,
765 .clk = "l4_wkup_clk_mux_ck",
766 .addr = omap44xx_counter_32k_addrs,
767 .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
768 .user = OCP_USER_MPU | OCP_USER_SDMA,
769};
770
771/* counter_32k slave ports */
772static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
773 &omap44xx_l4_wkup__counter_32k,
774};
775
776static struct omap_hwmod omap44xx_counter_32k_hwmod = {
777 .name = "counter_32k",
778 .class = &omap44xx_counter_hwmod_class,
779 .flags = HWMOD_SWSUP_SIDLE,
780 .main_clk = "sys_32k_ck",
781 .prcm = {
782 .omap4 = {
783 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
784 },
785 },
786 .slaves = omap44xx_counter_32k_slaves,
787 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
788 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
789};
790
d7cf5f33
BC		 791/*
792 * 'dma' class
793 * dma controller for data exchange between memory to memory (i.e. internal or
794 * external memory) and gp peripherals to memory or memory to gp peripherals
795 */
796
797static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
798 .rev_offs = 0x0000,
799 .sysc_offs = 0x002c,
800 .syss_offs = 0x0028,
801 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
802 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
803 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
804 SYSS_HAS_RESET_STATUS),
805 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
806 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
807 .sysc_fields = &omap_hwmod_sysc_type1,
808};
809
810static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
811 .name = "dma",
812 .sysc = &omap44xx_dma_sysc,
813};
814
815/* dma dev_attr */
816static struct omap_dma_dev_attr dma_dev_attr = {
817 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
818 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
819 .lch_count = 32,
820};
821
822/* dma_system */
823static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
824 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
825 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
826 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
827 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
828};
829
830/* dma_system master ports */
831static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
832 &omap44xx_dma_system__l3_main_2,
833};
834
835static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
836 {
837 .pa_start = 0x4a056000,
838 .pa_end = 0x4a0560ff,
839 .flags = ADDR_TYPE_RT
840 },
841};
842
843/* l4_cfg -> dma_system */
844static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
845 .master = &omap44xx_l4_cfg_hwmod,
846 .slave = &omap44xx_dma_system_hwmod,
847 .clk = "l4_div_ck",
848 .addr = omap44xx_dma_system_addrs,
849 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
850 .user = OCP_USER_MPU | OCP_USER_SDMA,
851};
852
853/* dma_system slave ports */
854static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
855 &omap44xx_l4_cfg__dma_system,
856};
857
858static struct omap_hwmod omap44xx_dma_system_hwmod = {
859 .name = "dma_system",
860 .class = &omap44xx_dma_hwmod_class,
861 .mpu_irqs = omap44xx_dma_system_irqs,
862 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
863 .main_clk = "l3_div_ck",
864 .prcm = {
865 .omap4 = {
866 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
867 },
868 },
869 .dev_attr = &dma_dev_attr,
870 .slaves = omap44xx_dma_system_slaves,
871 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
872 .masters = omap44xx_dma_system_masters,
873 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
874 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
875};
876
8ca476da
BC		 877/*
878 * 'dmic' class
879 * digital microphone controller
880 */
881
882static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
883 .rev_offs = 0x0000,
884 .sysc_offs = 0x0010,
885 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
886 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
887 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
888 SIDLE_SMART_WKUP),
889 .sysc_fields = &omap_hwmod_sysc_type2,
890};
891
892static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
893 .name = "dmic",
894 .sysc = &omap44xx_dmic_sysc,
895};
896
897/* dmic */
898static struct omap_hwmod omap44xx_dmic_hwmod;
899static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
900 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
901};
902
903static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
904 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
905};
906
907static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
908 {
909 .pa_start = 0x4012e000,
910 .pa_end = 0x4012e07f,
911 .flags = ADDR_TYPE_RT
912 },
913};
914
915/* l4_abe -> dmic */
916static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
917 .master = &omap44xx_l4_abe_hwmod,
918 .slave = &omap44xx_dmic_hwmod,
919 .clk = "ocp_abe_iclk",
920 .addr = omap44xx_dmic_addrs,
921 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
922 .user = OCP_USER_MPU,
923};
924
925static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
926 {
927 .pa_start = 0x4902e000,
928 .pa_end = 0x4902e07f,
929 .flags = ADDR_TYPE_RT
930 },
931};
932
933/* l4_abe -> dmic (dma) */
934static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
935 .master = &omap44xx_l4_abe_hwmod,
936 .slave = &omap44xx_dmic_hwmod,
937 .clk = "ocp_abe_iclk",
938 .addr = omap44xx_dmic_dma_addrs,
939 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
940 .user = OCP_USER_SDMA,
941};
942
943/* dmic slave ports */
944static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
945 &omap44xx_l4_abe__dmic,
946 &omap44xx_l4_abe__dmic_dma,
947};
948
949static struct omap_hwmod omap44xx_dmic_hwmod = {
950 .name = "dmic",
951 .class = &omap44xx_dmic_hwmod_class,
952 .mpu_irqs = omap44xx_dmic_irqs,
953 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
954 .sdma_reqs = omap44xx_dmic_sdma_reqs,
955 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
956 .main_clk = "dmic_fck",
957 .prcm = {
958 .omap4 = {
959 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
960 },
961 },
962 .slaves = omap44xx_dmic_slaves,
963 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
964 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
965};
966
8f25bdc5
BC		 967/*
968 * 'dsp' class
969 * dsp sub-system
970 */
971
972static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 973 .name = "dsp",
8f25bdc5
BC		 974};
975
976/* dsp */
977static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
978 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
979};
980
981static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
982 { .name = "mmu_cache", .rst_shift = 1 },
983};
984
985static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
986 { .name = "dsp", .rst_shift = 0 },
987};
988
989/* dsp -> iva */
990static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
991 .master = &omap44xx_dsp_hwmod,
992 .slave = &omap44xx_iva_hwmod,
993 .clk = "dpll_iva_m5x2_ck",
994};
995
996/* dsp master ports */
997static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
998 &omap44xx_dsp__l3_main_1,
999 &omap44xx_dsp__l4_abe,
1000 &omap44xx_dsp__iva,
1001};
1002
1003/* l4_cfg -> dsp */
1004static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1005 .master = &omap44xx_l4_cfg_hwmod,
1006 .slave = &omap44xx_dsp_hwmod,
1007 .clk = "l4_div_ck",
1008 .user = OCP_USER_MPU | OCP_USER_SDMA,
1009};
1010
1011/* dsp slave ports */
1012static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1013 &omap44xx_l4_cfg__dsp,
1014};
1015
1016/* Pseudo hwmod for reset control purpose only */
1017static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1018 .name = "dsp_c0",
1019 .class = &omap44xx_dsp_hwmod_class,
1020 .flags = HWMOD_INIT_NO_RESET,
1021 .rst_lines = omap44xx_dsp_c0_resets,
1022 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1023 .prcm = {
1024 .omap4 = {
1025 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1026 },
1027 },
1028 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1029};
1030
1031static struct omap_hwmod omap44xx_dsp_hwmod = {
1032 .name = "dsp",
1033 .class = &omap44xx_dsp_hwmod_class,
1034 .mpu_irqs = omap44xx_dsp_irqs,
1035 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
1036 .rst_lines = omap44xx_dsp_resets,
1037 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1038 .main_clk = "dsp_fck",
1039 .prcm = {
1040 .omap4 = {
1041 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1042 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1043 },
1044 },
1045 .slaves = omap44xx_dsp_slaves,
1046 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1047 .masters = omap44xx_dsp_masters,
1048 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1049 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1050};
1051
d63bd74f
BC		 1052/*
1053 * 'dss' class
1054 * display sub-system
1055 */
1056
1057static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1058 .rev_offs = 0x0000,
1059 .syss_offs = 0x0014,
1060 .sysc_flags = SYSS_HAS_RESET_STATUS,
1061};
1062
1063static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1064 .name = "dss",
1065 .sysc = &omap44xx_dss_sysc,
1066};
1067
1068/* dss */
1069/* dss master ports */
1070static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1071 &omap44xx_dss__l3_main_1,
1072};
1073
1074static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1075 {
1076 .pa_start = 0x58000000,
1077 .pa_end = 0x5800007f,
1078 .flags = ADDR_TYPE_RT
1079 },
1080};
1081
1082/* l3_main_2 -> dss */
1083static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1084 .master = &omap44xx_l3_main_2_hwmod,
1085 .slave = &omap44xx_dss_hwmod,
1086 .clk = "l3_div_ck",
1087 .addr = omap44xx_dss_dma_addrs,
1088 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1089 .user = OCP_USER_SDMA,
1090};
1091
1092static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1093 {
1094 .pa_start = 0x48040000,
1095 .pa_end = 0x4804007f,
1096 .flags = ADDR_TYPE_RT
1097 },
1098};
1099
1100/* l4_per -> dss */
1101static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1102 .master = &omap44xx_l4_per_hwmod,
1103 .slave = &omap44xx_dss_hwmod,
1104 .clk = "l4_div_ck",
1105 .addr = omap44xx_dss_addrs,
1106 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
1107 .user = OCP_USER_MPU,
1108};
1109
1110/* dss slave ports */
1111static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1112 &omap44xx_l3_main_2__dss,
1113 &omap44xx_l4_per__dss,
1114};
1115
1116static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1117 { .role = "sys_clk", .clk = "dss_sys_clk" },
1118 { .role = "tv_clk", .clk = "dss_tv_clk" },
1119 { .role = "dss_clk", .clk = "dss_dss_clk" },
1120 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1121};
1122
1123static struct omap_hwmod omap44xx_dss_hwmod = {
1124 .name = "dss_core",
1125 .class = &omap44xx_dss_hwmod_class,
1126 .main_clk = "dss_fck",
1127 .prcm = {
1128 .omap4 = {
1129 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1130 },
1131 },
1132 .opt_clks = dss_opt_clks,
1133 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1134 .slaves = omap44xx_dss_slaves,
1135 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1136 .masters = omap44xx_dss_masters,
1137 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1139};
1140
1141/*
1142 * 'dispc' class
1143 * display controller
1144 */
1145
1146static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1147 .rev_offs = 0x0000,
1148 .sysc_offs = 0x0010,
1149 .syss_offs = 0x0014,
1150 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1151 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1152 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1153 SYSS_HAS_RESET_STATUS),
1154 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1155 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1156 .sysc_fields = &omap_hwmod_sysc_type1,
1157};
1158
1159static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1160 .name = "dispc",
1161 .sysc = &omap44xx_dispc_sysc,
1162};
1163
1164/* dss_dispc */
1165static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1166static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1167 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1168};
1169
1170static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1171 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1172};
1173
1174static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1175 {
1176 .pa_start = 0x58001000,
1177 .pa_end = 0x58001fff,
1178 .flags = ADDR_TYPE_RT
1179 },
1180};
1181
1182/* l3_main_2 -> dss_dispc */
1183static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1184 .master = &omap44xx_l3_main_2_hwmod,
1185 .slave = &omap44xx_dss_dispc_hwmod,
1186 .clk = "l3_div_ck",
1187 .addr = omap44xx_dss_dispc_dma_addrs,
1188 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1189 .user = OCP_USER_SDMA,
1190};
1191
1192static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1193 {
1194 .pa_start = 0x48041000,
1195 .pa_end = 0x48041fff,
1196 .flags = ADDR_TYPE_RT
1197 },
1198};
1199
1200/* l4_per -> dss_dispc */
1201static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1202 .master = &omap44xx_l4_per_hwmod,
1203 .slave = &omap44xx_dss_dispc_hwmod,
1204 .clk = "l4_div_ck",
1205 .addr = omap44xx_dss_dispc_addrs,
1206 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1207 .user = OCP_USER_MPU,
1208};
1209
1210/* dss_dispc slave ports */
1211static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1212 &omap44xx_l3_main_2__dss_dispc,
1213 &omap44xx_l4_per__dss_dispc,
1214};
1215
1216static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1217 .name = "dss_dispc",
1218 .class = &omap44xx_dispc_hwmod_class,
1219 .mpu_irqs = omap44xx_dss_dispc_irqs,
1220 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1221 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1222 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1223 .main_clk = "dss_fck",
1224 .prcm = {
1225 .omap4 = {
1226 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1227 },
1228 },
1229 .slaves = omap44xx_dss_dispc_slaves,
1230 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1232};
1233
1234/*
1235 * 'dsi' class
1236 * display serial interface controller
1237 */
1238
1239static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1240 .rev_offs = 0x0000,
1241 .sysc_offs = 0x0010,
1242 .syss_offs = 0x0014,
1243 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1244 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1245 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1246 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1247 .sysc_fields = &omap_hwmod_sysc_type1,
1248};
1249
1250static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1251 .name = "dsi",
1252 .sysc = &omap44xx_dsi_sysc,
1253};
1254
1255/* dss_dsi1 */
1256static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1257static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1258 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1259};
1260
1261static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1262 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1263};
1264
1265static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1266 {
1267 .pa_start = 0x58004000,
1268 .pa_end = 0x580041ff,
1269 .flags = ADDR_TYPE_RT
1270 },
1271};
1272
1273/* l3_main_2 -> dss_dsi1 */
1274static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1275 .master = &omap44xx_l3_main_2_hwmod,
1276 .slave = &omap44xx_dss_dsi1_hwmod,
1277 .clk = "l3_div_ck",
1278 .addr = omap44xx_dss_dsi1_dma_addrs,
1279 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1280 .user = OCP_USER_SDMA,
1281};
1282
1283static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1284 {
1285 .pa_start = 0x48044000,
1286 .pa_end = 0x480441ff,
1287 .flags = ADDR_TYPE_RT
1288 },
1289};
1290
1291/* l4_per -> dss_dsi1 */
1292static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1293 .master = &omap44xx_l4_per_hwmod,
1294 .slave = &omap44xx_dss_dsi1_hwmod,
1295 .clk = "l4_div_ck",
1296 .addr = omap44xx_dss_dsi1_addrs,
1297 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1298 .user = OCP_USER_MPU,
1299};
1300
1301/* dss_dsi1 slave ports */
1302static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1303 &omap44xx_l3_main_2__dss_dsi1,
1304 &omap44xx_l4_per__dss_dsi1,
1305};
1306
1307static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1308 .name = "dss_dsi1",
1309 .class = &omap44xx_dsi_hwmod_class,
1310 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1311 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1312 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1313 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1314 .main_clk = "dss_fck",
1315 .prcm = {
1316 .omap4 = {
1317 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1318 },
1319 },
1320 .slaves = omap44xx_dss_dsi1_slaves,
1321 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1322 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1323};
1324
1325/* dss_dsi2 */
1326static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1327static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1328 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1329};
1330
1331static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1332 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1333};
1334
1335static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1336 {
1337 .pa_start = 0x58005000,
1338 .pa_end = 0x580051ff,
1339 .flags = ADDR_TYPE_RT
1340 },
1341};
1342
1343/* l3_main_2 -> dss_dsi2 */
1344static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1345 .master = &omap44xx_l3_main_2_hwmod,
1346 .slave = &omap44xx_dss_dsi2_hwmod,
1347 .clk = "l3_div_ck",
1348 .addr = omap44xx_dss_dsi2_dma_addrs,
1349 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1350 .user = OCP_USER_SDMA,
1351};
1352
1353static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1354 {
1355 .pa_start = 0x48045000,
1356 .pa_end = 0x480451ff,
1357 .flags = ADDR_TYPE_RT
1358 },
1359};
1360
1361/* l4_per -> dss_dsi2 */
1362static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1363 .master = &omap44xx_l4_per_hwmod,
1364 .slave = &omap44xx_dss_dsi2_hwmod,
1365 .clk = "l4_div_ck",
1366 .addr = omap44xx_dss_dsi2_addrs,
1367 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1368 .user = OCP_USER_MPU,
1369};
1370
1371/* dss_dsi2 slave ports */
1372static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1373 &omap44xx_l3_main_2__dss_dsi2,
1374 &omap44xx_l4_per__dss_dsi2,
1375};
1376
1377static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1378 .name = "dss_dsi2",
1379 .class = &omap44xx_dsi_hwmod_class,
1380 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1381 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1382 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1383 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1384 .main_clk = "dss_fck",
1385 .prcm = {
1386 .omap4 = {
1387 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1388 },
1389 },
1390 .slaves = omap44xx_dss_dsi2_slaves,
1391 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1392 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1393};
1394
1395/*
1396 * 'hdmi' class
1397 * hdmi controller
1398 */
1399
1400static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1401 .rev_offs = 0x0000,
1402 .sysc_offs = 0x0010,
1403 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1404 SYSC_HAS_SOFTRESET),
1405 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1406 SIDLE_SMART_WKUP),
1407 .sysc_fields = &omap_hwmod_sysc_type2,
1408};
1409
1410static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1411 .name = "hdmi",
1412 .sysc = &omap44xx_hdmi_sysc,
1413};
1414
1415/* dss_hdmi */
1416static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1417static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1418 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1419};
1420
1421static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1422 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1423};
1424
1425static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1426 {
1427 .pa_start = 0x58006000,
1428 .pa_end = 0x58006fff,
1429 .flags = ADDR_TYPE_RT
1430 },
1431};
1432
1433/* l3_main_2 -> dss_hdmi */
1434static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1435 .master = &omap44xx_l3_main_2_hwmod,
1436 .slave = &omap44xx_dss_hdmi_hwmod,
1437 .clk = "l3_div_ck",
1438 .addr = omap44xx_dss_hdmi_dma_addrs,
1439 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1440 .user = OCP_USER_SDMA,
1441};
1442
1443static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1444 {
1445 .pa_start = 0x48046000,
1446 .pa_end = 0x48046fff,
1447 .flags = ADDR_TYPE_RT
1448 },
1449};
1450
1451/* l4_per -> dss_hdmi */
1452static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1453 .master = &omap44xx_l4_per_hwmod,
1454 .slave = &omap44xx_dss_hdmi_hwmod,
1455 .clk = "l4_div_ck",
1456 .addr = omap44xx_dss_hdmi_addrs,
1457 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1458 .user = OCP_USER_MPU,
1459};
1460
1461/* dss_hdmi slave ports */
1462static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1463 &omap44xx_l3_main_2__dss_hdmi,
1464 &omap44xx_l4_per__dss_hdmi,
1465};
1466
1467static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1468 .name = "dss_hdmi",
1469 .class = &omap44xx_hdmi_hwmod_class,
1470 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1471 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1472 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1473 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1474 .main_clk = "dss_fck",
1475 .prcm = {
1476 .omap4 = {
1477 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1478 },
1479 },
1480 .slaves = omap44xx_dss_hdmi_slaves,
1481 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1482 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1483};
1484
1485/*
1486 * 'rfbi' class
1487 * remote frame buffer interface
1488 */
1489
1490static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1491 .rev_offs = 0x0000,
1492 .sysc_offs = 0x0010,
1493 .syss_offs = 0x0014,
1494 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1495 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1497 .sysc_fields = &omap_hwmod_sysc_type1,
1498};
1499
1500static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1501 .name = "rfbi",
1502 .sysc = &omap44xx_rfbi_sysc,
1503};
1504
1505/* dss_rfbi */
1506static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1507static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1508 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1509};
1510
1511static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1512 {
1513 .pa_start = 0x58002000,
1514 .pa_end = 0x580020ff,
1515 .flags = ADDR_TYPE_RT
1516 },
1517};
1518
1519/* l3_main_2 -> dss_rfbi */
1520static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1521 .master = &omap44xx_l3_main_2_hwmod,
1522 .slave = &omap44xx_dss_rfbi_hwmod,
1523 .clk = "l3_div_ck",
1524 .addr = omap44xx_dss_rfbi_dma_addrs,
1525 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1526 .user = OCP_USER_SDMA,
1527};
1528
1529static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1530 {
1531 .pa_start = 0x48042000,
1532 .pa_end = 0x480420ff,
1533 .flags = ADDR_TYPE_RT
1534 },
1535};
1536
1537/* l4_per -> dss_rfbi */
1538static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1539 .master = &omap44xx_l4_per_hwmod,
1540 .slave = &omap44xx_dss_rfbi_hwmod,
1541 .clk = "l4_div_ck",
1542 .addr = omap44xx_dss_rfbi_addrs,
1543 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1544 .user = OCP_USER_MPU,
1545};
1546
1547/* dss_rfbi slave ports */
1548static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1549 &omap44xx_l3_main_2__dss_rfbi,
1550 &omap44xx_l4_per__dss_rfbi,
1551};
1552
1553static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1554 .name = "dss_rfbi",
1555 .class = &omap44xx_rfbi_hwmod_class,
1556 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1557 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1558 .main_clk = "dss_fck",
1559 .prcm = {
1560 .omap4 = {
1561 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1562 },
1563 },
1564 .slaves = omap44xx_dss_rfbi_slaves,
1565 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1566 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1567};
1568
1569/*
1570 * 'venc' class
1571 * video encoder
1572 */
1573
1574static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1575 .name = "venc",
1576};
1577
1578/* dss_venc */
1579static struct omap_hwmod omap44xx_dss_venc_hwmod;
1580static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1581 {
1582 .pa_start = 0x58003000,
1583 .pa_end = 0x580030ff,
1584 .flags = ADDR_TYPE_RT
1585 },
1586};
1587
1588/* l3_main_2 -> dss_venc */
1589static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1590 .master = &omap44xx_l3_main_2_hwmod,
1591 .slave = &omap44xx_dss_venc_hwmod,
1592 .clk = "l3_div_ck",
1593 .addr = omap44xx_dss_venc_dma_addrs,
1594 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1595 .user = OCP_USER_SDMA,
1596};
1597
1598static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1599 {
1600 .pa_start = 0x48043000,
1601 .pa_end = 0x480430ff,
1602 .flags = ADDR_TYPE_RT
1603 },
1604};
1605
1606/* l4_per -> dss_venc */
1607static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1608 .master = &omap44xx_l4_per_hwmod,
1609 .slave = &omap44xx_dss_venc_hwmod,
1610 .clk = "l4_div_ck",
1611 .addr = omap44xx_dss_venc_addrs,
1612 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1613 .user = OCP_USER_MPU,
1614};
1615
1616/* dss_venc slave ports */
1617static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1618 &omap44xx_l3_main_2__dss_venc,
1619 &omap44xx_l4_per__dss_venc,
1620};
1621
1622static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1623 .name = "dss_venc",
1624 .class = &omap44xx_venc_hwmod_class,
1625 .main_clk = "dss_fck",
1626 .prcm = {
1627 .omap4 = {
1628 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1629 },
1630 },
1631 .slaves = omap44xx_dss_venc_slaves,
1632 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1633 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1634};
1635
3b54baad
BC		 1636/*
1637 * 'gpio' class
1638 * general purpose io module
1639 */
1640
1641static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1642 .rev_offs = 0x0000,
f776471f 1643 .sysc_offs = 0x0010,
3b54baad 1644 .syss_offs = 0x0114,
0cfe8751
BC		 1645 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1646 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1647 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1648 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1649 SIDLE_SMART_WKUP),
f776471f
BC		 1650 .sysc_fields = &omap_hwmod_sysc_type1,
1651};
1652
3b54baad 1653static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 1654 .name = "gpio",
1655 .sysc = &omap44xx_gpio_sysc,
1656 .rev = 2,
f776471f
BC		 1657};
1658
3b54baad
BC		 1659/* gpio dev_attr */
1660static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 1661 .bank_width = 32,
1662 .dbck_flag = true,
f776471f
BC		 1663};
1664
3b54baad
BC		 1665/* gpio1 */
1666static struct omap_hwmod omap44xx_gpio1_hwmod;
1667static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1668 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1669};
1670
3b54baad 1671static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 1672 {
3b54baad
BC		 1673 .pa_start = 0x4a310000,
1674 .pa_end = 0x4a3101ff,
f776471f
BC		 1675 .flags = ADDR_TYPE_RT
1676 },
1677};
1678
3b54baad
BC		 1679/* l4_wkup -> gpio1 */
1680static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1681 .master = &omap44xx_l4_wkup_hwmod,
1682 .slave = &omap44xx_gpio1_hwmod,
b399bca8 1683 .clk = "l4_wkup_clk_mux_ck",
3b54baad
BC		 1684 .addr = omap44xx_gpio1_addrs,
1685 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
f776471f
BC		 1686 .user = OCP_USER_MPU | OCP_USER_SDMA,
1687};
1688
3b54baad
BC		 1689/* gpio1 slave ports */
1690static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1691 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 1692};
1693
3b54baad 1694static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 1695 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 1696};
1697
1698static struct omap_hwmod omap44xx_gpio1_hwmod = {
1699 .name = "gpio1",
1700 .class = &omap44xx_gpio_hwmod_class,
1701 .mpu_irqs = omap44xx_gpio1_irqs,
1702 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1703 .main_clk = "gpio1_ick",
f776471f
BC		 1704 .prcm = {
1705 .omap4 = {
3b54baad 1706 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
f776471f
BC		 1707 },
1708 },
3b54baad
BC		 1709 .opt_clks = gpio1_opt_clks,
1710 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1711 .dev_attr = &gpio_dev_attr,
1712 .slaves = omap44xx_gpio1_slaves,
1713 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 1714 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1715};
1716
3b54baad
BC		 1717/* gpio2 */
1718static struct omap_hwmod omap44xx_gpio2_hwmod;
1719static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1720 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1721};
1722
3b54baad 1723static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 1724 {
3b54baad
BC		 1725 .pa_start = 0x48055000,
1726 .pa_end = 0x480551ff,
f776471f
BC		 1727 .flags = ADDR_TYPE_RT
1728 },
1729};
1730
3b54baad
BC		 1731/* l4_per -> gpio2 */
1732static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 1733 .master = &omap44xx_l4_per_hwmod,
3b54baad 1734 .slave = &omap44xx_gpio2_hwmod,
b399bca8 1735 .clk = "l4_div_ck",
3b54baad
BC		 1736 .addr = omap44xx_gpio2_addrs,
1737 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
f776471f
BC		 1738 .user = OCP_USER_MPU | OCP_USER_SDMA,
1739};
1740
3b54baad
BC		 1741/* gpio2 slave ports */
1742static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1743 &omap44xx_l4_per__gpio2,
f776471f
BC		 1744};
1745
3b54baad 1746static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 1747 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 1748};
1749
1750static struct omap_hwmod omap44xx_gpio2_hwmod = {
1751 .name = "gpio2",
1752 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1753 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1754 .mpu_irqs = omap44xx_gpio2_irqs,
1755 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1756 .main_clk = "gpio2_ick",
f776471f
BC		 1757 .prcm = {
1758 .omap4 = {
3b54baad 1759 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
f776471f
BC		 1760 },
1761 },
3b54baad
BC		 1762 .opt_clks = gpio2_opt_clks,
1763 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1764 .dev_attr = &gpio_dev_attr,
1765 .slaves = omap44xx_gpio2_slaves,
1766 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 1767 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1768};
1769
3b54baad
BC		 1770/* gpio3 */
1771static struct omap_hwmod omap44xx_gpio3_hwmod;
1772static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1773 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1774};
1775
3b54baad 1776static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 1777 {
3b54baad
BC		 1778 .pa_start = 0x48057000,
1779 .pa_end = 0x480571ff,
f776471f
BC		 1780 .flags = ADDR_TYPE_RT
1781 },
1782};
1783
3b54baad
BC		 1784/* l4_per -> gpio3 */
1785static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 1786 .master = &omap44xx_l4_per_hwmod,
3b54baad 1787 .slave = &omap44xx_gpio3_hwmod,
b399bca8 1788 .clk = "l4_div_ck",
3b54baad
BC		 1789 .addr = omap44xx_gpio3_addrs,
1790 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
f776471f
BC		 1791 .user = OCP_USER_MPU | OCP_USER_SDMA,
1792};
1793
3b54baad
BC		 1794/* gpio3 slave ports */
1795static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1796 &omap44xx_l4_per__gpio3,
f776471f
BC		 1797};
1798
3b54baad 1799static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 1800 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 1801};
1802
1803static struct omap_hwmod omap44xx_gpio3_hwmod = {
1804 .name = "gpio3",
1805 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1806 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1807 .mpu_irqs = omap44xx_gpio3_irqs,
1808 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
1809 .main_clk = "gpio3_ick",
f776471f
BC		 1810 .prcm = {
1811 .omap4 = {
3b54baad 1812 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
f776471f
BC		 1813 },
1814 },
3b54baad
BC		 1815 .opt_clks = gpio3_opt_clks,
1816 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1817 .dev_attr = &gpio_dev_attr,
1818 .slaves = omap44xx_gpio3_slaves,
1819 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 1820 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1821};
1822
3b54baad
BC		 1823/* gpio4 */
1824static struct omap_hwmod omap44xx_gpio4_hwmod;
1825static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1826 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1827};
1828
3b54baad 1829static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 1830 {
3b54baad
BC		 1831 .pa_start = 0x48059000,
1832 .pa_end = 0x480591ff,
f776471f
BC		 1833 .flags = ADDR_TYPE_RT
1834 },
1835};
1836
3b54baad
BC		 1837/* l4_per -> gpio4 */
1838static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 1839 .master = &omap44xx_l4_per_hwmod,
3b54baad 1840 .slave = &omap44xx_gpio4_hwmod,
b399bca8 1841 .clk = "l4_div_ck",
3b54baad
BC		 1842 .addr = omap44xx_gpio4_addrs,
1843 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
f776471f
BC		 1844 .user = OCP_USER_MPU | OCP_USER_SDMA,
1845};
1846
3b54baad
BC		 1847/* gpio4 slave ports */
1848static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1849 &omap44xx_l4_per__gpio4,
f776471f
BC		 1850};
1851
3b54baad 1852static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 1853 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 1854};
1855
1856static struct omap_hwmod omap44xx_gpio4_hwmod = {
1857 .name = "gpio4",
1858 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1859 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1860 .mpu_irqs = omap44xx_gpio4_irqs,
1861 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1862 .main_clk = "gpio4_ick",
f776471f
BC		 1863 .prcm = {
1864 .omap4 = {
3b54baad 1865 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
f776471f
BC		 1866 },
1867 },
3b54baad
BC		 1868 .opt_clks = gpio4_opt_clks,
1869 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1870 .dev_attr = &gpio_dev_attr,
1871 .slaves = omap44xx_gpio4_slaves,
1872 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 1873 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1874};
1875
3b54baad
BC		 1876/* gpio5 */
1877static struct omap_hwmod omap44xx_gpio5_hwmod;
1878static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1879 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
55d2cb08
BC		 1880};
1881
3b54baad
BC		 1882static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1883 {
1884 .pa_start = 0x4805b000,
1885 .pa_end = 0x4805b1ff,
1886 .flags = ADDR_TYPE_RT
1887 },
55d2cb08
BC		 1888};
1889
3b54baad
BC		 1890/* l4_per -> gpio5 */
1891static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1892 .master = &omap44xx_l4_per_hwmod,
1893 .slave = &omap44xx_gpio5_hwmod,
b399bca8 1894 .clk = "l4_div_ck",
3b54baad
BC		 1895 .addr = omap44xx_gpio5_addrs,
1896 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1897 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 1898};
1899
3b54baad
BC		 1900/* gpio5 slave ports */
1901static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1902 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 1903};
1904
3b54baad 1905static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 1906 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 1907};
1908
3b54baad
BC		 1909static struct omap_hwmod omap44xx_gpio5_hwmod = {
1910 .name = "gpio5",
1911 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1912 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1913 .mpu_irqs = omap44xx_gpio5_irqs,
1914 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1915 .main_clk = "gpio5_ick",
55d2cb08
BC		 1916 .prcm = {
1917 .omap4 = {
3b54baad 1918 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
55d2cb08
BC		 1919 },
1920 },
3b54baad
BC		 1921 .opt_clks = gpio5_opt_clks,
1922 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1923 .dev_attr = &gpio_dev_attr,
1924 .slaves = omap44xx_gpio5_slaves,
1925 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 1926 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1927};
1928
3b54baad
BC		 1929/* gpio6 */
1930static struct omap_hwmod omap44xx_gpio6_hwmod;
1931static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1932 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 1933};
1934
3b54baad 1935static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 1936 {
3b54baad
BC		 1937 .pa_start = 0x4805d000,
1938 .pa_end = 0x4805d1ff,
92b18d1c
BC		 1939 .flags = ADDR_TYPE_RT
1940 },
1941};
1942
3b54baad
BC		 1943/* l4_per -> gpio6 */
1944static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1945 .master = &omap44xx_l4_per_hwmod,
1946 .slave = &omap44xx_gpio6_hwmod,
b399bca8 1947 .clk = "l4_div_ck",
3b54baad
BC		 1948 .addr = omap44xx_gpio6_addrs,
1949 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
1950 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 1951};
1952
3b54baad
BC		 1953/* gpio6 slave ports */
1954static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1955 &omap44xx_l4_per__gpio6,
db12ba53
BC		 1956};
1957
3b54baad 1958static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 1959 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 1960};
1961
3b54baad
BC		 1962static struct omap_hwmod omap44xx_gpio6_hwmod = {
1963 .name = "gpio6",
1964 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1966 .mpu_irqs = omap44xx_gpio6_irqs,
1967 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
1968 .main_clk = "gpio6_ick",
1969 .prcm = {
1970 .omap4 = {
1971 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1972 },
db12ba53 1973 },
3b54baad
BC		 1974 .opt_clks = gpio6_opt_clks,
1975 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1976 .dev_attr = &gpio_dev_attr,
1977 .slaves = omap44xx_gpio6_slaves,
1978 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1979 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 1980};
1981
407a6888
BC		 1982/*
1983 * 'hsi' class
1984 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1985 * serial if)
1986 */
1987
1988static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1989 .rev_offs = 0x0000,
1990 .sysc_offs = 0x0010,
1991 .syss_offs = 0x0014,
1992 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1993 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1994 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1995 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1996 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1997 MSTANDBY_SMART),
1998 .sysc_fields = &omap_hwmod_sysc_type1,
1999};
2000
2001static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2002 .name = "hsi",
2003 .sysc = &omap44xx_hsi_sysc,
2004};
2005
2006/* hsi */
2007static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2008 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2009 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2010 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2011};
2012
2013/* hsi master ports */
2014static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2015 &omap44xx_hsi__l3_main_2,
2016};
2017
2018static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2019 {
2020 .pa_start = 0x4a058000,
2021 .pa_end = 0x4a05bfff,
2022 .flags = ADDR_TYPE_RT
2023 },
2024};
2025
2026/* l4_cfg -> hsi */
2027static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2028 .master = &omap44xx_l4_cfg_hwmod,
2029 .slave = &omap44xx_hsi_hwmod,
2030 .clk = "l4_div_ck",
2031 .addr = omap44xx_hsi_addrs,
2032 .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
2033 .user = OCP_USER_MPU | OCP_USER_SDMA,
2034};
2035
2036/* hsi slave ports */
2037static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2038 &omap44xx_l4_cfg__hsi,
2039};
2040
2041static struct omap_hwmod omap44xx_hsi_hwmod = {
2042 .name = "hsi",
2043 .class = &omap44xx_hsi_hwmod_class,
2044 .mpu_irqs = omap44xx_hsi_irqs,
2045 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
2046 .main_clk = "hsi_fck",
2047 .prcm = {
2048 .omap4 = {
2049 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2050 },
2051 },
2052 .slaves = omap44xx_hsi_slaves,
2053 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2054 .masters = omap44xx_hsi_masters,
2055 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2056 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2057};
2058
3b54baad
BC		 2059/*
2060 * 'i2c' class
2061 * multimaster high-speed i2c controller
2062 */
db12ba53 2063
3b54baad
BC		 2064static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2065 .sysc_offs = 0x0010,
2066 .syss_offs = 0x0090,
2067 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2068 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 2069 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2070 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2071 SIDLE_SMART_WKUP),
3b54baad 2072 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 2073};
2074
3b54baad 2075static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 2076 .name = "i2c",
2077 .sysc = &omap44xx_i2c_sysc,
db12ba53
BC		 2078};
2079
3b54baad
BC		 2080/* i2c1 */
2081static struct omap_hwmod omap44xx_i2c1_hwmod;
2082static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2083 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 2084};
2085
3b54baad
BC		 2086static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2087 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2088 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 2089};
2090
3b54baad 2091static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 2092 {
3b54baad
BC		 2093 .pa_start = 0x48070000,
2094 .pa_end = 0x480700ff,
db12ba53
BC		 2095 .flags = ADDR_TYPE_RT
2096 },
2097};
2098
3b54baad
BC		 2099/* l4_per -> i2c1 */
2100static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2101 .master = &omap44xx_l4_per_hwmod,
2102 .slave = &omap44xx_i2c1_hwmod,
2103 .clk = "l4_div_ck",
2104 .addr = omap44xx_i2c1_addrs,
2105 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
92b18d1c
BC		 2106 .user = OCP_USER_MPU | OCP_USER_SDMA,
2107};
2108
3b54baad
BC		 2109/* i2c1 slave ports */
2110static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2111 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 2112};
2113
3b54baad
BC		 2114static struct omap_hwmod omap44xx_i2c1_hwmod = {
2115 .name = "i2c1",
2116 .class = &omap44xx_i2c_hwmod_class,
2117 .flags = HWMOD_INIT_NO_RESET,
2118 .mpu_irqs = omap44xx_i2c1_irqs,
2119 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
2120 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2121 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2122 .main_clk = "i2c1_fck",
92b18d1c
BC		 2123 .prcm = {
2124 .omap4 = {
3b54baad 2125 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
92b18d1c
BC		 2126 },
2127 },
3b54baad
BC		 2128 .slaves = omap44xx_i2c1_slaves,
2129 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
92b18d1c
BC		 2130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2131};
2132
3b54baad
BC		 2133/* i2c2 */
2134static struct omap_hwmod omap44xx_i2c2_hwmod;
2135static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2136 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 2137};
2138
3b54baad
BC		 2139static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2140 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2141 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2142};
2143
2144static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 2145 {
3b54baad
BC		 2146 .pa_start = 0x48072000,
2147 .pa_end = 0x480720ff,
92b18d1c
BC		 2148 .flags = ADDR_TYPE_RT
2149 },
2150};
2151
3b54baad
BC		 2152/* l4_per -> i2c2 */
2153static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 2154 .master = &omap44xx_l4_per_hwmod,
3b54baad 2155 .slave = &omap44xx_i2c2_hwmod,
db12ba53 2156 .clk = "l4_div_ck",
3b54baad
BC		 2157 .addr = omap44xx_i2c2_addrs,
2158 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
db12ba53
BC		 2159 .user = OCP_USER_MPU | OCP_USER_SDMA,
2160};
2161
3b54baad
BC		 2162/* i2c2 slave ports */
2163static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2164 &omap44xx_l4_per__i2c2,
db12ba53
BC		 2165};
2166
3b54baad
BC		 2167static struct omap_hwmod omap44xx_i2c2_hwmod = {
2168 .name = "i2c2",
2169 .class = &omap44xx_i2c_hwmod_class,
2170 .flags = HWMOD_INIT_NO_RESET,
2171 .mpu_irqs = omap44xx_i2c2_irqs,
2172 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
2173 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2174 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2175 .main_clk = "i2c2_fck",
db12ba53
BC		 2176 .prcm = {
2177 .omap4 = {
3b54baad 2178 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
db12ba53
BC		 2179 },
2180 },
3b54baad
BC		 2181 .slaves = omap44xx_i2c2_slaves,
2182 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
db12ba53
BC		 2183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2184};
2185
3b54baad
BC		 2186/* i2c3 */
2187static struct omap_hwmod omap44xx_i2c3_hwmod;
2188static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2189 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 2190};
2191
3b54baad
BC		 2192static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2193 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2194 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
92b18d1c
BC		 2195};
2196
3b54baad 2197static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 2198 {
3b54baad
BC		 2199 .pa_start = 0x48060000,
2200 .pa_end = 0x480600ff,
92b18d1c
BC		 2201 .flags = ADDR_TYPE_RT
2202 },
2203};
2204
3b54baad
BC		 2205/* l4_per -> i2c3 */
2206static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 2207 .master = &omap44xx_l4_per_hwmod,
3b54baad 2208 .slave = &omap44xx_i2c3_hwmod,
db12ba53 2209 .clk = "l4_div_ck",
3b54baad
BC		 2210 .addr = omap44xx_i2c3_addrs,
2211 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
db12ba53
BC		 2212 .user = OCP_USER_MPU | OCP_USER_SDMA,
2213};
2214
3b54baad
BC		 2215/* i2c3 slave ports */
2216static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2217 &omap44xx_l4_per__i2c3,
db12ba53
BC		 2218};
2219
3b54baad
BC		 2220static struct omap_hwmod omap44xx_i2c3_hwmod = {
2221 .name = "i2c3",
2222 .class = &omap44xx_i2c_hwmod_class,
2223 .flags = HWMOD_INIT_NO_RESET,
2224 .mpu_irqs = omap44xx_i2c3_irqs,
2225 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
2226 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2227 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2228 .main_clk = "i2c3_fck",
db12ba53
BC		 2229 .prcm = {
2230 .omap4 = {
3b54baad 2231 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
db12ba53
BC		 2232 },
2233 },
3b54baad
BC		 2234 .slaves = omap44xx_i2c3_slaves,
2235 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
db12ba53
BC		 2236 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2237};
2238
3b54baad
BC		 2239/* i2c4 */
2240static struct omap_hwmod omap44xx_i2c4_hwmod;
2241static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2242 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 2243};
2244
3b54baad
BC		 2245static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2246 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2247 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 2248};
2249
3b54baad 2250static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 2251 {
3b54baad
BC		 2252 .pa_start = 0x48350000,
2253 .pa_end = 0x483500ff,
db12ba53
BC		 2254 .flags = ADDR_TYPE_RT
2255 },
2256};
2257
3b54baad
BC		 2258/* l4_per -> i2c4 */
2259static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2260 .master = &omap44xx_l4_per_hwmod,
2261 .slave = &omap44xx_i2c4_hwmod,
2262 .clk = "l4_div_ck",
2263 .addr = omap44xx_i2c4_addrs,
2264 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
2265 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 2266};
2267
3b54baad
BC		 2268/* i2c4 slave ports */
2269static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2270 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 2271};
2272
3b54baad
BC		 2273static struct omap_hwmod omap44xx_i2c4_hwmod = {
2274 .name = "i2c4",
2275 .class = &omap44xx_i2c_hwmod_class,
2276 .flags = HWMOD_INIT_NO_RESET,
2277 .mpu_irqs = omap44xx_i2c4_irqs,
2278 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
2279 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2280 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2281 .main_clk = "i2c4_fck",
92b18d1c
BC		 2282 .prcm = {
2283 .omap4 = {
3b54baad 2284 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
92b18d1c
BC		 2285 },
2286 },
3b54baad
BC		 2287 .slaves = omap44xx_i2c4_slaves,
2288 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
92b18d1c
BC		 2289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2290};
2291
407a6888
BC		 2292/*
2293 * 'ipu' class
2294 * imaging processor unit
2295 */
2296
2297static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2298 .name = "ipu",
2299};
2300
2301/* ipu */
2302static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2303 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2304};
2305
2306static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2307 { .name = "cpu0", .rst_shift = 0 },
2308};
2309
2310static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2311 { .name = "cpu1", .rst_shift = 1 },
2312};
2313
2314static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2315 { .name = "mmu_cache", .rst_shift = 2 },
2316};
2317
2318/* ipu master ports */
2319static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2320 &omap44xx_ipu__l3_main_2,
2321};
2322
2323/* l3_main_2 -> ipu */
2324static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2325 .master = &omap44xx_l3_main_2_hwmod,
2326 .slave = &omap44xx_ipu_hwmod,
2327 .clk = "l3_div_ck",
2328 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329};
2330
2331/* ipu slave ports */
2332static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2333 &omap44xx_l3_main_2__ipu,
2334};
2335
2336/* Pseudo hwmod for reset control purpose only */
2337static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2338 .name = "ipu_c0",
2339 .class = &omap44xx_ipu_hwmod_class,
2340 .flags = HWMOD_INIT_NO_RESET,
2341 .rst_lines = omap44xx_ipu_c0_resets,
2342 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2343 .prcm = {
2344 .omap4 = {
2345 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2346 },
2347 },
2348 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2349};
2350
2351/* Pseudo hwmod for reset control purpose only */
2352static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2353 .name = "ipu_c1",
2354 .class = &omap44xx_ipu_hwmod_class,
2355 .flags = HWMOD_INIT_NO_RESET,
2356 .rst_lines = omap44xx_ipu_c1_resets,
2357 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2358 .prcm = {
2359 .omap4 = {
2360 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2361 },
2362 },
2363 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2364};
2365
2366static struct omap_hwmod omap44xx_ipu_hwmod = {
2367 .name = "ipu",
2368 .class = &omap44xx_ipu_hwmod_class,
2369 .mpu_irqs = omap44xx_ipu_irqs,
2370 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
2371 .rst_lines = omap44xx_ipu_resets,
2372 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2373 .main_clk = "ipu_fck",
2374 .prcm = {
2375 .omap4 = {
2376 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2377 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2378 },
2379 },
2380 .slaves = omap44xx_ipu_slaves,
2381 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2382 .masters = omap44xx_ipu_masters,
2383 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2384 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2385};
2386
2387/*
2388 * 'iss' class
2389 * external images sensor pixel data processor
2390 */
2391
2392static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2393 .rev_offs = 0x0000,
2394 .sysc_offs = 0x0010,
2395 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2396 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2398 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2399 MSTANDBY_SMART),
2400 .sysc_fields = &omap_hwmod_sysc_type2,
2401};
2402
2403static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2404 .name = "iss",
2405 .sysc = &omap44xx_iss_sysc,
2406};
2407
2408/* iss */
2409static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2410 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2411};
2412
2413static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2414 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2415 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2416 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2417 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2418};
2419
2420/* iss master ports */
2421static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2422 &omap44xx_iss__l3_main_2,
2423};
2424
2425static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2426 {
2427 .pa_start = 0x52000000,
2428 .pa_end = 0x520000ff,
2429 .flags = ADDR_TYPE_RT
2430 },
2431};
2432
2433/* l3_main_2 -> iss */
2434static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2435 .master = &omap44xx_l3_main_2_hwmod,
2436 .slave = &omap44xx_iss_hwmod,
2437 .clk = "l3_div_ck",
2438 .addr = omap44xx_iss_addrs,
2439 .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
2440 .user = OCP_USER_MPU | OCP_USER_SDMA,
2441};
2442
2443/* iss slave ports */
2444static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2445 &omap44xx_l3_main_2__iss,
2446};
2447
2448static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2449 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2450};
2451
2452static struct omap_hwmod omap44xx_iss_hwmod = {
2453 .name = "iss",
2454 .class = &omap44xx_iss_hwmod_class,
2455 .mpu_irqs = omap44xx_iss_irqs,
2456 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
2457 .sdma_reqs = omap44xx_iss_sdma_reqs,
2458 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2459 .main_clk = "iss_fck",
2460 .prcm = {
2461 .omap4 = {
2462 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2463 },
2464 },
2465 .opt_clks = iss_opt_clks,
2466 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2467 .slaves = omap44xx_iss_slaves,
2468 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2469 .masters = omap44xx_iss_masters,
2470 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2472};
2473
8f25bdc5
BC		 2474/*
2475 * 'iva' class
2476 * multi-standard video encoder/decoder hardware accelerator
2477 */
2478
2479static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 2480 .name = "iva",
8f25bdc5
BC		 2481};
2482
2483/* iva */
2484static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2485 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2486 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2487 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2488};
2489
2490static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2491 { .name = "logic", .rst_shift = 2 },
2492};
2493
2494static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2495 { .name = "seq0", .rst_shift = 0 },
2496};
2497
2498static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2499 { .name = "seq1", .rst_shift = 1 },
2500};
2501
2502/* iva master ports */
2503static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2504 &omap44xx_iva__l3_main_2,
2505 &omap44xx_iva__l3_instr,
2506};
2507
2508static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2509 {
2510 .pa_start = 0x5a000000,
2511 .pa_end = 0x5a07ffff,
2512 .flags = ADDR_TYPE_RT
2513 },
2514};
2515
2516/* l3_main_2 -> iva */
2517static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2518 .master = &omap44xx_l3_main_2_hwmod,
2519 .slave = &omap44xx_iva_hwmod,
2520 .clk = "l3_div_ck",
2521 .addr = omap44xx_iva_addrs,
2522 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
2523 .user = OCP_USER_MPU,
2524};
2525
2526/* iva slave ports */
2527static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2528 &omap44xx_dsp__iva,
2529 &omap44xx_l3_main_2__iva,
2530};
2531
2532/* Pseudo hwmod for reset control purpose only */
2533static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2534 .name = "iva_seq0",
2535 .class = &omap44xx_iva_hwmod_class,
2536 .flags = HWMOD_INIT_NO_RESET,
2537 .rst_lines = omap44xx_iva_seq0_resets,
2538 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2539 .prcm = {
2540 .omap4 = {
2541 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2542 },
2543 },
2544 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2545};
2546
2547/* Pseudo hwmod for reset control purpose only */
2548static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2549 .name = "iva_seq1",
2550 .class = &omap44xx_iva_hwmod_class,
2551 .flags = HWMOD_INIT_NO_RESET,
2552 .rst_lines = omap44xx_iva_seq1_resets,
2553 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2554 .prcm = {
2555 .omap4 = {
2556 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2557 },
2558 },
2559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2560};
2561
2562static struct omap_hwmod omap44xx_iva_hwmod = {
2563 .name = "iva",
2564 .class = &omap44xx_iva_hwmod_class,
2565 .mpu_irqs = omap44xx_iva_irqs,
2566 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
2567 .rst_lines = omap44xx_iva_resets,
2568 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2569 .main_clk = "iva_fck",
2570 .prcm = {
2571 .omap4 = {
2572 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2573 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2574 },
2575 },
2576 .slaves = omap44xx_iva_slaves,
2577 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2578 .masters = omap44xx_iva_masters,
2579 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2581};
2582
407a6888
BC		 2583/*
2584 * 'kbd' class
2585 * keyboard controller
2586 */
2587
2588static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2589 .rev_offs = 0x0000,
2590 .sysc_offs = 0x0010,
2591 .syss_offs = 0x0014,
2592 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2593 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2594 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2595 SYSS_HAS_RESET_STATUS),
2596 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2597 .sysc_fields = &omap_hwmod_sysc_type1,
2598};
2599
2600static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2601 .name = "kbd",
2602 .sysc = &omap44xx_kbd_sysc,
2603};
2604
2605/* kbd */
2606static struct omap_hwmod omap44xx_kbd_hwmod;
2607static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2608 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2609};
2610
2611static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2612 {
2613 .pa_start = 0x4a31c000,
2614 .pa_end = 0x4a31c07f,
2615 .flags = ADDR_TYPE_RT
2616 },
2617};
2618
2619/* l4_wkup -> kbd */
2620static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2621 .master = &omap44xx_l4_wkup_hwmod,
2622 .slave = &omap44xx_kbd_hwmod,
2623 .clk = "l4_wkup_clk_mux_ck",
2624 .addr = omap44xx_kbd_addrs,
2625 .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
2626 .user = OCP_USER_MPU | OCP_USER_SDMA,
2627};
2628
2629/* kbd slave ports */
2630static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2631 &omap44xx_l4_wkup__kbd,
2632};
2633
2634static struct omap_hwmod omap44xx_kbd_hwmod = {
2635 .name = "kbd",
2636 .class = &omap44xx_kbd_hwmod_class,
2637 .mpu_irqs = omap44xx_kbd_irqs,
2638 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
2639 .main_clk = "kbd_fck",
2640 .prcm = {
2641 .omap4 = {
2642 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2643 },
2644 },
2645 .slaves = omap44xx_kbd_slaves,
2646 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2647 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2648};
2649
ec5df927
BC		 2650/*
2651 * 'mailbox' class
2652 * mailbox module allowing communication between the on-chip processors using a
2653 * queued mailbox-interrupt mechanism.
2654 */
2655
2656static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2657 .rev_offs = 0x0000,
2658 .sysc_offs = 0x0010,
2659 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2660 SYSC_HAS_SOFTRESET),
2661 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2662 .sysc_fields = &omap_hwmod_sysc_type2,
2663};
2664
2665static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2666 .name = "mailbox",
2667 .sysc = &omap44xx_mailbox_sysc,
2668};
2669
2670/* mailbox */
2671static struct omap_hwmod omap44xx_mailbox_hwmod;
2672static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2673 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2674};
2675
2676static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2677 {
2678 .pa_start = 0x4a0f4000,
2679 .pa_end = 0x4a0f41ff,
2680 .flags = ADDR_TYPE_RT
2681 },
2682};
2683
2684/* l4_cfg -> mailbox */
2685static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2686 .master = &omap44xx_l4_cfg_hwmod,
2687 .slave = &omap44xx_mailbox_hwmod,
2688 .clk = "l4_div_ck",
2689 .addr = omap44xx_mailbox_addrs,
2690 .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
2691 .user = OCP_USER_MPU | OCP_USER_SDMA,
2692};
2693
2694/* mailbox slave ports */
2695static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2696 &omap44xx_l4_cfg__mailbox,
2697};
2698
2699static struct omap_hwmod omap44xx_mailbox_hwmod = {
2700 .name = "mailbox",
2701 .class = &omap44xx_mailbox_hwmod_class,
2702 .mpu_irqs = omap44xx_mailbox_irqs,
2703 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
2704 .prcm = {
2705 .omap4 = {
2706 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2707 },
2708 },
2709 .slaves = omap44xx_mailbox_slaves,
2710 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2711 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2712};
2713
4ddff493
BC		 2714/*
2715 * 'mcbsp' class
2716 * multi channel buffered serial port controller
2717 */
2718
2719static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2720 .sysc_offs = 0x008c,
2721 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2722 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2723 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2724 .sysc_fields = &omap_hwmod_sysc_type1,
2725};
2726
2727static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2728 .name = "mcbsp",
2729 .sysc = &omap44xx_mcbsp_sysc,
2730};
2731
2732/* mcbsp1 */
2733static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2734static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2735 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2736};
2737
2738static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2739 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2740 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2741};
2742
2743static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2744 {
2745 .pa_start = 0x40122000,
2746 .pa_end = 0x401220ff,
2747 .flags = ADDR_TYPE_RT
2748 },
2749};
2750
2751/* l4_abe -> mcbsp1 */
2752static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2753 .master = &omap44xx_l4_abe_hwmod,
2754 .slave = &omap44xx_mcbsp1_hwmod,
2755 .clk = "ocp_abe_iclk",
2756 .addr = omap44xx_mcbsp1_addrs,
2757 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2758 .user = OCP_USER_MPU,
2759};
2760
2761static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2762 {
2763 .pa_start = 0x49022000,
2764 .pa_end = 0x490220ff,
2765 .flags = ADDR_TYPE_RT
2766 },
2767};
2768
2769/* l4_abe -> mcbsp1 (dma) */
2770static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2771 .master = &omap44xx_l4_abe_hwmod,
2772 .slave = &omap44xx_mcbsp1_hwmod,
2773 .clk = "ocp_abe_iclk",
2774 .addr = omap44xx_mcbsp1_dma_addrs,
2775 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2776 .user = OCP_USER_SDMA,
2777};
2778
2779/* mcbsp1 slave ports */
2780static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2781 &omap44xx_l4_abe__mcbsp1,
2782 &omap44xx_l4_abe__mcbsp1_dma,
2783};
2784
2785static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2786 .name = "mcbsp1",
2787 .class = &omap44xx_mcbsp_hwmod_class,
2788 .mpu_irqs = omap44xx_mcbsp1_irqs,
2789 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2790 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
2791 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2792 .main_clk = "mcbsp1_fck",
2793 .prcm = {
2794 .omap4 = {
2795 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2796 },
2797 },
2798 .slaves = omap44xx_mcbsp1_slaves,
2799 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2801};
2802
2803/* mcbsp2 */
2804static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2805static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2806 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2807};
2808
2809static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2810 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2811 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2812};
2813
2814static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2815 {
2816 .pa_start = 0x40124000,
2817 .pa_end = 0x401240ff,
2818 .flags = ADDR_TYPE_RT
2819 },
2820};
2821
2822/* l4_abe -> mcbsp2 */
2823static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2824 .master = &omap44xx_l4_abe_hwmod,
2825 .slave = &omap44xx_mcbsp2_hwmod,
2826 .clk = "ocp_abe_iclk",
2827 .addr = omap44xx_mcbsp2_addrs,
2828 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2829 .user = OCP_USER_MPU,
2830};
2831
2832static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2833 {
2834 .pa_start = 0x49024000,
2835 .pa_end = 0x490240ff,
2836 .flags = ADDR_TYPE_RT
2837 },
2838};
2839
2840/* l4_abe -> mcbsp2 (dma) */
2841static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2842 .master = &omap44xx_l4_abe_hwmod,
2843 .slave = &omap44xx_mcbsp2_hwmod,
2844 .clk = "ocp_abe_iclk",
2845 .addr = omap44xx_mcbsp2_dma_addrs,
2846 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2847 .user = OCP_USER_SDMA,
2848};
2849
2850/* mcbsp2 slave ports */
2851static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2852 &omap44xx_l4_abe__mcbsp2,
2853 &omap44xx_l4_abe__mcbsp2_dma,
2854};
2855
2856static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2857 .name = "mcbsp2",
2858 .class = &omap44xx_mcbsp_hwmod_class,
2859 .mpu_irqs = omap44xx_mcbsp2_irqs,
2860 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2861 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2862 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2863 .main_clk = "mcbsp2_fck",
2864 .prcm = {
2865 .omap4 = {
2866 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2867 },
2868 },
2869 .slaves = omap44xx_mcbsp2_slaves,
2870 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2871 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2872};
2873
2874/* mcbsp3 */
2875static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2876static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2877 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2878};
2879
2880static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2881 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2882 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2883};
2884
2885static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2886 {
2887 .pa_start = 0x40126000,
2888 .pa_end = 0x401260ff,
2889 .flags = ADDR_TYPE_RT
2890 },
2891};
2892
2893/* l4_abe -> mcbsp3 */
2894static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2895 .master = &omap44xx_l4_abe_hwmod,
2896 .slave = &omap44xx_mcbsp3_hwmod,
2897 .clk = "ocp_abe_iclk",
2898 .addr = omap44xx_mcbsp3_addrs,
2899 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2900 .user = OCP_USER_MPU,
2901};
2902
2903static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2904 {
2905 .pa_start = 0x49026000,
2906 .pa_end = 0x490260ff,
2907 .flags = ADDR_TYPE_RT
2908 },
2909};
2910
2911/* l4_abe -> mcbsp3 (dma) */
2912static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2913 .master = &omap44xx_l4_abe_hwmod,
2914 .slave = &omap44xx_mcbsp3_hwmod,
2915 .clk = "ocp_abe_iclk",
2916 .addr = omap44xx_mcbsp3_dma_addrs,
2917 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2918 .user = OCP_USER_SDMA,
2919};
2920
2921/* mcbsp3 slave ports */
2922static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2923 &omap44xx_l4_abe__mcbsp3,
2924 &omap44xx_l4_abe__mcbsp3_dma,
2925};
2926
2927static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2928 .name = "mcbsp3",
2929 .class = &omap44xx_mcbsp_hwmod_class,
2930 .mpu_irqs = omap44xx_mcbsp3_irqs,
2931 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2932 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2933 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2934 .main_clk = "mcbsp3_fck",
2935 .prcm = {
2936 .omap4 = {
2937 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2938 },
2939 },
2940 .slaves = omap44xx_mcbsp3_slaves,
2941 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2942 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2943};
2944
2945/* mcbsp4 */
2946static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2947static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2948 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2949};
2950
2951static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2952 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2953 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2954};
2955
2956static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2957 {
2958 .pa_start = 0x48096000,
2959 .pa_end = 0x480960ff,
2960 .flags = ADDR_TYPE_RT
2961 },
2962};
2963
2964/* l4_per -> mcbsp4 */
2965static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2966 .master = &omap44xx_l4_per_hwmod,
2967 .slave = &omap44xx_mcbsp4_hwmod,
2968 .clk = "l4_div_ck",
2969 .addr = omap44xx_mcbsp4_addrs,
2970 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
2971 .user = OCP_USER_MPU | OCP_USER_SDMA,
2972};
2973
2974/* mcbsp4 slave ports */
2975static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
2976 &omap44xx_l4_per__mcbsp4,
2977};
2978
2979static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2980 .name = "mcbsp4",
2981 .class = &omap44xx_mcbsp_hwmod_class,
2982 .mpu_irqs = omap44xx_mcbsp4_irqs,
2983 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
2984 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2985 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
2986 .main_clk = "mcbsp4_fck",
2987 .prcm = {
2988 .omap4 = {
2989 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2990 },
2991 },
2992 .slaves = omap44xx_mcbsp4_slaves,
2993 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
2994 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2995};
2996
407a6888
BC		 2997/*
2998 * 'mcpdm' class
2999 * multi channel pdm controller (proprietary interface with phoenix power
3000 * ic)
3001 */
3002
3003static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3004 .rev_offs = 0x0000,
3005 .sysc_offs = 0x0010,
3006 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3007 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3009 SIDLE_SMART_WKUP),
3010 .sysc_fields = &omap_hwmod_sysc_type2,
3011};
3012
3013static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3014 .name = "mcpdm",
3015 .sysc = &omap44xx_mcpdm_sysc,
3016};
3017
3018/* mcpdm */
3019static struct omap_hwmod omap44xx_mcpdm_hwmod;
3020static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3021 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3022};
3023
3024static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3025 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3026 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3027};
3028
3029static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3030 {
3031 .pa_start = 0x40132000,
3032 .pa_end = 0x4013207f,
3033 .flags = ADDR_TYPE_RT
3034 },
3035};
3036
3037/* l4_abe -> mcpdm */
3038static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3039 .master = &omap44xx_l4_abe_hwmod,
3040 .slave = &omap44xx_mcpdm_hwmod,
3041 .clk = "ocp_abe_iclk",
3042 .addr = omap44xx_mcpdm_addrs,
3043 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3044 .user = OCP_USER_MPU,
3045};
3046
3047static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3048 {
3049 .pa_start = 0x49032000,
3050 .pa_end = 0x4903207f,
3051 .flags = ADDR_TYPE_RT
3052 },
3053};
3054
3055/* l4_abe -> mcpdm (dma) */
3056static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3057 .master = &omap44xx_l4_abe_hwmod,
3058 .slave = &omap44xx_mcpdm_hwmod,
3059 .clk = "ocp_abe_iclk",
3060 .addr = omap44xx_mcpdm_dma_addrs,
3061 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3062 .user = OCP_USER_SDMA,
3063};
3064
3065/* mcpdm slave ports */
3066static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3067 &omap44xx_l4_abe__mcpdm,
3068 &omap44xx_l4_abe__mcpdm_dma,
3069};
3070
3071static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3072 .name = "mcpdm",
3073 .class = &omap44xx_mcpdm_hwmod_class,
3074 .mpu_irqs = omap44xx_mcpdm_irqs,
3075 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3076 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3077 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3078 .main_clk = "mcpdm_fck",
3079 .prcm = {
3080 .omap4 = {
3081 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3082 },
3083 },
3084 .slaves = omap44xx_mcpdm_slaves,
3085 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3086 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3087};
3088
9bcbd7f0
BC		 3089/*
3090 * 'mcspi' class
3091 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3092 * bus
3093 */
3094
3095static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3096 .rev_offs = 0x0000,
3097 .sysc_offs = 0x0010,
3098 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3099 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3100 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3101 SIDLE_SMART_WKUP),
3102 .sysc_fields = &omap_hwmod_sysc_type2,
3103};
3104
3105static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3106 .name = "mcspi",
3107 .sysc = &omap44xx_mcspi_sysc,
3108};
3109
3110/* mcspi1 */
3111static struct omap_hwmod omap44xx_mcspi1_hwmod;
3112static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3113 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3114};
3115
3116static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3117 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3118 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3119 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3120 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3121 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3122 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3123 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3124 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3125};
3126
3127static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3128 {
3129 .pa_start = 0x48098000,
3130 .pa_end = 0x480981ff,
3131 .flags = ADDR_TYPE_RT
3132 },
3133};
3134
3135/* l4_per -> mcspi1 */
3136static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3137 .master = &omap44xx_l4_per_hwmod,
3138 .slave = &omap44xx_mcspi1_hwmod,
3139 .clk = "l4_div_ck",
3140 .addr = omap44xx_mcspi1_addrs,
3141 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3142 .user = OCP_USER_MPU | OCP_USER_SDMA,
3143};
3144
3145/* mcspi1 slave ports */
3146static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3147 &omap44xx_l4_per__mcspi1,
3148};
3149
3150static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3151 .name = "mcspi1",
3152 .class = &omap44xx_mcspi_hwmod_class,
3153 .mpu_irqs = omap44xx_mcspi1_irqs,
3154 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3155 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3156 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3157 .main_clk = "mcspi1_fck",
3158 .prcm = {
3159 .omap4 = {
3160 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3161 },
3162 },
3163 .slaves = omap44xx_mcspi1_slaves,
3164 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3166};
3167
3168/* mcspi2 */
3169static struct omap_hwmod omap44xx_mcspi2_hwmod;
3170static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3171 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3172};
3173
3174static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3175 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3176 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3177 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3178 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3179};
3180
3181static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3182 {
3183 .pa_start = 0x4809a000,
3184 .pa_end = 0x4809a1ff,
3185 .flags = ADDR_TYPE_RT
3186 },
3187};
3188
3189/* l4_per -> mcspi2 */
3190static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3191 .master = &omap44xx_l4_per_hwmod,
3192 .slave = &omap44xx_mcspi2_hwmod,
3193 .clk = "l4_div_ck",
3194 .addr = omap44xx_mcspi2_addrs,
3195 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3196 .user = OCP_USER_MPU | OCP_USER_SDMA,
3197};
3198
3199/* mcspi2 slave ports */
3200static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3201 &omap44xx_l4_per__mcspi2,
3202};
3203
3204static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3205 .name = "mcspi2",
3206 .class = &omap44xx_mcspi_hwmod_class,
3207 .mpu_irqs = omap44xx_mcspi2_irqs,
3208 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3209 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3210 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3211 .main_clk = "mcspi2_fck",
3212 .prcm = {
3213 .omap4 = {
3214 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3215 },
3216 },
3217 .slaves = omap44xx_mcspi2_slaves,
3218 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3220};
3221
3222/* mcspi3 */
3223static struct omap_hwmod omap44xx_mcspi3_hwmod;
3224static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3225 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3226};
3227
3228static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3229 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3230 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3231 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3232 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3233};
3234
3235static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3236 {
3237 .pa_start = 0x480b8000,
3238 .pa_end = 0x480b81ff,
3239 .flags = ADDR_TYPE_RT
3240 },
3241};
3242
3243/* l4_per -> mcspi3 */
3244static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3245 .master = &omap44xx_l4_per_hwmod,
3246 .slave = &omap44xx_mcspi3_hwmod,
3247 .clk = "l4_div_ck",
3248 .addr = omap44xx_mcspi3_addrs,
3249 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3250 .user = OCP_USER_MPU | OCP_USER_SDMA,
3251};
3252
3253/* mcspi3 slave ports */
3254static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3255 &omap44xx_l4_per__mcspi3,
3256};
3257
3258static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3259 .name = "mcspi3",
3260 .class = &omap44xx_mcspi_hwmod_class,
3261 .mpu_irqs = omap44xx_mcspi3_irqs,
3262 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3263 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3264 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3265 .main_clk = "mcspi3_fck",
3266 .prcm = {
3267 .omap4 = {
3268 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3269 },
3270 },
3271 .slaves = omap44xx_mcspi3_slaves,
3272 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3273 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3274};
3275
3276/* mcspi4 */
3277static struct omap_hwmod omap44xx_mcspi4_hwmod;
3278static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3279 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3280};
3281
3282static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3283 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3284 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3285};
3286
3287static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3288 {
3289 .pa_start = 0x480ba000,
3290 .pa_end = 0x480ba1ff,
3291 .flags = ADDR_TYPE_RT
3292 },
3293};
3294
3295/* l4_per -> mcspi4 */
3296static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3297 .master = &omap44xx_l4_per_hwmod,
3298 .slave = &omap44xx_mcspi4_hwmod,
3299 .clk = "l4_div_ck",
3300 .addr = omap44xx_mcspi4_addrs,
3301 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303};
3304
3305/* mcspi4 slave ports */
3306static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3307 &omap44xx_l4_per__mcspi4,
3308};
3309
3310static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3311 .name = "mcspi4",
3312 .class = &omap44xx_mcspi_hwmod_class,
3313 .mpu_irqs = omap44xx_mcspi4_irqs,
3314 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3315 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3316 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3317 .main_clk = "mcspi4_fck",
3318 .prcm = {
3319 .omap4 = {
3320 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3321 },
3322 },
3323 .slaves = omap44xx_mcspi4_slaves,
3324 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3325 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3326};
3327
407a6888
BC		 3328/*
3329 * 'mmc' class
3330 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3331 */
3332
3333static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3334 .rev_offs = 0x0000,
3335 .sysc_offs = 0x0010,
3336 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3337 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3338 SYSC_HAS_SOFTRESET),
3339 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3340 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3341 MSTANDBY_SMART),
3342 .sysc_fields = &omap_hwmod_sysc_type2,
3343};
3344
3345static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3346 .name = "mmc",
3347 .sysc = &omap44xx_mmc_sysc,
3348};
3349
3350/* mmc1 */
3351static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3352 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3353};
3354
3355static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3356 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3357 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3358};
3359
3360/* mmc1 master ports */
3361static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3362 &omap44xx_mmc1__l3_main_1,
3363};
3364
3365static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3366 {
3367 .pa_start = 0x4809c000,
3368 .pa_end = 0x4809c3ff,
3369 .flags = ADDR_TYPE_RT
3370 },
3371};
3372
3373/* l4_per -> mmc1 */
3374static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3375 .master = &omap44xx_l4_per_hwmod,
3376 .slave = &omap44xx_mmc1_hwmod,
3377 .clk = "l4_div_ck",
3378 .addr = omap44xx_mmc1_addrs,
3379 .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
3380 .user = OCP_USER_MPU | OCP_USER_SDMA,
3381};
3382
3383/* mmc1 slave ports */
3384static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3385 &omap44xx_l4_per__mmc1,
3386};
3387
3388static struct omap_hwmod omap44xx_mmc1_hwmod = {
3389 .name = "mmc1",
3390 .class = &omap44xx_mmc_hwmod_class,
3391 .mpu_irqs = omap44xx_mmc1_irqs,
3392 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
3393 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3394 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3395 .main_clk = "mmc1_fck",
3396 .prcm = {
3397 .omap4 = {
3398 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3399 },
3400 },
3401 .slaves = omap44xx_mmc1_slaves,
3402 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3403 .masters = omap44xx_mmc1_masters,
3404 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3405 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3406};
3407
3408/* mmc2 */
3409static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3410 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3411};
3412
3413static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3414 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3415 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3416};
3417
3418/* mmc2 master ports */
3419static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3420 &omap44xx_mmc2__l3_main_1,
3421};
3422
3423static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3424 {
3425 .pa_start = 0x480b4000,
3426 .pa_end = 0x480b43ff,
3427 .flags = ADDR_TYPE_RT
3428 },
3429};
3430
3431/* l4_per -> mmc2 */
3432static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3433 .master = &omap44xx_l4_per_hwmod,
3434 .slave = &omap44xx_mmc2_hwmod,
3435 .clk = "l4_div_ck",
3436 .addr = omap44xx_mmc2_addrs,
3437 .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
3438 .user = OCP_USER_MPU | OCP_USER_SDMA,
3439};
3440
3441/* mmc2 slave ports */
3442static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3443 &omap44xx_l4_per__mmc2,
3444};
3445
3446static struct omap_hwmod omap44xx_mmc2_hwmod = {
3447 .name = "mmc2",
3448 .class = &omap44xx_mmc_hwmod_class,
3449 .mpu_irqs = omap44xx_mmc2_irqs,
3450 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
3451 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3452 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3453 .main_clk = "mmc2_fck",
3454 .prcm = {
3455 .omap4 = {
3456 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3457 },
3458 },
3459 .slaves = omap44xx_mmc2_slaves,
3460 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3461 .masters = omap44xx_mmc2_masters,
3462 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3463 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3464};
3465
3466/* mmc3 */
3467static struct omap_hwmod omap44xx_mmc3_hwmod;
3468static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3469 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3470};
3471
3472static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3473 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3474 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3475};
3476
3477static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3478 {
3479 .pa_start = 0x480ad000,
3480 .pa_end = 0x480ad3ff,
3481 .flags = ADDR_TYPE_RT
3482 },
3483};
3484
3485/* l4_per -> mmc3 */
3486static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3487 .master = &omap44xx_l4_per_hwmod,
3488 .slave = &omap44xx_mmc3_hwmod,
3489 .clk = "l4_div_ck",
3490 .addr = omap44xx_mmc3_addrs,
3491 .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
3492 .user = OCP_USER_MPU | OCP_USER_SDMA,
3493};
3494
3495/* mmc3 slave ports */
3496static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3497 &omap44xx_l4_per__mmc3,
3498};
3499
3500static struct omap_hwmod omap44xx_mmc3_hwmod = {
3501 .name = "mmc3",
3502 .class = &omap44xx_mmc_hwmod_class,
3503 .mpu_irqs = omap44xx_mmc3_irqs,
3504 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
3505 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3506 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3507 .main_clk = "mmc3_fck",
3508 .prcm = {
3509 .omap4 = {
3510 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3511 },
3512 },
3513 .slaves = omap44xx_mmc3_slaves,
3514 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3515 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3516};
3517
3518/* mmc4 */
3519static struct omap_hwmod omap44xx_mmc4_hwmod;
3520static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3521 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3522};
3523
3524static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3525 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3526 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3527};
3528
3529static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3530 {
3531 .pa_start = 0x480d1000,
3532 .pa_end = 0x480d13ff,
3533 .flags = ADDR_TYPE_RT
3534 },
3535};
3536
3537/* l4_per -> mmc4 */
3538static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3539 .master = &omap44xx_l4_per_hwmod,
3540 .slave = &omap44xx_mmc4_hwmod,
3541 .clk = "l4_div_ck",
3542 .addr = omap44xx_mmc4_addrs,
3543 .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
3544 .user = OCP_USER_MPU | OCP_USER_SDMA,
3545};
3546
3547/* mmc4 slave ports */
3548static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3549 &omap44xx_l4_per__mmc4,
3550};
3551
3552static struct omap_hwmod omap44xx_mmc4_hwmod = {
3553 .name = "mmc4",
3554 .class = &omap44xx_mmc_hwmod_class,
3555 .mpu_irqs = omap44xx_mmc4_irqs,
3556 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
3557 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3558 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3559 .main_clk = "mmc4_fck",
3560 .prcm = {
3561 .omap4 = {
3562 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3563 },
3564 },
3565 .slaves = omap44xx_mmc4_slaves,
3566 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3568};
3569
3570/* mmc5 */
3571static struct omap_hwmod omap44xx_mmc5_hwmod;
3572static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3573 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3574};
3575
3576static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3577 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3578 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3579};
3580
3581static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3582 {
3583 .pa_start = 0x480d5000,
3584 .pa_end = 0x480d53ff,
3585 .flags = ADDR_TYPE_RT
3586 },
3587};
3588
3589/* l4_per -> mmc5 */
3590static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3591 .master = &omap44xx_l4_per_hwmod,
3592 .slave = &omap44xx_mmc5_hwmod,
3593 .clk = "l4_div_ck",
3594 .addr = omap44xx_mmc5_addrs,
3595 .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
3596 .user = OCP_USER_MPU | OCP_USER_SDMA,
3597};
3598
3599/* mmc5 slave ports */
3600static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3601 &omap44xx_l4_per__mmc5,
3602};
3603
3604static struct omap_hwmod omap44xx_mmc5_hwmod = {
3605 .name = "mmc5",
3606 .class = &omap44xx_mmc_hwmod_class,
3607 .mpu_irqs = omap44xx_mmc5_irqs,
3608 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
3609 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3610 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3611 .main_clk = "mmc5_fck",
3612 .prcm = {
3613 .omap4 = {
3614 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3615 },
3616 },
3617 .slaves = omap44xx_mmc5_slaves,
3618 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3619 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3620};
3621
3b54baad
BC		 3622/*
3623 * 'mpu' class
3624 * mpu sub-system
3625 */
3626
3627static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 3628 .name = "mpu",
db12ba53
BC		 3629};
3630
3b54baad
BC		 3631/* mpu */
3632static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3633 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3634 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3635 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 3636};
3637
3b54baad
BC		 3638/* mpu master ports */
3639static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3640 &omap44xx_mpu__l3_main_1,
3641 &omap44xx_mpu__l4_abe,
3642 &omap44xx_mpu__dmm,
3643};
3644
3645static struct omap_hwmod omap44xx_mpu_hwmod = {
3646 .name = "mpu",
3647 .class = &omap44xx_mpu_hwmod_class,
3648 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3649 .mpu_irqs = omap44xx_mpu_irqs,
3650 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
3651 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 3652 .prcm = {
3653 .omap4 = {
3b54baad 3654 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
db12ba53
BC		 3655 },
3656 },
3b54baad
BC		 3657 .masters = omap44xx_mpu_masters,
3658 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 3659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3660};
3661
1f6a717f
BC		 3662/*
3663 * 'smartreflex' class
3664 * smartreflex module (monitor silicon performance and outputs a measure of
3665 * performance error)
3666 */
3667
3668/* The IP is not compliant to type1 / type2 scheme */
3669static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3670 .sidle_shift = 24,
3671 .enwkup_shift = 26,
3672};
3673
3674static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3675 .sysc_offs = 0x0038,
3676 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3677 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3678 SIDLE_SMART_WKUP),
3679 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3680};
3681
3682static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 3683 .name = "smartreflex",
3684 .sysc = &omap44xx_smartreflex_sysc,
3685 .rev = 2,
1f6a717f
BC		 3686};
3687
3688/* smartreflex_core */
3689static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3690static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3691 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3692};
3693
3694static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3695 {
3696 .pa_start = 0x4a0dd000,
3697 .pa_end = 0x4a0dd03f,
3698 .flags = ADDR_TYPE_RT
3699 },
3700};
3701
3702/* l4_cfg -> smartreflex_core */
3703static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3704 .master = &omap44xx_l4_cfg_hwmod,
3705 .slave = &omap44xx_smartreflex_core_hwmod,
3706 .clk = "l4_div_ck",
3707 .addr = omap44xx_smartreflex_core_addrs,
3708 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3709 .user = OCP_USER_MPU | OCP_USER_SDMA,
3710};
3711
3712/* smartreflex_core slave ports */
3713static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3714 &omap44xx_l4_cfg__smartreflex_core,
3715};
3716
3717static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3718 .name = "smartreflex_core",
3719 .class = &omap44xx_smartreflex_hwmod_class,
3720 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3721 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3722 .main_clk = "smartreflex_core_fck",
3723 .vdd_name = "core",
3724 .prcm = {
3725 .omap4 = {
3726 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3727 },
3728 },
3729 .slaves = omap44xx_smartreflex_core_slaves,
3730 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3731 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3732};
3733
3734/* smartreflex_iva */
3735static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3736static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3737 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3738};
3739
3740static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3741 {
3742 .pa_start = 0x4a0db000,
3743 .pa_end = 0x4a0db03f,
3744 .flags = ADDR_TYPE_RT
3745 },
3746};
3747
3748/* l4_cfg -> smartreflex_iva */
3749static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3750 .master = &omap44xx_l4_cfg_hwmod,
3751 .slave = &omap44xx_smartreflex_iva_hwmod,
3752 .clk = "l4_div_ck",
3753 .addr = omap44xx_smartreflex_iva_addrs,
3754 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3755 .user = OCP_USER_MPU | OCP_USER_SDMA,
3756};
3757
3758/* smartreflex_iva slave ports */
3759static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3760 &omap44xx_l4_cfg__smartreflex_iva,
3761};
3762
3763static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3764 .name = "smartreflex_iva",
3765 .class = &omap44xx_smartreflex_hwmod_class,
3766 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3767 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3768 .main_clk = "smartreflex_iva_fck",
3769 .vdd_name = "iva",
3770 .prcm = {
3771 .omap4 = {
3772 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3773 },
3774 },
3775 .slaves = omap44xx_smartreflex_iva_slaves,
3776 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3777 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3778};
3779
3780/* smartreflex_mpu */
3781static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3782static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3783 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3784};
3785
3786static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3787 {
3788 .pa_start = 0x4a0d9000,
3789 .pa_end = 0x4a0d903f,
3790 .flags = ADDR_TYPE_RT
3791 },
3792};
3793
3794/* l4_cfg -> smartreflex_mpu */
3795static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3796 .master = &omap44xx_l4_cfg_hwmod,
3797 .slave = &omap44xx_smartreflex_mpu_hwmod,
3798 .clk = "l4_div_ck",
3799 .addr = omap44xx_smartreflex_mpu_addrs,
3800 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3801 .user = OCP_USER_MPU | OCP_USER_SDMA,
3802};
3803
3804/* smartreflex_mpu slave ports */
3805static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3806 &omap44xx_l4_cfg__smartreflex_mpu,
3807};
3808
3809static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3810 .name = "smartreflex_mpu",
3811 .class = &omap44xx_smartreflex_hwmod_class,
3812 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3813 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3814 .main_clk = "smartreflex_mpu_fck",
3815 .vdd_name = "mpu",
3816 .prcm = {
3817 .omap4 = {
3818 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3819 },
3820 },
3821 .slaves = omap44xx_smartreflex_mpu_slaves,
3822 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3823 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3824};
3825
d11c217f
BC		 3826/*
3827 * 'spinlock' class
3828 * spinlock provides hardware assistance for synchronizing the processes
3829 * running on multiple processors
3830 */
3831
3832static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3833 .rev_offs = 0x0000,
3834 .sysc_offs = 0x0010,
3835 .syss_offs = 0x0014,
3836 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3837 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3838 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3839 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3840 SIDLE_SMART_WKUP),
3841 .sysc_fields = &omap_hwmod_sysc_type1,
3842};
3843
3844static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3845 .name = "spinlock",
3846 .sysc = &omap44xx_spinlock_sysc,
3847};
3848
3849/* spinlock */
3850static struct omap_hwmod omap44xx_spinlock_hwmod;
3851static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3852 {
3853 .pa_start = 0x4a0f6000,
3854 .pa_end = 0x4a0f6fff,
3855 .flags = ADDR_TYPE_RT
3856 },
3857};
3858
3859/* l4_cfg -> spinlock */
3860static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3861 .master = &omap44xx_l4_cfg_hwmod,
3862 .slave = &omap44xx_spinlock_hwmod,
3863 .clk = "l4_div_ck",
3864 .addr = omap44xx_spinlock_addrs,
3865 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
3866 .user = OCP_USER_MPU | OCP_USER_SDMA,
3867};
3868
3869/* spinlock slave ports */
3870static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3871 &omap44xx_l4_cfg__spinlock,
3872};
3873
3874static struct omap_hwmod omap44xx_spinlock_hwmod = {
3875 .name = "spinlock",
3876 .class = &omap44xx_spinlock_hwmod_class,
3877 .prcm = {
3878 .omap4 = {
3879 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3880 },
3881 },
3882 .slaves = omap44xx_spinlock_slaves,
3883 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
3884 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3885};
3886
35d1a66a
BC		 3887/*
3888 * 'timer' class
3889 * general purpose timer module with accurate 1ms tick
3890 * This class contains several variants: ['timer_1ms', 'timer']
3891 */
3892
3893static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3894 .rev_offs = 0x0000,
3895 .sysc_offs = 0x0010,
3896 .syss_offs = 0x0014,
3897 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3898 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3899 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3900 SYSS_HAS_RESET_STATUS),
3901 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3902 .sysc_fields = &omap_hwmod_sysc_type1,
3903};
3904
3905static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3906 .name = "timer",
3907 .sysc = &omap44xx_timer_1ms_sysc,
3908};
3909
3910static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3911 .rev_offs = 0x0000,
3912 .sysc_offs = 0x0010,
3913 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3914 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3915 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3916 SIDLE_SMART_WKUP),
3917 .sysc_fields = &omap_hwmod_sysc_type2,
3918};
3919
3920static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3921 .name = "timer",
3922 .sysc = &omap44xx_timer_sysc,
3923};
3924
3925/* timer1 */
3926static struct omap_hwmod omap44xx_timer1_hwmod;
3927static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3928 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3929};
3930
3931static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3932 {
3933 .pa_start = 0x4a318000,
3934 .pa_end = 0x4a31807f,
3935 .flags = ADDR_TYPE_RT
3936 },
3937};
3938
3939/* l4_wkup -> timer1 */
3940static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3941 .master = &omap44xx_l4_wkup_hwmod,
3942 .slave = &omap44xx_timer1_hwmod,
3943 .clk = "l4_wkup_clk_mux_ck",
3944 .addr = omap44xx_timer1_addrs,
3945 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
3946 .user = OCP_USER_MPU | OCP_USER_SDMA,
3947};
3948
3949/* timer1 slave ports */
3950static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3951 &omap44xx_l4_wkup__timer1,
3952};
3953
3954static struct omap_hwmod omap44xx_timer1_hwmod = {
3955 .name = "timer1",
3956 .class = &omap44xx_timer_1ms_hwmod_class,
3957 .mpu_irqs = omap44xx_timer1_irqs,
3958 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
3959 .main_clk = "timer1_fck",
3960 .prcm = {
3961 .omap4 = {
3962 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
3963 },
3964 },
3965 .slaves = omap44xx_timer1_slaves,
3966 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
3967 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3968};
3969
3970/* timer2 */
3971static struct omap_hwmod omap44xx_timer2_hwmod;
3972static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3973 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3974};
3975
3976static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
3977 {
3978 .pa_start = 0x48032000,
3979 .pa_end = 0x4803207f,
3980 .flags = ADDR_TYPE_RT
3981 },
3982};
3983
3984/* l4_per -> timer2 */
3985static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3986 .master = &omap44xx_l4_per_hwmod,
3987 .slave = &omap44xx_timer2_hwmod,
3988 .clk = "l4_div_ck",
3989 .addr = omap44xx_timer2_addrs,
3990 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
3991 .user = OCP_USER_MPU | OCP_USER_SDMA,
3992};
3993
3994/* timer2 slave ports */
3995static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
3996 &omap44xx_l4_per__timer2,
3997};
3998
3999static struct omap_hwmod omap44xx_timer2_hwmod = {
4000 .name = "timer2",
4001 .class = &omap44xx_timer_1ms_hwmod_class,
4002 .mpu_irqs = omap44xx_timer2_irqs,
4003 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
4004 .main_clk = "timer2_fck",
4005 .prcm = {
4006 .omap4 = {
4007 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4008 },
4009 },
4010 .slaves = omap44xx_timer2_slaves,
4011 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4012 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4013};
4014
4015/* timer3 */
4016static struct omap_hwmod omap44xx_timer3_hwmod;
4017static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4018 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4019};
4020
4021static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4022 {
4023 .pa_start = 0x48034000,
4024 .pa_end = 0x4803407f,
4025 .flags = ADDR_TYPE_RT
4026 },
4027};
4028
4029/* l4_per -> timer3 */
4030static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4031 .master = &omap44xx_l4_per_hwmod,
4032 .slave = &omap44xx_timer3_hwmod,
4033 .clk = "l4_div_ck",
4034 .addr = omap44xx_timer3_addrs,
4035 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
4036 .user = OCP_USER_MPU | OCP_USER_SDMA,
4037};
4038
4039/* timer3 slave ports */
4040static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4041 &omap44xx_l4_per__timer3,
4042};
4043
4044static struct omap_hwmod omap44xx_timer3_hwmod = {
4045 .name = "timer3",
4046 .class = &omap44xx_timer_hwmod_class,
4047 .mpu_irqs = omap44xx_timer3_irqs,
4048 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
4049 .main_clk = "timer3_fck",
4050 .prcm = {
4051 .omap4 = {
4052 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4053 },
4054 },
4055 .slaves = omap44xx_timer3_slaves,
4056 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4057 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4058};
4059
4060/* timer4 */
4061static struct omap_hwmod omap44xx_timer4_hwmod;
4062static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4063 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4064};
4065
4066static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4067 {
4068 .pa_start = 0x48036000,
4069 .pa_end = 0x4803607f,
4070 .flags = ADDR_TYPE_RT
4071 },
4072};
4073
4074/* l4_per -> timer4 */
4075static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4076 .master = &omap44xx_l4_per_hwmod,
4077 .slave = &omap44xx_timer4_hwmod,
4078 .clk = "l4_div_ck",
4079 .addr = omap44xx_timer4_addrs,
4080 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
4081 .user = OCP_USER_MPU | OCP_USER_SDMA,
4082};
4083
4084/* timer4 slave ports */
4085static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4086 &omap44xx_l4_per__timer4,
4087};
4088
4089static struct omap_hwmod omap44xx_timer4_hwmod = {
4090 .name = "timer4",
4091 .class = &omap44xx_timer_hwmod_class,
4092 .mpu_irqs = omap44xx_timer4_irqs,
4093 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
4094 .main_clk = "timer4_fck",
4095 .prcm = {
4096 .omap4 = {
4097 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4098 },
4099 },
4100 .slaves = omap44xx_timer4_slaves,
4101 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4103};
4104
4105/* timer5 */
4106static struct omap_hwmod omap44xx_timer5_hwmod;
4107static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4108 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4109};
4110
4111static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4112 {
4113 .pa_start = 0x40138000,
4114 .pa_end = 0x4013807f,
4115 .flags = ADDR_TYPE_RT
4116 },
4117};
4118
4119/* l4_abe -> timer5 */
4120static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4121 .master = &omap44xx_l4_abe_hwmod,
4122 .slave = &omap44xx_timer5_hwmod,
4123 .clk = "ocp_abe_iclk",
4124 .addr = omap44xx_timer5_addrs,
4125 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
4126 .user = OCP_USER_MPU,
4127};
4128
4129static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4130 {
4131 .pa_start = 0x49038000,
4132 .pa_end = 0x4903807f,
4133 .flags = ADDR_TYPE_RT
4134 },
4135};
4136
4137/* l4_abe -> timer5 (dma) */
4138static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4139 .master = &omap44xx_l4_abe_hwmod,
4140 .slave = &omap44xx_timer5_hwmod,
4141 .clk = "ocp_abe_iclk",
4142 .addr = omap44xx_timer5_dma_addrs,
4143 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4144 .user = OCP_USER_SDMA,
4145};
4146
4147/* timer5 slave ports */
4148static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4149 &omap44xx_l4_abe__timer5,
4150 &omap44xx_l4_abe__timer5_dma,
4151};
4152
4153static struct omap_hwmod omap44xx_timer5_hwmod = {
4154 .name = "timer5",
4155 .class = &omap44xx_timer_hwmod_class,
4156 .mpu_irqs = omap44xx_timer5_irqs,
4157 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
4158 .main_clk = "timer5_fck",
4159 .prcm = {
4160 .omap4 = {
4161 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4162 },
4163 },
4164 .slaves = omap44xx_timer5_slaves,
4165 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4167};
4168
4169/* timer6 */
4170static struct omap_hwmod omap44xx_timer6_hwmod;
4171static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4172 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4173};
4174
4175static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4176 {
4177 .pa_start = 0x4013a000,
4178 .pa_end = 0x4013a07f,
4179 .flags = ADDR_TYPE_RT
4180 },
4181};
4182
4183/* l4_abe -> timer6 */
4184static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4185 .master = &omap44xx_l4_abe_hwmod,
4186 .slave = &omap44xx_timer6_hwmod,
4187 .clk = "ocp_abe_iclk",
4188 .addr = omap44xx_timer6_addrs,
4189 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
4190 .user = OCP_USER_MPU,
4191};
4192
4193static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4194 {
4195 .pa_start = 0x4903a000,
4196 .pa_end = 0x4903a07f,
4197 .flags = ADDR_TYPE_RT
4198 },
4199};
4200
4201/* l4_abe -> timer6 (dma) */
4202static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4203 .master = &omap44xx_l4_abe_hwmod,
4204 .slave = &omap44xx_timer6_hwmod,
4205 .clk = "ocp_abe_iclk",
4206 .addr = omap44xx_timer6_dma_addrs,
4207 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4208 .user = OCP_USER_SDMA,
4209};
4210
4211/* timer6 slave ports */
4212static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4213 &omap44xx_l4_abe__timer6,
4214 &omap44xx_l4_abe__timer6_dma,
4215};
4216
4217static struct omap_hwmod omap44xx_timer6_hwmod = {
4218 .name = "timer6",
4219 .class = &omap44xx_timer_hwmod_class,
4220 .mpu_irqs = omap44xx_timer6_irqs,
4221 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
4222 .main_clk = "timer6_fck",
4223 .prcm = {
4224 .omap4 = {
4225 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4226 },
4227 },
4228 .slaves = omap44xx_timer6_slaves,
4229 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4231};
4232
4233/* timer7 */
4234static struct omap_hwmod omap44xx_timer7_hwmod;
4235static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4236 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4237};
4238
4239static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4240 {
4241 .pa_start = 0x4013c000,
4242 .pa_end = 0x4013c07f,
4243 .flags = ADDR_TYPE_RT
4244 },
4245};
4246
4247/* l4_abe -> timer7 */
4248static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4249 .master = &omap44xx_l4_abe_hwmod,
4250 .slave = &omap44xx_timer7_hwmod,
4251 .clk = "ocp_abe_iclk",
4252 .addr = omap44xx_timer7_addrs,
4253 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
4254 .user = OCP_USER_MPU,
4255};
4256
4257static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4258 {
4259 .pa_start = 0x4903c000,
4260 .pa_end = 0x4903c07f,
4261 .flags = ADDR_TYPE_RT
4262 },
4263};
4264
4265/* l4_abe -> timer7 (dma) */
4266static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4267 .master = &omap44xx_l4_abe_hwmod,
4268 .slave = &omap44xx_timer7_hwmod,
4269 .clk = "ocp_abe_iclk",
4270 .addr = omap44xx_timer7_dma_addrs,
4271 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4272 .user = OCP_USER_SDMA,
4273};
4274
4275/* timer7 slave ports */
4276static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4277 &omap44xx_l4_abe__timer7,
4278 &omap44xx_l4_abe__timer7_dma,
4279};
4280
4281static struct omap_hwmod omap44xx_timer7_hwmod = {
4282 .name = "timer7",
4283 .class = &omap44xx_timer_hwmod_class,
4284 .mpu_irqs = omap44xx_timer7_irqs,
4285 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
4286 .main_clk = "timer7_fck",
4287 .prcm = {
4288 .omap4 = {
4289 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4290 },
4291 },
4292 .slaves = omap44xx_timer7_slaves,
4293 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4295};
4296
4297/* timer8 */
4298static struct omap_hwmod omap44xx_timer8_hwmod;
4299static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4300 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4301};
4302
4303static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4304 {
4305 .pa_start = 0x4013e000,
4306 .pa_end = 0x4013e07f,
4307 .flags = ADDR_TYPE_RT
4308 },
4309};
4310
4311/* l4_abe -> timer8 */
4312static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4313 .master = &omap44xx_l4_abe_hwmod,
4314 .slave = &omap44xx_timer8_hwmod,
4315 .clk = "ocp_abe_iclk",
4316 .addr = omap44xx_timer8_addrs,
4317 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
4318 .user = OCP_USER_MPU,
4319};
4320
4321static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4322 {
4323 .pa_start = 0x4903e000,
4324 .pa_end = 0x4903e07f,
4325 .flags = ADDR_TYPE_RT
4326 },
4327};
4328
4329/* l4_abe -> timer8 (dma) */
4330static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4331 .master = &omap44xx_l4_abe_hwmod,
4332 .slave = &omap44xx_timer8_hwmod,
4333 .clk = "ocp_abe_iclk",
4334 .addr = omap44xx_timer8_dma_addrs,
4335 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4336 .user = OCP_USER_SDMA,
4337};
4338
4339/* timer8 slave ports */
4340static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4341 &omap44xx_l4_abe__timer8,
4342 &omap44xx_l4_abe__timer8_dma,
4343};
4344
4345static struct omap_hwmod omap44xx_timer8_hwmod = {
4346 .name = "timer8",
4347 .class = &omap44xx_timer_hwmod_class,
4348 .mpu_irqs = omap44xx_timer8_irqs,
4349 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
4350 .main_clk = "timer8_fck",
4351 .prcm = {
4352 .omap4 = {
4353 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4354 },
4355 },
4356 .slaves = omap44xx_timer8_slaves,
4357 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4358 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4359};
4360
4361/* timer9 */
4362static struct omap_hwmod omap44xx_timer9_hwmod;
4363static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4364 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4365};
4366
4367static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4368 {
4369 .pa_start = 0x4803e000,
4370 .pa_end = 0x4803e07f,
4371 .flags = ADDR_TYPE_RT
4372 },
4373};
4374
4375/* l4_per -> timer9 */
4376static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4377 .master = &omap44xx_l4_per_hwmod,
4378 .slave = &omap44xx_timer9_hwmod,
4379 .clk = "l4_div_ck",
4380 .addr = omap44xx_timer9_addrs,
4381 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
4382 .user = OCP_USER_MPU | OCP_USER_SDMA,
4383};
4384
4385/* timer9 slave ports */
4386static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4387 &omap44xx_l4_per__timer9,
4388};
4389
4390static struct omap_hwmod omap44xx_timer9_hwmod = {
4391 .name = "timer9",
4392 .class = &omap44xx_timer_hwmod_class,
4393 .mpu_irqs = omap44xx_timer9_irqs,
4394 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
4395 .main_clk = "timer9_fck",
4396 .prcm = {
4397 .omap4 = {
4398 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4399 },
4400 },
4401 .slaves = omap44xx_timer9_slaves,
4402 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4403 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4404};
4405
4406/* timer10 */
4407static struct omap_hwmod omap44xx_timer10_hwmod;
4408static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4409 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4410};
4411
4412static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4413 {
4414 .pa_start = 0x48086000,
4415 .pa_end = 0x4808607f,
4416 .flags = ADDR_TYPE_RT
4417 },
4418};
4419
4420/* l4_per -> timer10 */
4421static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4422 .master = &omap44xx_l4_per_hwmod,
4423 .slave = &omap44xx_timer10_hwmod,
4424 .clk = "l4_div_ck",
4425 .addr = omap44xx_timer10_addrs,
4426 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
4427 .user = OCP_USER_MPU | OCP_USER_SDMA,
4428};
4429
4430/* timer10 slave ports */
4431static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4432 &omap44xx_l4_per__timer10,
4433};
4434
4435static struct omap_hwmod omap44xx_timer10_hwmod = {
4436 .name = "timer10",
4437 .class = &omap44xx_timer_1ms_hwmod_class,
4438 .mpu_irqs = omap44xx_timer10_irqs,
4439 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
4440 .main_clk = "timer10_fck",
4441 .prcm = {
4442 .omap4 = {
4443 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4444 },
4445 },
4446 .slaves = omap44xx_timer10_slaves,
4447 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4448 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4449};
4450
4451/* timer11 */
4452static struct omap_hwmod omap44xx_timer11_hwmod;
4453static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4454 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4455};
4456
4457static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4458 {
4459 .pa_start = 0x48088000,
4460 .pa_end = 0x4808807f,
4461 .flags = ADDR_TYPE_RT
4462 },
4463};
4464
4465/* l4_per -> timer11 */
4466static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4467 .master = &omap44xx_l4_per_hwmod,
4468 .slave = &omap44xx_timer11_hwmod,
4469 .clk = "l4_div_ck",
4470 .addr = omap44xx_timer11_addrs,
4471 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
4472 .user = OCP_USER_MPU | OCP_USER_SDMA,
4473};
4474
4475/* timer11 slave ports */
4476static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4477 &omap44xx_l4_per__timer11,
4478};
4479
4480static struct omap_hwmod omap44xx_timer11_hwmod = {
4481 .name = "timer11",
4482 .class = &omap44xx_timer_hwmod_class,
4483 .mpu_irqs = omap44xx_timer11_irqs,
4484 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
4485 .main_clk = "timer11_fck",
4486 .prcm = {
4487 .omap4 = {
4488 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4489 },
4490 },
4491 .slaves = omap44xx_timer11_slaves,
4492 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4494};
4495
9780a9cf 4496/*
3b54baad
BC		 4497 * 'uart' class
4498 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 4499 */
4500
3b54baad
BC		 4501static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4502 .rev_offs = 0x0050,
4503 .sysc_offs = 0x0054,
4504 .syss_offs = 0x0058,
4505 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 4506 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4507 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4508 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4509 SIDLE_SMART_WKUP),
9780a9cf
BC		 4510 .sysc_fields = &omap_hwmod_sysc_type1,
4511};
4512
3b54baad 4513static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 4514 .name = "uart",
4515 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 4516};
4517
3b54baad
BC		 4518/* uart1 */
4519static struct omap_hwmod omap44xx_uart1_hwmod;
4520static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4521 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4522};
4523
3b54baad
BC		 4524static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4525 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4526 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
9780a9cf
BC		 4527};
4528
3b54baad 4529static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 4530 {
3b54baad
BC		 4531 .pa_start = 0x4806a000,
4532 .pa_end = 0x4806a0ff,
9780a9cf
BC		 4533 .flags = ADDR_TYPE_RT
4534 },
4535};
4536
3b54baad
BC		 4537/* l4_per -> uart1 */
4538static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4539 .master = &omap44xx_l4_per_hwmod,
4540 .slave = &omap44xx_uart1_hwmod,
4541 .clk = "l4_div_ck",
4542 .addr = omap44xx_uart1_addrs,
4543 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
9780a9cf
BC		 4544 .user = OCP_USER_MPU | OCP_USER_SDMA,
4545};
4546
3b54baad
BC		 4547/* uart1 slave ports */
4548static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4549 &omap44xx_l4_per__uart1,
9780a9cf
BC		 4550};
4551
3b54baad
BC		 4552static struct omap_hwmod omap44xx_uart1_hwmod = {
4553 .name = "uart1",
4554 .class = &omap44xx_uart_hwmod_class,
4555 .mpu_irqs = omap44xx_uart1_irqs,
4556 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
4557 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4558 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4559 .main_clk = "uart1_fck",
9780a9cf
BC		 4560 .prcm = {
4561 .omap4 = {
3b54baad 4562 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
9780a9cf
BC		 4563 },
4564 },
3b54baad
BC		 4565 .slaves = omap44xx_uart1_slaves,
4566 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 4567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4568};
4569
3b54baad
BC		 4570/* uart2 */
4571static struct omap_hwmod omap44xx_uart2_hwmod;
4572static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4573 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4574};
4575
3b54baad
BC		 4576static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4577 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4578 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4579};
4580
4581static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 4582 {
3b54baad
BC		 4583 .pa_start = 0x4806c000,
4584 .pa_end = 0x4806c0ff,
9780a9cf
BC		 4585 .flags = ADDR_TYPE_RT
4586 },
4587};
4588
3b54baad
BC		 4589/* l4_per -> uart2 */
4590static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 4591 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4592 .slave = &omap44xx_uart2_hwmod,
4593 .clk = "l4_div_ck",
4594 .addr = omap44xx_uart2_addrs,
4595 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
9780a9cf
BC		 4596 .user = OCP_USER_MPU | OCP_USER_SDMA,
4597};
4598
3b54baad
BC		 4599/* uart2 slave ports */
4600static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4601 &omap44xx_l4_per__uart2,
9780a9cf
BC		 4602};
4603
3b54baad
BC		 4604static struct omap_hwmod omap44xx_uart2_hwmod = {
4605 .name = "uart2",
4606 .class = &omap44xx_uart_hwmod_class,
4607 .mpu_irqs = omap44xx_uart2_irqs,
4608 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
4609 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4610 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4611 .main_clk = "uart2_fck",
9780a9cf
BC		 4612 .prcm = {
4613 .omap4 = {
3b54baad 4614 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
9780a9cf
BC		 4615 },
4616 },
3b54baad
BC		 4617 .slaves = omap44xx_uart2_slaves,
4618 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 4619 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4620};
4621
3b54baad
BC		 4622/* uart3 */
4623static struct omap_hwmod omap44xx_uart3_hwmod;
4624static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4625 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4626};
4627
3b54baad
BC		 4628static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4629 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4630 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4631};
4632
4633static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 4634 {
3b54baad
BC		 4635 .pa_start = 0x48020000,
4636 .pa_end = 0x480200ff,
9780a9cf
BC		 4637 .flags = ADDR_TYPE_RT
4638 },
4639};
4640
3b54baad
BC		 4641/* l4_per -> uart3 */
4642static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 4643 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4644 .slave = &omap44xx_uart3_hwmod,
4645 .clk = "l4_div_ck",
4646 .addr = omap44xx_uart3_addrs,
4647 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
9780a9cf
BC		 4648 .user = OCP_USER_MPU | OCP_USER_SDMA,
4649};
4650
3b54baad
BC		 4651/* uart3 slave ports */
4652static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4653 &omap44xx_l4_per__uart3,
4654};
4655
4656static struct omap_hwmod omap44xx_uart3_hwmod = {
4657 .name = "uart3",
4658 .class = &omap44xx_uart_hwmod_class,
4659 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4660 .mpu_irqs = omap44xx_uart3_irqs,
4661 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
4662 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4663 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4664 .main_clk = "uart3_fck",
9780a9cf
BC		 4665 .prcm = {
4666 .omap4 = {
3b54baad 4667 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
9780a9cf
BC		 4668 },
4669 },
3b54baad
BC		 4670 .slaves = omap44xx_uart3_slaves,
4671 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 4672 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4673};
4674
3b54baad
BC		 4675/* uart4 */
4676static struct omap_hwmod omap44xx_uart4_hwmod;
4677static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4678 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4679};
4680
3b54baad
BC		 4681static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4682 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4683 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4684};
4685
4686static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 4687 {
3b54baad
BC		 4688 .pa_start = 0x4806e000,
4689 .pa_end = 0x4806e0ff,
9780a9cf
BC		 4690 .flags = ADDR_TYPE_RT
4691 },
4692};
4693
3b54baad
BC		 4694/* l4_per -> uart4 */
4695static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 4696 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4697 .slave = &omap44xx_uart4_hwmod,
4698 .clk = "l4_div_ck",
4699 .addr = omap44xx_uart4_addrs,
4700 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
9780a9cf
BC		 4701 .user = OCP_USER_MPU | OCP_USER_SDMA,
4702};
4703
3b54baad
BC		 4704/* uart4 slave ports */
4705static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4706 &omap44xx_l4_per__uart4,
9780a9cf
BC		 4707};
4708
3b54baad
BC		 4709static struct omap_hwmod omap44xx_uart4_hwmod = {
4710 .name = "uart4",
4711 .class = &omap44xx_uart_hwmod_class,
4712 .mpu_irqs = omap44xx_uart4_irqs,
4713 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
4714 .sdma_reqs = omap44xx_uart4_sdma_reqs,
4715 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4716 .main_clk = "uart4_fck",
9780a9cf
BC		 4717 .prcm = {
4718 .omap4 = {
3b54baad 4719 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
9780a9cf
BC		 4720 },
4721 },
3b54baad
BC		 4722 .slaves = omap44xx_uart4_slaves,
4723 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 4724 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4725};
4726
3b54baad
BC		 4727/*
4728 * 'wd_timer' class
4729 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4730 * overflow condition
4731 */
4732
4733static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4734 .rev_offs = 0x0000,
4735 .sysc_offs = 0x0010,
4736 .syss_offs = 0x0014,
4737 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 4738 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4739 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4740 SIDLE_SMART_WKUP),
3b54baad 4741 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 4742};
4743
3b54baad
BC		 4744static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4745 .name = "wd_timer",
4746 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 4747 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 4748};
4749
4750/* wd_timer2 */
4751static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4752static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4753 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4754};
4755
4756static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 4757 {
3b54baad
BC		 4758 .pa_start = 0x4a314000,
4759 .pa_end = 0x4a31407f,
9780a9cf
BC		 4760 .flags = ADDR_TYPE_RT
4761 },
4762};
4763
3b54baad
BC		 4764/* l4_wkup -> wd_timer2 */
4765static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4766 .master = &omap44xx_l4_wkup_hwmod,
4767 .slave = &omap44xx_wd_timer2_hwmod,
4768 .clk = "l4_wkup_clk_mux_ck",
4769 .addr = omap44xx_wd_timer2_addrs,
4770 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
9780a9cf
BC		 4771 .user = OCP_USER_MPU | OCP_USER_SDMA,
4772};
4773
3b54baad
BC		 4774/* wd_timer2 slave ports */
4775static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4776 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 4777};
4778
3b54baad
BC		 4779static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4780 .name = "wd_timer2",
4781 .class = &omap44xx_wd_timer_hwmod_class,
4782 .mpu_irqs = omap44xx_wd_timer2_irqs,
4783 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4784 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 4785 .prcm = {
4786 .omap4 = {
3b54baad 4787 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
9780a9cf
BC		 4788 },
4789 },
3b54baad
BC		 4790 .slaves = omap44xx_wd_timer2_slaves,
4791 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 4792 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4793};
4794
3b54baad
BC		 4795/* wd_timer3 */
4796static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4797static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4798 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 4799};
4800
3b54baad 4801static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 4802 {
3b54baad
BC		 4803 .pa_start = 0x40130000,
4804 .pa_end = 0x4013007f,
9780a9cf
BC		 4805 .flags = ADDR_TYPE_RT
4806 },
4807};
4808
3b54baad
BC		 4809/* l4_abe -> wd_timer3 */
4810static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4811 .master = &omap44xx_l4_abe_hwmod,
4812 .slave = &omap44xx_wd_timer3_hwmod,
4813 .clk = "ocp_abe_iclk",
4814 .addr = omap44xx_wd_timer3_addrs,
4815 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4816 .user = OCP_USER_MPU,
9780a9cf
BC		 4817};
4818
3b54baad
BC		 4819static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4820 {
4821 .pa_start = 0x49030000,
4822 .pa_end = 0x4903007f,
4823 .flags = ADDR_TYPE_RT
4824 },
9780a9cf
BC		 4825};
4826
3b54baad
BC		 4827/* l4_abe -> wd_timer3 (dma) */
4828static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4829 .master = &omap44xx_l4_abe_hwmod,
4830 .slave = &omap44xx_wd_timer3_hwmod,
4831 .clk = "ocp_abe_iclk",
4832 .addr = omap44xx_wd_timer3_dma_addrs,
4833 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
4834 .user = OCP_USER_SDMA,
9780a9cf
BC		 4835};
4836
3b54baad
BC		 4837/* wd_timer3 slave ports */
4838static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
4839 &omap44xx_l4_abe__wd_timer3,
4840 &omap44xx_l4_abe__wd_timer3_dma,
4841};
4842
4843static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
4844 .name = "wd_timer3",
4845 .class = &omap44xx_wd_timer_hwmod_class,
4846 .mpu_irqs = omap44xx_wd_timer3_irqs,
4847 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
4848 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 4849 .prcm = {
4850 .omap4 = {
3b54baad 4851 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
9780a9cf
BC		 4852 },
4853 },
3b54baad
BC		 4854 .slaves = omap44xx_wd_timer3_slaves,
4855 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 4856 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4857};
531ce0d5 4858
55d2cb08 4859static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 4860
55d2cb08
BC		 4861 /* dmm class */
4862 &omap44xx_dmm_hwmod,
3b54baad 4863
55d2cb08
BC		 4864 /* emif_fw class */
4865 &omap44xx_emif_fw_hwmod,
3b54baad 4866
55d2cb08
BC		 4867 /* l3 class */
4868 &omap44xx_l3_instr_hwmod,
4869 &omap44xx_l3_main_1_hwmod,
4870 &omap44xx_l3_main_2_hwmod,
4871 &omap44xx_l3_main_3_hwmod,
3b54baad 4872
55d2cb08
BC		 4873 /* l4 class */
4874 &omap44xx_l4_abe_hwmod,
4875 &omap44xx_l4_cfg_hwmod,
4876 &omap44xx_l4_per_hwmod,
4877 &omap44xx_l4_wkup_hwmod,
531ce0d5 4878
55d2cb08
BC		 4879 /* mpu_bus class */
4880 &omap44xx_mpu_private_hwmod,
4881
407a6888
BC		 4882 /* aess class */
4883/* &omap44xx_aess_hwmod, */
4884
4885 /* bandgap class */
4886 &omap44xx_bandgap_hwmod,
4887
4888 /* counter class */
4889/* &omap44xx_counter_32k_hwmod, */
4890
d7cf5f33
BC		 4891 /* dma class */
4892 &omap44xx_dma_system_hwmod,
4893
8ca476da
BC		 4894 /* dmic class */
4895 &omap44xx_dmic_hwmod,
4896
8f25bdc5
BC		 4897 /* dsp class */
4898 &omap44xx_dsp_hwmod,
4899 &omap44xx_dsp_c0_hwmod,
4900
d63bd74f
BC		 4901 /* dss class */
4902 &omap44xx_dss_hwmod,
4903 &omap44xx_dss_dispc_hwmod,
4904 &omap44xx_dss_dsi1_hwmod,
4905 &omap44xx_dss_dsi2_hwmod,
4906 &omap44xx_dss_hdmi_hwmod,
4907 &omap44xx_dss_rfbi_hwmod,
4908 &omap44xx_dss_venc_hwmod,
4909
9780a9cf
BC		 4910 /* gpio class */
4911 &omap44xx_gpio1_hwmod,
4912 &omap44xx_gpio2_hwmod,
4913 &omap44xx_gpio3_hwmod,
4914 &omap44xx_gpio4_hwmod,
4915 &omap44xx_gpio5_hwmod,
4916 &omap44xx_gpio6_hwmod,
4917
407a6888
BC		 4918 /* hsi class */
4919/* &omap44xx_hsi_hwmod, */
4920
3b54baad
BC		 4921 /* i2c class */
4922 &omap44xx_i2c1_hwmod,
4923 &omap44xx_i2c2_hwmod,
4924 &omap44xx_i2c3_hwmod,
4925 &omap44xx_i2c4_hwmod,
4926
407a6888
BC		 4927 /* ipu class */
4928 &omap44xx_ipu_hwmod,
4929 &omap44xx_ipu_c0_hwmod,
4930 &omap44xx_ipu_c1_hwmod,
4931
4932 /* iss class */
4933/* &omap44xx_iss_hwmod, */
4934
8f25bdc5
BC		 4935 /* iva class */
4936 &omap44xx_iva_hwmod,
4937 &omap44xx_iva_seq0_hwmod,
4938 &omap44xx_iva_seq1_hwmod,
4939
407a6888
BC		 4940 /* kbd class */
4941/* &omap44xx_kbd_hwmod, */
4942
ec5df927
BC		 4943 /* mailbox class */
4944 &omap44xx_mailbox_hwmod,
4945
4ddff493
BC		 4946 /* mcbsp class */
4947 &omap44xx_mcbsp1_hwmod,
4948 &omap44xx_mcbsp2_hwmod,
4949 &omap44xx_mcbsp3_hwmod,
4950 &omap44xx_mcbsp4_hwmod,
4951
407a6888
BC		 4952 /* mcpdm class */
4953/* &omap44xx_mcpdm_hwmod, */
4954
9bcbd7f0
BC		 4955 /* mcspi class */
4956 &omap44xx_mcspi1_hwmod,
4957 &omap44xx_mcspi2_hwmod,
4958 &omap44xx_mcspi3_hwmod,
4959 &omap44xx_mcspi4_hwmod,
4960
407a6888
BC		 4961 /* mmc class */
4962/* &omap44xx_mmc1_hwmod, */
4963/* &omap44xx_mmc2_hwmod, */
4964/* &omap44xx_mmc3_hwmod, */
4965/* &omap44xx_mmc4_hwmod, */
4966/* &omap44xx_mmc5_hwmod, */
4967
55d2cb08
BC		 4968 /* mpu class */
4969 &omap44xx_mpu_hwmod,
db12ba53 4970
1f6a717f
BC		 4971 /* smartreflex class */
4972 &omap44xx_smartreflex_core_hwmod,
4973 &omap44xx_smartreflex_iva_hwmod,
4974 &omap44xx_smartreflex_mpu_hwmod,
4975
d11c217f
BC		 4976 /* spinlock class */
4977 &omap44xx_spinlock_hwmod,
4978
35d1a66a
BC		 4979 /* timer class */
4980 &omap44xx_timer1_hwmod,
4981 &omap44xx_timer2_hwmod,
4982 &omap44xx_timer3_hwmod,
4983 &omap44xx_timer4_hwmod,
4984 &omap44xx_timer5_hwmod,
4985 &omap44xx_timer6_hwmod,
4986 &omap44xx_timer7_hwmod,
4987 &omap44xx_timer8_hwmod,
4988 &omap44xx_timer9_hwmod,
4989 &omap44xx_timer10_hwmod,
4990 &omap44xx_timer11_hwmod,
4991
db12ba53
BC		 4992 /* uart class */
4993 &omap44xx_uart1_hwmod,
4994 &omap44xx_uart2_hwmod,
4995 &omap44xx_uart3_hwmod,
4996 &omap44xx_uart4_hwmod,
3b54baad
BC		 4997
4998 /* wd_timer class */
4999 &omap44xx_wd_timer2_hwmod,
5000 &omap44xx_wd_timer3_hwmod,
5001
55d2cb08
BC		 5002 NULL,
5003};
5004
5005int __init omap44xx_hwmod_init(void)
5006{
5007 return omap_hwmod_init(omap44xx_hwmods);
5008}
5009
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