]>
Commit | Line | Data |
---|---|---|
55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
9780a9cf | 25 | #include <plat/gpio.h> |
531ce0d5 | 26 | #include <plat/dma.h> |
55d2cb08 BC |
27 | |
28 | #include "omap_hwmod_common_data.h" | |
29 | ||
d198b514 PW |
30 | #include "cm1_44xx.h" |
31 | #include "cm2_44xx.h" | |
32 | #include "prm44xx.h" | |
55d2cb08 | 33 | #include "prm-regbits-44xx.h" |
ff2516fb | 34 | #include "wd_timer.h" |
55d2cb08 BC |
35 | |
36 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
37 | #define OMAP44XX_IRQ_GIC_START 32 | |
38 | ||
39 | /* Base offset for all OMAP4 dma requests */ | |
40 | #define OMAP44XX_DMA_REQ_START 1 | |
41 | ||
42 | /* Backward references (IPs with Bus Master capability) */ | |
531ce0d5 | 43 | static struct omap_hwmod omap44xx_dma_system_hwmod; |
55d2cb08 BC |
44 | static struct omap_hwmod omap44xx_dmm_hwmod; |
45 | static struct omap_hwmod omap44xx_emif_fw_hwmod; | |
46 | static struct omap_hwmod omap44xx_l3_instr_hwmod; | |
47 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; | |
48 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; | |
49 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; | |
50 | static struct omap_hwmod omap44xx_l4_abe_hwmod; | |
51 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; | |
52 | static struct omap_hwmod omap44xx_l4_per_hwmod; | |
53 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; | |
54 | static struct omap_hwmod omap44xx_mpu_hwmod; | |
55 | static struct omap_hwmod omap44xx_mpu_private_hwmod; | |
56 | ||
57 | /* | |
58 | * Interconnects omap_hwmod structures | |
59 | * hwmods that compose the global OMAP interconnect | |
60 | */ | |
61 | ||
62 | /* | |
63 | * 'dmm' class | |
64 | * instance(s): dmm | |
65 | */ | |
66 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
67 | .name = "dmm", | |
68 | }; | |
69 | ||
70 | /* dmm interface data */ | |
71 | /* l3_main_1 -> dmm */ | |
72 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
73 | .master = &omap44xx_l3_main_1_hwmod, | |
74 | .slave = &omap44xx_dmm_hwmod, | |
75 | .clk = "l3_div_ck", | |
659fa822 BC |
76 | .user = OCP_USER_SDMA, |
77 | }; | |
78 | ||
79 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { | |
80 | { | |
81 | .pa_start = 0x4e000000, | |
82 | .pa_end = 0x4e0007ff, | |
83 | .flags = ADDR_TYPE_RT | |
84 | }, | |
55d2cb08 BC |
85 | }; |
86 | ||
87 | /* mpu -> dmm */ | |
88 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
89 | .master = &omap44xx_mpu_hwmod, | |
90 | .slave = &omap44xx_dmm_hwmod, | |
91 | .clk = "l3_div_ck", | |
659fa822 BC |
92 | .addr = omap44xx_dmm_addrs, |
93 | .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs), | |
94 | .user = OCP_USER_MPU, | |
55d2cb08 BC |
95 | }; |
96 | ||
97 | /* dmm slave ports */ | |
98 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { | |
99 | &omap44xx_l3_main_1__dmm, | |
100 | &omap44xx_mpu__dmm, | |
101 | }; | |
102 | ||
103 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
104 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
105 | }; | |
106 | ||
107 | static struct omap_hwmod omap44xx_dmm_hwmod = { | |
108 | .name = "dmm", | |
109 | .class = &omap44xx_dmm_hwmod_class, | |
110 | .slaves = omap44xx_dmm_slaves, | |
111 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | |
112 | .mpu_irqs = omap44xx_dmm_irqs, | |
113 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), | |
114 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
115 | }; | |
116 | ||
117 | /* | |
118 | * 'emif_fw' class | |
119 | * instance(s): emif_fw | |
120 | */ | |
121 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
122 | .name = "emif_fw", | |
123 | }; | |
124 | ||
125 | /* emif_fw interface data */ | |
126 | /* dmm -> emif_fw */ | |
127 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
128 | .master = &omap44xx_dmm_hwmod, | |
129 | .slave = &omap44xx_emif_fw_hwmod, | |
130 | .clk = "l3_div_ck", | |
131 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
132 | }; | |
133 | ||
659fa822 BC |
134 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { |
135 | { | |
136 | .pa_start = 0x4a20c000, | |
137 | .pa_end = 0x4a20c0ff, | |
138 | .flags = ADDR_TYPE_RT | |
139 | }, | |
140 | }; | |
141 | ||
55d2cb08 BC |
142 | /* l4_cfg -> emif_fw */ |
143 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
144 | .master = &omap44xx_l4_cfg_hwmod, | |
145 | .slave = &omap44xx_emif_fw_hwmod, | |
146 | .clk = "l4_div_ck", | |
659fa822 BC |
147 | .addr = omap44xx_emif_fw_addrs, |
148 | .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs), | |
149 | .user = OCP_USER_MPU, | |
55d2cb08 BC |
150 | }; |
151 | ||
152 | /* emif_fw slave ports */ | |
153 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { | |
154 | &omap44xx_dmm__emif_fw, | |
155 | &omap44xx_l4_cfg__emif_fw, | |
156 | }; | |
157 | ||
158 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |
159 | .name = "emif_fw", | |
160 | .class = &omap44xx_emif_fw_hwmod_class, | |
161 | .slaves = omap44xx_emif_fw_slaves, | |
162 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), | |
163 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
164 | }; | |
165 | ||
166 | /* | |
167 | * 'l3' class | |
168 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
169 | */ | |
170 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
171 | .name = "l3", | |
172 | }; | |
173 | ||
174 | /* l3_instr interface data */ | |
175 | /* l3_main_3 -> l3_instr */ | |
176 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
177 | .master = &omap44xx_l3_main_3_hwmod, | |
178 | .slave = &omap44xx_l3_instr_hwmod, | |
179 | .clk = "l3_div_ck", | |
180 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
181 | }; | |
182 | ||
183 | /* l3_instr slave ports */ | |
184 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { | |
185 | &omap44xx_l3_main_3__l3_instr, | |
186 | }; | |
187 | ||
188 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |
189 | .name = "l3_instr", | |
190 | .class = &omap44xx_l3_hwmod_class, | |
191 | .slaves = omap44xx_l3_instr_slaves, | |
192 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), | |
193 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
194 | }; | |
195 | ||
3b54baad | 196 | /* l3_main_1 interface data */ |
55d2cb08 BC |
197 | /* l3_main_2 -> l3_main_1 */ |
198 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
199 | .master = &omap44xx_l3_main_2_hwmod, | |
200 | .slave = &omap44xx_l3_main_1_hwmod, | |
201 | .clk = "l3_div_ck", | |
202 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
203 | }; | |
204 | ||
205 | /* l4_cfg -> l3_main_1 */ | |
206 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
207 | .master = &omap44xx_l4_cfg_hwmod, | |
208 | .slave = &omap44xx_l3_main_1_hwmod, | |
209 | .clk = "l4_div_ck", | |
210 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
211 | }; | |
212 | ||
213 | /* mpu -> l3_main_1 */ | |
214 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
215 | .master = &omap44xx_mpu_hwmod, | |
216 | .slave = &omap44xx_l3_main_1_hwmod, | |
217 | .clk = "l3_div_ck", | |
218 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
219 | }; | |
220 | ||
221 | /* l3_main_1 slave ports */ | |
222 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { | |
223 | &omap44xx_l3_main_2__l3_main_1, | |
224 | &omap44xx_l4_cfg__l3_main_1, | |
225 | &omap44xx_mpu__l3_main_1, | |
226 | }; | |
227 | ||
228 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |
229 | .name = "l3_main_1", | |
230 | .class = &omap44xx_l3_hwmod_class, | |
231 | .slaves = omap44xx_l3_main_1_slaves, | |
232 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | |
233 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
234 | }; | |
235 | ||
236 | /* l3_main_2 interface data */ | |
237 | /* l3_main_1 -> l3_main_2 */ | |
238 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
239 | .master = &omap44xx_l3_main_1_hwmod, | |
240 | .slave = &omap44xx_l3_main_2_hwmod, | |
241 | .clk = "l3_div_ck", | |
242 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
243 | }; | |
244 | ||
531ce0d5 BC |
245 | /* dma_system -> l3_main_2 */ |
246 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
247 | .master = &omap44xx_dma_system_hwmod, | |
248 | .slave = &omap44xx_l3_main_2_hwmod, | |
249 | .clk = "l3_div_ck", | |
250 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
251 | }; | |
252 | ||
55d2cb08 BC |
253 | /* l4_cfg -> l3_main_2 */ |
254 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
255 | .master = &omap44xx_l4_cfg_hwmod, | |
256 | .slave = &omap44xx_l3_main_2_hwmod, | |
257 | .clk = "l4_div_ck", | |
258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
259 | }; | |
260 | ||
261 | /* l3_main_2 slave ports */ | |
262 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { | |
531ce0d5 | 263 | &omap44xx_dma_system__l3_main_2, |
55d2cb08 BC |
264 | &omap44xx_l3_main_1__l3_main_2, |
265 | &omap44xx_l4_cfg__l3_main_2, | |
266 | }; | |
267 | ||
268 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { | |
269 | .name = "l3_main_2", | |
270 | .class = &omap44xx_l3_hwmod_class, | |
271 | .slaves = omap44xx_l3_main_2_slaves, | |
272 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), | |
273 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
274 | }; | |
275 | ||
276 | /* l3_main_3 interface data */ | |
277 | /* l3_main_1 -> l3_main_3 */ | |
278 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
279 | .master = &omap44xx_l3_main_1_hwmod, | |
280 | .slave = &omap44xx_l3_main_3_hwmod, | |
281 | .clk = "l3_div_ck", | |
282 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
283 | }; | |
284 | ||
285 | /* l3_main_2 -> l3_main_3 */ | |
286 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
287 | .master = &omap44xx_l3_main_2_hwmod, | |
288 | .slave = &omap44xx_l3_main_3_hwmod, | |
289 | .clk = "l3_div_ck", | |
290 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
291 | }; | |
292 | ||
293 | /* l4_cfg -> l3_main_3 */ | |
294 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
295 | .master = &omap44xx_l4_cfg_hwmod, | |
296 | .slave = &omap44xx_l3_main_3_hwmod, | |
297 | .clk = "l4_div_ck", | |
298 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
299 | }; | |
300 | ||
301 | /* l3_main_3 slave ports */ | |
302 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { | |
303 | &omap44xx_l3_main_1__l3_main_3, | |
304 | &omap44xx_l3_main_2__l3_main_3, | |
305 | &omap44xx_l4_cfg__l3_main_3, | |
306 | }; | |
307 | ||
308 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |
309 | .name = "l3_main_3", | |
310 | .class = &omap44xx_l3_hwmod_class, | |
311 | .slaves = omap44xx_l3_main_3_slaves, | |
312 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), | |
313 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
314 | }; | |
315 | ||
316 | /* | |
317 | * 'l4' class | |
318 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
319 | */ | |
320 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
321 | .name = "l4", | |
322 | }; | |
323 | ||
324 | /* l4_abe interface data */ | |
325 | /* l3_main_1 -> l4_abe */ | |
326 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
327 | .master = &omap44xx_l3_main_1_hwmod, | |
328 | .slave = &omap44xx_l4_abe_hwmod, | |
329 | .clk = "l3_div_ck", | |
330 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
331 | }; | |
332 | ||
333 | /* mpu -> l4_abe */ | |
334 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
335 | .master = &omap44xx_mpu_hwmod, | |
336 | .slave = &omap44xx_l4_abe_hwmod, | |
337 | .clk = "ocp_abe_iclk", | |
338 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
339 | }; | |
340 | ||
341 | /* l4_abe slave ports */ | |
342 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { | |
343 | &omap44xx_l3_main_1__l4_abe, | |
344 | &omap44xx_mpu__l4_abe, | |
345 | }; | |
346 | ||
347 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { | |
348 | .name = "l4_abe", | |
349 | .class = &omap44xx_l4_hwmod_class, | |
350 | .slaves = omap44xx_l4_abe_slaves, | |
351 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), | |
352 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
353 | }; | |
354 | ||
355 | /* l4_cfg interface data */ | |
356 | /* l3_main_1 -> l4_cfg */ | |
357 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
358 | .master = &omap44xx_l3_main_1_hwmod, | |
359 | .slave = &omap44xx_l4_cfg_hwmod, | |
360 | .clk = "l3_div_ck", | |
361 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
362 | }; | |
363 | ||
364 | /* l4_cfg slave ports */ | |
365 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { | |
366 | &omap44xx_l3_main_1__l4_cfg, | |
367 | }; | |
368 | ||
369 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { | |
370 | .name = "l4_cfg", | |
371 | .class = &omap44xx_l4_hwmod_class, | |
372 | .slaves = omap44xx_l4_cfg_slaves, | |
373 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), | |
374 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
375 | }; | |
376 | ||
377 | /* l4_per interface data */ | |
378 | /* l3_main_2 -> l4_per */ | |
379 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
380 | .master = &omap44xx_l3_main_2_hwmod, | |
381 | .slave = &omap44xx_l4_per_hwmod, | |
382 | .clk = "l3_div_ck", | |
383 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
384 | }; | |
385 | ||
386 | /* l4_per slave ports */ | |
387 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { | |
388 | &omap44xx_l3_main_2__l4_per, | |
389 | }; | |
390 | ||
391 | static struct omap_hwmod omap44xx_l4_per_hwmod = { | |
392 | .name = "l4_per", | |
393 | .class = &omap44xx_l4_hwmod_class, | |
394 | .slaves = omap44xx_l4_per_slaves, | |
395 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), | |
396 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
397 | }; | |
398 | ||
399 | /* l4_wkup interface data */ | |
400 | /* l4_cfg -> l4_wkup */ | |
401 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
402 | .master = &omap44xx_l4_cfg_hwmod, | |
403 | .slave = &omap44xx_l4_wkup_hwmod, | |
404 | .clk = "l4_div_ck", | |
405 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
406 | }; | |
407 | ||
408 | /* l4_wkup slave ports */ | |
409 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { | |
410 | &omap44xx_l4_cfg__l4_wkup, | |
411 | }; | |
412 | ||
413 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |
414 | .name = "l4_wkup", | |
415 | .class = &omap44xx_l4_hwmod_class, | |
416 | .slaves = omap44xx_l4_wkup_slaves, | |
417 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), | |
418 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
419 | }; | |
420 | ||
f776471f | 421 | /* |
3b54baad BC |
422 | * 'mpu_bus' class |
423 | * instance(s): mpu_private | |
f776471f | 424 | */ |
3b54baad BC |
425 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
426 | .name = "mpu_bus", | |
427 | }; | |
f776471f | 428 | |
3b54baad BC |
429 | /* mpu_private interface data */ |
430 | /* mpu -> mpu_private */ | |
431 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
432 | .master = &omap44xx_mpu_hwmod, | |
433 | .slave = &omap44xx_mpu_private_hwmod, | |
434 | .clk = "l3_div_ck", | |
435 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
436 | }; | |
437 | ||
438 | /* mpu_private slave ports */ | |
439 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { | |
440 | &omap44xx_mpu__mpu_private, | |
441 | }; | |
442 | ||
443 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |
444 | .name = "mpu_private", | |
445 | .class = &omap44xx_mpu_bus_hwmod_class, | |
446 | .slaves = omap44xx_mpu_private_slaves, | |
447 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), | |
448 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
449 | }; | |
450 | ||
451 | /* | |
452 | * Modules omap_hwmod structures | |
453 | * | |
454 | * The following IPs are excluded for the moment because: | |
455 | * - They do not need an explicit SW control using omap_hwmod API. | |
456 | * - They still need to be validated with the driver | |
457 | * properly adapted to omap_hwmod / omap_device | |
458 | * | |
459 | * aess | |
460 | * bandgap | |
461 | * c2c | |
462 | * c2c_target_fw | |
463 | * cm_core | |
464 | * cm_core_aon | |
465 | * counter_32k | |
466 | * ctrl_module_core | |
467 | * ctrl_module_pad_core | |
468 | * ctrl_module_pad_wkup | |
469 | * ctrl_module_wkup | |
470 | * debugss | |
471 | * dma_system | |
472 | * dmic | |
473 | * dsp | |
474 | * dss | |
475 | * dss_dispc | |
476 | * dss_dsi1 | |
477 | * dss_dsi2 | |
478 | * dss_hdmi | |
479 | * dss_rfbi | |
480 | * dss_venc | |
481 | * efuse_ctrl_cust | |
482 | * efuse_ctrl_std | |
483 | * elm | |
484 | * emif1 | |
485 | * emif2 | |
486 | * fdif | |
487 | * gpmc | |
488 | * gpu | |
489 | * hdq1w | |
490 | * hsi | |
491 | * ipu | |
492 | * iss | |
493 | * iva | |
494 | * kbd | |
495 | * mailbox | |
496 | * mcasp | |
497 | * mcbsp1 | |
498 | * mcbsp2 | |
499 | * mcbsp3 | |
500 | * mcbsp4 | |
501 | * mcpdm | |
502 | * mcspi1 | |
503 | * mcspi2 | |
504 | * mcspi3 | |
505 | * mcspi4 | |
506 | * mmc1 | |
507 | * mmc2 | |
508 | * mmc3 | |
509 | * mmc4 | |
510 | * mmc5 | |
511 | * mpu_c0 | |
512 | * mpu_c1 | |
513 | * ocmc_ram | |
514 | * ocp2scp_usb_phy | |
515 | * ocp_wp_noc | |
516 | * prcm | |
517 | * prcm_mpu | |
518 | * prm | |
519 | * scrm | |
520 | * sl2if | |
521 | * slimbus1 | |
522 | * slimbus2 | |
523 | * smartreflex_core | |
524 | * smartreflex_iva | |
525 | * smartreflex_mpu | |
526 | * spinlock | |
527 | * timer1 | |
528 | * timer10 | |
529 | * timer11 | |
530 | * timer2 | |
531 | * timer3 | |
532 | * timer4 | |
533 | * timer5 | |
534 | * timer6 | |
535 | * timer7 | |
536 | * timer8 | |
537 | * timer9 | |
538 | * usb_host_fs | |
539 | * usb_host_hs | |
540 | * usb_otg_hs | |
541 | * usb_phy_cm | |
542 | * usb_tll_hs | |
543 | * usim | |
544 | */ | |
545 | ||
546 | /* | |
547 | * 'gpio' class | |
548 | * general purpose io module | |
549 | */ | |
550 | ||
551 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
552 | .rev_offs = 0x0000, | |
f776471f | 553 | .sysc_offs = 0x0010, |
3b54baad | 554 | .syss_offs = 0x0114, |
0cfe8751 BC |
555 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
556 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
557 | SYSS_HAS_RESET_STATUS), | |
f776471f BC |
558 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
559 | .sysc_fields = &omap_hwmod_sysc_type1, | |
560 | }; | |
561 | ||
3b54baad BC |
562 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
563 | .name = "gpio", | |
564 | .sysc = &omap44xx_gpio_sysc, | |
565 | .rev = 2, | |
f776471f BC |
566 | }; |
567 | ||
3b54baad BC |
568 | /* gpio dev_attr */ |
569 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
570 | .bank_width = 32, | |
571 | .dbck_flag = true, | |
f776471f BC |
572 | }; |
573 | ||
3b54baad BC |
574 | /* gpio1 */ |
575 | static struct omap_hwmod omap44xx_gpio1_hwmod; | |
576 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | |
577 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
578 | }; |
579 | ||
3b54baad | 580 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
f776471f | 581 | { |
3b54baad BC |
582 | .pa_start = 0x4a310000, |
583 | .pa_end = 0x4a3101ff, | |
f776471f BC |
584 | .flags = ADDR_TYPE_RT |
585 | }, | |
586 | }; | |
587 | ||
3b54baad BC |
588 | /* l4_wkup -> gpio1 */ |
589 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
590 | .master = &omap44xx_l4_wkup_hwmod, | |
591 | .slave = &omap44xx_gpio1_hwmod, | |
592 | .addr = omap44xx_gpio1_addrs, | |
593 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), | |
f776471f BC |
594 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
595 | }; | |
596 | ||
3b54baad BC |
597 | /* gpio1 slave ports */ |
598 | static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { | |
599 | &omap44xx_l4_wkup__gpio1, | |
f776471f BC |
600 | }; |
601 | ||
3b54baad BC |
602 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
603 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
604 | }; | |
605 | ||
606 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
607 | .name = "gpio1", | |
608 | .class = &omap44xx_gpio_hwmod_class, | |
609 | .mpu_irqs = omap44xx_gpio1_irqs, | |
610 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), | |
611 | .main_clk = "gpio1_ick", | |
f776471f BC |
612 | .prcm = { |
613 | .omap4 = { | |
3b54baad | 614 | .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
f776471f BC |
615 | }, |
616 | }, | |
3b54baad BC |
617 | .opt_clks = gpio1_opt_clks, |
618 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
619 | .dev_attr = &gpio_dev_attr, | |
620 | .slaves = omap44xx_gpio1_slaves, | |
621 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), | |
f776471f BC |
622 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
623 | }; | |
624 | ||
3b54baad BC |
625 | /* gpio2 */ |
626 | static struct omap_hwmod omap44xx_gpio2_hwmod; | |
627 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | |
628 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
629 | }; |
630 | ||
3b54baad | 631 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
f776471f | 632 | { |
3b54baad BC |
633 | .pa_start = 0x48055000, |
634 | .pa_end = 0x480551ff, | |
f776471f BC |
635 | .flags = ADDR_TYPE_RT |
636 | }, | |
637 | }; | |
638 | ||
3b54baad BC |
639 | /* l4_per -> gpio2 */ |
640 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
f776471f | 641 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
642 | .slave = &omap44xx_gpio2_hwmod, |
643 | .addr = omap44xx_gpio2_addrs, | |
644 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), | |
f776471f BC |
645 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
646 | }; | |
647 | ||
3b54baad BC |
648 | /* gpio2 slave ports */ |
649 | static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { | |
650 | &omap44xx_l4_per__gpio2, | |
f776471f BC |
651 | }; |
652 | ||
3b54baad BC |
653 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
654 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
655 | }; | |
656 | ||
657 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
658 | .name = "gpio2", | |
659 | .class = &omap44xx_gpio_hwmod_class, | |
660 | .mpu_irqs = omap44xx_gpio2_irqs, | |
661 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), | |
662 | .main_clk = "gpio2_ick", | |
f776471f BC |
663 | .prcm = { |
664 | .omap4 = { | |
3b54baad | 665 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
f776471f BC |
666 | }, |
667 | }, | |
3b54baad BC |
668 | .opt_clks = gpio2_opt_clks, |
669 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
670 | .dev_attr = &gpio_dev_attr, | |
671 | .slaves = omap44xx_gpio2_slaves, | |
672 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), | |
f776471f BC |
673 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
674 | }; | |
675 | ||
3b54baad BC |
676 | /* gpio3 */ |
677 | static struct omap_hwmod omap44xx_gpio3_hwmod; | |
678 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | |
679 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
680 | }; |
681 | ||
3b54baad | 682 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
f776471f | 683 | { |
3b54baad BC |
684 | .pa_start = 0x48057000, |
685 | .pa_end = 0x480571ff, | |
f776471f BC |
686 | .flags = ADDR_TYPE_RT |
687 | }, | |
688 | }; | |
689 | ||
3b54baad BC |
690 | /* l4_per -> gpio3 */ |
691 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
f776471f | 692 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
693 | .slave = &omap44xx_gpio3_hwmod, |
694 | .addr = omap44xx_gpio3_addrs, | |
695 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), | |
f776471f BC |
696 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
697 | }; | |
698 | ||
3b54baad BC |
699 | /* gpio3 slave ports */ |
700 | static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { | |
701 | &omap44xx_l4_per__gpio3, | |
f776471f BC |
702 | }; |
703 | ||
3b54baad BC |
704 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
705 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
706 | }; | |
707 | ||
708 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
709 | .name = "gpio3", | |
710 | .class = &omap44xx_gpio_hwmod_class, | |
711 | .mpu_irqs = omap44xx_gpio3_irqs, | |
712 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), | |
713 | .main_clk = "gpio3_ick", | |
f776471f BC |
714 | .prcm = { |
715 | .omap4 = { | |
3b54baad | 716 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
f776471f BC |
717 | }, |
718 | }, | |
3b54baad BC |
719 | .opt_clks = gpio3_opt_clks, |
720 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
721 | .dev_attr = &gpio_dev_attr, | |
722 | .slaves = omap44xx_gpio3_slaves, | |
723 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), | |
f776471f BC |
724 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
725 | }; | |
726 | ||
3b54baad BC |
727 | /* gpio4 */ |
728 | static struct omap_hwmod omap44xx_gpio4_hwmod; | |
729 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | |
730 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
731 | }; |
732 | ||
3b54baad | 733 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
f776471f | 734 | { |
3b54baad BC |
735 | .pa_start = 0x48059000, |
736 | .pa_end = 0x480591ff, | |
f776471f BC |
737 | .flags = ADDR_TYPE_RT |
738 | }, | |
739 | }; | |
740 | ||
3b54baad BC |
741 | /* l4_per -> gpio4 */ |
742 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
f776471f | 743 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
744 | .slave = &omap44xx_gpio4_hwmod, |
745 | .addr = omap44xx_gpio4_addrs, | |
746 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), | |
f776471f BC |
747 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
748 | }; | |
749 | ||
3b54baad BC |
750 | /* gpio4 slave ports */ |
751 | static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { | |
752 | &omap44xx_l4_per__gpio4, | |
f776471f BC |
753 | }; |
754 | ||
3b54baad BC |
755 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
756 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
757 | }; | |
758 | ||
759 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
760 | .name = "gpio4", | |
761 | .class = &omap44xx_gpio_hwmod_class, | |
762 | .mpu_irqs = omap44xx_gpio4_irqs, | |
763 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), | |
764 | .main_clk = "gpio4_ick", | |
f776471f BC |
765 | .prcm = { |
766 | .omap4 = { | |
3b54baad | 767 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
f776471f BC |
768 | }, |
769 | }, | |
3b54baad BC |
770 | .opt_clks = gpio4_opt_clks, |
771 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
772 | .dev_attr = &gpio_dev_attr, | |
773 | .slaves = omap44xx_gpio4_slaves, | |
774 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), | |
f776471f BC |
775 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
776 | }; | |
777 | ||
3b54baad BC |
778 | /* gpio5 */ |
779 | static struct omap_hwmod omap44xx_gpio5_hwmod; | |
780 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | |
781 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
55d2cb08 BC |
782 | }; |
783 | ||
3b54baad BC |
784 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
785 | { | |
786 | .pa_start = 0x4805b000, | |
787 | .pa_end = 0x4805b1ff, | |
788 | .flags = ADDR_TYPE_RT | |
789 | }, | |
55d2cb08 BC |
790 | }; |
791 | ||
3b54baad BC |
792 | /* l4_per -> gpio5 */ |
793 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
794 | .master = &omap44xx_l4_per_hwmod, | |
795 | .slave = &omap44xx_gpio5_hwmod, | |
796 | .addr = omap44xx_gpio5_addrs, | |
797 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), | |
798 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
55d2cb08 BC |
799 | }; |
800 | ||
3b54baad BC |
801 | /* gpio5 slave ports */ |
802 | static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { | |
803 | &omap44xx_l4_per__gpio5, | |
55d2cb08 BC |
804 | }; |
805 | ||
3b54baad BC |
806 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
807 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
55d2cb08 BC |
808 | }; |
809 | ||
3b54baad BC |
810 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
811 | .name = "gpio5", | |
812 | .class = &omap44xx_gpio_hwmod_class, | |
813 | .mpu_irqs = omap44xx_gpio5_irqs, | |
814 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), | |
815 | .main_clk = "gpio5_ick", | |
55d2cb08 BC |
816 | .prcm = { |
817 | .omap4 = { | |
3b54baad | 818 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
55d2cb08 BC |
819 | }, |
820 | }, | |
3b54baad BC |
821 | .opt_clks = gpio5_opt_clks, |
822 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
823 | .dev_attr = &gpio_dev_attr, | |
824 | .slaves = omap44xx_gpio5_slaves, | |
825 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), | |
55d2cb08 BC |
826 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
827 | }; | |
828 | ||
3b54baad BC |
829 | /* gpio6 */ |
830 | static struct omap_hwmod omap44xx_gpio6_hwmod; | |
831 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | |
832 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
92b18d1c BC |
833 | }; |
834 | ||
3b54baad | 835 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
92b18d1c | 836 | { |
3b54baad BC |
837 | .pa_start = 0x4805d000, |
838 | .pa_end = 0x4805d1ff, | |
92b18d1c BC |
839 | .flags = ADDR_TYPE_RT |
840 | }, | |
841 | }; | |
842 | ||
3b54baad BC |
843 | /* l4_per -> gpio6 */ |
844 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
845 | .master = &omap44xx_l4_per_hwmod, | |
846 | .slave = &omap44xx_gpio6_hwmod, | |
847 | .addr = omap44xx_gpio6_addrs, | |
848 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), | |
849 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
db12ba53 BC |
850 | }; |
851 | ||
3b54baad BC |
852 | /* gpio6 slave ports */ |
853 | static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { | |
854 | &omap44xx_l4_per__gpio6, | |
db12ba53 BC |
855 | }; |
856 | ||
3b54baad BC |
857 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
858 | { .role = "dbclk", .clk = "sys_32k_ck" }, | |
db12ba53 BC |
859 | }; |
860 | ||
3b54baad BC |
861 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
862 | .name = "gpio6", | |
863 | .class = &omap44xx_gpio_hwmod_class, | |
864 | .mpu_irqs = omap44xx_gpio6_irqs, | |
865 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), | |
866 | .main_clk = "gpio6_ick", | |
867 | .prcm = { | |
868 | .omap4 = { | |
869 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
870 | }, | |
db12ba53 | 871 | }, |
3b54baad BC |
872 | .opt_clks = gpio6_opt_clks, |
873 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
874 | .dev_attr = &gpio_dev_attr, | |
875 | .slaves = omap44xx_gpio6_slaves, | |
876 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), | |
877 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
db12ba53 BC |
878 | }; |
879 | ||
3b54baad BC |
880 | /* |
881 | * 'i2c' class | |
882 | * multimaster high-speed i2c controller | |
883 | */ | |
db12ba53 | 884 | |
3b54baad BC |
885 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
886 | .sysc_offs = 0x0010, | |
887 | .syss_offs = 0x0090, | |
888 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
889 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 890 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
3b54baad BC |
891 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
892 | .sysc_fields = &omap_hwmod_sysc_type1, | |
db12ba53 BC |
893 | }; |
894 | ||
3b54baad BC |
895 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
896 | .name = "i2c", | |
897 | .sysc = &omap44xx_i2c_sysc, | |
db12ba53 BC |
898 | }; |
899 | ||
3b54baad BC |
900 | /* i2c1 */ |
901 | static struct omap_hwmod omap44xx_i2c1_hwmod; | |
902 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | |
903 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
904 | }; |
905 | ||
3b54baad BC |
906 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
907 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
908 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
db12ba53 BC |
909 | }; |
910 | ||
3b54baad | 911 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
db12ba53 | 912 | { |
3b54baad BC |
913 | .pa_start = 0x48070000, |
914 | .pa_end = 0x480700ff, | |
db12ba53 BC |
915 | .flags = ADDR_TYPE_RT |
916 | }, | |
917 | }; | |
918 | ||
3b54baad BC |
919 | /* l4_per -> i2c1 */ |
920 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
921 | .master = &omap44xx_l4_per_hwmod, | |
922 | .slave = &omap44xx_i2c1_hwmod, | |
923 | .clk = "l4_div_ck", | |
924 | .addr = omap44xx_i2c1_addrs, | |
925 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), | |
92b18d1c BC |
926 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
927 | }; | |
928 | ||
3b54baad BC |
929 | /* i2c1 slave ports */ |
930 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | |
931 | &omap44xx_l4_per__i2c1, | |
92b18d1c BC |
932 | }; |
933 | ||
3b54baad BC |
934 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
935 | .name = "i2c1", | |
936 | .class = &omap44xx_i2c_hwmod_class, | |
937 | .flags = HWMOD_INIT_NO_RESET, | |
938 | .mpu_irqs = omap44xx_i2c1_irqs, | |
939 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), | |
940 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | |
941 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), | |
942 | .main_clk = "i2c1_fck", | |
92b18d1c BC |
943 | .prcm = { |
944 | .omap4 = { | |
3b54baad | 945 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
92b18d1c BC |
946 | }, |
947 | }, | |
3b54baad BC |
948 | .slaves = omap44xx_i2c1_slaves, |
949 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | |
92b18d1c BC |
950 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
951 | }; | |
952 | ||
3b54baad BC |
953 | /* i2c2 */ |
954 | static struct omap_hwmod omap44xx_i2c2_hwmod; | |
955 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | |
956 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
92b18d1c BC |
957 | }; |
958 | ||
3b54baad BC |
959 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
960 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
961 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
962 | }; | |
963 | ||
964 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
92b18d1c | 965 | { |
3b54baad BC |
966 | .pa_start = 0x48072000, |
967 | .pa_end = 0x480720ff, | |
92b18d1c BC |
968 | .flags = ADDR_TYPE_RT |
969 | }, | |
970 | }; | |
971 | ||
3b54baad BC |
972 | /* l4_per -> i2c2 */ |
973 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
db12ba53 | 974 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 975 | .slave = &omap44xx_i2c2_hwmod, |
db12ba53 | 976 | .clk = "l4_div_ck", |
3b54baad BC |
977 | .addr = omap44xx_i2c2_addrs, |
978 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), | |
db12ba53 BC |
979 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
980 | }; | |
981 | ||
3b54baad BC |
982 | /* i2c2 slave ports */ |
983 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | |
984 | &omap44xx_l4_per__i2c2, | |
db12ba53 BC |
985 | }; |
986 | ||
3b54baad BC |
987 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
988 | .name = "i2c2", | |
989 | .class = &omap44xx_i2c_hwmod_class, | |
990 | .flags = HWMOD_INIT_NO_RESET, | |
991 | .mpu_irqs = omap44xx_i2c2_irqs, | |
992 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), | |
993 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | |
994 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), | |
995 | .main_clk = "i2c2_fck", | |
db12ba53 BC |
996 | .prcm = { |
997 | .omap4 = { | |
3b54baad | 998 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
db12ba53 BC |
999 | }, |
1000 | }, | |
3b54baad BC |
1001 | .slaves = omap44xx_i2c2_slaves, |
1002 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | |
db12ba53 BC |
1003 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1004 | }; | |
1005 | ||
3b54baad BC |
1006 | /* i2c3 */ |
1007 | static struct omap_hwmod omap44xx_i2c3_hwmod; | |
1008 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | |
1009 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1010 | }; |
1011 | ||
3b54baad BC |
1012 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1013 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1014 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
92b18d1c BC |
1015 | }; |
1016 | ||
3b54baad | 1017 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
92b18d1c | 1018 | { |
3b54baad BC |
1019 | .pa_start = 0x48060000, |
1020 | .pa_end = 0x480600ff, | |
92b18d1c BC |
1021 | .flags = ADDR_TYPE_RT |
1022 | }, | |
1023 | }; | |
1024 | ||
3b54baad BC |
1025 | /* l4_per -> i2c3 */ |
1026 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
db12ba53 | 1027 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1028 | .slave = &omap44xx_i2c3_hwmod, |
db12ba53 | 1029 | .clk = "l4_div_ck", |
3b54baad BC |
1030 | .addr = omap44xx_i2c3_addrs, |
1031 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), | |
db12ba53 BC |
1032 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1033 | }; | |
1034 | ||
3b54baad BC |
1035 | /* i2c3 slave ports */ |
1036 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | |
1037 | &omap44xx_l4_per__i2c3, | |
db12ba53 BC |
1038 | }; |
1039 | ||
3b54baad BC |
1040 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1041 | .name = "i2c3", | |
1042 | .class = &omap44xx_i2c_hwmod_class, | |
1043 | .flags = HWMOD_INIT_NO_RESET, | |
1044 | .mpu_irqs = omap44xx_i2c3_irqs, | |
1045 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), | |
1046 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | |
1047 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), | |
1048 | .main_clk = "i2c3_fck", | |
db12ba53 BC |
1049 | .prcm = { |
1050 | .omap4 = { | |
3b54baad | 1051 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
db12ba53 BC |
1052 | }, |
1053 | }, | |
3b54baad BC |
1054 | .slaves = omap44xx_i2c3_slaves, |
1055 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | |
db12ba53 BC |
1056 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1057 | }; | |
1058 | ||
3b54baad BC |
1059 | /* i2c4 */ |
1060 | static struct omap_hwmod omap44xx_i2c4_hwmod; | |
1061 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | |
1062 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1063 | }; |
1064 | ||
3b54baad BC |
1065 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1066 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1067 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
db12ba53 BC |
1068 | }; |
1069 | ||
3b54baad | 1070 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
db12ba53 | 1071 | { |
3b54baad BC |
1072 | .pa_start = 0x48350000, |
1073 | .pa_end = 0x483500ff, | |
db12ba53 BC |
1074 | .flags = ADDR_TYPE_RT |
1075 | }, | |
1076 | }; | |
1077 | ||
3b54baad BC |
1078 | /* l4_per -> i2c4 */ |
1079 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
1080 | .master = &omap44xx_l4_per_hwmod, | |
1081 | .slave = &omap44xx_i2c4_hwmod, | |
1082 | .clk = "l4_div_ck", | |
1083 | .addr = omap44xx_i2c4_addrs, | |
1084 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), | |
1085 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
92b18d1c BC |
1086 | }; |
1087 | ||
3b54baad BC |
1088 | /* i2c4 slave ports */ |
1089 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | |
1090 | &omap44xx_l4_per__i2c4, | |
92b18d1c BC |
1091 | }; |
1092 | ||
3b54baad BC |
1093 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1094 | .name = "i2c4", | |
1095 | .class = &omap44xx_i2c_hwmod_class, | |
1096 | .flags = HWMOD_INIT_NO_RESET, | |
1097 | .mpu_irqs = omap44xx_i2c4_irqs, | |
1098 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), | |
1099 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | |
1100 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), | |
1101 | .main_clk = "i2c4_fck", | |
92b18d1c BC |
1102 | .prcm = { |
1103 | .omap4 = { | |
3b54baad | 1104 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
92b18d1c BC |
1105 | }, |
1106 | }, | |
3b54baad BC |
1107 | .slaves = omap44xx_i2c4_slaves, |
1108 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | |
92b18d1c BC |
1109 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1110 | }; | |
1111 | ||
3b54baad BC |
1112 | /* |
1113 | * 'mpu' class | |
1114 | * mpu sub-system | |
1115 | */ | |
1116 | ||
1117 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
1118 | .name = "mpu", | |
db12ba53 BC |
1119 | }; |
1120 | ||
3b54baad BC |
1121 | /* mpu */ |
1122 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
1123 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
1124 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
1125 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1126 | }; |
1127 | ||
3b54baad BC |
1128 | /* mpu master ports */ |
1129 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { | |
1130 | &omap44xx_mpu__l3_main_1, | |
1131 | &omap44xx_mpu__l4_abe, | |
1132 | &omap44xx_mpu__dmm, | |
1133 | }; | |
1134 | ||
1135 | static struct omap_hwmod omap44xx_mpu_hwmod = { | |
1136 | .name = "mpu", | |
1137 | .class = &omap44xx_mpu_hwmod_class, | |
1138 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
1139 | .mpu_irqs = omap44xx_mpu_irqs, | |
1140 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), | |
1141 | .main_clk = "dpll_mpu_m2_ck", | |
db12ba53 BC |
1142 | .prcm = { |
1143 | .omap4 = { | |
3b54baad | 1144 | .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, |
db12ba53 BC |
1145 | }, |
1146 | }, | |
3b54baad BC |
1147 | .masters = omap44xx_mpu_masters, |
1148 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), | |
db12ba53 BC |
1149 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1150 | }; | |
1151 | ||
9780a9cf | 1152 | /* |
3b54baad BC |
1153 | * 'uart' class |
1154 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
1155 | */ |
1156 | ||
3b54baad BC |
1157 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
1158 | .rev_offs = 0x0050, | |
1159 | .sysc_offs = 0x0054, | |
1160 | .syss_offs = 0x0058, | |
1161 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
1162 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
1163 | SYSS_HAS_RESET_STATUS), | |
9780a9cf BC |
1164 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1165 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1166 | }; | |
1167 | ||
3b54baad BC |
1168 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
1169 | .name = "uart", | |
1170 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
1171 | }; |
1172 | ||
3b54baad BC |
1173 | /* uart1 */ |
1174 | static struct omap_hwmod omap44xx_uart1_hwmod; | |
1175 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | |
1176 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1177 | }; |
1178 | ||
3b54baad BC |
1179 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
1180 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
1181 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
9780a9cf BC |
1182 | }; |
1183 | ||
3b54baad | 1184 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
9780a9cf | 1185 | { |
3b54baad BC |
1186 | .pa_start = 0x4806a000, |
1187 | .pa_end = 0x4806a0ff, | |
9780a9cf BC |
1188 | .flags = ADDR_TYPE_RT |
1189 | }, | |
1190 | }; | |
1191 | ||
3b54baad BC |
1192 | /* l4_per -> uart1 */ |
1193 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
1194 | .master = &omap44xx_l4_per_hwmod, | |
1195 | .slave = &omap44xx_uart1_hwmod, | |
1196 | .clk = "l4_div_ck", | |
1197 | .addr = omap44xx_uart1_addrs, | |
1198 | .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), | |
9780a9cf BC |
1199 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1200 | }; | |
1201 | ||
3b54baad BC |
1202 | /* uart1 slave ports */ |
1203 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { | |
1204 | &omap44xx_l4_per__uart1, | |
9780a9cf BC |
1205 | }; |
1206 | ||
3b54baad BC |
1207 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
1208 | .name = "uart1", | |
1209 | .class = &omap44xx_uart_hwmod_class, | |
1210 | .mpu_irqs = omap44xx_uart1_irqs, | |
1211 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), | |
1212 | .sdma_reqs = omap44xx_uart1_sdma_reqs, | |
1213 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), | |
1214 | .main_clk = "uart1_fck", | |
9780a9cf BC |
1215 | .prcm = { |
1216 | .omap4 = { | |
3b54baad | 1217 | .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
9780a9cf BC |
1218 | }, |
1219 | }, | |
3b54baad BC |
1220 | .slaves = omap44xx_uart1_slaves, |
1221 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), | |
9780a9cf BC |
1222 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1223 | }; | |
1224 | ||
3b54baad BC |
1225 | /* uart2 */ |
1226 | static struct omap_hwmod omap44xx_uart2_hwmod; | |
1227 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | |
1228 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1229 | }; |
1230 | ||
3b54baad BC |
1231 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
1232 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
1233 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
1234 | }; | |
1235 | ||
1236 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | |
9780a9cf | 1237 | { |
3b54baad BC |
1238 | .pa_start = 0x4806c000, |
1239 | .pa_end = 0x4806c0ff, | |
9780a9cf BC |
1240 | .flags = ADDR_TYPE_RT |
1241 | }, | |
1242 | }; | |
1243 | ||
3b54baad BC |
1244 | /* l4_per -> uart2 */ |
1245 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
9780a9cf | 1246 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
1247 | .slave = &omap44xx_uart2_hwmod, |
1248 | .clk = "l4_div_ck", | |
1249 | .addr = omap44xx_uart2_addrs, | |
1250 | .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), | |
9780a9cf BC |
1251 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1252 | }; | |
1253 | ||
3b54baad BC |
1254 | /* uart2 slave ports */ |
1255 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { | |
1256 | &omap44xx_l4_per__uart2, | |
9780a9cf BC |
1257 | }; |
1258 | ||
3b54baad BC |
1259 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
1260 | .name = "uart2", | |
1261 | .class = &omap44xx_uart_hwmod_class, | |
1262 | .mpu_irqs = omap44xx_uart2_irqs, | |
1263 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), | |
1264 | .sdma_reqs = omap44xx_uart2_sdma_reqs, | |
1265 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), | |
1266 | .main_clk = "uart2_fck", | |
9780a9cf BC |
1267 | .prcm = { |
1268 | .omap4 = { | |
3b54baad | 1269 | .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
9780a9cf BC |
1270 | }, |
1271 | }, | |
3b54baad BC |
1272 | .slaves = omap44xx_uart2_slaves, |
1273 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), | |
9780a9cf BC |
1274 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1275 | }; | |
1276 | ||
3b54baad BC |
1277 | /* uart3 */ |
1278 | static struct omap_hwmod omap44xx_uart3_hwmod; | |
1279 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | |
1280 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1281 | }; |
1282 | ||
3b54baad BC |
1283 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
1284 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
1285 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
1286 | }; | |
1287 | ||
1288 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | |
9780a9cf | 1289 | { |
3b54baad BC |
1290 | .pa_start = 0x48020000, |
1291 | .pa_end = 0x480200ff, | |
9780a9cf BC |
1292 | .flags = ADDR_TYPE_RT |
1293 | }, | |
1294 | }; | |
1295 | ||
3b54baad BC |
1296 | /* l4_per -> uart3 */ |
1297 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
9780a9cf | 1298 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
1299 | .slave = &omap44xx_uart3_hwmod, |
1300 | .clk = "l4_div_ck", | |
1301 | .addr = omap44xx_uart3_addrs, | |
1302 | .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), | |
9780a9cf BC |
1303 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1304 | }; | |
1305 | ||
3b54baad BC |
1306 | /* uart3 slave ports */ |
1307 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { | |
1308 | &omap44xx_l4_per__uart3, | |
1309 | }; | |
1310 | ||
1311 | static struct omap_hwmod omap44xx_uart3_hwmod = { | |
1312 | .name = "uart3", | |
1313 | .class = &omap44xx_uart_hwmod_class, | |
1314 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
1315 | .mpu_irqs = omap44xx_uart3_irqs, | |
1316 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), | |
1317 | .sdma_reqs = omap44xx_uart3_sdma_reqs, | |
1318 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), | |
1319 | .main_clk = "uart3_fck", | |
9780a9cf BC |
1320 | .prcm = { |
1321 | .omap4 = { | |
3b54baad | 1322 | .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
9780a9cf BC |
1323 | }, |
1324 | }, | |
3b54baad BC |
1325 | .slaves = omap44xx_uart3_slaves, |
1326 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), | |
9780a9cf BC |
1327 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1328 | }; | |
1329 | ||
3b54baad BC |
1330 | /* uart4 */ |
1331 | static struct omap_hwmod omap44xx_uart4_hwmod; | |
1332 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | |
1333 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1334 | }; |
1335 | ||
3b54baad BC |
1336 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
1337 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
1338 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
1339 | }; | |
1340 | ||
1341 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | |
9780a9cf | 1342 | { |
3b54baad BC |
1343 | .pa_start = 0x4806e000, |
1344 | .pa_end = 0x4806e0ff, | |
9780a9cf BC |
1345 | .flags = ADDR_TYPE_RT |
1346 | }, | |
1347 | }; | |
1348 | ||
3b54baad BC |
1349 | /* l4_per -> uart4 */ |
1350 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
9780a9cf | 1351 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
1352 | .slave = &omap44xx_uart4_hwmod, |
1353 | .clk = "l4_div_ck", | |
1354 | .addr = omap44xx_uart4_addrs, | |
1355 | .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), | |
9780a9cf BC |
1356 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1357 | }; | |
1358 | ||
3b54baad BC |
1359 | /* uart4 slave ports */ |
1360 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { | |
1361 | &omap44xx_l4_per__uart4, | |
9780a9cf BC |
1362 | }; |
1363 | ||
3b54baad BC |
1364 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
1365 | .name = "uart4", | |
1366 | .class = &omap44xx_uart_hwmod_class, | |
1367 | .mpu_irqs = omap44xx_uart4_irqs, | |
1368 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), | |
1369 | .sdma_reqs = omap44xx_uart4_sdma_reqs, | |
1370 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), | |
1371 | .main_clk = "uart4_fck", | |
9780a9cf BC |
1372 | .prcm = { |
1373 | .omap4 = { | |
3b54baad | 1374 | .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
9780a9cf BC |
1375 | }, |
1376 | }, | |
3b54baad BC |
1377 | .slaves = omap44xx_uart4_slaves, |
1378 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), | |
9780a9cf BC |
1379 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1380 | }; | |
1381 | ||
3b54baad BC |
1382 | /* |
1383 | * 'wd_timer' class | |
1384 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
1385 | * overflow condition | |
1386 | */ | |
1387 | ||
1388 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
1389 | .rev_offs = 0x0000, | |
1390 | .sysc_offs = 0x0010, | |
1391 | .syss_offs = 0x0014, | |
1392 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1393 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
3b54baad BC |
1394 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1395 | .sysc_fields = &omap_hwmod_sysc_type1, | |
9780a9cf BC |
1396 | }; |
1397 | ||
3b54baad BC |
1398 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
1399 | .name = "wd_timer", | |
1400 | .sysc = &omap44xx_wd_timer_sysc, | |
1401 | .pre_shutdown = &omap2_wd_timer_disable | |
1402 | }; | |
1403 | ||
1404 | /* wd_timer2 */ | |
1405 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | |
1406 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | |
1407 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
1408 | }; | |
1409 | ||
1410 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | |
9780a9cf | 1411 | { |
3b54baad BC |
1412 | .pa_start = 0x4a314000, |
1413 | .pa_end = 0x4a31407f, | |
9780a9cf BC |
1414 | .flags = ADDR_TYPE_RT |
1415 | }, | |
1416 | }; | |
1417 | ||
3b54baad BC |
1418 | /* l4_wkup -> wd_timer2 */ |
1419 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
1420 | .master = &omap44xx_l4_wkup_hwmod, | |
1421 | .slave = &omap44xx_wd_timer2_hwmod, | |
1422 | .clk = "l4_wkup_clk_mux_ck", | |
1423 | .addr = omap44xx_wd_timer2_addrs, | |
1424 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), | |
9780a9cf BC |
1425 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1426 | }; | |
1427 | ||
3b54baad BC |
1428 | /* wd_timer2 slave ports */ |
1429 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | |
1430 | &omap44xx_l4_wkup__wd_timer2, | |
9780a9cf BC |
1431 | }; |
1432 | ||
3b54baad BC |
1433 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
1434 | .name = "wd_timer2", | |
1435 | .class = &omap44xx_wd_timer_hwmod_class, | |
1436 | .mpu_irqs = omap44xx_wd_timer2_irqs, | |
1437 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), | |
1438 | .main_clk = "wd_timer2_fck", | |
9780a9cf BC |
1439 | .prcm = { |
1440 | .omap4 = { | |
3b54baad | 1441 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
9780a9cf BC |
1442 | }, |
1443 | }, | |
3b54baad BC |
1444 | .slaves = omap44xx_wd_timer2_slaves, |
1445 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | |
9780a9cf BC |
1446 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1447 | }; | |
1448 | ||
3b54baad BC |
1449 | /* wd_timer3 */ |
1450 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | |
1451 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | |
1452 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1453 | }; |
1454 | ||
3b54baad | 1455 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
9780a9cf | 1456 | { |
3b54baad BC |
1457 | .pa_start = 0x40130000, |
1458 | .pa_end = 0x4013007f, | |
9780a9cf BC |
1459 | .flags = ADDR_TYPE_RT |
1460 | }, | |
1461 | }; | |
1462 | ||
3b54baad BC |
1463 | /* l4_abe -> wd_timer3 */ |
1464 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
1465 | .master = &omap44xx_l4_abe_hwmod, | |
1466 | .slave = &omap44xx_wd_timer3_hwmod, | |
1467 | .clk = "ocp_abe_iclk", | |
1468 | .addr = omap44xx_wd_timer3_addrs, | |
1469 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), | |
1470 | .user = OCP_USER_MPU, | |
9780a9cf BC |
1471 | }; |
1472 | ||
3b54baad BC |
1473 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
1474 | { | |
1475 | .pa_start = 0x49030000, | |
1476 | .pa_end = 0x4903007f, | |
1477 | .flags = ADDR_TYPE_RT | |
1478 | }, | |
9780a9cf BC |
1479 | }; |
1480 | ||
3b54baad BC |
1481 | /* l4_abe -> wd_timer3 (dma) */ |
1482 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
1483 | .master = &omap44xx_l4_abe_hwmod, | |
1484 | .slave = &omap44xx_wd_timer3_hwmod, | |
1485 | .clk = "ocp_abe_iclk", | |
1486 | .addr = omap44xx_wd_timer3_dma_addrs, | |
1487 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), | |
1488 | .user = OCP_USER_SDMA, | |
9780a9cf BC |
1489 | }; |
1490 | ||
3b54baad BC |
1491 | /* wd_timer3 slave ports */ |
1492 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | |
1493 | &omap44xx_l4_abe__wd_timer3, | |
1494 | &omap44xx_l4_abe__wd_timer3_dma, | |
1495 | }; | |
1496 | ||
1497 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |
1498 | .name = "wd_timer3", | |
1499 | .class = &omap44xx_wd_timer_hwmod_class, | |
1500 | .mpu_irqs = omap44xx_wd_timer3_irqs, | |
1501 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), | |
1502 | .main_clk = "wd_timer3_fck", | |
9780a9cf BC |
1503 | .prcm = { |
1504 | .omap4 = { | |
3b54baad | 1505 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
9780a9cf BC |
1506 | }, |
1507 | }, | |
3b54baad BC |
1508 | .slaves = omap44xx_wd_timer3_slaves, |
1509 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | |
9780a9cf BC |
1510 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1511 | }; | |
531ce0d5 | 1512 | |
3b54baad | 1513 | |
531ce0d5 BC |
1514 | /* |
1515 | * 'dma' class | |
1516 | * dma controller for data exchange between memory to memory (i.e. internal or | |
1517 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
1518 | */ | |
1519 | ||
1520 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
1521 | .rev_offs = 0x0000, | |
1522 | .sysc_offs = 0x002c, | |
1523 | .syss_offs = 0x0028, | |
1524 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1525 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1526 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1527 | SYSS_HAS_RESET_STATUS), | |
1528 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1529 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1530 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1531 | }; | |
1532 | ||
1533 | /* dma attributes */ | |
1534 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1535 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1536 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1537 | .lch_count = 32, | |
1538 | }; | |
1539 | ||
1540 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
1541 | .name = "dma", | |
1542 | .sysc = &omap44xx_dma_sysc, | |
1543 | }; | |
1544 | ||
1545 | /* dma_system */ | |
1546 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
1547 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
1548 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
1549 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
1550 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
1551 | }; | |
1552 | ||
1553 | /* dma_system master ports */ | |
1554 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { | |
1555 | &omap44xx_dma_system__l3_main_2, | |
1556 | }; | |
1557 | ||
1558 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
1559 | { | |
1560 | .pa_start = 0x4a056000, | |
1561 | .pa_end = 0x4a0560ff, | |
1562 | .flags = ADDR_TYPE_RT | |
1563 | }, | |
1564 | }; | |
1565 | ||
1566 | /* l4_cfg -> dma_system */ | |
1567 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
1568 | .master = &omap44xx_l4_cfg_hwmod, | |
1569 | .slave = &omap44xx_dma_system_hwmod, | |
1570 | .clk = "l4_div_ck", | |
1571 | .addr = omap44xx_dma_system_addrs, | |
1572 | .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs), | |
1573 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1574 | }; | |
1575 | ||
1576 | /* dma_system slave ports */ | |
1577 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { | |
1578 | &omap44xx_l4_cfg__dma_system, | |
1579 | }; | |
1580 | ||
1581 | static struct omap_hwmod omap44xx_dma_system_hwmod = { | |
1582 | .name = "dma_system", | |
1583 | .class = &omap44xx_dma_hwmod_class, | |
1584 | .mpu_irqs = omap44xx_dma_system_irqs, | |
1585 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs), | |
1586 | .main_clk = "l3_div_ck", | |
1587 | .prcm = { | |
1588 | .omap4 = { | |
1589 | .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL, | |
1590 | }, | |
1591 | }, | |
1592 | .slaves = omap44xx_dma_system_slaves, | |
1593 | .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), | |
1594 | .masters = omap44xx_dma_system_masters, | |
1595 | .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), | |
1596 | .dev_attr = &dma_dev_attr, | |
1597 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1598 | }; | |
1599 | ||
55d2cb08 BC |
1600 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
1601 | /* dmm class */ | |
1602 | &omap44xx_dmm_hwmod, | |
3b54baad | 1603 | |
55d2cb08 BC |
1604 | /* emif_fw class */ |
1605 | &omap44xx_emif_fw_hwmod, | |
3b54baad | 1606 | |
55d2cb08 BC |
1607 | /* l3 class */ |
1608 | &omap44xx_l3_instr_hwmod, | |
1609 | &omap44xx_l3_main_1_hwmod, | |
1610 | &omap44xx_l3_main_2_hwmod, | |
1611 | &omap44xx_l3_main_3_hwmod, | |
3b54baad | 1612 | |
55d2cb08 BC |
1613 | /* l4 class */ |
1614 | &omap44xx_l4_abe_hwmod, | |
1615 | &omap44xx_l4_cfg_hwmod, | |
1616 | &omap44xx_l4_per_hwmod, | |
1617 | &omap44xx_l4_wkup_hwmod, | |
531ce0d5 BC |
1618 | |
1619 | /* dma class */ | |
1620 | &omap44xx_dma_system_hwmod, | |
1621 | ||
55d2cb08 BC |
1622 | /* mpu_bus class */ |
1623 | &omap44xx_mpu_private_hwmod, | |
1624 | ||
9780a9cf BC |
1625 | /* gpio class */ |
1626 | &omap44xx_gpio1_hwmod, | |
1627 | &omap44xx_gpio2_hwmod, | |
1628 | &omap44xx_gpio3_hwmod, | |
1629 | &omap44xx_gpio4_hwmod, | |
1630 | &omap44xx_gpio5_hwmod, | |
1631 | &omap44xx_gpio6_hwmod, | |
1632 | ||
3b54baad BC |
1633 | /* i2c class */ |
1634 | &omap44xx_i2c1_hwmod, | |
1635 | &omap44xx_i2c2_hwmod, | |
1636 | &omap44xx_i2c3_hwmod, | |
1637 | &omap44xx_i2c4_hwmod, | |
1638 | ||
55d2cb08 BC |
1639 | /* mpu class */ |
1640 | &omap44xx_mpu_hwmod, | |
db12ba53 BC |
1641 | |
1642 | /* uart class */ | |
1643 | &omap44xx_uart1_hwmod, | |
1644 | &omap44xx_uart2_hwmod, | |
1645 | &omap44xx_uart3_hwmod, | |
1646 | &omap44xx_uart4_hwmod, | |
3b54baad BC |
1647 | |
1648 | /* wd_timer class */ | |
1649 | &omap44xx_wd_timer2_hwmod, | |
1650 | &omap44xx_wd_timer3_hwmod, | |
1651 | ||
55d2cb08 BC |
1652 | NULL, |
1653 | }; | |
1654 | ||
1655 | int __init omap44xx_hwmod_init(void) | |
1656 | { | |
1657 | return omap_hwmod_init(omap44xx_hwmods); | |
1658 | } | |
1659 |