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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
3b9b1015 S |
15 | * Note that this file is currently not in sync with autogeneration scripts. |
16 | * The above note to be removed, once it is synced up. | |
55d2cb08 BC |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License version 2 as | |
20 | * published by the Free Software Foundation. | |
21 | */ | |
22 | ||
23 | #include <linux/io.h> | |
4b25408f | 24 | #include <linux/platform_data/gpio-omap.h> |
55143438 | 25 | #include <linux/platform_data/hsmmc-omap.h> |
b86aeafc | 26 | #include <linux/power/smartreflex.h> |
3a8761c0 | 27 | #include <linux/i2c-omap.h> |
55d2cb08 | 28 | |
45c3eb7d | 29 | #include <linux/omap-dma.h> |
2a296c8f | 30 | |
2203747c AB |
31 | #include <linux/platform_data/spi-omap2-mcspi.h> |
32 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
c345c8b0 | 33 | #include <plat/dmtimer.h> |
55d2cb08 | 34 | |
2a296c8f | 35 | #include "omap_hwmod.h" |
55d2cb08 | 36 | #include "omap_hwmod_common_data.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
3a8761c0 | 41 | #include "i2c.h" |
ff2516fb | 42 | #include "wd_timer.h" |
55d2cb08 BC |
43 | |
44 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
45 | #define OMAP44XX_IRQ_GIC_START 32 | |
46 | ||
47 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 48 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
49 | |
50 | /* | |
844a3b63 | 51 | * IP blocks |
55d2cb08 BC |
52 | */ |
53 | ||
54 | /* | |
55 | * 'dmm' class | |
56 | * instance(s): dmm | |
57 | */ | |
58 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 59 | .name = "dmm", |
55d2cb08 BC |
60 | }; |
61 | ||
7e69ed97 | 62 | /* dmm */ |
55d2cb08 BC |
63 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
64 | .name = "dmm", | |
65 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 66 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
67 | .prcm = { |
68 | .omap4 = { | |
69 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 70 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
71 | }, |
72 | }, | |
55d2cb08 BC |
73 | }; |
74 | ||
55d2cb08 BC |
75 | /* |
76 | * 'l3' class | |
77 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
78 | */ | |
79 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 80 | .name = "l3", |
55d2cb08 BC |
81 | }; |
82 | ||
7e69ed97 | 83 | /* l3_instr */ |
55d2cb08 BC |
84 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
85 | .name = "l3_instr", | |
86 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 87 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
88 | .prcm = { |
89 | .omap4 = { | |
90 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 91 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 92 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
93 | }, |
94 | }, | |
55d2cb08 BC |
95 | }; |
96 | ||
7e69ed97 | 97 | /* l3_main_1 */ |
55d2cb08 BC |
98 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
99 | .name = "l3_main_1", | |
100 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 101 | .clkdm_name = "l3_1_clkdm", |
d0f0631d BC |
102 | .prcm = { |
103 | .omap4 = { | |
104 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 105 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
106 | }, |
107 | }, | |
55d2cb08 BC |
108 | }; |
109 | ||
7e69ed97 | 110 | /* l3_main_2 */ |
55d2cb08 BC |
111 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
112 | .name = "l3_main_2", | |
113 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 114 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
115 | .prcm = { |
116 | .omap4 = { | |
117 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 118 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
119 | }, |
120 | }, | |
55d2cb08 BC |
121 | }; |
122 | ||
7e69ed97 | 123 | /* l3_main_3 */ |
55d2cb08 BC |
124 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
125 | .name = "l3_main_3", | |
126 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 127 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
128 | .prcm = { |
129 | .omap4 = { | |
130 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 131 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 132 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
133 | }, |
134 | }, | |
55d2cb08 BC |
135 | }; |
136 | ||
137 | /* | |
138 | * 'l4' class | |
139 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
140 | */ | |
141 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 142 | .name = "l4", |
55d2cb08 BC |
143 | }; |
144 | ||
7e69ed97 | 145 | /* l4_abe */ |
55d2cb08 BC |
146 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
147 | .name = "l4_abe", | |
148 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 149 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
150 | .prcm = { |
151 | .omap4 = { | |
152 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
ce80979a TK |
153 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
154 | .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, | |
46b3af27 | 155 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
d0f0631d BC |
156 | }, |
157 | }, | |
55d2cb08 BC |
158 | }; |
159 | ||
7e69ed97 | 160 | /* l4_cfg */ |
55d2cb08 BC |
161 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
162 | .name = "l4_cfg", | |
163 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 164 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
165 | .prcm = { |
166 | .omap4 = { | |
167 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 168 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
169 | }, |
170 | }, | |
55d2cb08 BC |
171 | }; |
172 | ||
7e69ed97 | 173 | /* l4_per */ |
55d2cb08 BC |
174 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
175 | .name = "l4_per", | |
176 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 177 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
178 | .prcm = { |
179 | .omap4 = { | |
180 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 181 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
182 | }, |
183 | }, | |
55d2cb08 BC |
184 | }; |
185 | ||
7e69ed97 | 186 | /* l4_wkup */ |
55d2cb08 BC |
187 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
188 | .name = "l4_wkup", | |
189 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 190 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
191 | .prcm = { |
192 | .omap4 = { | |
193 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 194 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
195 | }, |
196 | }, | |
55d2cb08 BC |
197 | }; |
198 | ||
f776471f | 199 | /* |
3b54baad BC |
200 | * 'mpu_bus' class |
201 | * instance(s): mpu_private | |
f776471f | 202 | */ |
3b54baad | 203 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 204 | .name = "mpu_bus", |
3b54baad | 205 | }; |
f776471f | 206 | |
7e69ed97 | 207 | /* mpu_private */ |
3b54baad BC |
208 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
209 | .name = "mpu_private", | |
210 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 211 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
212 | .prcm = { |
213 | .omap4 = { | |
214 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
215 | }, | |
216 | }, | |
3b54baad BC |
217 | }; |
218 | ||
9a817bc8 BC |
219 | /* |
220 | * 'ocp_wp_noc' class | |
221 | * instance(s): ocp_wp_noc | |
222 | */ | |
223 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
224 | .name = "ocp_wp_noc", | |
225 | }; | |
226 | ||
227 | /* ocp_wp_noc */ | |
228 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
229 | .name = "ocp_wp_noc", | |
230 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
231 | .clkdm_name = "l3_instr_clkdm", | |
232 | .prcm = { | |
233 | .omap4 = { | |
234 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
235 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
236 | .modulemode = MODULEMODE_HWCTRL, | |
237 | }, | |
238 | }, | |
239 | }; | |
240 | ||
3b54baad BC |
241 | /* |
242 | * Modules omap_hwmod structures | |
243 | * | |
244 | * The following IPs are excluded for the moment because: | |
245 | * - They do not need an explicit SW control using omap_hwmod API. | |
246 | * - They still need to be validated with the driver | |
247 | * properly adapted to omap_hwmod / omap_device | |
248 | * | |
96566043 | 249 | * usim |
3b54baad BC |
250 | */ |
251 | ||
407a6888 BC |
252 | /* |
253 | * 'aess' class | |
254 | * audio engine sub system | |
255 | */ | |
256 | ||
257 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
258 | .rev_offs = 0x0000, | |
259 | .sysc_offs = 0x0010, | |
260 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
261 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
262 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
263 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
264 | .sysc_fields = &omap_hwmod_sysc_type2, |
265 | }; | |
266 | ||
267 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
268 | .name = "aess", | |
269 | .sysc = &omap44xx_aess_sysc, | |
c02060d8 | 270 | .enable_preprogram = omap_hwmod_aess_preprogram, |
407a6888 BC |
271 | }; |
272 | ||
273 | /* aess */ | |
407a6888 BC |
274 | static struct omap_hwmod omap44xx_aess_hwmod = { |
275 | .name = "aess", | |
276 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 277 | .clkdm_name = "abe_clkdm", |
9f0c5996 | 278 | .main_clk = "aess_fclk", |
00fe610b | 279 | .prcm = { |
407a6888 | 280 | .omap4 = { |
d0f0631d | 281 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 282 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
ce80979a | 283 | .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, |
03fdefe5 | 284 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
285 | }, |
286 | }, | |
407a6888 BC |
287 | }; |
288 | ||
42b9e387 PW |
289 | /* |
290 | * 'c2c' class | |
291 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
292 | * soc | |
293 | */ | |
294 | ||
295 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
296 | .name = "c2c", | |
297 | }; | |
298 | ||
299 | /* c2c */ | |
42b9e387 PW |
300 | static struct omap_hwmod omap44xx_c2c_hwmod = { |
301 | .name = "c2c", | |
302 | .class = &omap44xx_c2c_hwmod_class, | |
303 | .clkdm_name = "d2d_clkdm", | |
42b9e387 PW |
304 | .prcm = { |
305 | .omap4 = { | |
306 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
307 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
308 | }, | |
309 | }, | |
310 | }; | |
311 | ||
407a6888 BC |
312 | /* |
313 | * 'counter' class | |
314 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
315 | */ | |
316 | ||
317 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
318 | .rev_offs = 0x0000, | |
319 | .sysc_offs = 0x0004, | |
320 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 321 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
322 | .sysc_fields = &omap_hwmod_sysc_type1, |
323 | }; | |
324 | ||
325 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
326 | .name = "counter", | |
327 | .sysc = &omap44xx_counter_sysc, | |
328 | }; | |
329 | ||
330 | /* counter_32k */ | |
407a6888 BC |
331 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
332 | .name = "counter_32k", | |
333 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 334 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
335 | .flags = HWMOD_SWSUP_SIDLE, |
336 | .main_clk = "sys_32k_ck", | |
00fe610b | 337 | .prcm = { |
407a6888 | 338 | .omap4 = { |
d0f0631d | 339 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 340 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
341 | }, |
342 | }, | |
407a6888 BC |
343 | }; |
344 | ||
a0b5d813 PW |
345 | /* |
346 | * 'ctrl_module' class | |
347 | * attila core control module + core pad control module + wkup pad control | |
348 | * module + attila wkup control module | |
349 | */ | |
350 | ||
351 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
352 | .rev_offs = 0x0000, | |
353 | .sysc_offs = 0x0010, | |
354 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
355 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
356 | SIDLE_SMART_WKUP), | |
357 | .sysc_fields = &omap_hwmod_sysc_type2, | |
358 | }; | |
359 | ||
360 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
361 | .name = "ctrl_module", | |
362 | .sysc = &omap44xx_ctrl_module_sysc, | |
363 | }; | |
364 | ||
365 | /* ctrl_module_core */ | |
a0b5d813 PW |
366 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { |
367 | .name = "ctrl_module_core", | |
368 | .class = &omap44xx_ctrl_module_hwmod_class, | |
369 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
370 | .prcm = { |
371 | .omap4 = { | |
372 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
373 | }, | |
374 | }, | |
a0b5d813 PW |
375 | }; |
376 | ||
377 | /* ctrl_module_pad_core */ | |
378 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
379 | .name = "ctrl_module_pad_core", | |
380 | .class = &omap44xx_ctrl_module_hwmod_class, | |
381 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
382 | .prcm = { |
383 | .omap4 = { | |
384 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
385 | }, | |
386 | }, | |
a0b5d813 PW |
387 | }; |
388 | ||
389 | /* ctrl_module_wkup */ | |
390 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
391 | .name = "ctrl_module_wkup", | |
392 | .class = &omap44xx_ctrl_module_hwmod_class, | |
393 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
394 | .prcm = { |
395 | .omap4 = { | |
396 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
397 | }, | |
398 | }, | |
a0b5d813 PW |
399 | }; |
400 | ||
401 | /* ctrl_module_pad_wkup */ | |
402 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
403 | .name = "ctrl_module_pad_wkup", | |
404 | .class = &omap44xx_ctrl_module_hwmod_class, | |
405 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
406 | .prcm = { |
407 | .omap4 = { | |
408 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
409 | }, | |
410 | }, | |
a0b5d813 PW |
411 | }; |
412 | ||
96566043 BC |
413 | /* |
414 | * 'debugss' class | |
415 | * debug and emulation sub system | |
416 | */ | |
417 | ||
418 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
419 | .name = "debugss", | |
420 | }; | |
421 | ||
422 | /* debugss */ | |
423 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
424 | .name = "debugss", | |
425 | .class = &omap44xx_debugss_hwmod_class, | |
426 | .clkdm_name = "emu_sys_clkdm", | |
427 | .main_clk = "trace_clk_div_ck", | |
428 | .prcm = { | |
429 | .omap4 = { | |
430 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
431 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
432 | }, | |
433 | }, | |
434 | }; | |
435 | ||
d7cf5f33 BC |
436 | /* |
437 | * 'dma' class | |
438 | * dma controller for data exchange between memory to memory (i.e. internal or | |
439 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
440 | */ | |
441 | ||
442 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
443 | .rev_offs = 0x0000, | |
444 | .sysc_offs = 0x002c, | |
445 | .syss_offs = 0x0028, | |
446 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
447 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
448 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
449 | SYSS_HAS_RESET_STATUS), | |
450 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
451 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
452 | .sysc_fields = &omap_hwmod_sysc_type1, | |
453 | }; | |
454 | ||
455 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
456 | .name = "dma", | |
457 | .sysc = &omap44xx_dma_sysc, | |
458 | }; | |
459 | ||
460 | /* dma dev_attr */ | |
461 | static struct omap_dma_dev_attr dma_dev_attr = { | |
462 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
463 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
464 | .lch_count = 32, | |
465 | }; | |
466 | ||
467 | /* dma_system */ | |
468 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
469 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
470 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
471 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
472 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 473 | { .irq = -1 } |
d7cf5f33 BC |
474 | }; |
475 | ||
d7cf5f33 BC |
476 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
477 | .name = "dma_system", | |
478 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 479 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 480 | .mpu_irqs = omap44xx_dma_system_irqs, |
0fb22a8f | 481 | .xlate_irq = omap4_xlate_irq, |
d7cf5f33 BC |
482 | .main_clk = "l3_div_ck", |
483 | .prcm = { | |
484 | .omap4 = { | |
d0f0631d | 485 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 486 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
487 | }, |
488 | }, | |
489 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
490 | }; |
491 | ||
8ca476da BC |
492 | /* |
493 | * 'dmic' class | |
494 | * digital microphone controller | |
495 | */ | |
496 | ||
497 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
498 | .rev_offs = 0x0000, | |
499 | .sysc_offs = 0x0010, | |
500 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
501 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
502 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
503 | SIDLE_SMART_WKUP), | |
504 | .sysc_fields = &omap_hwmod_sysc_type2, | |
505 | }; | |
506 | ||
507 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
508 | .name = "dmic", | |
509 | .sysc = &omap44xx_dmic_sysc, | |
510 | }; | |
511 | ||
512 | /* dmic */ | |
8ca476da BC |
513 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
514 | .name = "dmic", | |
515 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 516 | .clkdm_name = "abe_clkdm", |
ee877acd | 517 | .main_clk = "func_dmic_abe_gfclk", |
00fe610b | 518 | .prcm = { |
8ca476da | 519 | .omap4 = { |
d0f0631d | 520 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 521 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 522 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
523 | }, |
524 | }, | |
8ca476da BC |
525 | }; |
526 | ||
8f25bdc5 BC |
527 | /* |
528 | * 'dsp' class | |
529 | * dsp sub-system | |
530 | */ | |
531 | ||
532 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 533 | .name = "dsp", |
8f25bdc5 BC |
534 | }; |
535 | ||
536 | /* dsp */ | |
8f25bdc5 | 537 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { |
8f25bdc5 BC |
538 | { .name = "dsp", .rst_shift = 0 }, |
539 | }; | |
540 | ||
8f25bdc5 BC |
541 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
542 | .name = "dsp", | |
543 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 544 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 BC |
545 | .rst_lines = omap44xx_dsp_resets, |
546 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
298ea44f | 547 | .main_clk = "dpll_iva_m4x2_ck", |
8f25bdc5 BC |
548 | .prcm = { |
549 | .omap4 = { | |
d0f0631d | 550 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 551 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 552 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 553 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
554 | }, |
555 | }, | |
8f25bdc5 BC |
556 | }; |
557 | ||
d63bd74f BC |
558 | /* |
559 | * 'dss' class | |
560 | * display sub-system | |
561 | */ | |
562 | ||
563 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
564 | .rev_offs = 0x0000, | |
565 | .syss_offs = 0x0014, | |
566 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
567 | }; | |
568 | ||
569 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
570 | .name = "dss", | |
571 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 572 | .reset = omap_dss_reset, |
d63bd74f BC |
573 | }; |
574 | ||
575 | /* dss */ | |
d63bd74f BC |
576 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
577 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
578 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 579 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
580 | }; |
581 | ||
582 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
583 | .name = "dss_core", | |
37ad0855 | 584 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 585 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 586 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 587 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
588 | .prcm = { |
589 | .omap4 = { | |
d0f0631d | 590 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 591 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
7ede8561 | 592 | .modulemode = MODULEMODE_SWCTRL, |
d63bd74f BC |
593 | }, |
594 | }, | |
595 | .opt_clks = dss_opt_clks, | |
596 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
597 | }; |
598 | ||
599 | /* | |
600 | * 'dispc' class | |
601 | * display controller | |
602 | */ | |
603 | ||
604 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
605 | .rev_offs = 0x0000, | |
606 | .sysc_offs = 0x0010, | |
607 | .syss_offs = 0x0014, | |
608 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
609 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
610 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
611 | SYSS_HAS_RESET_STATUS), | |
612 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
613 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
614 | .sysc_fields = &omap_hwmod_sysc_type1, | |
615 | }; | |
616 | ||
617 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
618 | .name = "dispc", | |
619 | .sysc = &omap44xx_dispc_sysc, | |
620 | }; | |
621 | ||
622 | /* dss_dispc */ | |
b38911f3 TV |
623 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
624 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
625 | { .irq = -1 } | |
626 | }; | |
627 | ||
628 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
629 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
630 | { .dma_req = -1 } | |
631 | }; | |
632 | ||
b923d40d AT |
633 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
634 | .manager_count = 3, | |
635 | .has_framedonetv_irq = 1 | |
636 | }; | |
637 | ||
d63bd74f BC |
638 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
639 | .name = "dss_dispc", | |
640 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 641 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 642 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
0fb22a8f | 643 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 644 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 645 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
646 | .prcm = { |
647 | .omap4 = { | |
d0f0631d | 648 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 649 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
650 | }, |
651 | }, | |
543b2847 TV |
652 | .dev_attr = &omap44xx_dss_dispc_dev_attr, |
653 | .parent_hwmod = &omap44xx_dss_hwmod, | |
d63bd74f BC |
654 | }; |
655 | ||
656 | /* | |
657 | * 'dsi' class | |
658 | * display serial interface controller | |
659 | */ | |
660 | ||
661 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
662 | .rev_offs = 0x0000, | |
663 | .sysc_offs = 0x0010, | |
664 | .syss_offs = 0x0014, | |
665 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
666 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
667 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
668 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
669 | .sysc_fields = &omap_hwmod_sysc_type1, | |
670 | }; | |
671 | ||
672 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
673 | .name = "dsi", | |
674 | .sysc = &omap44xx_dsi_sysc, | |
675 | }; | |
676 | ||
677 | /* dss_dsi1 */ | |
b38911f3 TV |
678 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
679 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
680 | { .irq = -1 } | |
681 | }; | |
682 | ||
683 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
684 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
685 | { .dma_req = -1 } | |
686 | }; | |
687 | ||
3a23aafc TV |
688 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
689 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
690 | }; | |
691 | ||
d63bd74f BC |
692 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
693 | .name = "dss_dsi1", | |
694 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 695 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 696 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
0fb22a8f | 697 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 698 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 699 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
700 | .prcm = { |
701 | .omap4 = { | |
d0f0631d | 702 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 703 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
704 | }, |
705 | }, | |
3a23aafc TV |
706 | .opt_clks = dss_dsi1_opt_clks, |
707 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
543b2847 | 708 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
709 | }; |
710 | ||
711 | /* dss_dsi2 */ | |
b38911f3 TV |
712 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
713 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
714 | { .irq = -1 } | |
715 | }; | |
716 | ||
717 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
718 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
719 | { .dma_req = -1 } | |
720 | }; | |
721 | ||
3a23aafc TV |
722 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
723 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
724 | }; | |
725 | ||
d63bd74f BC |
726 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
727 | .name = "dss_dsi2", | |
728 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 729 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 730 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
0fb22a8f | 731 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 732 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 733 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
734 | .prcm = { |
735 | .omap4 = { | |
d0f0631d | 736 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 737 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
738 | }, |
739 | }, | |
3a23aafc TV |
740 | .opt_clks = dss_dsi2_opt_clks, |
741 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
543b2847 | 742 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
743 | }; |
744 | ||
745 | /* | |
746 | * 'hdmi' class | |
747 | * hdmi controller | |
748 | */ | |
749 | ||
750 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
751 | .rev_offs = 0x0000, | |
752 | .sysc_offs = 0x0010, | |
753 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
754 | SYSC_HAS_SOFTRESET), | |
755 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
756 | SIDLE_SMART_WKUP), | |
757 | .sysc_fields = &omap_hwmod_sysc_type2, | |
758 | }; | |
759 | ||
760 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
761 | .name = "hdmi", | |
762 | .sysc = &omap44xx_hdmi_sysc, | |
763 | }; | |
764 | ||
765 | /* dss_hdmi */ | |
b38911f3 TV |
766 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
767 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
768 | { .irq = -1 } | |
769 | }; | |
770 | ||
771 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
772 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
773 | { .dma_req = -1 } | |
774 | }; | |
775 | ||
3a23aafc TV |
776 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
777 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
24d8d498 | 778 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
3a23aafc TV |
779 | }; |
780 | ||
d63bd74f BC |
781 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
782 | .name = "dss_hdmi", | |
783 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 784 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
785 | /* |
786 | * HDMI audio requires to use no-idle mode. Hence, | |
787 | * set idle mode by software. | |
788 | */ | |
24d8d498 | 789 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED, |
b38911f3 | 790 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
0fb22a8f | 791 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 792 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 793 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
794 | .prcm = { |
795 | .omap4 = { | |
d0f0631d | 796 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 797 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
798 | }, |
799 | }, | |
3a23aafc TV |
800 | .opt_clks = dss_hdmi_opt_clks, |
801 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
543b2847 | 802 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
803 | }; |
804 | ||
805 | /* | |
806 | * 'rfbi' class | |
807 | * remote frame buffer interface | |
808 | */ | |
809 | ||
810 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
811 | .rev_offs = 0x0000, | |
812 | .sysc_offs = 0x0010, | |
813 | .syss_offs = 0x0014, | |
814 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
815 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
816 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
817 | .sysc_fields = &omap_hwmod_sysc_type1, | |
818 | }; | |
819 | ||
820 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
821 | .name = "rfbi", | |
822 | .sysc = &omap44xx_rfbi_sysc, | |
823 | }; | |
824 | ||
825 | /* dss_rfbi */ | |
b38911f3 TV |
826 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
827 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
828 | { .dma_req = -1 } | |
829 | }; | |
830 | ||
3a23aafc | 831 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
2cc84f46 | 832 | { .role = "ick", .clk = "l3_div_ck" }, |
3a23aafc TV |
833 | }; |
834 | ||
d63bd74f BC |
835 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
836 | .name = "dss_rfbi", | |
837 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 838 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 839 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 840 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
841 | .prcm = { |
842 | .omap4 = { | |
d0f0631d | 843 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 844 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
845 | }, |
846 | }, | |
3a23aafc TV |
847 | .opt_clks = dss_rfbi_opt_clks, |
848 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
543b2847 | 849 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
850 | }; |
851 | ||
852 | /* | |
853 | * 'venc' class | |
854 | * video encoder | |
855 | */ | |
856 | ||
857 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
858 | .name = "venc", | |
859 | }; | |
860 | ||
861 | /* dss_venc */ | |
24d8d498 TK |
862 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
863 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
864 | }; | |
865 | ||
d63bd74f BC |
866 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
867 | .name = "dss_venc", | |
868 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 869 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 870 | .main_clk = "dss_tv_clk", |
24d8d498 | 871 | .flags = HWMOD_OPT_CLKS_NEEDED, |
d63bd74f BC |
872 | .prcm = { |
873 | .omap4 = { | |
d0f0631d | 874 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 875 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
876 | }, |
877 | }, | |
543b2847 | 878 | .parent_hwmod = &omap44xx_dss_hwmod, |
24d8d498 TK |
879 | .opt_clks = dss_venc_opt_clks, |
880 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
d63bd74f BC |
881 | }; |
882 | ||
42b9e387 PW |
883 | /* |
884 | * 'elm' class | |
885 | * bch error location module | |
886 | */ | |
887 | ||
888 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
889 | .rev_offs = 0x0000, | |
890 | .sysc_offs = 0x0010, | |
891 | .syss_offs = 0x0014, | |
892 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
893 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
894 | SYSS_HAS_RESET_STATUS), | |
895 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
896 | .sysc_fields = &omap_hwmod_sysc_type1, | |
897 | }; | |
898 | ||
899 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
900 | .name = "elm", | |
901 | .sysc = &omap44xx_elm_sysc, | |
902 | }; | |
903 | ||
904 | /* elm */ | |
42b9e387 PW |
905 | static struct omap_hwmod omap44xx_elm_hwmod = { |
906 | .name = "elm", | |
907 | .class = &omap44xx_elm_hwmod_class, | |
908 | .clkdm_name = "l4_per_clkdm", | |
42b9e387 PW |
909 | .prcm = { |
910 | .omap4 = { | |
911 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
912 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
913 | }, | |
914 | }, | |
915 | }; | |
916 | ||
bf30f950 PW |
917 | /* |
918 | * 'emif' class | |
919 | * external memory interface no1 | |
920 | */ | |
921 | ||
922 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
923 | .rev_offs = 0x0000, | |
924 | }; | |
925 | ||
926 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
927 | .name = "emif", | |
928 | .sysc = &omap44xx_emif_sysc, | |
929 | }; | |
930 | ||
931 | /* emif1 */ | |
bf30f950 PW |
932 | static struct omap_hwmod omap44xx_emif1_hwmod = { |
933 | .name = "emif1", | |
934 | .class = &omap44xx_emif_hwmod_class, | |
935 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 936 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
937 | .main_clk = "ddrphy_ck", |
938 | .prcm = { | |
939 | .omap4 = { | |
940 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
941 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
942 | .modulemode = MODULEMODE_HWCTRL, | |
943 | }, | |
944 | }, | |
945 | }; | |
946 | ||
947 | /* emif2 */ | |
bf30f950 PW |
948 | static struct omap_hwmod omap44xx_emif2_hwmod = { |
949 | .name = "emif2", | |
950 | .class = &omap44xx_emif_hwmod_class, | |
951 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 952 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
953 | .main_clk = "ddrphy_ck", |
954 | .prcm = { | |
955 | .omap4 = { | |
956 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
957 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
958 | .modulemode = MODULEMODE_HWCTRL, | |
959 | }, | |
960 | }, | |
961 | }; | |
962 | ||
b050f688 ML |
963 | /* |
964 | * 'fdif' class | |
965 | * face detection hw accelerator module | |
966 | */ | |
967 | ||
968 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
969 | .rev_offs = 0x0000, | |
970 | .sysc_offs = 0x0010, | |
971 | /* | |
972 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
973 | * accessing sysconfig again. | |
974 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
975 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
976 | * | |
977 | * TODO: Indicate errata when available. | |
978 | */ | |
979 | .srst_udelay = 2, | |
980 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
981 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
982 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
983 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
984 | .sysc_fields = &omap_hwmod_sysc_type2, | |
985 | }; | |
986 | ||
987 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
988 | .name = "fdif", | |
989 | .sysc = &omap44xx_fdif_sysc, | |
990 | }; | |
991 | ||
992 | /* fdif */ | |
b050f688 ML |
993 | static struct omap_hwmod omap44xx_fdif_hwmod = { |
994 | .name = "fdif", | |
995 | .class = &omap44xx_fdif_hwmod_class, | |
996 | .clkdm_name = "iss_clkdm", | |
b050f688 ML |
997 | .main_clk = "fdif_fck", |
998 | .prcm = { | |
999 | .omap4 = { | |
1000 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1001 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1002 | .modulemode = MODULEMODE_SWCTRL, | |
1003 | }, | |
1004 | }, | |
1005 | }; | |
1006 | ||
3b54baad BC |
1007 | /* |
1008 | * 'gpio' class | |
1009 | * general purpose io module | |
1010 | */ | |
1011 | ||
1012 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1013 | .rev_offs = 0x0000, | |
f776471f | 1014 | .sysc_offs = 0x0010, |
3b54baad | 1015 | .syss_offs = 0x0114, |
0cfe8751 BC |
1016 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1017 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1018 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1019 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1020 | SIDLE_SMART_WKUP), | |
f776471f BC |
1021 | .sysc_fields = &omap_hwmod_sysc_type1, |
1022 | }; | |
1023 | ||
3b54baad | 1024 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1025 | .name = "gpio", |
1026 | .sysc = &omap44xx_gpio_sysc, | |
1027 | .rev = 2, | |
f776471f BC |
1028 | }; |
1029 | ||
3b54baad BC |
1030 | /* gpio dev_attr */ |
1031 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1032 | .bank_width = 32, |
1033 | .dbck_flag = true, | |
f776471f BC |
1034 | }; |
1035 | ||
3b54baad | 1036 | /* gpio1 */ |
3b54baad | 1037 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1038 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1039 | }; |
1040 | ||
1041 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1042 | .name = "gpio1", | |
1043 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1044 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 1045 | .main_clk = "l4_wkup_clk_mux_ck", |
f776471f BC |
1046 | .prcm = { |
1047 | .omap4 = { | |
d0f0631d | 1048 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1049 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1050 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1051 | }, |
1052 | }, | |
3b54baad BC |
1053 | .opt_clks = gpio1_opt_clks, |
1054 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1055 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1056 | }; |
1057 | ||
3b54baad | 1058 | /* gpio2 */ |
3b54baad | 1059 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1060 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1061 | }; |
1062 | ||
1063 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1064 | .name = "gpio2", | |
1065 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1066 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1067 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1068 | .main_clk = "l4_div_ck", |
f776471f BC |
1069 | .prcm = { |
1070 | .omap4 = { | |
d0f0631d | 1071 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1072 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1073 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1074 | }, |
1075 | }, | |
3b54baad BC |
1076 | .opt_clks = gpio2_opt_clks, |
1077 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1078 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1079 | }; |
1080 | ||
3b54baad | 1081 | /* gpio3 */ |
3b54baad | 1082 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1083 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1084 | }; |
1085 | ||
1086 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1087 | .name = "gpio3", | |
1088 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1089 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1090 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1091 | .main_clk = "l4_div_ck", |
f776471f BC |
1092 | .prcm = { |
1093 | .omap4 = { | |
d0f0631d | 1094 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1095 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1096 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1097 | }, |
1098 | }, | |
3b54baad BC |
1099 | .opt_clks = gpio3_opt_clks, |
1100 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1101 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1102 | }; |
1103 | ||
3b54baad | 1104 | /* gpio4 */ |
3b54baad | 1105 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1106 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1107 | }; |
1108 | ||
1109 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1110 | .name = "gpio4", | |
1111 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1112 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1113 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1114 | .main_clk = "l4_div_ck", |
f776471f BC |
1115 | .prcm = { |
1116 | .omap4 = { | |
d0f0631d | 1117 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1118 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1119 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1120 | }, |
1121 | }, | |
3b54baad BC |
1122 | .opt_clks = gpio4_opt_clks, |
1123 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1124 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1125 | }; |
1126 | ||
3b54baad | 1127 | /* gpio5 */ |
844a3b63 PW |
1128 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1129 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1130 | }; |
1131 | ||
3b54baad BC |
1132 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1133 | .name = "gpio5", | |
1134 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1135 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1136 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1137 | .main_clk = "l4_div_ck", |
55d2cb08 BC |
1138 | .prcm = { |
1139 | .omap4 = { | |
d0f0631d | 1140 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1141 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1142 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1143 | }, |
1144 | }, | |
3b54baad BC |
1145 | .opt_clks = gpio5_opt_clks, |
1146 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1147 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1148 | }; |
1149 | ||
3b54baad | 1150 | /* gpio6 */ |
3b54baad | 1151 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1152 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1153 | }; |
1154 | ||
3b54baad BC |
1155 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1156 | .name = "gpio6", | |
1157 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1158 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1159 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1160 | .main_clk = "l4_div_ck", |
3b54baad BC |
1161 | .prcm = { |
1162 | .omap4 = { | |
d0f0631d | 1163 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1164 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1165 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1166 | }, |
db12ba53 | 1167 | }, |
3b54baad BC |
1168 | .opt_clks = gpio6_opt_clks, |
1169 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1170 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1171 | }; |
1172 | ||
eb42b5d3 BC |
1173 | /* |
1174 | * 'gpmc' class | |
1175 | * general purpose memory controller | |
1176 | */ | |
1177 | ||
1178 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1179 | .rev_offs = 0x0000, | |
1180 | .sysc_offs = 0x0010, | |
1181 | .syss_offs = 0x0014, | |
1182 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1183 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1184 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1185 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1186 | }; | |
1187 | ||
1188 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1189 | .name = "gpmc", | |
1190 | .sysc = &omap44xx_gpmc_sysc, | |
1191 | }; | |
1192 | ||
1193 | /* gpmc */ | |
eb42b5d3 BC |
1194 | static struct omap_hwmod omap44xx_gpmc_hwmod = { |
1195 | .name = "gpmc", | |
1196 | .class = &omap44xx_gpmc_hwmod_class, | |
1197 | .clkdm_name = "l3_2_clkdm", | |
63aa945b TL |
1198 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
1199 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
eb42b5d3 BC |
1200 | .prcm = { |
1201 | .omap4 = { | |
1202 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1203 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1204 | .modulemode = MODULEMODE_HWCTRL, | |
1205 | }, | |
1206 | }, | |
1207 | }; | |
1208 | ||
9def390e PW |
1209 | /* |
1210 | * 'gpu' class | |
1211 | * 2d/3d graphics accelerator | |
1212 | */ | |
1213 | ||
1214 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1215 | .rev_offs = 0x1fc00, | |
1216 | .sysc_offs = 0x1fc10, | |
1217 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1218 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1219 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1220 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1221 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1222 | }; | |
1223 | ||
1224 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1225 | .name = "gpu", | |
1226 | .sysc = &omap44xx_gpu_sysc, | |
1227 | }; | |
1228 | ||
1229 | /* gpu */ | |
9def390e PW |
1230 | static struct omap_hwmod omap44xx_gpu_hwmod = { |
1231 | .name = "gpu", | |
1232 | .class = &omap44xx_gpu_hwmod_class, | |
1233 | .clkdm_name = "l3_gfx_clkdm", | |
ee877acd | 1234 | .main_clk = "sgx_clk_mux", |
9def390e PW |
1235 | .prcm = { |
1236 | .omap4 = { | |
1237 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1238 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1239 | .modulemode = MODULEMODE_SWCTRL, | |
1240 | }, | |
1241 | }, | |
1242 | }; | |
1243 | ||
a091c08e PW |
1244 | /* |
1245 | * 'hdq1w' class | |
1246 | * hdq / 1-wire serial interface controller | |
1247 | */ | |
1248 | ||
1249 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1250 | .rev_offs = 0x0000, | |
1251 | .sysc_offs = 0x0014, | |
1252 | .syss_offs = 0x0018, | |
1253 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1254 | SYSS_HAS_RESET_STATUS), | |
1255 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1256 | }; | |
1257 | ||
1258 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1259 | .name = "hdq1w", | |
1260 | .sysc = &omap44xx_hdq1w_sysc, | |
1261 | }; | |
1262 | ||
1263 | /* hdq1w */ | |
a091c08e PW |
1264 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { |
1265 | .name = "hdq1w", | |
1266 | .class = &omap44xx_hdq1w_hwmod_class, | |
1267 | .clkdm_name = "l4_per_clkdm", | |
1268 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
17b7e7d3 | 1269 | .main_clk = "func_12m_fclk", |
a091c08e PW |
1270 | .prcm = { |
1271 | .omap4 = { | |
1272 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1273 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1274 | .modulemode = MODULEMODE_SWCTRL, | |
1275 | }, | |
1276 | }, | |
1277 | }; | |
1278 | ||
407a6888 BC |
1279 | /* |
1280 | * 'hsi' class | |
1281 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1282 | * serial if) | |
1283 | */ | |
1284 | ||
1285 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1286 | .rev_offs = 0x0000, | |
1287 | .sysc_offs = 0x0010, | |
1288 | .syss_offs = 0x0014, | |
1289 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1290 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1291 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1292 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1293 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1294 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1295 | .sysc_fields = &omap_hwmod_sysc_type1, |
1296 | }; | |
1297 | ||
1298 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1299 | .name = "hsi", | |
1300 | .sysc = &omap44xx_hsi_sysc, | |
1301 | }; | |
1302 | ||
1303 | /* hsi */ | |
407a6888 BC |
1304 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1305 | .name = "hsi", | |
1306 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1307 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1308 | .main_clk = "hsi_fck", |
00fe610b | 1309 | .prcm = { |
407a6888 | 1310 | .omap4 = { |
d0f0631d | 1311 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1312 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1313 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1314 | }, |
1315 | }, | |
407a6888 BC |
1316 | }; |
1317 | ||
3b54baad BC |
1318 | /* |
1319 | * 'i2c' class | |
1320 | * multimaster high-speed i2c controller | |
1321 | */ | |
db12ba53 | 1322 | |
3b54baad BC |
1323 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1324 | .sysc_offs = 0x0010, | |
1325 | .syss_offs = 0x0090, | |
1326 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1327 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1328 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1329 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1330 | SIDLE_SMART_WKUP), | |
3b54baad | 1331 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1332 | }; |
1333 | ||
3b54baad | 1334 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1335 | .name = "i2c", |
1336 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1337 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1338 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1339 | }; |
1340 | ||
4d4441a6 | 1341 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
972deb4f | 1342 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
4d4441a6 AG |
1343 | }; |
1344 | ||
3b54baad | 1345 | /* i2c1 */ |
3b54baad BC |
1346 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1347 | .name = "i2c1", | |
1348 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1349 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1350 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1351 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1352 | .prcm = { |
1353 | .omap4 = { | |
d0f0631d | 1354 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1355 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1356 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1357 | }, |
1358 | }, | |
4d4441a6 | 1359 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1360 | }; |
1361 | ||
3b54baad | 1362 | /* i2c2 */ |
3b54baad BC |
1363 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1364 | .name = "i2c2", | |
1365 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1366 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1367 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1368 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1369 | .prcm = { |
1370 | .omap4 = { | |
d0f0631d | 1371 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1372 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1373 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1374 | }, |
1375 | }, | |
4d4441a6 | 1376 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1377 | }; |
1378 | ||
3b54baad | 1379 | /* i2c3 */ |
3b54baad BC |
1380 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1381 | .name = "i2c3", | |
1382 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1383 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1384 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1385 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1386 | .prcm = { |
1387 | .omap4 = { | |
d0f0631d | 1388 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1389 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1390 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1391 | }, |
1392 | }, | |
4d4441a6 | 1393 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1394 | }; |
1395 | ||
3b54baad | 1396 | /* i2c4 */ |
3b54baad BC |
1397 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1398 | .name = "i2c4", | |
1399 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1400 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1401 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1402 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1403 | .prcm = { |
1404 | .omap4 = { | |
d0f0631d | 1405 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1406 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1407 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1408 | }, |
1409 | }, | |
4d4441a6 | 1410 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1411 | }; |
1412 | ||
407a6888 BC |
1413 | /* |
1414 | * 'ipu' class | |
1415 | * imaging processor unit | |
1416 | */ | |
1417 | ||
1418 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1419 | .name = "ipu", | |
1420 | }; | |
1421 | ||
1422 | /* ipu */ | |
f2f5736c | 1423 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1424 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1425 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1426 | }; |
1427 | ||
407a6888 BC |
1428 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1429 | .name = "ipu", | |
1430 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1431 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
1432 | .rst_lines = omap44xx_ipu_resets, |
1433 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
298ea44f | 1434 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1435 | .prcm = { |
407a6888 | 1436 | .omap4 = { |
d0f0631d | 1437 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1438 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1439 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1440 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1441 | }, |
1442 | }, | |
407a6888 BC |
1443 | }; |
1444 | ||
1445 | /* | |
1446 | * 'iss' class | |
1447 | * external images sensor pixel data processor | |
1448 | */ | |
1449 | ||
1450 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1451 | .rev_offs = 0x0000, | |
1452 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1453 | /* |
1454 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1455 | * accessing sysconfig again. | |
1456 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1457 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1458 | * | |
1459 | * TODO: Indicate errata when available. | |
1460 | */ | |
1461 | .srst_udelay = 2, | |
407a6888 BC |
1462 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1463 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1464 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1465 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1466 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1467 | .sysc_fields = &omap_hwmod_sysc_type2, |
1468 | }; | |
1469 | ||
1470 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1471 | .name = "iss", | |
1472 | .sysc = &omap44xx_iss_sysc, | |
1473 | }; | |
1474 | ||
1475 | /* iss */ | |
407a6888 BC |
1476 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1477 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1478 | }; | |
1479 | ||
1480 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1481 | .name = "iss", | |
1482 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1483 | .clkdm_name = "iss_clkdm", |
17b7e7d3 | 1484 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1485 | .prcm = { |
407a6888 | 1486 | .omap4 = { |
d0f0631d | 1487 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1488 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1489 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1490 | }, |
1491 | }, | |
1492 | .opt_clks = iss_opt_clks, | |
1493 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1494 | }; |
1495 | ||
8f25bdc5 BC |
1496 | /* |
1497 | * 'iva' class | |
1498 | * multi-standard video encoder/decoder hardware accelerator | |
1499 | */ | |
1500 | ||
1501 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1502 | .name = "iva", |
8f25bdc5 BC |
1503 | }; |
1504 | ||
1505 | /* iva */ | |
8f25bdc5 | 1506 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { |
8f25bdc5 | 1507 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1508 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1509 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1510 | }; |
1511 | ||
8f25bdc5 BC |
1512 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1513 | .name = "iva", | |
1514 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1515 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
1516 | .rst_lines = omap44xx_iva_resets, |
1517 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
17b7e7d3 | 1518 | .main_clk = "dpll_iva_m5x2_ck", |
8f25bdc5 BC |
1519 | .prcm = { |
1520 | .omap4 = { | |
d0f0631d | 1521 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1522 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1523 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1524 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1525 | }, |
1526 | }, | |
8f25bdc5 BC |
1527 | }; |
1528 | ||
407a6888 BC |
1529 | /* |
1530 | * 'kbd' class | |
1531 | * keyboard controller | |
1532 | */ | |
1533 | ||
1534 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1535 | .rev_offs = 0x0000, | |
1536 | .sysc_offs = 0x0010, | |
1537 | .syss_offs = 0x0014, | |
1538 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1539 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1540 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1541 | SYSS_HAS_RESET_STATUS), | |
1542 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1543 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1544 | }; | |
1545 | ||
1546 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1547 | .name = "kbd", | |
1548 | .sysc = &omap44xx_kbd_sysc, | |
1549 | }; | |
1550 | ||
1551 | /* kbd */ | |
407a6888 BC |
1552 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1553 | .name = "kbd", | |
1554 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1555 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 1556 | .main_clk = "sys_32k_ck", |
00fe610b | 1557 | .prcm = { |
407a6888 | 1558 | .omap4 = { |
d0f0631d | 1559 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1560 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1561 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1562 | }, |
1563 | }, | |
407a6888 BC |
1564 | }; |
1565 | ||
ec5df927 BC |
1566 | /* |
1567 | * 'mailbox' class | |
1568 | * mailbox module allowing communication between the on-chip processors using a | |
1569 | * queued mailbox-interrupt mechanism. | |
1570 | */ | |
1571 | ||
1572 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1573 | .rev_offs = 0x0000, | |
1574 | .sysc_offs = 0x0010, | |
1575 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1576 | SYSC_HAS_SOFTRESET), | |
1577 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1578 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1579 | }; | |
1580 | ||
1581 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1582 | .name = "mailbox", | |
1583 | .sysc = &omap44xx_mailbox_sysc, | |
1584 | }; | |
1585 | ||
1586 | /* mailbox */ | |
ec5df927 BC |
1587 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1588 | .name = "mailbox", | |
1589 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1590 | .clkdm_name = "l4_cfg_clkdm", |
00fe610b | 1591 | .prcm = { |
ec5df927 | 1592 | .omap4 = { |
d0f0631d | 1593 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1594 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1595 | }, |
1596 | }, | |
ec5df927 BC |
1597 | }; |
1598 | ||
896d4e98 BC |
1599 | /* |
1600 | * 'mcasp' class | |
1601 | * multi-channel audio serial port controller | |
1602 | */ | |
1603 | ||
1604 | /* The IP is not compliant to type1 / type2 scheme */ | |
1605 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1606 | .sidle_shift = 0, | |
1607 | }; | |
1608 | ||
1609 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1610 | .sysc_offs = 0x0004, | |
1611 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1612 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1613 | SIDLE_SMART_WKUP), | |
1614 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1615 | }; | |
1616 | ||
1617 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1618 | .name = "mcasp", | |
1619 | .sysc = &omap44xx_mcasp_sysc, | |
1620 | }; | |
1621 | ||
1622 | /* mcasp */ | |
896d4e98 BC |
1623 | static struct omap_hwmod omap44xx_mcasp_hwmod = { |
1624 | .name = "mcasp", | |
1625 | .class = &omap44xx_mcasp_hwmod_class, | |
1626 | .clkdm_name = "abe_clkdm", | |
ee877acd | 1627 | .main_clk = "func_mcasp_abe_gfclk", |
896d4e98 BC |
1628 | .prcm = { |
1629 | .omap4 = { | |
1630 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1631 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1632 | .modulemode = MODULEMODE_SWCTRL, | |
1633 | }, | |
1634 | }, | |
1635 | }; | |
1636 | ||
4ddff493 BC |
1637 | /* |
1638 | * 'mcbsp' class | |
1639 | * multi channel buffered serial port controller | |
1640 | */ | |
1641 | ||
1642 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1643 | .sysc_offs = 0x008c, | |
1644 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1645 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1646 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1647 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1648 | }; | |
1649 | ||
1650 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1651 | .name = "mcbsp", | |
1652 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1653 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1654 | }; |
1655 | ||
1656 | /* mcbsp1 */ | |
503d0ea2 PW |
1657 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1658 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1659 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1660 | }; |
1661 | ||
4ddff493 BC |
1662 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1663 | .name = "mcbsp1", | |
1664 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1665 | .clkdm_name = "abe_clkdm", |
ee877acd | 1666 | .main_clk = "func_mcbsp1_gfclk", |
4ddff493 BC |
1667 | .prcm = { |
1668 | .omap4 = { | |
d0f0631d | 1669 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1670 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1671 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1672 | }, |
1673 | }, | |
503d0ea2 PW |
1674 | .opt_clks = mcbsp1_opt_clks, |
1675 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1676 | }; |
1677 | ||
1678 | /* mcbsp2 */ | |
844a3b63 PW |
1679 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1680 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1681 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
1682 | }; |
1683 | ||
4ddff493 BC |
1684 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1685 | .name = "mcbsp2", | |
1686 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1687 | .clkdm_name = "abe_clkdm", |
ee877acd | 1688 | .main_clk = "func_mcbsp2_gfclk", |
4ddff493 BC |
1689 | .prcm = { |
1690 | .omap4 = { | |
d0f0631d | 1691 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1692 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1693 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1694 | }, |
1695 | }, | |
503d0ea2 PW |
1696 | .opt_clks = mcbsp2_opt_clks, |
1697 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1698 | }; |
1699 | ||
1700 | /* mcbsp3 */ | |
503d0ea2 PW |
1701 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1702 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1703 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
1704 | }; |
1705 | ||
4ddff493 BC |
1706 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1707 | .name = "mcbsp3", | |
1708 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1709 | .clkdm_name = "abe_clkdm", |
ee877acd | 1710 | .main_clk = "func_mcbsp3_gfclk", |
4ddff493 BC |
1711 | .prcm = { |
1712 | .omap4 = { | |
d0f0631d | 1713 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1714 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1715 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1716 | }, |
1717 | }, | |
503d0ea2 PW |
1718 | .opt_clks = mcbsp3_opt_clks, |
1719 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1720 | }; |
1721 | ||
1722 | /* mcbsp4 */ | |
503d0ea2 PW |
1723 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
1724 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1725 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
1726 | }; |
1727 | ||
4ddff493 BC |
1728 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
1729 | .name = "mcbsp4", | |
1730 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1731 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 1732 | .main_clk = "per_mcbsp4_gfclk", |
4ddff493 BC |
1733 | .prcm = { |
1734 | .omap4 = { | |
d0f0631d | 1735 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 1736 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 1737 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1738 | }, |
1739 | }, | |
503d0ea2 PW |
1740 | .opt_clks = mcbsp4_opt_clks, |
1741 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
1742 | }; |
1743 | ||
407a6888 BC |
1744 | /* |
1745 | * 'mcpdm' class | |
1746 | * multi channel pdm controller (proprietary interface with phoenix power | |
1747 | * ic) | |
1748 | */ | |
1749 | ||
1750 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
1751 | .rev_offs = 0x0000, | |
1752 | .sysc_offs = 0x0010, | |
1753 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1754 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1755 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1756 | SIDLE_SMART_WKUP), | |
1757 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1758 | }; | |
1759 | ||
1760 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
1761 | .name = "mcpdm", | |
1762 | .sysc = &omap44xx_mcpdm_sysc, | |
1763 | }; | |
1764 | ||
1765 | /* mcpdm */ | |
407a6888 BC |
1766 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
1767 | .name = "mcpdm", | |
1768 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 1769 | .clkdm_name = "abe_clkdm", |
bc05244e PW |
1770 | /* |
1771 | * It's suspected that the McPDM requires an off-chip main | |
1772 | * functional clock, controlled via I2C. This IP block is | |
1773 | * currently reset very early during boot, before I2C is | |
1774 | * available, so it doesn't seem that we have any choice in | |
1775 | * the kernel other than to avoid resetting it. | |
12d82e4b PU |
1776 | * |
1777 | * Also, McPDM needs to be configured to NO_IDLE mode when it | |
1778 | * is in used otherwise vital clocks will be gated which | |
1779 | * results 'slow motion' audio playback. | |
bc05244e | 1780 | */ |
12d82e4b | 1781 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, |
17b7e7d3 | 1782 | .main_clk = "pad_clks_ck", |
00fe610b | 1783 | .prcm = { |
407a6888 | 1784 | .omap4 = { |
d0f0631d | 1785 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 1786 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 1787 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1788 | }, |
1789 | }, | |
407a6888 BC |
1790 | }; |
1791 | ||
9bcbd7f0 BC |
1792 | /* |
1793 | * 'mcspi' class | |
1794 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1795 | * bus | |
1796 | */ | |
1797 | ||
1798 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
1799 | .rev_offs = 0x0000, | |
1800 | .sysc_offs = 0x0010, | |
1801 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1802 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1803 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1804 | SIDLE_SMART_WKUP), | |
1805 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1806 | }; | |
1807 | ||
1808 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
1809 | .name = "mcspi", | |
1810 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 1811 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
1812 | }; |
1813 | ||
1814 | /* mcspi1 */ | |
9bcbd7f0 BC |
1815 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { |
1816 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
1817 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
1818 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
1819 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
1820 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
1821 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
1822 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
1823 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1824 | { .dma_req = -1 } |
9bcbd7f0 BC |
1825 | }; |
1826 | ||
905a74d9 BC |
1827 | /* mcspi1 dev_attr */ |
1828 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
1829 | .num_chipselect = 4, | |
1830 | }; | |
1831 | ||
9bcbd7f0 BC |
1832 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
1833 | .name = "mcspi1", | |
1834 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1835 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1836 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
17b7e7d3 | 1837 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1838 | .prcm = { |
1839 | .omap4 = { | |
d0f0631d | 1840 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 1841 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 1842 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1843 | }, |
1844 | }, | |
905a74d9 | 1845 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
1846 | }; |
1847 | ||
1848 | /* mcspi2 */ | |
9bcbd7f0 BC |
1849 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { |
1850 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
1851 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
1852 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
1853 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1854 | { .dma_req = -1 } |
9bcbd7f0 BC |
1855 | }; |
1856 | ||
905a74d9 BC |
1857 | /* mcspi2 dev_attr */ |
1858 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
1859 | .num_chipselect = 2, | |
1860 | }; | |
1861 | ||
9bcbd7f0 BC |
1862 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
1863 | .name = "mcspi2", | |
1864 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1865 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1866 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
17b7e7d3 | 1867 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1868 | .prcm = { |
1869 | .omap4 = { | |
d0f0631d | 1870 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 1871 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 1872 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1873 | }, |
1874 | }, | |
905a74d9 | 1875 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
1876 | }; |
1877 | ||
1878 | /* mcspi3 */ | |
9bcbd7f0 BC |
1879 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { |
1880 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
1881 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
1882 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
1883 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1884 | { .dma_req = -1 } |
9bcbd7f0 BC |
1885 | }; |
1886 | ||
905a74d9 BC |
1887 | /* mcspi3 dev_attr */ |
1888 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
1889 | .num_chipselect = 2, | |
1890 | }; | |
1891 | ||
9bcbd7f0 BC |
1892 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
1893 | .name = "mcspi3", | |
1894 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1895 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1896 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
17b7e7d3 | 1897 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1898 | .prcm = { |
1899 | .omap4 = { | |
d0f0631d | 1900 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 1901 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 1902 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1903 | }, |
1904 | }, | |
905a74d9 | 1905 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
1906 | }; |
1907 | ||
1908 | /* mcspi4 */ | |
9bcbd7f0 BC |
1909 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { |
1910 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
1911 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1912 | { .dma_req = -1 } |
9bcbd7f0 BC |
1913 | }; |
1914 | ||
905a74d9 BC |
1915 | /* mcspi4 dev_attr */ |
1916 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
1917 | .num_chipselect = 1, | |
1918 | }; | |
1919 | ||
9bcbd7f0 BC |
1920 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
1921 | .name = "mcspi4", | |
1922 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1923 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1924 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
17b7e7d3 | 1925 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1926 | .prcm = { |
1927 | .omap4 = { | |
d0f0631d | 1928 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 1929 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 1930 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1931 | }, |
1932 | }, | |
905a74d9 | 1933 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
1934 | }; |
1935 | ||
407a6888 BC |
1936 | /* |
1937 | * 'mmc' class | |
1938 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
1939 | */ | |
1940 | ||
1941 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
1942 | .rev_offs = 0x0000, | |
1943 | .sysc_offs = 0x0010, | |
1944 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1945 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1946 | SYSC_HAS_SOFTRESET), | |
1947 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1948 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1949 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1950 | .sysc_fields = &omap_hwmod_sysc_type2, |
1951 | }; | |
1952 | ||
1953 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
1954 | .name = "mmc", | |
1955 | .sysc = &omap44xx_mmc_sysc, | |
1956 | }; | |
1957 | ||
1958 | /* mmc1 */ | |
407a6888 BC |
1959 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { |
1960 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
1961 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1962 | { .dma_req = -1 } |
407a6888 BC |
1963 | }; |
1964 | ||
6ab8946f | 1965 | /* mmc1 dev_attr */ |
55143438 | 1966 | static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
6ab8946f KK |
1967 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
1968 | }; | |
1969 | ||
407a6888 BC |
1970 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
1971 | .name = "mmc1", | |
1972 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 1973 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1974 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
ee877acd | 1975 | .main_clk = "hsmmc1_fclk", |
00fe610b | 1976 | .prcm = { |
407a6888 | 1977 | .omap4 = { |
d0f0631d | 1978 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 1979 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 1980 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1981 | }, |
1982 | }, | |
6ab8946f | 1983 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
1984 | }; |
1985 | ||
1986 | /* mmc2 */ | |
407a6888 BC |
1987 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { |
1988 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
1989 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1990 | { .dma_req = -1 } |
407a6888 BC |
1991 | }; |
1992 | ||
407a6888 BC |
1993 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
1994 | .name = "mmc2", | |
1995 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 1996 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1997 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
ee877acd | 1998 | .main_clk = "hsmmc2_fclk", |
00fe610b | 1999 | .prcm = { |
407a6888 | 2000 | .omap4 = { |
d0f0631d | 2001 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2002 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2003 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2004 | }, |
2005 | }, | |
407a6888 BC |
2006 | }; |
2007 | ||
2008 | /* mmc3 */ | |
407a6888 BC |
2009 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { |
2010 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2011 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2012 | { .dma_req = -1 } |
407a6888 BC |
2013 | }; |
2014 | ||
407a6888 BC |
2015 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2016 | .name = "mmc3", | |
2017 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2018 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2019 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
17b7e7d3 | 2020 | .main_clk = "func_48m_fclk", |
00fe610b | 2021 | .prcm = { |
407a6888 | 2022 | .omap4 = { |
d0f0631d | 2023 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2024 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2025 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2026 | }, |
2027 | }, | |
407a6888 BC |
2028 | }; |
2029 | ||
2030 | /* mmc4 */ | |
407a6888 BC |
2031 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { |
2032 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2033 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2034 | { .dma_req = -1 } |
407a6888 BC |
2035 | }; |
2036 | ||
407a6888 BC |
2037 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2038 | .name = "mmc4", | |
2039 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2040 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2041 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
17b7e7d3 | 2042 | .main_clk = "func_48m_fclk", |
00fe610b | 2043 | .prcm = { |
407a6888 | 2044 | .omap4 = { |
d0f0631d | 2045 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2046 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2047 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2048 | }, |
2049 | }, | |
407a6888 BC |
2050 | }; |
2051 | ||
2052 | /* mmc5 */ | |
407a6888 BC |
2053 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { |
2054 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2055 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2056 | { .dma_req = -1 } |
407a6888 BC |
2057 | }; |
2058 | ||
407a6888 BC |
2059 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2060 | .name = "mmc5", | |
2061 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2062 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2063 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
17b7e7d3 | 2064 | .main_clk = "func_48m_fclk", |
00fe610b | 2065 | .prcm = { |
407a6888 | 2066 | .omap4 = { |
d0f0631d | 2067 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2068 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2069 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2070 | }, |
2071 | }, | |
407a6888 BC |
2072 | }; |
2073 | ||
230844db ORL |
2074 | /* |
2075 | * 'mmu' class | |
2076 | * The memory management unit performs virtual to physical address translation | |
2077 | * for its requestors. | |
2078 | */ | |
2079 | ||
2080 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2081 | .rev_offs = 0x000, | |
2082 | .sysc_offs = 0x010, | |
2083 | .syss_offs = 0x014, | |
2084 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2085 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2086 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2087 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2088 | }; | |
2089 | ||
2090 | static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { | |
2091 | .name = "mmu", | |
2092 | .sysc = &mmu_sysc, | |
2093 | }; | |
2094 | ||
2095 | /* mmu ipu */ | |
2096 | ||
230844db | 2097 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; |
230844db ORL |
2098 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { |
2099 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2100 | }; | |
2101 | ||
230844db ORL |
2102 | /* l3_main_2 -> mmu_ipu */ |
2103 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { | |
2104 | .master = &omap44xx_l3_main_2_hwmod, | |
2105 | .slave = &omap44xx_mmu_ipu_hwmod, | |
2106 | .clk = "l3_div_ck", | |
230844db ORL |
2107 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2108 | }; | |
2109 | ||
2110 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |
2111 | .name = "mmu_ipu", | |
2112 | .class = &omap44xx_mmu_hwmod_class, | |
2113 | .clkdm_name = "ducati_clkdm", | |
230844db ORL |
2114 | .rst_lines = omap44xx_mmu_ipu_resets, |
2115 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | |
2116 | .main_clk = "ducati_clk_mux_ck", | |
2117 | .prcm = { | |
2118 | .omap4 = { | |
2119 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, | |
2120 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, | |
2121 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, | |
2122 | .modulemode = MODULEMODE_HWCTRL, | |
2123 | }, | |
2124 | }, | |
230844db ORL |
2125 | }; |
2126 | ||
2127 | /* mmu dsp */ | |
2128 | ||
230844db | 2129 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; |
230844db ORL |
2130 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { |
2131 | { .name = "mmu_cache", .rst_shift = 1 }, | |
2132 | }; | |
2133 | ||
230844db ORL |
2134 | /* l4_cfg -> dsp */ |
2135 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { | |
2136 | .master = &omap44xx_l4_cfg_hwmod, | |
2137 | .slave = &omap44xx_mmu_dsp_hwmod, | |
2138 | .clk = "l4_div_ck", | |
230844db ORL |
2139 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2140 | }; | |
2141 | ||
2142 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |
2143 | .name = "mmu_dsp", | |
2144 | .class = &omap44xx_mmu_hwmod_class, | |
2145 | .clkdm_name = "tesla_clkdm", | |
230844db ORL |
2146 | .rst_lines = omap44xx_mmu_dsp_resets, |
2147 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | |
2148 | .main_clk = "dpll_iva_m4x2_ck", | |
2149 | .prcm = { | |
2150 | .omap4 = { | |
2151 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, | |
2152 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, | |
2153 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, | |
2154 | .modulemode = MODULEMODE_HWCTRL, | |
2155 | }, | |
2156 | }, | |
230844db ORL |
2157 | }; |
2158 | ||
3b54baad BC |
2159 | /* |
2160 | * 'mpu' class | |
2161 | * mpu sub-system | |
2162 | */ | |
2163 | ||
2164 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2165 | .name = "mpu", |
db12ba53 BC |
2166 | }; |
2167 | ||
3b54baad | 2168 | /* mpu */ |
3b54baad BC |
2169 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2170 | .name = "mpu", | |
2171 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2172 | .clkdm_name = "mpuss_clkdm", |
b2eb0002 | 2173 | .flags = HWMOD_INIT_NO_IDLE, |
3b54baad | 2174 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2175 | .prcm = { |
2176 | .omap4 = { | |
d0f0631d | 2177 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2178 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2179 | }, |
2180 | }, | |
db12ba53 BC |
2181 | }; |
2182 | ||
e17f18c0 PW |
2183 | /* |
2184 | * 'ocmc_ram' class | |
2185 | * top-level core on-chip ram | |
2186 | */ | |
2187 | ||
2188 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2189 | .name = "ocmc_ram", | |
2190 | }; | |
2191 | ||
2192 | /* ocmc_ram */ | |
2193 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2194 | .name = "ocmc_ram", | |
2195 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2196 | .clkdm_name = "l3_2_clkdm", | |
2197 | .prcm = { | |
2198 | .omap4 = { | |
2199 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2200 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2201 | }, | |
2202 | }, | |
2203 | }; | |
2204 | ||
0c668875 BC |
2205 | /* |
2206 | * 'ocp2scp' class | |
2207 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2208 | * protocol | |
2209 | */ | |
2210 | ||
33c976ec BC |
2211 | static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { |
2212 | .rev_offs = 0x0000, | |
2213 | .sysc_offs = 0x0010, | |
2214 | .syss_offs = 0x0014, | |
2215 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2216 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2217 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2218 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2219 | }; | |
2220 | ||
0c668875 BC |
2221 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { |
2222 | .name = "ocp2scp", | |
33c976ec | 2223 | .sysc = &omap44xx_ocp2scp_sysc, |
0c668875 BC |
2224 | }; |
2225 | ||
2226 | /* ocp2scp_usb_phy */ | |
0c668875 BC |
2227 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
2228 | .name = "ocp2scp_usb_phy", | |
2229 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2230 | .clkdm_name = "l3_init_clkdm", | |
f4d7a536 KVA |
2231 | /* |
2232 | * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP | |
2233 | * block as an "optional clock," and normally should never be | |
2234 | * specified as the main_clk for an OMAP IP block. However it | |
2235 | * turns out that this clock is actually the main clock for | |
2236 | * the ocp2scp_usb_phy IP block: | |
2237 | * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html | |
2238 | * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems | |
2239 | * to be the best workaround. | |
2240 | */ | |
2241 | .main_clk = "ocp2scp_usb_phy_phy_48m", | |
0c668875 BC |
2242 | .prcm = { |
2243 | .omap4 = { | |
2244 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2245 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2246 | .modulemode = MODULEMODE_HWCTRL, | |
2247 | }, | |
2248 | }, | |
0c668875 BC |
2249 | }; |
2250 | ||
794b480a PW |
2251 | /* |
2252 | * 'prcm' class | |
2253 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2254 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2255 | */ | |
2256 | ||
2257 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2258 | .name = "prcm", | |
2259 | }; | |
2260 | ||
2261 | /* prcm_mpu */ | |
2262 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2263 | .name = "prcm_mpu", | |
2264 | .class = &omap44xx_prcm_hwmod_class, | |
2265 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 2266 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2267 | .prcm = { |
2268 | .omap4 = { | |
2269 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2270 | }, | |
2271 | }, | |
794b480a PW |
2272 | }; |
2273 | ||
2274 | /* cm_core_aon */ | |
2275 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2276 | .name = "cm_core_aon", | |
2277 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2278 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2279 | .prcm = { |
2280 | .omap4 = { | |
2281 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2282 | }, | |
2283 | }, | |
794b480a PW |
2284 | }; |
2285 | ||
2286 | /* cm_core */ | |
2287 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2288 | .name = "cm_core", | |
2289 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2290 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2291 | .prcm = { |
2292 | .omap4 = { | |
2293 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2294 | }, | |
2295 | }, | |
794b480a PW |
2296 | }; |
2297 | ||
2298 | /* prm */ | |
794b480a PW |
2299 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { |
2300 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2301 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2302 | }; | |
2303 | ||
2304 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2305 | .name = "prm", | |
2306 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2307 | .rst_lines = omap44xx_prm_resets, |
2308 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2309 | }; | |
2310 | ||
2311 | /* | |
2312 | * 'scrm' class | |
2313 | * system clock and reset manager | |
2314 | */ | |
2315 | ||
2316 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2317 | .name = "scrm", | |
2318 | }; | |
2319 | ||
2320 | /* scrm */ | |
2321 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2322 | .name = "scrm", | |
2323 | .class = &omap44xx_scrm_hwmod_class, | |
2324 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
2325 | .prcm = { |
2326 | .omap4 = { | |
2327 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2328 | }, | |
2329 | }, | |
794b480a PW |
2330 | }; |
2331 | ||
42b9e387 PW |
2332 | /* |
2333 | * 'sl2if' class | |
2334 | * shared level 2 memory interface | |
2335 | */ | |
2336 | ||
2337 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2338 | .name = "sl2if", | |
2339 | }; | |
2340 | ||
2341 | /* sl2if */ | |
2342 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2343 | .name = "sl2if", | |
2344 | .class = &omap44xx_sl2if_hwmod_class, | |
2345 | .clkdm_name = "ivahd_clkdm", | |
2346 | .prcm = { | |
2347 | .omap4 = { | |
2348 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2349 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2350 | .modulemode = MODULEMODE_HWCTRL, | |
2351 | }, | |
2352 | }, | |
2353 | }; | |
2354 | ||
1e3b5e59 BC |
2355 | /* |
2356 | * 'slimbus' class | |
2357 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2358 | * the device and external components | |
2359 | */ | |
2360 | ||
2361 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2362 | .rev_offs = 0x0000, | |
2363 | .sysc_offs = 0x0010, | |
2364 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2365 | SYSC_HAS_SOFTRESET), | |
2366 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2367 | SIDLE_SMART_WKUP), | |
2368 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2369 | }; | |
2370 | ||
2371 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2372 | .name = "slimbus", | |
2373 | .sysc = &omap44xx_slimbus_sysc, | |
2374 | }; | |
2375 | ||
2376 | /* slimbus1 */ | |
1e3b5e59 BC |
2377 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { |
2378 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2379 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2380 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2381 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2382 | }; | |
2383 | ||
2384 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2385 | .name = "slimbus1", | |
2386 | .class = &omap44xx_slimbus_hwmod_class, | |
2387 | .clkdm_name = "abe_clkdm", | |
1e3b5e59 BC |
2388 | .prcm = { |
2389 | .omap4 = { | |
2390 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2391 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2392 | .modulemode = MODULEMODE_SWCTRL, | |
2393 | }, | |
2394 | }, | |
2395 | .opt_clks = slimbus1_opt_clks, | |
2396 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2397 | }; | |
2398 | ||
2399 | /* slimbus2 */ | |
1e3b5e59 BC |
2400 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { |
2401 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2402 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2403 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2404 | }; | |
2405 | ||
2406 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2407 | .name = "slimbus2", | |
2408 | .class = &omap44xx_slimbus_hwmod_class, | |
2409 | .clkdm_name = "l4_per_clkdm", | |
1e3b5e59 BC |
2410 | .prcm = { |
2411 | .omap4 = { | |
2412 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2413 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2414 | .modulemode = MODULEMODE_SWCTRL, | |
2415 | }, | |
2416 | }, | |
2417 | .opt_clks = slimbus2_opt_clks, | |
2418 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2419 | }; | |
2420 | ||
1f6a717f BC |
2421 | /* |
2422 | * 'smartreflex' class | |
2423 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2424 | * performance error) | |
2425 | */ | |
2426 | ||
2427 | /* The IP is not compliant to type1 / type2 scheme */ | |
2428 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2429 | .sidle_shift = 24, | |
2430 | .enwkup_shift = 26, | |
2431 | }; | |
2432 | ||
2433 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2434 | .sysc_offs = 0x0038, | |
2435 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2436 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2437 | SIDLE_SMART_WKUP), | |
2438 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2439 | }; | |
2440 | ||
2441 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2442 | .name = "smartreflex", |
2443 | .sysc = &omap44xx_smartreflex_sysc, | |
2444 | .rev = 2, | |
1f6a717f BC |
2445 | }; |
2446 | ||
2447 | /* smartreflex_core */ | |
cea6b942 SG |
2448 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2449 | .sensor_voltdm_name = "core", | |
2450 | }; | |
2451 | ||
1f6a717f BC |
2452 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2453 | .name = "smartreflex_core", | |
2454 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2455 | .clkdm_name = "l4_ao_clkdm", |
212738a4 | 2456 | |
1f6a717f | 2457 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2458 | .prcm = { |
2459 | .omap4 = { | |
d0f0631d | 2460 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2461 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2462 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2463 | }, |
2464 | }, | |
cea6b942 | 2465 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2466 | }; |
2467 | ||
2468 | /* smartreflex_iva */ | |
cea6b942 SG |
2469 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2470 | .sensor_voltdm_name = "iva", | |
2471 | }; | |
2472 | ||
1f6a717f BC |
2473 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2474 | .name = "smartreflex_iva", | |
2475 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2476 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2477 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2478 | .prcm = { |
2479 | .omap4 = { | |
d0f0631d | 2480 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2481 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2482 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2483 | }, |
2484 | }, | |
cea6b942 | 2485 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2486 | }; |
2487 | ||
2488 | /* smartreflex_mpu */ | |
cea6b942 SG |
2489 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2490 | .sensor_voltdm_name = "mpu", | |
2491 | }; | |
2492 | ||
1f6a717f BC |
2493 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2494 | .name = "smartreflex_mpu", | |
2495 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2496 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2497 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2498 | .prcm = { |
2499 | .omap4 = { | |
d0f0631d | 2500 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2501 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2502 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2503 | }, |
2504 | }, | |
cea6b942 | 2505 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2506 | }; |
2507 | ||
d11c217f BC |
2508 | /* |
2509 | * 'spinlock' class | |
2510 | * spinlock provides hardware assistance for synchronizing the processes | |
2511 | * running on multiple processors | |
2512 | */ | |
2513 | ||
2514 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2515 | .rev_offs = 0x0000, | |
2516 | .sysc_offs = 0x0010, | |
2517 | .syss_offs = 0x0014, | |
2518 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2519 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2520 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
77319669 | 2521 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
d11c217f BC |
2522 | .sysc_fields = &omap_hwmod_sysc_type1, |
2523 | }; | |
2524 | ||
2525 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2526 | .name = "spinlock", | |
2527 | .sysc = &omap44xx_spinlock_sysc, | |
2528 | }; | |
2529 | ||
2530 | /* spinlock */ | |
d11c217f BC |
2531 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2532 | .name = "spinlock", | |
2533 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2534 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2535 | .prcm = { |
2536 | .omap4 = { | |
d0f0631d | 2537 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2538 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2539 | }, |
2540 | }, | |
d11c217f BC |
2541 | }; |
2542 | ||
35d1a66a BC |
2543 | /* |
2544 | * 'timer' class | |
2545 | * general purpose timer module with accurate 1ms tick | |
2546 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2547 | */ | |
2548 | ||
2549 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2550 | .rev_offs = 0x0000, | |
2551 | .sysc_offs = 0x0010, | |
2552 | .syss_offs = 0x0014, | |
2553 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2554 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2555 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2556 | SYSS_HAS_RESET_STATUS), | |
2557 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2558 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2559 | }; | |
2560 | ||
2561 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2562 | .name = "timer", | |
2563 | .sysc = &omap44xx_timer_1ms_sysc, | |
2564 | }; | |
2565 | ||
2566 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2567 | .rev_offs = 0x0000, | |
2568 | .sysc_offs = 0x0010, | |
2569 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2570 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2571 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2572 | SIDLE_SMART_WKUP), | |
2573 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2574 | }; | |
2575 | ||
2576 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2577 | .name = "timer", | |
2578 | .sysc = &omap44xx_timer_sysc, | |
2579 | }; | |
2580 | ||
c345c8b0 TKD |
2581 | /* always-on timers dev attribute */ |
2582 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2583 | .timer_capability = OMAP_TIMER_ALWON, | |
2584 | }; | |
2585 | ||
2586 | /* pwm timers dev attribute */ | |
2587 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2588 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2589 | }; | |
2590 | ||
5c3e4ec4 JH |
2591 | /* timers with DSP interrupt dev attribute */ |
2592 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
2593 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
2594 | }; | |
2595 | ||
2596 | /* pwm timers with DSP interrupt dev attribute */ | |
2597 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
2598 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
2599 | }; | |
2600 | ||
35d1a66a | 2601 | /* timer1 */ |
35d1a66a BC |
2602 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2603 | .name = "timer1", | |
2604 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2605 | .clkdm_name = "l4_wkup_clkdm", |
10759e82 | 2606 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2607 | .main_clk = "dmt1_clk_mux", |
35d1a66a BC |
2608 | .prcm = { |
2609 | .omap4 = { | |
d0f0631d | 2610 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2611 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2612 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2613 | }, |
2614 | }, | |
c345c8b0 | 2615 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2616 | }; |
2617 | ||
2618 | /* timer2 */ | |
35d1a66a BC |
2619 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2620 | .name = "timer2", | |
2621 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2622 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2623 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2624 | .main_clk = "cm2_dm2_mux", |
35d1a66a BC |
2625 | .prcm = { |
2626 | .omap4 = { | |
d0f0631d | 2627 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2628 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2629 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2630 | }, |
2631 | }, | |
35d1a66a BC |
2632 | }; |
2633 | ||
2634 | /* timer3 */ | |
35d1a66a BC |
2635 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2636 | .name = "timer3", | |
2637 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2638 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2639 | .main_clk = "cm2_dm3_mux", |
35d1a66a BC |
2640 | .prcm = { |
2641 | .omap4 = { | |
d0f0631d | 2642 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2643 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2644 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2645 | }, |
2646 | }, | |
35d1a66a BC |
2647 | }; |
2648 | ||
2649 | /* timer4 */ | |
35d1a66a BC |
2650 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2651 | .name = "timer4", | |
2652 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2653 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2654 | .main_clk = "cm2_dm4_mux", |
35d1a66a BC |
2655 | .prcm = { |
2656 | .omap4 = { | |
d0f0631d | 2657 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2658 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2659 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2660 | }, |
2661 | }, | |
35d1a66a BC |
2662 | }; |
2663 | ||
2664 | /* timer5 */ | |
35d1a66a BC |
2665 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2666 | .name = "timer5", | |
2667 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2668 | .clkdm_name = "abe_clkdm", |
ee877acd | 2669 | .main_clk = "timer5_sync_mux", |
35d1a66a BC |
2670 | .prcm = { |
2671 | .omap4 = { | |
d0f0631d | 2672 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2673 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2674 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2675 | }, |
2676 | }, | |
5c3e4ec4 | 2677 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2678 | }; |
2679 | ||
2680 | /* timer6 */ | |
35d1a66a BC |
2681 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
2682 | .name = "timer6", | |
2683 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2684 | .clkdm_name = "abe_clkdm", |
ee877acd | 2685 | .main_clk = "timer6_sync_mux", |
35d1a66a BC |
2686 | .prcm = { |
2687 | .omap4 = { | |
d0f0631d | 2688 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 2689 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 2690 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2691 | }, |
2692 | }, | |
5c3e4ec4 | 2693 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2694 | }; |
2695 | ||
2696 | /* timer7 */ | |
35d1a66a BC |
2697 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
2698 | .name = "timer7", | |
2699 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2700 | .clkdm_name = "abe_clkdm", |
ee877acd | 2701 | .main_clk = "timer7_sync_mux", |
35d1a66a BC |
2702 | .prcm = { |
2703 | .omap4 = { | |
d0f0631d | 2704 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 2705 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 2706 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2707 | }, |
2708 | }, | |
5c3e4ec4 | 2709 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2710 | }; |
2711 | ||
2712 | /* timer8 */ | |
35d1a66a BC |
2713 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
2714 | .name = "timer8", | |
2715 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2716 | .clkdm_name = "abe_clkdm", |
ee877acd | 2717 | .main_clk = "timer8_sync_mux", |
35d1a66a BC |
2718 | .prcm = { |
2719 | .omap4 = { | |
d0f0631d | 2720 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 2721 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 2722 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2723 | }, |
2724 | }, | |
5c3e4ec4 | 2725 | .dev_attr = &capability_dsp_pwm_dev_attr, |
35d1a66a BC |
2726 | }; |
2727 | ||
2728 | /* timer9 */ | |
35d1a66a BC |
2729 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
2730 | .name = "timer9", | |
2731 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2732 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2733 | .main_clk = "cm2_dm9_mux", |
35d1a66a BC |
2734 | .prcm = { |
2735 | .omap4 = { | |
d0f0631d | 2736 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 2737 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 2738 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2739 | }, |
2740 | }, | |
c345c8b0 | 2741 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2742 | }; |
2743 | ||
2744 | /* timer10 */ | |
35d1a66a BC |
2745 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
2746 | .name = "timer10", | |
2747 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2748 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2749 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2750 | .main_clk = "cm2_dm10_mux", |
35d1a66a BC |
2751 | .prcm = { |
2752 | .omap4 = { | |
d0f0631d | 2753 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 2754 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 2755 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2756 | }, |
2757 | }, | |
c345c8b0 | 2758 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2759 | }; |
2760 | ||
2761 | /* timer11 */ | |
35d1a66a BC |
2762 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
2763 | .name = "timer11", | |
2764 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2765 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2766 | .main_clk = "cm2_dm11_mux", |
35d1a66a BC |
2767 | .prcm = { |
2768 | .omap4 = { | |
d0f0631d | 2769 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 2770 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 2771 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2772 | }, |
2773 | }, | |
c345c8b0 | 2774 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2775 | }; |
2776 | ||
9780a9cf | 2777 | /* |
3b54baad BC |
2778 | * 'uart' class |
2779 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
2780 | */ |
2781 | ||
3b54baad BC |
2782 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
2783 | .rev_offs = 0x0050, | |
2784 | .sysc_offs = 0x0054, | |
2785 | .syss_offs = 0x0058, | |
2786 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
2787 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
2788 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
2789 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2790 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
2791 | .sysc_fields = &omap_hwmod_sysc_type1, |
2792 | }; | |
2793 | ||
3b54baad | 2794 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
2795 | .name = "uart", |
2796 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
2797 | }; |
2798 | ||
3b54baad | 2799 | /* uart1 */ |
3b54baad BC |
2800 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
2801 | .name = "uart1", | |
2802 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2803 | .clkdm_name = "l4_per_clkdm", |
66dde54e | 2804 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2805 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2806 | .prcm = { |
2807 | .omap4 = { | |
d0f0631d | 2808 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 2809 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 2810 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2811 | }, |
2812 | }, | |
9780a9cf BC |
2813 | }; |
2814 | ||
3b54baad | 2815 | /* uart2 */ |
3b54baad BC |
2816 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
2817 | .name = "uart2", | |
2818 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2819 | .clkdm_name = "l4_per_clkdm", |
66dde54e | 2820 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2821 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2822 | .prcm = { |
2823 | .omap4 = { | |
d0f0631d | 2824 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 2825 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 2826 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2827 | }, |
2828 | }, | |
9780a9cf BC |
2829 | }; |
2830 | ||
3b54baad | 2831 | /* uart3 */ |
3b54baad BC |
2832 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
2833 | .name = "uart3", | |
2834 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2835 | .clkdm_name = "l4_per_clkdm", |
7dedd346 | 2836 | .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2837 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2838 | .prcm = { |
2839 | .omap4 = { | |
d0f0631d | 2840 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 2841 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 2842 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2843 | }, |
2844 | }, | |
9780a9cf BC |
2845 | }; |
2846 | ||
3b54baad | 2847 | /* uart4 */ |
3b54baad BC |
2848 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
2849 | .name = "uart4", | |
2850 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2851 | .clkdm_name = "l4_per_clkdm", |
7dedd346 | 2852 | .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2853 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2854 | .prcm = { |
2855 | .omap4 = { | |
d0f0631d | 2856 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 2857 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 2858 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2859 | }, |
2860 | }, | |
9780a9cf BC |
2861 | }; |
2862 | ||
0c668875 BC |
2863 | /* |
2864 | * 'usb_host_fs' class | |
2865 | * full-speed usb host controller | |
2866 | */ | |
2867 | ||
2868 | /* The IP is not compliant to type1 / type2 scheme */ | |
2869 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
2870 | .midle_shift = 4, | |
2871 | .sidle_shift = 2, | |
2872 | .srst_shift = 1, | |
2873 | }; | |
2874 | ||
2875 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
2876 | .rev_offs = 0x0000, | |
2877 | .sysc_offs = 0x0210, | |
2878 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2879 | SYSC_HAS_SOFTRESET), | |
2880 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2881 | SIDLE_SMART_WKUP), | |
2882 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
2883 | }; | |
2884 | ||
2885 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
2886 | .name = "usb_host_fs", | |
2887 | .sysc = &omap44xx_usb_host_fs_sysc, | |
2888 | }; | |
2889 | ||
2890 | /* usb_host_fs */ | |
0c668875 BC |
2891 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { |
2892 | .name = "usb_host_fs", | |
2893 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
2894 | .clkdm_name = "l3_init_clkdm", | |
0c668875 BC |
2895 | .main_clk = "usb_host_fs_fck", |
2896 | .prcm = { | |
2897 | .omap4 = { | |
2898 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
2899 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
2900 | .modulemode = MODULEMODE_SWCTRL, | |
2901 | }, | |
2902 | }, | |
2903 | }; | |
2904 | ||
5844c4ea | 2905 | /* |
844a3b63 PW |
2906 | * 'usb_host_hs' class |
2907 | * high-speed multi-port usb host controller | |
5844c4ea BC |
2908 | */ |
2909 | ||
844a3b63 PW |
2910 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
2911 | .rev_offs = 0x0000, | |
2912 | .sysc_offs = 0x0010, | |
2913 | .syss_offs = 0x0014, | |
2914 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
b483a4a5 | 2915 | SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS), |
5844c4ea BC |
2916 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2917 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
2918 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
2919 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
2920 | }; |
2921 | ||
844a3b63 PW |
2922 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
2923 | .name = "usb_host_hs", | |
2924 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
2925 | }; |
2926 | ||
844a3b63 | 2927 | /* usb_host_hs */ |
844a3b63 PW |
2928 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
2929 | .name = "usb_host_hs", | |
2930 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 2931 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 2932 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
2933 | .prcm = { |
2934 | .omap4 = { | |
844a3b63 PW |
2935 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
2936 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
2937 | .modulemode = MODULEMODE_SWCTRL, | |
2938 | }, | |
2939 | }, | |
844a3b63 PW |
2940 | |
2941 | /* | |
2942 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
2943 | * id: i660 | |
2944 | * | |
2945 | * Description: | |
2946 | * In the following configuration : | |
2947 | * - USBHOST module is set to smart-idle mode | |
2948 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
2949 | * happens when the system is going to a low power mode : all ports | |
2950 | * have been suspended, the master part of the USBHOST module has | |
2951 | * entered the standby state, and SW has cut the functional clocks) | |
2952 | * - an USBHOST interrupt occurs before the module is able to answer | |
2953 | * idle_ack, typically a remote wakeup IRQ. | |
2954 | * Then the USB HOST module will enter a deadlock situation where it | |
2955 | * is no more accessible nor functional. | |
2956 | * | |
2957 | * Workaround: | |
2958 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
2959 | */ | |
2960 | ||
2961 | /* | |
2962 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
2963 | * Id: i571 | |
2964 | * | |
2965 | * Description: | |
2966 | * When the USBHOST module is set to smart-standby mode, and when it is | |
2967 | * ready to enter the standby state (i.e. all ports are suspended and | |
2968 | * all attached devices are in suspend mode), then it can wrongly assert | |
2969 | * the Mstandby signal too early while there are still some residual OCP | |
2970 | * transactions ongoing. If this condition occurs, the internal state | |
2971 | * machine may go to an undefined state and the USB link may be stuck | |
2972 | * upon the next resume. | |
2973 | * | |
2974 | * Workaround: | |
2975 | * Don't use smart standby; use only force standby, | |
2976 | * hence HWMOD_SWSUP_MSTANDBY | |
2977 | */ | |
2978 | ||
b483a4a5 | 2979 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
844a3b63 PW |
2980 | }; |
2981 | ||
2982 | /* | |
2983 | * 'usb_otg_hs' class | |
2984 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
2985 | */ | |
2986 | ||
2987 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
2988 | .rev_offs = 0x0400, | |
2989 | .sysc_offs = 0x0404, | |
2990 | .syss_offs = 0x0408, | |
2991 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
2992 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2993 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2994 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2995 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
2996 | MSTANDBY_SMART), | |
2997 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2998 | }; | |
2999 | ||
3000 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3001 | .name = "usb_otg_hs", | |
3002 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3003 | }; | |
3004 | ||
3005 | /* usb_otg_hs */ | |
844a3b63 PW |
3006 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { |
3007 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3008 | }; | |
3009 | ||
3010 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3011 | .name = "usb_otg_hs", | |
3012 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3013 | .clkdm_name = "l3_init_clkdm", | |
3014 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
844a3b63 PW |
3015 | .main_clk = "usb_otg_hs_ick", |
3016 | .prcm = { | |
3017 | .omap4 = { | |
3018 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3019 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3020 | .modulemode = MODULEMODE_HWCTRL, | |
3021 | }, | |
3022 | }, | |
3023 | .opt_clks = usb_otg_hs_opt_clks, | |
3024 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3025 | }; | |
3026 | ||
3027 | /* | |
3028 | * 'usb_tll_hs' class | |
3029 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3030 | */ | |
3031 | ||
3032 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3033 | .rev_offs = 0x0000, | |
3034 | .sysc_offs = 0x0010, | |
3035 | .syss_offs = 0x0014, | |
3036 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3037 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3038 | SYSC_HAS_AUTOIDLE), | |
3039 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3040 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3041 | }; | |
3042 | ||
3043 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3044 | .name = "usb_tll_hs", | |
3045 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3046 | }; | |
3047 | ||
844a3b63 PW |
3048 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { |
3049 | .name = "usb_tll_hs", | |
3050 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3051 | .clkdm_name = "l3_init_clkdm", | |
844a3b63 PW |
3052 | .main_clk = "usb_tll_hs_ick", |
3053 | .prcm = { | |
3054 | .omap4 = { | |
3055 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3056 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3057 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3058 | }, |
3059 | }, | |
5844c4ea BC |
3060 | }; |
3061 | ||
3b54baad BC |
3062 | /* |
3063 | * 'wd_timer' class | |
3064 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3065 | * overflow condition | |
3066 | */ | |
3067 | ||
3068 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3069 | .rev_offs = 0x0000, | |
3070 | .sysc_offs = 0x0010, | |
3071 | .syss_offs = 0x0014, | |
3072 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3073 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3074 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3075 | SIDLE_SMART_WKUP), | |
3b54baad | 3076 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3077 | }; |
3078 | ||
3b54baad BC |
3079 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3080 | .name = "wd_timer", | |
3081 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3082 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 3083 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
3084 | }; |
3085 | ||
3086 | /* wd_timer2 */ | |
3b54baad BC |
3087 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3088 | .name = "wd_timer2", | |
3089 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3090 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 3091 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3092 | .prcm = { |
3093 | .omap4 = { | |
d0f0631d | 3094 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3095 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3096 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3097 | }, |
3098 | }, | |
9780a9cf BC |
3099 | }; |
3100 | ||
3b54baad | 3101 | /* wd_timer3 */ |
3b54baad BC |
3102 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3103 | .name = "wd_timer3", | |
3104 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3105 | .clkdm_name = "abe_clkdm", |
17b7e7d3 | 3106 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3107 | .prcm = { |
3108 | .omap4 = { | |
d0f0631d | 3109 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3110 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3111 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3112 | }, |
3113 | }, | |
9780a9cf | 3114 | }; |
531ce0d5 | 3115 | |
844a3b63 | 3116 | |
af88fa9a | 3117 | /* |
844a3b63 | 3118 | * interfaces |
af88fa9a | 3119 | */ |
af88fa9a | 3120 | |
844a3b63 PW |
3121 | /* l3_main_1 -> dmm */ |
3122 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3123 | .master = &omap44xx_l3_main_1_hwmod, | |
3124 | .slave = &omap44xx_dmm_hwmod, | |
3125 | .clk = "l3_div_ck", | |
3126 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3127 | }; |
3128 | ||
844a3b63 PW |
3129 | /* mpu -> dmm */ |
3130 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3131 | .master = &omap44xx_mpu_hwmod, | |
3132 | .slave = &omap44xx_dmm_hwmod, | |
3133 | .clk = "l3_div_ck", | |
844a3b63 PW |
3134 | .user = OCP_USER_MPU, |
3135 | }; | |
3136 | ||
3137 | /* iva -> l3_instr */ | |
3138 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3139 | .master = &omap44xx_iva_hwmod, | |
3140 | .slave = &omap44xx_l3_instr_hwmod, | |
3141 | .clk = "l3_div_ck", | |
3142 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3143 | }; | |
3144 | ||
3145 | /* l3_main_3 -> l3_instr */ | |
3146 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3147 | .master = &omap44xx_l3_main_3_hwmod, | |
3148 | .slave = &omap44xx_l3_instr_hwmod, | |
3149 | .clk = "l3_div_ck", | |
3150 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3151 | }; | |
3152 | ||
9a817bc8 BC |
3153 | /* ocp_wp_noc -> l3_instr */ |
3154 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3155 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3156 | .slave = &omap44xx_l3_instr_hwmod, | |
3157 | .clk = "l3_div_ck", | |
3158 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3159 | }; | |
3160 | ||
844a3b63 PW |
3161 | /* dsp -> l3_main_1 */ |
3162 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3163 | .master = &omap44xx_dsp_hwmod, | |
3164 | .slave = &omap44xx_l3_main_1_hwmod, | |
3165 | .clk = "l3_div_ck", | |
3166 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3167 | }; | |
3168 | ||
3169 | /* dss -> l3_main_1 */ | |
3170 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3171 | .master = &omap44xx_dss_hwmod, | |
3172 | .slave = &omap44xx_l3_main_1_hwmod, | |
3173 | .clk = "l3_div_ck", | |
3174 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3175 | }; | |
3176 | ||
3177 | /* l3_main_2 -> l3_main_1 */ | |
3178 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3179 | .master = &omap44xx_l3_main_2_hwmod, | |
3180 | .slave = &omap44xx_l3_main_1_hwmod, | |
3181 | .clk = "l3_div_ck", | |
3182 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3183 | }; | |
3184 | ||
3185 | /* l4_cfg -> l3_main_1 */ | |
3186 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3187 | .master = &omap44xx_l4_cfg_hwmod, | |
3188 | .slave = &omap44xx_l3_main_1_hwmod, | |
3189 | .clk = "l4_div_ck", | |
3190 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3191 | }; | |
3192 | ||
3193 | /* mmc1 -> l3_main_1 */ | |
3194 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3195 | .master = &omap44xx_mmc1_hwmod, | |
3196 | .slave = &omap44xx_l3_main_1_hwmod, | |
3197 | .clk = "l3_div_ck", | |
3198 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3199 | }; | |
3200 | ||
3201 | /* mmc2 -> l3_main_1 */ | |
3202 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3203 | .master = &omap44xx_mmc2_hwmod, | |
3204 | .slave = &omap44xx_l3_main_1_hwmod, | |
3205 | .clk = "l3_div_ck", | |
3206 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3207 | }; | |
3208 | ||
844a3b63 PW |
3209 | /* mpu -> l3_main_1 */ |
3210 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3211 | .master = &omap44xx_mpu_hwmod, | |
3212 | .slave = &omap44xx_l3_main_1_hwmod, | |
3213 | .clk = "l3_div_ck", | |
844a3b63 PW |
3214 | .user = OCP_USER_MPU, |
3215 | }; | |
3216 | ||
96566043 BC |
3217 | /* debugss -> l3_main_2 */ |
3218 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
3219 | .master = &omap44xx_debugss_hwmod, | |
3220 | .slave = &omap44xx_l3_main_2_hwmod, | |
3221 | .clk = "dbgclk_mux_ck", | |
3222 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3223 | }; | |
3224 | ||
844a3b63 PW |
3225 | /* dma_system -> l3_main_2 */ |
3226 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3227 | .master = &omap44xx_dma_system_hwmod, | |
3228 | .slave = &omap44xx_l3_main_2_hwmod, | |
3229 | .clk = "l3_div_ck", | |
3230 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3231 | }; | |
3232 | ||
b050f688 ML |
3233 | /* fdif -> l3_main_2 */ |
3234 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3235 | .master = &omap44xx_fdif_hwmod, | |
3236 | .slave = &omap44xx_l3_main_2_hwmod, | |
3237 | .clk = "l3_div_ck", | |
3238 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3239 | }; | |
3240 | ||
9def390e PW |
3241 | /* gpu -> l3_main_2 */ |
3242 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3243 | .master = &omap44xx_gpu_hwmod, | |
3244 | .slave = &omap44xx_l3_main_2_hwmod, | |
3245 | .clk = "l3_div_ck", | |
3246 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3247 | }; | |
3248 | ||
844a3b63 PW |
3249 | /* hsi -> l3_main_2 */ |
3250 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3251 | .master = &omap44xx_hsi_hwmod, | |
3252 | .slave = &omap44xx_l3_main_2_hwmod, | |
3253 | .clk = "l3_div_ck", | |
3254 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3255 | }; | |
3256 | ||
3257 | /* ipu -> l3_main_2 */ | |
3258 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3259 | .master = &omap44xx_ipu_hwmod, | |
3260 | .slave = &omap44xx_l3_main_2_hwmod, | |
3261 | .clk = "l3_div_ck", | |
3262 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3263 | }; | |
3264 | ||
3265 | /* iss -> l3_main_2 */ | |
3266 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3267 | .master = &omap44xx_iss_hwmod, | |
3268 | .slave = &omap44xx_l3_main_2_hwmod, | |
3269 | .clk = "l3_div_ck", | |
3270 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3271 | }; | |
3272 | ||
3273 | /* iva -> l3_main_2 */ | |
3274 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3275 | .master = &omap44xx_iva_hwmod, | |
3276 | .slave = &omap44xx_l3_main_2_hwmod, | |
3277 | .clk = "l3_div_ck", | |
3278 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3279 | }; | |
3280 | ||
844a3b63 PW |
3281 | /* l3_main_1 -> l3_main_2 */ |
3282 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3283 | .master = &omap44xx_l3_main_1_hwmod, | |
3284 | .slave = &omap44xx_l3_main_2_hwmod, | |
3285 | .clk = "l3_div_ck", | |
844a3b63 PW |
3286 | .user = OCP_USER_MPU, |
3287 | }; | |
3288 | ||
3289 | /* l4_cfg -> l3_main_2 */ | |
3290 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3291 | .master = &omap44xx_l4_cfg_hwmod, | |
3292 | .slave = &omap44xx_l3_main_2_hwmod, | |
3293 | .clk = "l4_div_ck", | |
3294 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3295 | }; | |
3296 | ||
0c668875 | 3297 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 3298 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
3299 | .master = &omap44xx_usb_host_fs_hwmod, |
3300 | .slave = &omap44xx_l3_main_2_hwmod, | |
3301 | .clk = "l3_div_ck", | |
3302 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3303 | }; | |
3304 | ||
844a3b63 PW |
3305 | /* usb_host_hs -> l3_main_2 */ |
3306 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3307 | .master = &omap44xx_usb_host_hs_hwmod, | |
3308 | .slave = &omap44xx_l3_main_2_hwmod, | |
3309 | .clk = "l3_div_ck", | |
3310 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3311 | }; | |
3312 | ||
3313 | /* usb_otg_hs -> l3_main_2 */ | |
3314 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3315 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3316 | .slave = &omap44xx_l3_main_2_hwmod, | |
3317 | .clk = "l3_div_ck", | |
3318 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3319 | }; | |
3320 | ||
844a3b63 PW |
3321 | /* l3_main_1 -> l3_main_3 */ |
3322 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3323 | .master = &omap44xx_l3_main_1_hwmod, | |
3324 | .slave = &omap44xx_l3_main_3_hwmod, | |
3325 | .clk = "l3_div_ck", | |
844a3b63 PW |
3326 | .user = OCP_USER_MPU, |
3327 | }; | |
3328 | ||
3329 | /* l3_main_2 -> l3_main_3 */ | |
3330 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3331 | .master = &omap44xx_l3_main_2_hwmod, | |
3332 | .slave = &omap44xx_l3_main_3_hwmod, | |
3333 | .clk = "l3_div_ck", | |
3334 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3335 | }; | |
3336 | ||
3337 | /* l4_cfg -> l3_main_3 */ | |
3338 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3339 | .master = &omap44xx_l4_cfg_hwmod, | |
3340 | .slave = &omap44xx_l3_main_3_hwmod, | |
3341 | .clk = "l4_div_ck", | |
3342 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3343 | }; | |
3344 | ||
3345 | /* aess -> l4_abe */ | |
b0a70cc8 | 3346 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
3347 | .master = &omap44xx_aess_hwmod, |
3348 | .slave = &omap44xx_l4_abe_hwmod, | |
3349 | .clk = "ocp_abe_iclk", | |
3350 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3351 | }; | |
3352 | ||
3353 | /* dsp -> l4_abe */ | |
3354 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3355 | .master = &omap44xx_dsp_hwmod, | |
3356 | .slave = &omap44xx_l4_abe_hwmod, | |
3357 | .clk = "ocp_abe_iclk", | |
3358 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3359 | }; | |
3360 | ||
3361 | /* l3_main_1 -> l4_abe */ | |
3362 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3363 | .master = &omap44xx_l3_main_1_hwmod, | |
3364 | .slave = &omap44xx_l4_abe_hwmod, | |
3365 | .clk = "l3_div_ck", | |
3366 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3367 | }; | |
3368 | ||
3369 | /* mpu -> l4_abe */ | |
3370 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3371 | .master = &omap44xx_mpu_hwmod, | |
3372 | .slave = &omap44xx_l4_abe_hwmod, | |
3373 | .clk = "ocp_abe_iclk", | |
3374 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3375 | }; | |
3376 | ||
3377 | /* l3_main_1 -> l4_cfg */ | |
3378 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3379 | .master = &omap44xx_l3_main_1_hwmod, | |
3380 | .slave = &omap44xx_l4_cfg_hwmod, | |
3381 | .clk = "l3_div_ck", | |
3382 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3383 | }; | |
3384 | ||
3385 | /* l3_main_2 -> l4_per */ | |
3386 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3387 | .master = &omap44xx_l3_main_2_hwmod, | |
3388 | .slave = &omap44xx_l4_per_hwmod, | |
3389 | .clk = "l3_div_ck", | |
3390 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3391 | }; | |
3392 | ||
3393 | /* l4_cfg -> l4_wkup */ | |
3394 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3395 | .master = &omap44xx_l4_cfg_hwmod, | |
3396 | .slave = &omap44xx_l4_wkup_hwmod, | |
3397 | .clk = "l4_div_ck", | |
3398 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3399 | }; | |
3400 | ||
3401 | /* mpu -> mpu_private */ | |
3402 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3403 | .master = &omap44xx_mpu_hwmod, | |
3404 | .slave = &omap44xx_mpu_private_hwmod, | |
3405 | .clk = "l3_div_ck", | |
3406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3407 | }; | |
3408 | ||
9a817bc8 BC |
3409 | /* l4_cfg -> ocp_wp_noc */ |
3410 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
3411 | .master = &omap44xx_l4_cfg_hwmod, | |
3412 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
3413 | .clk = "l4_div_ck", | |
9a817bc8 BC |
3414 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3415 | }; | |
3416 | ||
844a3b63 PW |
3417 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
3418 | { | |
9f0c5996 SG |
3419 | .name = "dmem", |
3420 | .pa_start = 0x40180000, | |
3421 | .pa_end = 0x4018ffff | |
3422 | }, | |
3423 | { | |
3424 | .name = "cmem", | |
3425 | .pa_start = 0x401a0000, | |
3426 | .pa_end = 0x401a1fff | |
3427 | }, | |
3428 | { | |
3429 | .name = "smem", | |
3430 | .pa_start = 0x401c0000, | |
3431 | .pa_end = 0x401c5fff | |
3432 | }, | |
3433 | { | |
3434 | .name = "pmem", | |
3435 | .pa_start = 0x401e0000, | |
3436 | .pa_end = 0x401e1fff | |
3437 | }, | |
3438 | { | |
3439 | .name = "mpu", | |
844a3b63 PW |
3440 | .pa_start = 0x401f1000, |
3441 | .pa_end = 0x401f13ff, | |
3442 | .flags = ADDR_TYPE_RT | |
3443 | }, | |
3444 | { } | |
3445 | }; | |
3446 | ||
3447 | /* l4_abe -> aess */ | |
b0a70cc8 | 3448 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
3449 | .master = &omap44xx_l4_abe_hwmod, |
3450 | .slave = &omap44xx_aess_hwmod, | |
3451 | .clk = "ocp_abe_iclk", | |
3452 | .addr = omap44xx_aess_addrs, | |
3453 | .user = OCP_USER_MPU, | |
3454 | }; | |
3455 | ||
3456 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
3457 | { | |
9f0c5996 SG |
3458 | .name = "dmem_dma", |
3459 | .pa_start = 0x49080000, | |
3460 | .pa_end = 0x4908ffff | |
3461 | }, | |
3462 | { | |
3463 | .name = "cmem_dma", | |
3464 | .pa_start = 0x490a0000, | |
3465 | .pa_end = 0x490a1fff | |
3466 | }, | |
3467 | { | |
3468 | .name = "smem_dma", | |
3469 | .pa_start = 0x490c0000, | |
3470 | .pa_end = 0x490c5fff | |
3471 | }, | |
3472 | { | |
3473 | .name = "pmem_dma", | |
3474 | .pa_start = 0x490e0000, | |
3475 | .pa_end = 0x490e1fff | |
3476 | }, | |
3477 | { | |
3478 | .name = "dma", | |
844a3b63 PW |
3479 | .pa_start = 0x490f1000, |
3480 | .pa_end = 0x490f13ff, | |
3481 | .flags = ADDR_TYPE_RT | |
3482 | }, | |
3483 | { } | |
3484 | }; | |
3485 | ||
3486 | /* l4_abe -> aess (dma) */ | |
b0a70cc8 | 3487 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
3488 | .master = &omap44xx_l4_abe_hwmod, |
3489 | .slave = &omap44xx_aess_hwmod, | |
3490 | .clk = "ocp_abe_iclk", | |
3491 | .addr = omap44xx_aess_dma_addrs, | |
3492 | .user = OCP_USER_SDMA, | |
3493 | }; | |
3494 | ||
42b9e387 PW |
3495 | /* l3_main_2 -> c2c */ |
3496 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
3497 | .master = &omap44xx_l3_main_2_hwmod, | |
3498 | .slave = &omap44xx_c2c_hwmod, | |
3499 | .clk = "l3_div_ck", | |
3500 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3501 | }; | |
3502 | ||
844a3b63 PW |
3503 | /* l4_wkup -> counter_32k */ |
3504 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
3505 | .master = &omap44xx_l4_wkup_hwmod, | |
3506 | .slave = &omap44xx_counter_32k_hwmod, | |
3507 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3508 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3509 | }; | |
3510 | ||
a0b5d813 PW |
3511 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
3512 | { | |
3513 | .pa_start = 0x4a002000, | |
3514 | .pa_end = 0x4a0027ff, | |
3515 | .flags = ADDR_TYPE_RT | |
3516 | }, | |
3517 | { } | |
3518 | }; | |
3519 | ||
3520 | /* l4_cfg -> ctrl_module_core */ | |
3521 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
3522 | .master = &omap44xx_l4_cfg_hwmod, | |
3523 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
3524 | .clk = "l4_div_ck", | |
3525 | .addr = omap44xx_ctrl_module_core_addrs, | |
3526 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3527 | }; | |
3528 | ||
3529 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
3530 | { | |
3531 | .pa_start = 0x4a100000, | |
3532 | .pa_end = 0x4a1007ff, | |
3533 | .flags = ADDR_TYPE_RT | |
3534 | }, | |
3535 | { } | |
3536 | }; | |
3537 | ||
3538 | /* l4_cfg -> ctrl_module_pad_core */ | |
3539 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
3540 | .master = &omap44xx_l4_cfg_hwmod, | |
3541 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
3542 | .clk = "l4_div_ck", | |
3543 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
3544 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3545 | }; | |
3546 | ||
3547 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
3548 | { | |
3549 | .pa_start = 0x4a30c000, | |
3550 | .pa_end = 0x4a30c7ff, | |
3551 | .flags = ADDR_TYPE_RT | |
3552 | }, | |
3553 | { } | |
3554 | }; | |
3555 | ||
3556 | /* l4_wkup -> ctrl_module_wkup */ | |
3557 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
3558 | .master = &omap44xx_l4_wkup_hwmod, | |
3559 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
3560 | .clk = "l4_wkup_clk_mux_ck", | |
3561 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
3562 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3563 | }; | |
3564 | ||
3565 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
3566 | { | |
3567 | .pa_start = 0x4a31e000, | |
3568 | .pa_end = 0x4a31e7ff, | |
3569 | .flags = ADDR_TYPE_RT | |
3570 | }, | |
3571 | { } | |
3572 | }; | |
3573 | ||
3574 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
3575 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
3576 | .master = &omap44xx_l4_wkup_hwmod, | |
3577 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
3578 | .clk = "l4_wkup_clk_mux_ck", | |
3579 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
3580 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3581 | }; | |
3582 | ||
96566043 BC |
3583 | /* l3_instr -> debugss */ |
3584 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
3585 | .master = &omap44xx_l3_instr_hwmod, | |
3586 | .slave = &omap44xx_debugss_hwmod, | |
3587 | .clk = "l3_div_ck", | |
96566043 BC |
3588 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3589 | }; | |
3590 | ||
844a3b63 PW |
3591 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
3592 | { | |
3593 | .pa_start = 0x4a056000, | |
3594 | .pa_end = 0x4a056fff, | |
3595 | .flags = ADDR_TYPE_RT | |
3596 | }, | |
3597 | { } | |
3598 | }; | |
3599 | ||
3600 | /* l4_cfg -> dma_system */ | |
3601 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
3602 | .master = &omap44xx_l4_cfg_hwmod, | |
3603 | .slave = &omap44xx_dma_system_hwmod, | |
3604 | .clk = "l4_div_ck", | |
3605 | .addr = omap44xx_dma_system_addrs, | |
3606 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3607 | }; | |
3608 | ||
844a3b63 PW |
3609 | /* l4_abe -> dmic */ |
3610 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
3611 | .master = &omap44xx_l4_abe_hwmod, | |
3612 | .slave = &omap44xx_dmic_hwmod, | |
3613 | .clk = "ocp_abe_iclk", | |
e3491795 | 3614 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3615 | }; |
3616 | ||
3617 | /* dsp -> iva */ | |
3618 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
3619 | .master = &omap44xx_dsp_hwmod, | |
3620 | .slave = &omap44xx_iva_hwmod, | |
3621 | .clk = "dpll_iva_m5x2_ck", | |
3622 | .user = OCP_USER_DSP, | |
3623 | }; | |
3624 | ||
42b9e387 | 3625 | /* dsp -> sl2if */ |
b360124e | 3626 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
42b9e387 PW |
3627 | .master = &omap44xx_dsp_hwmod, |
3628 | .slave = &omap44xx_sl2if_hwmod, | |
3629 | .clk = "dpll_iva_m5x2_ck", | |
3630 | .user = OCP_USER_DSP, | |
3631 | }; | |
3632 | ||
844a3b63 PW |
3633 | /* l4_cfg -> dsp */ |
3634 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
3635 | .master = &omap44xx_l4_cfg_hwmod, | |
3636 | .slave = &omap44xx_dsp_hwmod, | |
3637 | .clk = "l4_div_ck", | |
3638 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3639 | }; | |
3640 | ||
3641 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
3642 | { | |
3643 | .pa_start = 0x58000000, | |
3644 | .pa_end = 0x5800007f, | |
3645 | .flags = ADDR_TYPE_RT | |
3646 | }, | |
3647 | { } | |
3648 | }; | |
3649 | ||
3650 | /* l3_main_2 -> dss */ | |
3651 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
3652 | .master = &omap44xx_l3_main_2_hwmod, | |
3653 | .slave = &omap44xx_dss_hwmod, | |
7ede8561 | 3654 | .clk = "l3_div_ck", |
844a3b63 PW |
3655 | .addr = omap44xx_dss_dma_addrs, |
3656 | .user = OCP_USER_SDMA, | |
3657 | }; | |
3658 | ||
3659 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
3660 | { | |
3661 | .pa_start = 0x48040000, | |
3662 | .pa_end = 0x4804007f, | |
3663 | .flags = ADDR_TYPE_RT | |
3664 | }, | |
3665 | { } | |
3666 | }; | |
3667 | ||
3668 | /* l4_per -> dss */ | |
3669 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
3670 | .master = &omap44xx_l4_per_hwmod, | |
3671 | .slave = &omap44xx_dss_hwmod, | |
3672 | .clk = "l4_div_ck", | |
3673 | .addr = omap44xx_dss_addrs, | |
3674 | .user = OCP_USER_MPU, | |
3675 | }; | |
3676 | ||
3677 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
3678 | { | |
3679 | .pa_start = 0x58001000, | |
3680 | .pa_end = 0x58001fff, | |
3681 | .flags = ADDR_TYPE_RT | |
3682 | }, | |
3683 | { } | |
3684 | }; | |
3685 | ||
3686 | /* l3_main_2 -> dss_dispc */ | |
3687 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
3688 | .master = &omap44xx_l3_main_2_hwmod, | |
3689 | .slave = &omap44xx_dss_dispc_hwmod, | |
7ede8561 | 3690 | .clk = "l3_div_ck", |
844a3b63 PW |
3691 | .addr = omap44xx_dss_dispc_dma_addrs, |
3692 | .user = OCP_USER_SDMA, | |
3693 | }; | |
3694 | ||
3695 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
3696 | { | |
3697 | .pa_start = 0x48041000, | |
3698 | .pa_end = 0x48041fff, | |
3699 | .flags = ADDR_TYPE_RT | |
3700 | }, | |
3701 | { } | |
3702 | }; | |
3703 | ||
3704 | /* l4_per -> dss_dispc */ | |
3705 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
3706 | .master = &omap44xx_l4_per_hwmod, | |
3707 | .slave = &omap44xx_dss_dispc_hwmod, | |
3708 | .clk = "l4_div_ck", | |
3709 | .addr = omap44xx_dss_dispc_addrs, | |
3710 | .user = OCP_USER_MPU, | |
3711 | }; | |
3712 | ||
3713 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
3714 | { | |
3715 | .pa_start = 0x58004000, | |
3716 | .pa_end = 0x580041ff, | |
3717 | .flags = ADDR_TYPE_RT | |
3718 | }, | |
3719 | { } | |
3720 | }; | |
3721 | ||
3722 | /* l3_main_2 -> dss_dsi1 */ | |
3723 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
3724 | .master = &omap44xx_l3_main_2_hwmod, | |
3725 | .slave = &omap44xx_dss_dsi1_hwmod, | |
7ede8561 | 3726 | .clk = "l3_div_ck", |
844a3b63 PW |
3727 | .addr = omap44xx_dss_dsi1_dma_addrs, |
3728 | .user = OCP_USER_SDMA, | |
3729 | }; | |
3730 | ||
3731 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
3732 | { | |
3733 | .pa_start = 0x48044000, | |
3734 | .pa_end = 0x480441ff, | |
3735 | .flags = ADDR_TYPE_RT | |
3736 | }, | |
3737 | { } | |
3738 | }; | |
3739 | ||
3740 | /* l4_per -> dss_dsi1 */ | |
3741 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
3742 | .master = &omap44xx_l4_per_hwmod, | |
3743 | .slave = &omap44xx_dss_dsi1_hwmod, | |
3744 | .clk = "l4_div_ck", | |
3745 | .addr = omap44xx_dss_dsi1_addrs, | |
3746 | .user = OCP_USER_MPU, | |
3747 | }; | |
3748 | ||
3749 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
3750 | { | |
3751 | .pa_start = 0x58005000, | |
3752 | .pa_end = 0x580051ff, | |
3753 | .flags = ADDR_TYPE_RT | |
3754 | }, | |
3755 | { } | |
3756 | }; | |
3757 | ||
3758 | /* l3_main_2 -> dss_dsi2 */ | |
3759 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
3760 | .master = &omap44xx_l3_main_2_hwmod, | |
3761 | .slave = &omap44xx_dss_dsi2_hwmod, | |
7ede8561 | 3762 | .clk = "l3_div_ck", |
844a3b63 PW |
3763 | .addr = omap44xx_dss_dsi2_dma_addrs, |
3764 | .user = OCP_USER_SDMA, | |
3765 | }; | |
3766 | ||
3767 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
3768 | { | |
3769 | .pa_start = 0x48045000, | |
3770 | .pa_end = 0x480451ff, | |
3771 | .flags = ADDR_TYPE_RT | |
3772 | }, | |
3773 | { } | |
3774 | }; | |
3775 | ||
3776 | /* l4_per -> dss_dsi2 */ | |
3777 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
3778 | .master = &omap44xx_l4_per_hwmod, | |
3779 | .slave = &omap44xx_dss_dsi2_hwmod, | |
3780 | .clk = "l4_div_ck", | |
3781 | .addr = omap44xx_dss_dsi2_addrs, | |
3782 | .user = OCP_USER_MPU, | |
3783 | }; | |
3784 | ||
3785 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
3786 | { | |
3787 | .pa_start = 0x58006000, | |
3788 | .pa_end = 0x58006fff, | |
3789 | .flags = ADDR_TYPE_RT | |
3790 | }, | |
3791 | { } | |
3792 | }; | |
3793 | ||
3794 | /* l3_main_2 -> dss_hdmi */ | |
3795 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
3796 | .master = &omap44xx_l3_main_2_hwmod, | |
3797 | .slave = &omap44xx_dss_hdmi_hwmod, | |
7ede8561 | 3798 | .clk = "l3_div_ck", |
844a3b63 PW |
3799 | .addr = omap44xx_dss_hdmi_dma_addrs, |
3800 | .user = OCP_USER_SDMA, | |
3801 | }; | |
3802 | ||
3803 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
3804 | { | |
3805 | .pa_start = 0x48046000, | |
3806 | .pa_end = 0x48046fff, | |
3807 | .flags = ADDR_TYPE_RT | |
3808 | }, | |
3809 | { } | |
3810 | }; | |
3811 | ||
3812 | /* l4_per -> dss_hdmi */ | |
3813 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
3814 | .master = &omap44xx_l4_per_hwmod, | |
3815 | .slave = &omap44xx_dss_hdmi_hwmod, | |
3816 | .clk = "l4_div_ck", | |
3817 | .addr = omap44xx_dss_hdmi_addrs, | |
3818 | .user = OCP_USER_MPU, | |
3819 | }; | |
3820 | ||
3821 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
3822 | { | |
3823 | .pa_start = 0x58002000, | |
3824 | .pa_end = 0x580020ff, | |
3825 | .flags = ADDR_TYPE_RT | |
3826 | }, | |
3827 | { } | |
3828 | }; | |
3829 | ||
3830 | /* l3_main_2 -> dss_rfbi */ | |
3831 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
3832 | .master = &omap44xx_l3_main_2_hwmod, | |
3833 | .slave = &omap44xx_dss_rfbi_hwmod, | |
7ede8561 | 3834 | .clk = "l3_div_ck", |
844a3b63 PW |
3835 | .addr = omap44xx_dss_rfbi_dma_addrs, |
3836 | .user = OCP_USER_SDMA, | |
3837 | }; | |
3838 | ||
3839 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
3840 | { | |
3841 | .pa_start = 0x48042000, | |
3842 | .pa_end = 0x480420ff, | |
3843 | .flags = ADDR_TYPE_RT | |
3844 | }, | |
3845 | { } | |
3846 | }; | |
3847 | ||
3848 | /* l4_per -> dss_rfbi */ | |
3849 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
3850 | .master = &omap44xx_l4_per_hwmod, | |
3851 | .slave = &omap44xx_dss_rfbi_hwmod, | |
3852 | .clk = "l4_div_ck", | |
3853 | .addr = omap44xx_dss_rfbi_addrs, | |
3854 | .user = OCP_USER_MPU, | |
3855 | }; | |
3856 | ||
3857 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
3858 | { | |
3859 | .pa_start = 0x58003000, | |
3860 | .pa_end = 0x580030ff, | |
3861 | .flags = ADDR_TYPE_RT | |
3862 | }, | |
3863 | { } | |
3864 | }; | |
3865 | ||
3866 | /* l3_main_2 -> dss_venc */ | |
3867 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
3868 | .master = &omap44xx_l3_main_2_hwmod, | |
3869 | .slave = &omap44xx_dss_venc_hwmod, | |
7ede8561 | 3870 | .clk = "l3_div_ck", |
844a3b63 PW |
3871 | .addr = omap44xx_dss_venc_dma_addrs, |
3872 | .user = OCP_USER_SDMA, | |
3873 | }; | |
3874 | ||
3875 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
3876 | { | |
3877 | .pa_start = 0x48043000, | |
3878 | .pa_end = 0x480430ff, | |
3879 | .flags = ADDR_TYPE_RT | |
3880 | }, | |
3881 | { } | |
3882 | }; | |
3883 | ||
3884 | /* l4_per -> dss_venc */ | |
3885 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
3886 | .master = &omap44xx_l4_per_hwmod, | |
3887 | .slave = &omap44xx_dss_venc_hwmod, | |
3888 | .clk = "l4_div_ck", | |
3889 | .addr = omap44xx_dss_venc_addrs, | |
3890 | .user = OCP_USER_MPU, | |
3891 | }; | |
3892 | ||
42b9e387 PW |
3893 | /* l4_per -> elm */ |
3894 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
3895 | .master = &omap44xx_l4_per_hwmod, | |
3896 | .slave = &omap44xx_elm_hwmod, | |
3897 | .clk = "l4_div_ck", | |
42b9e387 PW |
3898 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3899 | }; | |
3900 | ||
b050f688 ML |
3901 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
3902 | { | |
3903 | .pa_start = 0x4a10a000, | |
3904 | .pa_end = 0x4a10a1ff, | |
3905 | .flags = ADDR_TYPE_RT | |
3906 | }, | |
3907 | { } | |
3908 | }; | |
3909 | ||
3910 | /* l4_cfg -> fdif */ | |
3911 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
3912 | .master = &omap44xx_l4_cfg_hwmod, | |
3913 | .slave = &omap44xx_fdif_hwmod, | |
3914 | .clk = "l4_div_ck", | |
3915 | .addr = omap44xx_fdif_addrs, | |
3916 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3917 | }; | |
3918 | ||
844a3b63 PW |
3919 | /* l4_wkup -> gpio1 */ |
3920 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
3921 | .master = &omap44xx_l4_wkup_hwmod, | |
3922 | .slave = &omap44xx_gpio1_hwmod, | |
3923 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3924 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3925 | }; | |
3926 | ||
844a3b63 PW |
3927 | /* l4_per -> gpio2 */ |
3928 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
3929 | .master = &omap44xx_l4_per_hwmod, | |
3930 | .slave = &omap44xx_gpio2_hwmod, | |
3931 | .clk = "l4_div_ck", | |
844a3b63 PW |
3932 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3933 | }; | |
3934 | ||
844a3b63 PW |
3935 | /* l4_per -> gpio3 */ |
3936 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
3937 | .master = &omap44xx_l4_per_hwmod, | |
3938 | .slave = &omap44xx_gpio3_hwmod, | |
3939 | .clk = "l4_div_ck", | |
844a3b63 PW |
3940 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3941 | }; | |
3942 | ||
844a3b63 PW |
3943 | /* l4_per -> gpio4 */ |
3944 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
3945 | .master = &omap44xx_l4_per_hwmod, | |
3946 | .slave = &omap44xx_gpio4_hwmod, | |
3947 | .clk = "l4_div_ck", | |
844a3b63 PW |
3948 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3949 | }; | |
3950 | ||
844a3b63 PW |
3951 | /* l4_per -> gpio5 */ |
3952 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
3953 | .master = &omap44xx_l4_per_hwmod, | |
3954 | .slave = &omap44xx_gpio5_hwmod, | |
3955 | .clk = "l4_div_ck", | |
844a3b63 PW |
3956 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3957 | }; | |
3958 | ||
844a3b63 PW |
3959 | /* l4_per -> gpio6 */ |
3960 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
3961 | .master = &omap44xx_l4_per_hwmod, | |
3962 | .slave = &omap44xx_gpio6_hwmod, | |
3963 | .clk = "l4_div_ck", | |
844a3b63 PW |
3964 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3965 | }; | |
3966 | ||
eb42b5d3 BC |
3967 | /* l3_main_2 -> gpmc */ |
3968 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
3969 | .master = &omap44xx_l3_main_2_hwmod, | |
3970 | .slave = &omap44xx_gpmc_hwmod, | |
3971 | .clk = "l3_div_ck", | |
eb42b5d3 BC |
3972 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3973 | }; | |
3974 | ||
9def390e PW |
3975 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
3976 | { | |
3977 | .pa_start = 0x56000000, | |
3978 | .pa_end = 0x5600ffff, | |
3979 | .flags = ADDR_TYPE_RT | |
3980 | }, | |
3981 | { } | |
3982 | }; | |
3983 | ||
3984 | /* l3_main_2 -> gpu */ | |
3985 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
3986 | .master = &omap44xx_l3_main_2_hwmod, | |
3987 | .slave = &omap44xx_gpu_hwmod, | |
3988 | .clk = "l3_div_ck", | |
3989 | .addr = omap44xx_gpu_addrs, | |
3990 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3991 | }; | |
3992 | ||
a091c08e PW |
3993 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
3994 | { | |
3995 | .pa_start = 0x480b2000, | |
3996 | .pa_end = 0x480b201f, | |
3997 | .flags = ADDR_TYPE_RT | |
3998 | }, | |
3999 | { } | |
4000 | }; | |
4001 | ||
4002 | /* l4_per -> hdq1w */ | |
4003 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4004 | .master = &omap44xx_l4_per_hwmod, | |
4005 | .slave = &omap44xx_hdq1w_hwmod, | |
4006 | .clk = "l4_div_ck", | |
4007 | .addr = omap44xx_hdq1w_addrs, | |
4008 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4009 | }; | |
4010 | ||
844a3b63 PW |
4011 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4012 | { | |
4013 | .pa_start = 0x4a058000, | |
4014 | .pa_end = 0x4a05bfff, | |
4015 | .flags = ADDR_TYPE_RT | |
4016 | }, | |
4017 | { } | |
4018 | }; | |
4019 | ||
4020 | /* l4_cfg -> hsi */ | |
4021 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4022 | .master = &omap44xx_l4_cfg_hwmod, | |
4023 | .slave = &omap44xx_hsi_hwmod, | |
4024 | .clk = "l4_div_ck", | |
4025 | .addr = omap44xx_hsi_addrs, | |
4026 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4027 | }; | |
4028 | ||
844a3b63 PW |
4029 | /* l4_per -> i2c1 */ |
4030 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4031 | .master = &omap44xx_l4_per_hwmod, | |
4032 | .slave = &omap44xx_i2c1_hwmod, | |
4033 | .clk = "l4_div_ck", | |
844a3b63 PW |
4034 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4035 | }; | |
4036 | ||
844a3b63 PW |
4037 | /* l4_per -> i2c2 */ |
4038 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4039 | .master = &omap44xx_l4_per_hwmod, | |
4040 | .slave = &omap44xx_i2c2_hwmod, | |
4041 | .clk = "l4_div_ck", | |
844a3b63 PW |
4042 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4043 | }; | |
4044 | ||
844a3b63 PW |
4045 | /* l4_per -> i2c3 */ |
4046 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4047 | .master = &omap44xx_l4_per_hwmod, | |
4048 | .slave = &omap44xx_i2c3_hwmod, | |
4049 | .clk = "l4_div_ck", | |
844a3b63 PW |
4050 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4051 | }; | |
4052 | ||
844a3b63 PW |
4053 | /* l4_per -> i2c4 */ |
4054 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4055 | .master = &omap44xx_l4_per_hwmod, | |
4056 | .slave = &omap44xx_i2c4_hwmod, | |
4057 | .clk = "l4_div_ck", | |
844a3b63 PW |
4058 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4059 | }; | |
4060 | ||
4061 | /* l3_main_2 -> ipu */ | |
4062 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4063 | .master = &omap44xx_l3_main_2_hwmod, | |
4064 | .slave = &omap44xx_ipu_hwmod, | |
4065 | .clk = "l3_div_ck", | |
4066 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4067 | }; | |
4068 | ||
4069 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
4070 | { | |
4071 | .pa_start = 0x52000000, | |
4072 | .pa_end = 0x520000ff, | |
4073 | .flags = ADDR_TYPE_RT | |
4074 | }, | |
4075 | { } | |
4076 | }; | |
4077 | ||
4078 | /* l3_main_2 -> iss */ | |
4079 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
4080 | .master = &omap44xx_l3_main_2_hwmod, | |
4081 | .slave = &omap44xx_iss_hwmod, | |
4082 | .clk = "l3_div_ck", | |
4083 | .addr = omap44xx_iss_addrs, | |
4084 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4085 | }; | |
4086 | ||
42b9e387 | 4087 | /* iva -> sl2if */ |
b360124e | 4088 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
42b9e387 PW |
4089 | .master = &omap44xx_iva_hwmod, |
4090 | .slave = &omap44xx_sl2if_hwmod, | |
4091 | .clk = "dpll_iva_m5x2_ck", | |
4092 | .user = OCP_USER_IVA, | |
4093 | }; | |
4094 | ||
844a3b63 PW |
4095 | /* l3_main_2 -> iva */ |
4096 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
4097 | .master = &omap44xx_l3_main_2_hwmod, | |
4098 | .slave = &omap44xx_iva_hwmod, | |
4099 | .clk = "l3_div_ck", | |
844a3b63 PW |
4100 | .user = OCP_USER_MPU, |
4101 | }; | |
4102 | ||
844a3b63 PW |
4103 | /* l4_wkup -> kbd */ |
4104 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
4105 | .master = &omap44xx_l4_wkup_hwmod, | |
4106 | .slave = &omap44xx_kbd_hwmod, | |
4107 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4108 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4109 | }; | |
4110 | ||
844a3b63 PW |
4111 | /* l4_cfg -> mailbox */ |
4112 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4113 | .master = &omap44xx_l4_cfg_hwmod, | |
4114 | .slave = &omap44xx_mailbox_hwmod, | |
4115 | .clk = "l4_div_ck", | |
844a3b63 PW |
4116 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4117 | }; | |
4118 | ||
896d4e98 BC |
4119 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
4120 | { | |
4121 | .pa_start = 0x40128000, | |
4122 | .pa_end = 0x401283ff, | |
4123 | .flags = ADDR_TYPE_RT | |
4124 | }, | |
4125 | { } | |
4126 | }; | |
4127 | ||
4128 | /* l4_abe -> mcasp */ | |
4129 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
4130 | .master = &omap44xx_l4_abe_hwmod, | |
4131 | .slave = &omap44xx_mcasp_hwmod, | |
4132 | .clk = "ocp_abe_iclk", | |
4133 | .addr = omap44xx_mcasp_addrs, | |
4134 | .user = OCP_USER_MPU, | |
4135 | }; | |
4136 | ||
4137 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
4138 | { | |
4139 | .pa_start = 0x49028000, | |
4140 | .pa_end = 0x490283ff, | |
4141 | .flags = ADDR_TYPE_RT | |
4142 | }, | |
4143 | { } | |
4144 | }; | |
4145 | ||
4146 | /* l4_abe -> mcasp (dma) */ | |
4147 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
4148 | .master = &omap44xx_l4_abe_hwmod, | |
4149 | .slave = &omap44xx_mcasp_hwmod, | |
4150 | .clk = "ocp_abe_iclk", | |
4151 | .addr = omap44xx_mcasp_dma_addrs, | |
4152 | .user = OCP_USER_SDMA, | |
4153 | }; | |
4154 | ||
844a3b63 PW |
4155 | /* l4_abe -> mcbsp1 */ |
4156 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4157 | .master = &omap44xx_l4_abe_hwmod, | |
4158 | .slave = &omap44xx_mcbsp1_hwmod, | |
4159 | .clk = "ocp_abe_iclk", | |
e3491795 | 4160 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4161 | }; |
4162 | ||
844a3b63 PW |
4163 | /* l4_abe -> mcbsp2 */ |
4164 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4165 | .master = &omap44xx_l4_abe_hwmod, | |
4166 | .slave = &omap44xx_mcbsp2_hwmod, | |
4167 | .clk = "ocp_abe_iclk", | |
e3491795 | 4168 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4169 | }; |
4170 | ||
844a3b63 PW |
4171 | /* l4_abe -> mcbsp3 */ |
4172 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
4173 | .master = &omap44xx_l4_abe_hwmod, | |
4174 | .slave = &omap44xx_mcbsp3_hwmod, | |
4175 | .clk = "ocp_abe_iclk", | |
e3491795 | 4176 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4177 | }; |
4178 | ||
844a3b63 PW |
4179 | /* l4_per -> mcbsp4 */ |
4180 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
4181 | .master = &omap44xx_l4_per_hwmod, | |
4182 | .slave = &omap44xx_mcbsp4_hwmod, | |
4183 | .clk = "l4_div_ck", | |
844a3b63 PW |
4184 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4185 | }; | |
4186 | ||
844a3b63 PW |
4187 | /* l4_abe -> mcpdm */ |
4188 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
4189 | .master = &omap44xx_l4_abe_hwmod, | |
4190 | .slave = &omap44xx_mcpdm_hwmod, | |
4191 | .clk = "ocp_abe_iclk", | |
e3491795 | 4192 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4193 | }; |
4194 | ||
844a3b63 PW |
4195 | /* l4_per -> mcspi1 */ |
4196 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
4197 | .master = &omap44xx_l4_per_hwmod, | |
4198 | .slave = &omap44xx_mcspi1_hwmod, | |
4199 | .clk = "l4_div_ck", | |
844a3b63 PW |
4200 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4201 | }; | |
4202 | ||
844a3b63 PW |
4203 | /* l4_per -> mcspi2 */ |
4204 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
4205 | .master = &omap44xx_l4_per_hwmod, | |
4206 | .slave = &omap44xx_mcspi2_hwmod, | |
4207 | .clk = "l4_div_ck", | |
844a3b63 PW |
4208 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4209 | }; | |
4210 | ||
844a3b63 PW |
4211 | /* l4_per -> mcspi3 */ |
4212 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
4213 | .master = &omap44xx_l4_per_hwmod, | |
4214 | .slave = &omap44xx_mcspi3_hwmod, | |
4215 | .clk = "l4_div_ck", | |
844a3b63 PW |
4216 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4217 | }; | |
4218 | ||
844a3b63 PW |
4219 | /* l4_per -> mcspi4 */ |
4220 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
4221 | .master = &omap44xx_l4_per_hwmod, | |
4222 | .slave = &omap44xx_mcspi4_hwmod, | |
4223 | .clk = "l4_div_ck", | |
844a3b63 PW |
4224 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4225 | }; | |
4226 | ||
844a3b63 PW |
4227 | /* l4_per -> mmc1 */ |
4228 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
4229 | .master = &omap44xx_l4_per_hwmod, | |
4230 | .slave = &omap44xx_mmc1_hwmod, | |
4231 | .clk = "l4_div_ck", | |
844a3b63 PW |
4232 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4233 | }; | |
4234 | ||
844a3b63 PW |
4235 | /* l4_per -> mmc2 */ |
4236 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
4237 | .master = &omap44xx_l4_per_hwmod, | |
4238 | .slave = &omap44xx_mmc2_hwmod, | |
4239 | .clk = "l4_div_ck", | |
844a3b63 PW |
4240 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4241 | }; | |
4242 | ||
844a3b63 PW |
4243 | /* l4_per -> mmc3 */ |
4244 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
4245 | .master = &omap44xx_l4_per_hwmod, | |
4246 | .slave = &omap44xx_mmc3_hwmod, | |
4247 | .clk = "l4_div_ck", | |
844a3b63 PW |
4248 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4249 | }; | |
4250 | ||
844a3b63 PW |
4251 | /* l4_per -> mmc4 */ |
4252 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
4253 | .master = &omap44xx_l4_per_hwmod, | |
4254 | .slave = &omap44xx_mmc4_hwmod, | |
4255 | .clk = "l4_div_ck", | |
844a3b63 PW |
4256 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4257 | }; | |
4258 | ||
844a3b63 PW |
4259 | /* l4_per -> mmc5 */ |
4260 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
4261 | .master = &omap44xx_l4_per_hwmod, | |
4262 | .slave = &omap44xx_mmc5_hwmod, | |
4263 | .clk = "l4_div_ck", | |
844a3b63 PW |
4264 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4265 | }; | |
4266 | ||
e17f18c0 PW |
4267 | /* l3_main_2 -> ocmc_ram */ |
4268 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
4269 | .master = &omap44xx_l3_main_2_hwmod, | |
4270 | .slave = &omap44xx_ocmc_ram_hwmod, | |
4271 | .clk = "l3_div_ck", | |
4272 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4273 | }; | |
4274 | ||
0c668875 BC |
4275 | /* l4_cfg -> ocp2scp_usb_phy */ |
4276 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
4277 | .master = &omap44xx_l4_cfg_hwmod, | |
4278 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
4279 | .clk = "l4_div_ck", | |
4280 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4281 | }; | |
4282 | ||
794b480a PW |
4283 | /* mpu_private -> prcm_mpu */ |
4284 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
4285 | .master = &omap44xx_mpu_private_hwmod, | |
4286 | .slave = &omap44xx_prcm_mpu_hwmod, | |
4287 | .clk = "l3_div_ck", | |
794b480a PW |
4288 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4289 | }; | |
4290 | ||
794b480a PW |
4291 | /* l4_wkup -> cm_core_aon */ |
4292 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
4293 | .master = &omap44xx_l4_wkup_hwmod, | |
4294 | .slave = &omap44xx_cm_core_aon_hwmod, | |
4295 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4296 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4297 | }; | |
4298 | ||
794b480a PW |
4299 | /* l4_cfg -> cm_core */ |
4300 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
4301 | .master = &omap44xx_l4_cfg_hwmod, | |
4302 | .slave = &omap44xx_cm_core_hwmod, | |
4303 | .clk = "l4_div_ck", | |
794b480a PW |
4304 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4305 | }; | |
4306 | ||
794b480a PW |
4307 | /* l4_wkup -> prm */ |
4308 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
4309 | .master = &omap44xx_l4_wkup_hwmod, | |
4310 | .slave = &omap44xx_prm_hwmod, | |
4311 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4312 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4313 | }; | |
4314 | ||
794b480a PW |
4315 | /* l4_wkup -> scrm */ |
4316 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
4317 | .master = &omap44xx_l4_wkup_hwmod, | |
4318 | .slave = &omap44xx_scrm_hwmod, | |
4319 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4320 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4321 | }; | |
4322 | ||
42b9e387 | 4323 | /* l3_main_2 -> sl2if */ |
b360124e | 4324 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
4325 | .master = &omap44xx_l3_main_2_hwmod, |
4326 | .slave = &omap44xx_sl2if_hwmod, | |
4327 | .clk = "l3_div_ck", | |
4328 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4329 | }; | |
4330 | ||
1e3b5e59 BC |
4331 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
4332 | { | |
4333 | .pa_start = 0x4012c000, | |
4334 | .pa_end = 0x4012c3ff, | |
4335 | .flags = ADDR_TYPE_RT | |
4336 | }, | |
4337 | { } | |
4338 | }; | |
4339 | ||
4340 | /* l4_abe -> slimbus1 */ | |
4341 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
4342 | .master = &omap44xx_l4_abe_hwmod, | |
4343 | .slave = &omap44xx_slimbus1_hwmod, | |
4344 | .clk = "ocp_abe_iclk", | |
4345 | .addr = omap44xx_slimbus1_addrs, | |
4346 | .user = OCP_USER_MPU, | |
4347 | }; | |
4348 | ||
4349 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
4350 | { | |
4351 | .pa_start = 0x4902c000, | |
4352 | .pa_end = 0x4902c3ff, | |
4353 | .flags = ADDR_TYPE_RT | |
4354 | }, | |
4355 | { } | |
4356 | }; | |
4357 | ||
4358 | /* l4_abe -> slimbus1 (dma) */ | |
4359 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
4360 | .master = &omap44xx_l4_abe_hwmod, | |
4361 | .slave = &omap44xx_slimbus1_hwmod, | |
4362 | .clk = "ocp_abe_iclk", | |
4363 | .addr = omap44xx_slimbus1_dma_addrs, | |
4364 | .user = OCP_USER_SDMA, | |
4365 | }; | |
4366 | ||
4367 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
4368 | { | |
4369 | .pa_start = 0x48076000, | |
4370 | .pa_end = 0x480763ff, | |
4371 | .flags = ADDR_TYPE_RT | |
4372 | }, | |
4373 | { } | |
4374 | }; | |
4375 | ||
4376 | /* l4_per -> slimbus2 */ | |
4377 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
4378 | .master = &omap44xx_l4_per_hwmod, | |
4379 | .slave = &omap44xx_slimbus2_hwmod, | |
4380 | .clk = "l4_div_ck", | |
4381 | .addr = omap44xx_slimbus2_addrs, | |
4382 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4383 | }; | |
4384 | ||
844a3b63 PW |
4385 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
4386 | { | |
4387 | .pa_start = 0x4a0dd000, | |
4388 | .pa_end = 0x4a0dd03f, | |
4389 | .flags = ADDR_TYPE_RT | |
4390 | }, | |
4391 | { } | |
4392 | }; | |
4393 | ||
4394 | /* l4_cfg -> smartreflex_core */ | |
4395 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
4396 | .master = &omap44xx_l4_cfg_hwmod, | |
4397 | .slave = &omap44xx_smartreflex_core_hwmod, | |
4398 | .clk = "l4_div_ck", | |
4399 | .addr = omap44xx_smartreflex_core_addrs, | |
4400 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4401 | }; | |
4402 | ||
4403 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
4404 | { | |
4405 | .pa_start = 0x4a0db000, | |
4406 | .pa_end = 0x4a0db03f, | |
4407 | .flags = ADDR_TYPE_RT | |
4408 | }, | |
4409 | { } | |
4410 | }; | |
4411 | ||
4412 | /* l4_cfg -> smartreflex_iva */ | |
4413 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
4414 | .master = &omap44xx_l4_cfg_hwmod, | |
4415 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
4416 | .clk = "l4_div_ck", | |
4417 | .addr = omap44xx_smartreflex_iva_addrs, | |
4418 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4419 | }; | |
4420 | ||
4421 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
4422 | { | |
4423 | .pa_start = 0x4a0d9000, | |
4424 | .pa_end = 0x4a0d903f, | |
4425 | .flags = ADDR_TYPE_RT | |
4426 | }, | |
4427 | { } | |
4428 | }; | |
4429 | ||
4430 | /* l4_cfg -> smartreflex_mpu */ | |
4431 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
4432 | .master = &omap44xx_l4_cfg_hwmod, | |
4433 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
4434 | .clk = "l4_div_ck", | |
4435 | .addr = omap44xx_smartreflex_mpu_addrs, | |
4436 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4437 | }; | |
4438 | ||
844a3b63 PW |
4439 | /* l4_cfg -> spinlock */ |
4440 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
4441 | .master = &omap44xx_l4_cfg_hwmod, | |
4442 | .slave = &omap44xx_spinlock_hwmod, | |
4443 | .clk = "l4_div_ck", | |
844a3b63 PW |
4444 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4445 | }; | |
4446 | ||
844a3b63 PW |
4447 | /* l4_wkup -> timer1 */ |
4448 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
4449 | .master = &omap44xx_l4_wkup_hwmod, | |
4450 | .slave = &omap44xx_timer1_hwmod, | |
4451 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4452 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4453 | }; | |
4454 | ||
844a3b63 PW |
4455 | /* l4_per -> timer2 */ |
4456 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
4457 | .master = &omap44xx_l4_per_hwmod, | |
4458 | .slave = &omap44xx_timer2_hwmod, | |
4459 | .clk = "l4_div_ck", | |
844a3b63 PW |
4460 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4461 | }; | |
4462 | ||
844a3b63 PW |
4463 | /* l4_per -> timer3 */ |
4464 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
4465 | .master = &omap44xx_l4_per_hwmod, | |
4466 | .slave = &omap44xx_timer3_hwmod, | |
4467 | .clk = "l4_div_ck", | |
844a3b63 PW |
4468 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4469 | }; | |
4470 | ||
844a3b63 PW |
4471 | /* l4_per -> timer4 */ |
4472 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
4473 | .master = &omap44xx_l4_per_hwmod, | |
4474 | .slave = &omap44xx_timer4_hwmod, | |
4475 | .clk = "l4_div_ck", | |
844a3b63 PW |
4476 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4477 | }; | |
4478 | ||
844a3b63 PW |
4479 | /* l4_abe -> timer5 */ |
4480 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
4481 | .master = &omap44xx_l4_abe_hwmod, | |
4482 | .slave = &omap44xx_timer5_hwmod, | |
4483 | .clk = "ocp_abe_iclk", | |
e3491795 | 4484 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4485 | }; |
4486 | ||
844a3b63 PW |
4487 | /* l4_abe -> timer6 */ |
4488 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
4489 | .master = &omap44xx_l4_abe_hwmod, | |
4490 | .slave = &omap44xx_timer6_hwmod, | |
4491 | .clk = "ocp_abe_iclk", | |
e3491795 | 4492 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4493 | }; |
4494 | ||
844a3b63 PW |
4495 | /* l4_abe -> timer7 */ |
4496 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
4497 | .master = &omap44xx_l4_abe_hwmod, | |
4498 | .slave = &omap44xx_timer7_hwmod, | |
4499 | .clk = "ocp_abe_iclk", | |
e3491795 | 4500 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4501 | }; |
4502 | ||
844a3b63 PW |
4503 | /* l4_abe -> timer8 */ |
4504 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
4505 | .master = &omap44xx_l4_abe_hwmod, | |
4506 | .slave = &omap44xx_timer8_hwmod, | |
4507 | .clk = "ocp_abe_iclk", | |
e3491795 | 4508 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4509 | }; |
4510 | ||
844a3b63 PW |
4511 | /* l4_per -> timer9 */ |
4512 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
4513 | .master = &omap44xx_l4_per_hwmod, | |
4514 | .slave = &omap44xx_timer9_hwmod, | |
4515 | .clk = "l4_div_ck", | |
844a3b63 PW |
4516 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4517 | }; | |
4518 | ||
844a3b63 PW |
4519 | /* l4_per -> timer10 */ |
4520 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
4521 | .master = &omap44xx_l4_per_hwmod, | |
4522 | .slave = &omap44xx_timer10_hwmod, | |
4523 | .clk = "l4_div_ck", | |
844a3b63 PW |
4524 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4525 | }; | |
4526 | ||
844a3b63 PW |
4527 | /* l4_per -> timer11 */ |
4528 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
4529 | .master = &omap44xx_l4_per_hwmod, | |
4530 | .slave = &omap44xx_timer11_hwmod, | |
4531 | .clk = "l4_div_ck", | |
af88fa9a BC |
4532 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4533 | }; | |
4534 | ||
844a3b63 PW |
4535 | /* l4_per -> uart1 */ |
4536 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
4537 | .master = &omap44xx_l4_per_hwmod, | |
4538 | .slave = &omap44xx_uart1_hwmod, | |
4539 | .clk = "l4_div_ck", | |
844a3b63 PW |
4540 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4541 | }; | |
af88fa9a | 4542 | |
844a3b63 PW |
4543 | /* l4_per -> uart2 */ |
4544 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
4545 | .master = &omap44xx_l4_per_hwmod, | |
4546 | .slave = &omap44xx_uart2_hwmod, | |
4547 | .clk = "l4_div_ck", | |
844a3b63 PW |
4548 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4549 | }; | |
af88fa9a | 4550 | |
844a3b63 PW |
4551 | /* l4_per -> uart3 */ |
4552 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
4553 | .master = &omap44xx_l4_per_hwmod, | |
4554 | .slave = &omap44xx_uart3_hwmod, | |
4555 | .clk = "l4_div_ck", | |
844a3b63 | 4556 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
af88fa9a BC |
4557 | }; |
4558 | ||
844a3b63 PW |
4559 | /* l4_per -> uart4 */ |
4560 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
4561 | .master = &omap44xx_l4_per_hwmod, | |
4562 | .slave = &omap44xx_uart4_hwmod, | |
4563 | .clk = "l4_div_ck", | |
844a3b63 PW |
4564 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4565 | }; | |
4566 | ||
0c668875 | 4567 | /* l4_cfg -> usb_host_fs */ |
b0a70cc8 | 4568 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
4569 | .master = &omap44xx_l4_cfg_hwmod, |
4570 | .slave = &omap44xx_usb_host_fs_hwmod, | |
4571 | .clk = "l4_div_ck", | |
0c668875 BC |
4572 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4573 | }; | |
4574 | ||
844a3b63 PW |
4575 | /* l4_cfg -> usb_host_hs */ |
4576 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
4577 | .master = &omap44xx_l4_cfg_hwmod, | |
4578 | .slave = &omap44xx_usb_host_hs_hwmod, | |
4579 | .clk = "l4_div_ck", | |
844a3b63 PW |
4580 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4581 | }; | |
4582 | ||
844a3b63 PW |
4583 | /* l4_cfg -> usb_otg_hs */ |
4584 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
4585 | .master = &omap44xx_l4_cfg_hwmod, | |
4586 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
4587 | .clk = "l4_div_ck", | |
844a3b63 | 4588 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
af88fa9a BC |
4589 | }; |
4590 | ||
844a3b63 | 4591 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
4592 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
4593 | .master = &omap44xx_l4_cfg_hwmod, | |
4594 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
4595 | .clk = "l4_div_ck", | |
af88fa9a BC |
4596 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4597 | }; | |
4598 | ||
844a3b63 PW |
4599 | /* l4_wkup -> wd_timer2 */ |
4600 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
4601 | .master = &omap44xx_l4_wkup_hwmod, | |
4602 | .slave = &omap44xx_wd_timer2_hwmod, | |
4603 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4604 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4605 | }; | |
4606 | ||
4607 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
4608 | { | |
4609 | .pa_start = 0x40130000, | |
4610 | .pa_end = 0x4013007f, | |
4611 | .flags = ADDR_TYPE_RT | |
4612 | }, | |
4613 | { } | |
4614 | }; | |
4615 | ||
4616 | /* l4_abe -> wd_timer3 */ | |
4617 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
4618 | .master = &omap44xx_l4_abe_hwmod, | |
4619 | .slave = &omap44xx_wd_timer3_hwmod, | |
4620 | .clk = "ocp_abe_iclk", | |
4621 | .addr = omap44xx_wd_timer3_addrs, | |
4622 | .user = OCP_USER_MPU, | |
4623 | }; | |
4624 | ||
4625 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
4626 | { | |
4627 | .pa_start = 0x49030000, | |
4628 | .pa_end = 0x4903007f, | |
4629 | .flags = ADDR_TYPE_RT | |
4630 | }, | |
4631 | { } | |
4632 | }; | |
4633 | ||
4634 | /* l4_abe -> wd_timer3 (dma) */ | |
4635 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
4636 | .master = &omap44xx_l4_abe_hwmod, | |
4637 | .slave = &omap44xx_wd_timer3_hwmod, | |
4638 | .clk = "ocp_abe_iclk", | |
4639 | .addr = omap44xx_wd_timer3_dma_addrs, | |
4640 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
4641 | }; |
4642 | ||
3b9b1015 S |
4643 | /* mpu -> emif1 */ |
4644 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { | |
4645 | .master = &omap44xx_mpu_hwmod, | |
4646 | .slave = &omap44xx_emif1_hwmod, | |
4647 | .clk = "l3_div_ck", | |
4648 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4649 | }; | |
4650 | ||
4651 | /* mpu -> emif2 */ | |
4652 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { | |
4653 | .master = &omap44xx_mpu_hwmod, | |
4654 | .slave = &omap44xx_emif2_hwmod, | |
4655 | .clk = "l3_div_ck", | |
4656 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4657 | }; | |
4658 | ||
0a78c5c5 PW |
4659 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
4660 | &omap44xx_l3_main_1__dmm, | |
4661 | &omap44xx_mpu__dmm, | |
0a78c5c5 PW |
4662 | &omap44xx_iva__l3_instr, |
4663 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 4664 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
4665 | &omap44xx_dsp__l3_main_1, |
4666 | &omap44xx_dss__l3_main_1, | |
4667 | &omap44xx_l3_main_2__l3_main_1, | |
4668 | &omap44xx_l4_cfg__l3_main_1, | |
4669 | &omap44xx_mmc1__l3_main_1, | |
4670 | &omap44xx_mmc2__l3_main_1, | |
4671 | &omap44xx_mpu__l3_main_1, | |
96566043 | 4672 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 4673 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 4674 | &omap44xx_fdif__l3_main_2, |
9def390e | 4675 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
4676 | &omap44xx_hsi__l3_main_2, |
4677 | &omap44xx_ipu__l3_main_2, | |
4678 | &omap44xx_iss__l3_main_2, | |
4679 | &omap44xx_iva__l3_main_2, | |
4680 | &omap44xx_l3_main_1__l3_main_2, | |
4681 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 4682 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
4683 | &omap44xx_usb_host_hs__l3_main_2, |
4684 | &omap44xx_usb_otg_hs__l3_main_2, | |
4685 | &omap44xx_l3_main_1__l3_main_3, | |
4686 | &omap44xx_l3_main_2__l3_main_3, | |
4687 | &omap44xx_l4_cfg__l3_main_3, | |
5cebb23c | 4688 | &omap44xx_aess__l4_abe, |
0a78c5c5 PW |
4689 | &omap44xx_dsp__l4_abe, |
4690 | &omap44xx_l3_main_1__l4_abe, | |
4691 | &omap44xx_mpu__l4_abe, | |
4692 | &omap44xx_l3_main_1__l4_cfg, | |
4693 | &omap44xx_l3_main_2__l4_per, | |
4694 | &omap44xx_l4_cfg__l4_wkup, | |
4695 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 4696 | &omap44xx_l4_cfg__ocp_wp_noc, |
5cebb23c SG |
4697 | &omap44xx_l4_abe__aess, |
4698 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 4699 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 4700 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
4701 | &omap44xx_l4_cfg__ctrl_module_core, |
4702 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
4703 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
4704 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 4705 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
4706 | &omap44xx_l4_cfg__dma_system, |
4707 | &omap44xx_l4_abe__dmic, | |
0a78c5c5 | 4708 | &omap44xx_dsp__iva, |
b360124e | 4709 | /* &omap44xx_dsp__sl2if, */ |
0a78c5c5 PW |
4710 | &omap44xx_l4_cfg__dsp, |
4711 | &omap44xx_l3_main_2__dss, | |
4712 | &omap44xx_l4_per__dss, | |
4713 | &omap44xx_l3_main_2__dss_dispc, | |
4714 | &omap44xx_l4_per__dss_dispc, | |
4715 | &omap44xx_l3_main_2__dss_dsi1, | |
4716 | &omap44xx_l4_per__dss_dsi1, | |
4717 | &omap44xx_l3_main_2__dss_dsi2, | |
4718 | &omap44xx_l4_per__dss_dsi2, | |
4719 | &omap44xx_l3_main_2__dss_hdmi, | |
4720 | &omap44xx_l4_per__dss_hdmi, | |
4721 | &omap44xx_l3_main_2__dss_rfbi, | |
4722 | &omap44xx_l4_per__dss_rfbi, | |
4723 | &omap44xx_l3_main_2__dss_venc, | |
4724 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 4725 | &omap44xx_l4_per__elm, |
b050f688 | 4726 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
4727 | &omap44xx_l4_wkup__gpio1, |
4728 | &omap44xx_l4_per__gpio2, | |
4729 | &omap44xx_l4_per__gpio3, | |
4730 | &omap44xx_l4_per__gpio4, | |
4731 | &omap44xx_l4_per__gpio5, | |
4732 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 4733 | &omap44xx_l3_main_2__gpmc, |
9def390e | 4734 | &omap44xx_l3_main_2__gpu, |
a091c08e | 4735 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
4736 | &omap44xx_l4_cfg__hsi, |
4737 | &omap44xx_l4_per__i2c1, | |
4738 | &omap44xx_l4_per__i2c2, | |
4739 | &omap44xx_l4_per__i2c3, | |
4740 | &omap44xx_l4_per__i2c4, | |
4741 | &omap44xx_l3_main_2__ipu, | |
4742 | &omap44xx_l3_main_2__iss, | |
b360124e | 4743 | /* &omap44xx_iva__sl2if, */ |
0a78c5c5 PW |
4744 | &omap44xx_l3_main_2__iva, |
4745 | &omap44xx_l4_wkup__kbd, | |
4746 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
4747 | &omap44xx_l4_abe__mcasp, |
4748 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 | 4749 | &omap44xx_l4_abe__mcbsp1, |
0a78c5c5 | 4750 | &omap44xx_l4_abe__mcbsp2, |
0a78c5c5 | 4751 | &omap44xx_l4_abe__mcbsp3, |
0a78c5c5 PW |
4752 | &omap44xx_l4_per__mcbsp4, |
4753 | &omap44xx_l4_abe__mcpdm, | |
0a78c5c5 PW |
4754 | &omap44xx_l4_per__mcspi1, |
4755 | &omap44xx_l4_per__mcspi2, | |
4756 | &omap44xx_l4_per__mcspi3, | |
4757 | &omap44xx_l4_per__mcspi4, | |
4758 | &omap44xx_l4_per__mmc1, | |
4759 | &omap44xx_l4_per__mmc2, | |
4760 | &omap44xx_l4_per__mmc3, | |
4761 | &omap44xx_l4_per__mmc4, | |
4762 | &omap44xx_l4_per__mmc5, | |
230844db ORL |
4763 | &omap44xx_l3_main_2__mmu_ipu, |
4764 | &omap44xx_l4_cfg__mmu_dsp, | |
e17f18c0 | 4765 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 4766 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
4767 | &omap44xx_mpu_private__prcm_mpu, |
4768 | &omap44xx_l4_wkup__cm_core_aon, | |
4769 | &omap44xx_l4_cfg__cm_core, | |
4770 | &omap44xx_l4_wkup__prm, | |
4771 | &omap44xx_l4_wkup__scrm, | |
b360124e | 4772 | /* &omap44xx_l3_main_2__sl2if, */ |
1e3b5e59 BC |
4773 | &omap44xx_l4_abe__slimbus1, |
4774 | &omap44xx_l4_abe__slimbus1_dma, | |
4775 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
4776 | &omap44xx_l4_cfg__smartreflex_core, |
4777 | &omap44xx_l4_cfg__smartreflex_iva, | |
4778 | &omap44xx_l4_cfg__smartreflex_mpu, | |
4779 | &omap44xx_l4_cfg__spinlock, | |
4780 | &omap44xx_l4_wkup__timer1, | |
4781 | &omap44xx_l4_per__timer2, | |
4782 | &omap44xx_l4_per__timer3, | |
4783 | &omap44xx_l4_per__timer4, | |
4784 | &omap44xx_l4_abe__timer5, | |
0a78c5c5 | 4785 | &omap44xx_l4_abe__timer6, |
0a78c5c5 | 4786 | &omap44xx_l4_abe__timer7, |
0a78c5c5 | 4787 | &omap44xx_l4_abe__timer8, |
0a78c5c5 PW |
4788 | &omap44xx_l4_per__timer9, |
4789 | &omap44xx_l4_per__timer10, | |
4790 | &omap44xx_l4_per__timer11, | |
4791 | &omap44xx_l4_per__uart1, | |
4792 | &omap44xx_l4_per__uart2, | |
4793 | &omap44xx_l4_per__uart3, | |
4794 | &omap44xx_l4_per__uart4, | |
b0a70cc8 | 4795 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
4796 | &omap44xx_l4_cfg__usb_host_hs, |
4797 | &omap44xx_l4_cfg__usb_otg_hs, | |
4798 | &omap44xx_l4_cfg__usb_tll_hs, | |
4799 | &omap44xx_l4_wkup__wd_timer2, | |
4800 | &omap44xx_l4_abe__wd_timer3, | |
4801 | &omap44xx_l4_abe__wd_timer3_dma, | |
3b9b1015 S |
4802 | &omap44xx_mpu__emif1, |
4803 | &omap44xx_mpu__emif2, | |
55d2cb08 BC |
4804 | NULL, |
4805 | }; | |
4806 | ||
4807 | int __init omap44xx_hwmod_init(void) | |
4808 | { | |
9ebfd285 | 4809 | omap_hwmod_init(); |
0a78c5c5 | 4810 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
4811 | } |
4812 |