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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
6d3c55fd | 25 | #include <plat/i2c.h> |
9780a9cf | 26 | #include <plat/gpio.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
c345c8b0 | 31 | #include <plat/dmtimer.h> |
13662dc5 | 32 | #include <plat/common.h> |
55d2cb08 BC |
33 | |
34 | #include "omap_hwmod_common_data.h" | |
35 | ||
cea6b942 | 36 | #include "smartreflex.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
ff2516fb | 41 | #include "wd_timer.h" |
55d2cb08 BC |
42 | |
43 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
44 | #define OMAP44XX_IRQ_GIC_START 32 | |
45 | ||
46 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 47 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
48 | |
49 | /* | |
844a3b63 | 50 | * IP blocks |
55d2cb08 BC |
51 | */ |
52 | ||
42b9e387 PW |
53 | /* |
54 | * 'c2c_target_fw' class | |
55 | * instance(s): c2c_target_fw | |
56 | */ | |
57 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | |
58 | .name = "c2c_target_fw", | |
59 | }; | |
60 | ||
61 | /* c2c_target_fw */ | |
62 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | |
63 | .name = "c2c_target_fw", | |
64 | .class = &omap44xx_c2c_target_fw_hwmod_class, | |
65 | .clkdm_name = "d2d_clkdm", | |
66 | .prcm = { | |
67 | .omap4 = { | |
68 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | |
69 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | |
70 | }, | |
71 | }, | |
72 | }; | |
73 | ||
55d2cb08 BC |
74 | /* |
75 | * 'dmm' class | |
76 | * instance(s): dmm | |
77 | */ | |
78 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 79 | .name = "dmm", |
55d2cb08 BC |
80 | }; |
81 | ||
7e69ed97 BC |
82 | /* dmm */ |
83 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
84 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
85 | { .irq = -1 } | |
86 | }; | |
87 | ||
55d2cb08 BC |
88 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
89 | .name = "dmm", | |
90 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 91 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 92 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
93 | .prcm = { |
94 | .omap4 = { | |
95 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 96 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
97 | }, |
98 | }, | |
55d2cb08 BC |
99 | }; |
100 | ||
101 | /* | |
102 | * 'emif_fw' class | |
103 | * instance(s): emif_fw | |
104 | */ | |
105 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 106 | .name = "emif_fw", |
55d2cb08 BC |
107 | }; |
108 | ||
7e69ed97 | 109 | /* emif_fw */ |
55d2cb08 BC |
110 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
111 | .name = "emif_fw", | |
112 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 113 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
114 | .prcm = { |
115 | .omap4 = { | |
116 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 117 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
118 | }, |
119 | }, | |
55d2cb08 BC |
120 | }; |
121 | ||
122 | /* | |
123 | * 'l3' class | |
124 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
125 | */ | |
126 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 127 | .name = "l3", |
55d2cb08 BC |
128 | }; |
129 | ||
7e69ed97 | 130 | /* l3_instr */ |
55d2cb08 BC |
131 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
132 | .name = "l3_instr", | |
133 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 134 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
135 | .prcm = { |
136 | .omap4 = { | |
137 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 138 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 139 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
140 | }, |
141 | }, | |
55d2cb08 BC |
142 | }; |
143 | ||
7e69ed97 | 144 | /* l3_main_1 */ |
9b4021be BC |
145 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
146 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
147 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
148 | { .irq = -1 } | |
149 | }; | |
150 | ||
55d2cb08 BC |
151 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
152 | .name = "l3_main_1", | |
153 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 154 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 155 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
156 | .prcm = { |
157 | .omap4 = { | |
158 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 159 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
160 | }, |
161 | }, | |
55d2cb08 BC |
162 | }; |
163 | ||
7e69ed97 | 164 | /* l3_main_2 */ |
55d2cb08 BC |
165 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
166 | .name = "l3_main_2", | |
167 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 168 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
169 | .prcm = { |
170 | .omap4 = { | |
171 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 172 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
173 | }, |
174 | }, | |
55d2cb08 BC |
175 | }; |
176 | ||
7e69ed97 | 177 | /* l3_main_3 */ |
55d2cb08 BC |
178 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
179 | .name = "l3_main_3", | |
180 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 181 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
182 | .prcm = { |
183 | .omap4 = { | |
184 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 185 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 186 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
187 | }, |
188 | }, | |
55d2cb08 BC |
189 | }; |
190 | ||
191 | /* | |
192 | * 'l4' class | |
193 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
194 | */ | |
195 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 196 | .name = "l4", |
55d2cb08 BC |
197 | }; |
198 | ||
7e69ed97 | 199 | /* l4_abe */ |
55d2cb08 BC |
200 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
201 | .name = "l4_abe", | |
202 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 203 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
204 | .prcm = { |
205 | .omap4 = { | |
206 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
207 | }, | |
208 | }, | |
55d2cb08 BC |
209 | }; |
210 | ||
7e69ed97 | 211 | /* l4_cfg */ |
55d2cb08 BC |
212 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
213 | .name = "l4_cfg", | |
214 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 215 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
216 | .prcm = { |
217 | .omap4 = { | |
218 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 219 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
220 | }, |
221 | }, | |
55d2cb08 BC |
222 | }; |
223 | ||
7e69ed97 | 224 | /* l4_per */ |
55d2cb08 BC |
225 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
226 | .name = "l4_per", | |
227 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 228 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
229 | .prcm = { |
230 | .omap4 = { | |
231 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 232 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
233 | }, |
234 | }, | |
55d2cb08 BC |
235 | }; |
236 | ||
7e69ed97 | 237 | /* l4_wkup */ |
55d2cb08 BC |
238 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
239 | .name = "l4_wkup", | |
240 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 241 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
242 | .prcm = { |
243 | .omap4 = { | |
244 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 245 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
246 | }, |
247 | }, | |
55d2cb08 BC |
248 | }; |
249 | ||
f776471f | 250 | /* |
3b54baad BC |
251 | * 'mpu_bus' class |
252 | * instance(s): mpu_private | |
f776471f | 253 | */ |
3b54baad | 254 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 255 | .name = "mpu_bus", |
3b54baad | 256 | }; |
f776471f | 257 | |
7e69ed97 | 258 | /* mpu_private */ |
3b54baad BC |
259 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
260 | .name = "mpu_private", | |
261 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 262 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
263 | }; |
264 | ||
9a817bc8 BC |
265 | /* |
266 | * 'ocp_wp_noc' class | |
267 | * instance(s): ocp_wp_noc | |
268 | */ | |
269 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
270 | .name = "ocp_wp_noc", | |
271 | }; | |
272 | ||
273 | /* ocp_wp_noc */ | |
274 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
275 | .name = "ocp_wp_noc", | |
276 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
277 | .clkdm_name = "l3_instr_clkdm", | |
278 | .prcm = { | |
279 | .omap4 = { | |
280 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
281 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
282 | .modulemode = MODULEMODE_HWCTRL, | |
283 | }, | |
284 | }, | |
285 | }; | |
286 | ||
3b54baad BC |
287 | /* |
288 | * Modules omap_hwmod structures | |
289 | * | |
290 | * The following IPs are excluded for the moment because: | |
291 | * - They do not need an explicit SW control using omap_hwmod API. | |
292 | * - They still need to be validated with the driver | |
293 | * properly adapted to omap_hwmod / omap_device | |
294 | * | |
3b54baad | 295 | * debugss |
3b54baad BC |
296 | * efuse_ctrl_cust |
297 | * efuse_ctrl_std | |
00fe610b BC |
298 | * mpu_c0 |
299 | * mpu_c1 | |
3b54baad | 300 | * usb_phy_cm |
3b54baad BC |
301 | * usim |
302 | */ | |
303 | ||
407a6888 BC |
304 | /* |
305 | * 'aess' class | |
306 | * audio engine sub system | |
307 | */ | |
308 | ||
309 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
310 | .rev_offs = 0x0000, | |
311 | .sysc_offs = 0x0010, | |
312 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
313 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
314 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
315 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
316 | .sysc_fields = &omap_hwmod_sysc_type2, |
317 | }; | |
318 | ||
319 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
320 | .name = "aess", | |
321 | .sysc = &omap44xx_aess_sysc, | |
322 | }; | |
323 | ||
324 | /* aess */ | |
325 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
326 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 327 | { .irq = -1 } |
407a6888 BC |
328 | }; |
329 | ||
330 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
331 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
332 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
333 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
334 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
335 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
336 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
337 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
338 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 339 | { .dma_req = -1 } |
407a6888 BC |
340 | }; |
341 | ||
407a6888 BC |
342 | static struct omap_hwmod omap44xx_aess_hwmod = { |
343 | .name = "aess", | |
344 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 345 | .clkdm_name = "abe_clkdm", |
407a6888 | 346 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 347 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 348 | .main_clk = "aess_fck", |
00fe610b | 349 | .prcm = { |
407a6888 | 350 | .omap4 = { |
d0f0631d | 351 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 352 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 353 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
354 | }, |
355 | }, | |
407a6888 BC |
356 | }; |
357 | ||
42b9e387 PW |
358 | /* |
359 | * 'c2c' class | |
360 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
361 | * soc | |
362 | */ | |
363 | ||
364 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
365 | .name = "c2c", | |
366 | }; | |
367 | ||
368 | /* c2c */ | |
369 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | |
370 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | |
371 | { .irq = -1 } | |
372 | }; | |
373 | ||
374 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | |
375 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | |
376 | { .dma_req = -1 } | |
377 | }; | |
378 | ||
379 | static struct omap_hwmod omap44xx_c2c_hwmod = { | |
380 | .name = "c2c", | |
381 | .class = &omap44xx_c2c_hwmod_class, | |
382 | .clkdm_name = "d2d_clkdm", | |
383 | .mpu_irqs = omap44xx_c2c_irqs, | |
384 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | |
385 | .prcm = { | |
386 | .omap4 = { | |
387 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
388 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
389 | }, | |
390 | }, | |
391 | }; | |
392 | ||
407a6888 BC |
393 | /* |
394 | * 'counter' class | |
395 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
396 | */ | |
397 | ||
398 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
399 | .rev_offs = 0x0000, | |
400 | .sysc_offs = 0x0004, | |
401 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
402 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
403 | SIDLE_SMART_WKUP), | |
404 | .sysc_fields = &omap_hwmod_sysc_type1, | |
405 | }; | |
406 | ||
407 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
408 | .name = "counter", | |
409 | .sysc = &omap44xx_counter_sysc, | |
410 | }; | |
411 | ||
412 | /* counter_32k */ | |
407a6888 BC |
413 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
414 | .name = "counter_32k", | |
415 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 416 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
417 | .flags = HWMOD_SWSUP_SIDLE, |
418 | .main_clk = "sys_32k_ck", | |
00fe610b | 419 | .prcm = { |
407a6888 | 420 | .omap4 = { |
d0f0631d | 421 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 422 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
423 | }, |
424 | }, | |
407a6888 BC |
425 | }; |
426 | ||
a0b5d813 PW |
427 | /* |
428 | * 'ctrl_module' class | |
429 | * attila core control module + core pad control module + wkup pad control | |
430 | * module + attila wkup control module | |
431 | */ | |
432 | ||
433 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
434 | .rev_offs = 0x0000, | |
435 | .sysc_offs = 0x0010, | |
436 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
437 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
438 | SIDLE_SMART_WKUP), | |
439 | .sysc_fields = &omap_hwmod_sysc_type2, | |
440 | }; | |
441 | ||
442 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
443 | .name = "ctrl_module", | |
444 | .sysc = &omap44xx_ctrl_module_sysc, | |
445 | }; | |
446 | ||
447 | /* ctrl_module_core */ | |
448 | static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { | |
449 | { .irq = 8 + OMAP44XX_IRQ_GIC_START }, | |
450 | { .irq = -1 } | |
451 | }; | |
452 | ||
453 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { | |
454 | .name = "ctrl_module_core", | |
455 | .class = &omap44xx_ctrl_module_hwmod_class, | |
456 | .clkdm_name = "l4_cfg_clkdm", | |
457 | .mpu_irqs = omap44xx_ctrl_module_core_irqs, | |
458 | }; | |
459 | ||
460 | /* ctrl_module_pad_core */ | |
461 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
462 | .name = "ctrl_module_pad_core", | |
463 | .class = &omap44xx_ctrl_module_hwmod_class, | |
464 | .clkdm_name = "l4_cfg_clkdm", | |
465 | }; | |
466 | ||
467 | /* ctrl_module_wkup */ | |
468 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
469 | .name = "ctrl_module_wkup", | |
470 | .class = &omap44xx_ctrl_module_hwmod_class, | |
471 | .clkdm_name = "l4_wkup_clkdm", | |
472 | }; | |
473 | ||
474 | /* ctrl_module_pad_wkup */ | |
475 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
476 | .name = "ctrl_module_pad_wkup", | |
477 | .class = &omap44xx_ctrl_module_hwmod_class, | |
478 | .clkdm_name = "l4_wkup_clkdm", | |
479 | }; | |
480 | ||
d7cf5f33 BC |
481 | /* |
482 | * 'dma' class | |
483 | * dma controller for data exchange between memory to memory (i.e. internal or | |
484 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
485 | */ | |
486 | ||
487 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
488 | .rev_offs = 0x0000, | |
489 | .sysc_offs = 0x002c, | |
490 | .syss_offs = 0x0028, | |
491 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
492 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
493 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
494 | SYSS_HAS_RESET_STATUS), | |
495 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
496 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
497 | .sysc_fields = &omap_hwmod_sysc_type1, | |
498 | }; | |
499 | ||
500 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
501 | .name = "dma", | |
502 | .sysc = &omap44xx_dma_sysc, | |
503 | }; | |
504 | ||
505 | /* dma dev_attr */ | |
506 | static struct omap_dma_dev_attr dma_dev_attr = { | |
507 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
508 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
509 | .lch_count = 32, | |
510 | }; | |
511 | ||
512 | /* dma_system */ | |
513 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
514 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
515 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
516 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
517 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 518 | { .irq = -1 } |
d7cf5f33 BC |
519 | }; |
520 | ||
d7cf5f33 BC |
521 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
522 | .name = "dma_system", | |
523 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 524 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 525 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
526 | .main_clk = "l3_div_ck", |
527 | .prcm = { | |
528 | .omap4 = { | |
d0f0631d | 529 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 530 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
531 | }, |
532 | }, | |
533 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
534 | }; |
535 | ||
8ca476da BC |
536 | /* |
537 | * 'dmic' class | |
538 | * digital microphone controller | |
539 | */ | |
540 | ||
541 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
542 | .rev_offs = 0x0000, | |
543 | .sysc_offs = 0x0010, | |
544 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
545 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
546 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
547 | SIDLE_SMART_WKUP), | |
548 | .sysc_fields = &omap_hwmod_sysc_type2, | |
549 | }; | |
550 | ||
551 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
552 | .name = "dmic", | |
553 | .sysc = &omap44xx_dmic_sysc, | |
554 | }; | |
555 | ||
556 | /* dmic */ | |
8ca476da BC |
557 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
558 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 559 | { .irq = -1 } |
8ca476da BC |
560 | }; |
561 | ||
562 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
563 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 564 | { .dma_req = -1 } |
8ca476da BC |
565 | }; |
566 | ||
8ca476da BC |
567 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
568 | .name = "dmic", | |
569 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 570 | .clkdm_name = "abe_clkdm", |
8ca476da | 571 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 572 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 573 | .main_clk = "dmic_fck", |
00fe610b | 574 | .prcm = { |
8ca476da | 575 | .omap4 = { |
d0f0631d | 576 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 577 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 578 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
579 | }, |
580 | }, | |
8ca476da BC |
581 | }; |
582 | ||
8f25bdc5 BC |
583 | /* |
584 | * 'dsp' class | |
585 | * dsp sub-system | |
586 | */ | |
587 | ||
588 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 589 | .name = "dsp", |
8f25bdc5 BC |
590 | }; |
591 | ||
592 | /* dsp */ | |
593 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
594 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 595 | { .irq = -1 } |
8f25bdc5 BC |
596 | }; |
597 | ||
598 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 | 599 | { .name = "dsp", .rst_shift = 0 }, |
f2f5736c | 600 | { .name = "mmu_cache", .rst_shift = 1 }, |
8f25bdc5 BC |
601 | }; |
602 | ||
8f25bdc5 BC |
603 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
604 | .name = "dsp", | |
605 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 606 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 607 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
608 | .rst_lines = omap44xx_dsp_resets, |
609 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
610 | .main_clk = "dsp_fck", | |
611 | .prcm = { | |
612 | .omap4 = { | |
d0f0631d | 613 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 614 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 615 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 616 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
617 | }, |
618 | }, | |
8f25bdc5 BC |
619 | }; |
620 | ||
d63bd74f BC |
621 | /* |
622 | * 'dss' class | |
623 | * display sub-system | |
624 | */ | |
625 | ||
626 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
627 | .rev_offs = 0x0000, | |
628 | .syss_offs = 0x0014, | |
629 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
630 | }; | |
631 | ||
632 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
633 | .name = "dss", | |
634 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 635 | .reset = omap_dss_reset, |
d63bd74f BC |
636 | }; |
637 | ||
638 | /* dss */ | |
d63bd74f BC |
639 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
640 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
641 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 642 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
643 | }; |
644 | ||
645 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
646 | .name = "dss_core", | |
37ad0855 | 647 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 648 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 649 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 650 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
651 | .prcm = { |
652 | .omap4 = { | |
d0f0631d | 653 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 654 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
655 | }, |
656 | }, | |
657 | .opt_clks = dss_opt_clks, | |
658 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
659 | }; |
660 | ||
661 | /* | |
662 | * 'dispc' class | |
663 | * display controller | |
664 | */ | |
665 | ||
666 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
667 | .rev_offs = 0x0000, | |
668 | .sysc_offs = 0x0010, | |
669 | .syss_offs = 0x0014, | |
670 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
671 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
672 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
673 | SYSS_HAS_RESET_STATUS), | |
674 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
675 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
676 | .sysc_fields = &omap_hwmod_sysc_type1, | |
677 | }; | |
678 | ||
679 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
680 | .name = "dispc", | |
681 | .sysc = &omap44xx_dispc_sysc, | |
682 | }; | |
683 | ||
684 | /* dss_dispc */ | |
d63bd74f BC |
685 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
686 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 687 | { .irq = -1 } |
d63bd74f BC |
688 | }; |
689 | ||
690 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
691 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 692 | { .dma_req = -1 } |
d63bd74f BC |
693 | }; |
694 | ||
b923d40d AT |
695 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
696 | .manager_count = 3, | |
697 | .has_framedonetv_irq = 1 | |
698 | }; | |
699 | ||
d63bd74f BC |
700 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
701 | .name = "dss_dispc", | |
702 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 703 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 704 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 705 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 706 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
707 | .prcm = { |
708 | .omap4 = { | |
d0f0631d | 709 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 710 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
711 | }, |
712 | }, | |
b923d40d | 713 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
714 | }; |
715 | ||
716 | /* | |
717 | * 'dsi' class | |
718 | * display serial interface controller | |
719 | */ | |
720 | ||
721 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
722 | .rev_offs = 0x0000, | |
723 | .sysc_offs = 0x0010, | |
724 | .syss_offs = 0x0014, | |
725 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
726 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
727 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
728 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
729 | .sysc_fields = &omap_hwmod_sysc_type1, | |
730 | }; | |
731 | ||
732 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
733 | .name = "dsi", | |
734 | .sysc = &omap44xx_dsi_sysc, | |
735 | }; | |
736 | ||
737 | /* dss_dsi1 */ | |
d63bd74f BC |
738 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
739 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 740 | { .irq = -1 } |
d63bd74f BC |
741 | }; |
742 | ||
743 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
744 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 745 | { .dma_req = -1 } |
d63bd74f BC |
746 | }; |
747 | ||
3a23aafc TV |
748 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
749 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
750 | }; | |
751 | ||
d63bd74f BC |
752 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
753 | .name = "dss_dsi1", | |
754 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 755 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 756 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 757 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 758 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
759 | .prcm = { |
760 | .omap4 = { | |
d0f0631d | 761 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 762 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
763 | }, |
764 | }, | |
3a23aafc TV |
765 | .opt_clks = dss_dsi1_opt_clks, |
766 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
767 | }; |
768 | ||
769 | /* dss_dsi2 */ | |
d63bd74f BC |
770 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
771 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 772 | { .irq = -1 } |
d63bd74f BC |
773 | }; |
774 | ||
775 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
776 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 777 | { .dma_req = -1 } |
d63bd74f BC |
778 | }; |
779 | ||
3a23aafc TV |
780 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
781 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
782 | }; | |
783 | ||
d63bd74f BC |
784 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
785 | .name = "dss_dsi2", | |
786 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 787 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 788 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 789 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 790 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
791 | .prcm = { |
792 | .omap4 = { | |
d0f0631d | 793 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 794 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
795 | }, |
796 | }, | |
3a23aafc TV |
797 | .opt_clks = dss_dsi2_opt_clks, |
798 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
799 | }; |
800 | ||
801 | /* | |
802 | * 'hdmi' class | |
803 | * hdmi controller | |
804 | */ | |
805 | ||
806 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
807 | .rev_offs = 0x0000, | |
808 | .sysc_offs = 0x0010, | |
809 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
810 | SYSC_HAS_SOFTRESET), | |
811 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
812 | SIDLE_SMART_WKUP), | |
813 | .sysc_fields = &omap_hwmod_sysc_type2, | |
814 | }; | |
815 | ||
816 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
817 | .name = "hdmi", | |
818 | .sysc = &omap44xx_hdmi_sysc, | |
819 | }; | |
820 | ||
821 | /* dss_hdmi */ | |
d63bd74f BC |
822 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
823 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 824 | { .irq = -1 } |
d63bd74f BC |
825 | }; |
826 | ||
827 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
828 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 829 | { .dma_req = -1 } |
d63bd74f BC |
830 | }; |
831 | ||
3a23aafc TV |
832 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
833 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
834 | }; | |
835 | ||
d63bd74f BC |
836 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
837 | .name = "dss_hdmi", | |
838 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 839 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 840 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 841 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 842 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
843 | .prcm = { |
844 | .omap4 = { | |
d0f0631d | 845 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 846 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
847 | }, |
848 | }, | |
3a23aafc TV |
849 | .opt_clks = dss_hdmi_opt_clks, |
850 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
851 | }; |
852 | ||
853 | /* | |
854 | * 'rfbi' class | |
855 | * remote frame buffer interface | |
856 | */ | |
857 | ||
858 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
859 | .rev_offs = 0x0000, | |
860 | .sysc_offs = 0x0010, | |
861 | .syss_offs = 0x0014, | |
862 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
863 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
864 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
865 | .sysc_fields = &omap_hwmod_sysc_type1, | |
866 | }; | |
867 | ||
868 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
869 | .name = "rfbi", | |
870 | .sysc = &omap44xx_rfbi_sysc, | |
871 | }; | |
872 | ||
873 | /* dss_rfbi */ | |
d63bd74f BC |
874 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
875 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 876 | { .dma_req = -1 } |
d63bd74f BC |
877 | }; |
878 | ||
3a23aafc TV |
879 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
880 | { .role = "ick", .clk = "dss_fck" }, | |
881 | }; | |
882 | ||
d63bd74f BC |
883 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
884 | .name = "dss_rfbi", | |
885 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 886 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 887 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 888 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
889 | .prcm = { |
890 | .omap4 = { | |
d0f0631d | 891 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 892 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
893 | }, |
894 | }, | |
3a23aafc TV |
895 | .opt_clks = dss_rfbi_opt_clks, |
896 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
897 | }; |
898 | ||
899 | /* | |
900 | * 'venc' class | |
901 | * video encoder | |
902 | */ | |
903 | ||
904 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
905 | .name = "venc", | |
906 | }; | |
907 | ||
908 | /* dss_venc */ | |
d63bd74f BC |
909 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
910 | .name = "dss_venc", | |
911 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 912 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 913 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
914 | .prcm = { |
915 | .omap4 = { | |
d0f0631d | 916 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 917 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
918 | }, |
919 | }, | |
d63bd74f BC |
920 | }; |
921 | ||
42b9e387 PW |
922 | /* |
923 | * 'elm' class | |
924 | * bch error location module | |
925 | */ | |
926 | ||
927 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
928 | .rev_offs = 0x0000, | |
929 | .sysc_offs = 0x0010, | |
930 | .syss_offs = 0x0014, | |
931 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
932 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
933 | SYSS_HAS_RESET_STATUS), | |
934 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
935 | .sysc_fields = &omap_hwmod_sysc_type1, | |
936 | }; | |
937 | ||
938 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
939 | .name = "elm", | |
940 | .sysc = &omap44xx_elm_sysc, | |
941 | }; | |
942 | ||
943 | /* elm */ | |
944 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | |
945 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | |
946 | { .irq = -1 } | |
947 | }; | |
948 | ||
949 | static struct omap_hwmod omap44xx_elm_hwmod = { | |
950 | .name = "elm", | |
951 | .class = &omap44xx_elm_hwmod_class, | |
952 | .clkdm_name = "l4_per_clkdm", | |
953 | .mpu_irqs = omap44xx_elm_irqs, | |
954 | .prcm = { | |
955 | .omap4 = { | |
956 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
957 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
958 | }, | |
959 | }, | |
960 | }; | |
961 | ||
bf30f950 PW |
962 | /* |
963 | * 'emif' class | |
964 | * external memory interface no1 | |
965 | */ | |
966 | ||
967 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
968 | .rev_offs = 0x0000, | |
969 | }; | |
970 | ||
971 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
972 | .name = "emif", | |
973 | .sysc = &omap44xx_emif_sysc, | |
974 | }; | |
975 | ||
976 | /* emif1 */ | |
977 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | |
978 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | |
979 | { .irq = -1 } | |
980 | }; | |
981 | ||
982 | static struct omap_hwmod omap44xx_emif1_hwmod = { | |
983 | .name = "emif1", | |
984 | .class = &omap44xx_emif_hwmod_class, | |
985 | .clkdm_name = "l3_emif_clkdm", | |
986 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
987 | .mpu_irqs = omap44xx_emif1_irqs, | |
988 | .main_clk = "ddrphy_ck", | |
989 | .prcm = { | |
990 | .omap4 = { | |
991 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
992 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
993 | .modulemode = MODULEMODE_HWCTRL, | |
994 | }, | |
995 | }, | |
996 | }; | |
997 | ||
998 | /* emif2 */ | |
999 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | |
1000 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | |
1001 | { .irq = -1 } | |
1002 | }; | |
1003 | ||
1004 | static struct omap_hwmod omap44xx_emif2_hwmod = { | |
1005 | .name = "emif2", | |
1006 | .class = &omap44xx_emif_hwmod_class, | |
1007 | .clkdm_name = "l3_emif_clkdm", | |
1008 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1009 | .mpu_irqs = omap44xx_emif2_irqs, | |
1010 | .main_clk = "ddrphy_ck", | |
1011 | .prcm = { | |
1012 | .omap4 = { | |
1013 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
1014 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
1015 | .modulemode = MODULEMODE_HWCTRL, | |
1016 | }, | |
1017 | }, | |
1018 | }; | |
1019 | ||
b050f688 ML |
1020 | /* |
1021 | * 'fdif' class | |
1022 | * face detection hw accelerator module | |
1023 | */ | |
1024 | ||
1025 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
1026 | .rev_offs = 0x0000, | |
1027 | .sysc_offs = 0x0010, | |
1028 | /* | |
1029 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
1030 | * accessing sysconfig again. | |
1031 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1032 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1033 | * | |
1034 | * TODO: Indicate errata when available. | |
1035 | */ | |
1036 | .srst_udelay = 2, | |
1037 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
1038 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1039 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1040 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1041 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1042 | }; | |
1043 | ||
1044 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1045 | .name = "fdif", | |
1046 | .sysc = &omap44xx_fdif_sysc, | |
1047 | }; | |
1048 | ||
1049 | /* fdif */ | |
1050 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
1051 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
1052 | { .irq = -1 } | |
1053 | }; | |
1054 | ||
1055 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
1056 | .name = "fdif", | |
1057 | .class = &omap44xx_fdif_hwmod_class, | |
1058 | .clkdm_name = "iss_clkdm", | |
1059 | .mpu_irqs = omap44xx_fdif_irqs, | |
1060 | .main_clk = "fdif_fck", | |
1061 | .prcm = { | |
1062 | .omap4 = { | |
1063 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1064 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1065 | .modulemode = MODULEMODE_SWCTRL, | |
1066 | }, | |
1067 | }, | |
1068 | }; | |
1069 | ||
3b54baad BC |
1070 | /* |
1071 | * 'gpio' class | |
1072 | * general purpose io module | |
1073 | */ | |
1074 | ||
1075 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1076 | .rev_offs = 0x0000, | |
f776471f | 1077 | .sysc_offs = 0x0010, |
3b54baad | 1078 | .syss_offs = 0x0114, |
0cfe8751 BC |
1079 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1080 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1081 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1082 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1083 | SIDLE_SMART_WKUP), | |
f776471f BC |
1084 | .sysc_fields = &omap_hwmod_sysc_type1, |
1085 | }; | |
1086 | ||
3b54baad | 1087 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1088 | .name = "gpio", |
1089 | .sysc = &omap44xx_gpio_sysc, | |
1090 | .rev = 2, | |
f776471f BC |
1091 | }; |
1092 | ||
3b54baad BC |
1093 | /* gpio dev_attr */ |
1094 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1095 | .bank_width = 32, |
1096 | .dbck_flag = true, | |
f776471f BC |
1097 | }; |
1098 | ||
3b54baad | 1099 | /* gpio1 */ |
3b54baad BC |
1100 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1101 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1102 | { .irq = -1 } |
f776471f BC |
1103 | }; |
1104 | ||
3b54baad | 1105 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1106 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1107 | }; |
1108 | ||
1109 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1110 | .name = "gpio1", | |
1111 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1112 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1113 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1114 | .main_clk = "gpio1_ick", |
f776471f BC |
1115 | .prcm = { |
1116 | .omap4 = { | |
d0f0631d | 1117 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1118 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1119 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1120 | }, |
1121 | }, | |
3b54baad BC |
1122 | .opt_clks = gpio1_opt_clks, |
1123 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1124 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1125 | }; |
1126 | ||
3b54baad | 1127 | /* gpio2 */ |
3b54baad BC |
1128 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1129 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1130 | { .irq = -1 } |
f776471f BC |
1131 | }; |
1132 | ||
3b54baad | 1133 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1134 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1135 | }; |
1136 | ||
1137 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1138 | .name = "gpio2", | |
1139 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1140 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1141 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1142 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1143 | .main_clk = "gpio2_ick", |
f776471f BC |
1144 | .prcm = { |
1145 | .omap4 = { | |
d0f0631d | 1146 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1147 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1148 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1149 | }, |
1150 | }, | |
3b54baad BC |
1151 | .opt_clks = gpio2_opt_clks, |
1152 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1153 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1154 | }; |
1155 | ||
3b54baad | 1156 | /* gpio3 */ |
3b54baad BC |
1157 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1158 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1159 | { .irq = -1 } |
f776471f BC |
1160 | }; |
1161 | ||
3b54baad | 1162 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1163 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1164 | }; |
1165 | ||
1166 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1167 | .name = "gpio3", | |
1168 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1169 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1170 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1171 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1172 | .main_clk = "gpio3_ick", |
f776471f BC |
1173 | .prcm = { |
1174 | .omap4 = { | |
d0f0631d | 1175 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1176 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1177 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1178 | }, |
1179 | }, | |
3b54baad BC |
1180 | .opt_clks = gpio3_opt_clks, |
1181 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1182 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1183 | }; |
1184 | ||
3b54baad | 1185 | /* gpio4 */ |
3b54baad BC |
1186 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1187 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1188 | { .irq = -1 } |
f776471f BC |
1189 | }; |
1190 | ||
3b54baad | 1191 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1192 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1193 | }; |
1194 | ||
1195 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1196 | .name = "gpio4", | |
1197 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1198 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1199 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1200 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 1201 | .main_clk = "gpio4_ick", |
f776471f BC |
1202 | .prcm = { |
1203 | .omap4 = { | |
d0f0631d | 1204 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1205 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1206 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1207 | }, |
1208 | }, | |
3b54baad BC |
1209 | .opt_clks = gpio4_opt_clks, |
1210 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1211 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1212 | }; |
1213 | ||
3b54baad | 1214 | /* gpio5 */ |
3b54baad BC |
1215 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1216 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1217 | { .irq = -1 } |
55d2cb08 BC |
1218 | }; |
1219 | ||
844a3b63 PW |
1220 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1221 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1222 | }; |
1223 | ||
3b54baad BC |
1224 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1225 | .name = "gpio5", | |
1226 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1227 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1228 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1229 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 1230 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
1231 | .prcm = { |
1232 | .omap4 = { | |
d0f0631d | 1233 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1234 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1235 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1236 | }, |
1237 | }, | |
3b54baad BC |
1238 | .opt_clks = gpio5_opt_clks, |
1239 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1240 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1241 | }; |
1242 | ||
3b54baad | 1243 | /* gpio6 */ |
3b54baad BC |
1244 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1245 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1246 | { .irq = -1 } |
92b18d1c BC |
1247 | }; |
1248 | ||
3b54baad | 1249 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1250 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1251 | }; |
1252 | ||
3b54baad BC |
1253 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1254 | .name = "gpio6", | |
1255 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1256 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1257 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1258 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
1259 | .main_clk = "gpio6_ick", |
1260 | .prcm = { | |
1261 | .omap4 = { | |
d0f0631d | 1262 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1263 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1264 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1265 | }, |
db12ba53 | 1266 | }, |
3b54baad BC |
1267 | .opt_clks = gpio6_opt_clks, |
1268 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1269 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1270 | }; |
1271 | ||
eb42b5d3 BC |
1272 | /* |
1273 | * 'gpmc' class | |
1274 | * general purpose memory controller | |
1275 | */ | |
1276 | ||
1277 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1278 | .rev_offs = 0x0000, | |
1279 | .sysc_offs = 0x0010, | |
1280 | .syss_offs = 0x0014, | |
1281 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1282 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1283 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1284 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1285 | }; | |
1286 | ||
1287 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1288 | .name = "gpmc", | |
1289 | .sysc = &omap44xx_gpmc_sysc, | |
1290 | }; | |
1291 | ||
1292 | /* gpmc */ | |
1293 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1294 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1295 | { .irq = -1 } | |
1296 | }; | |
1297 | ||
1298 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1299 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1300 | { .dma_req = -1 } | |
1301 | }; | |
1302 | ||
1303 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1304 | .name = "gpmc", | |
1305 | .class = &omap44xx_gpmc_hwmod_class, | |
1306 | .clkdm_name = "l3_2_clkdm", | |
1307 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1308 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1309 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1310 | .prcm = { | |
1311 | .omap4 = { | |
1312 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1313 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1314 | .modulemode = MODULEMODE_HWCTRL, | |
1315 | }, | |
1316 | }, | |
1317 | }; | |
1318 | ||
9def390e PW |
1319 | /* |
1320 | * 'gpu' class | |
1321 | * 2d/3d graphics accelerator | |
1322 | */ | |
1323 | ||
1324 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1325 | .rev_offs = 0x1fc00, | |
1326 | .sysc_offs = 0x1fc10, | |
1327 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1328 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1329 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1330 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1331 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1332 | }; | |
1333 | ||
1334 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1335 | .name = "gpu", | |
1336 | .sysc = &omap44xx_gpu_sysc, | |
1337 | }; | |
1338 | ||
1339 | /* gpu */ | |
1340 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | |
1341 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | |
1342 | { .irq = -1 } | |
1343 | }; | |
1344 | ||
1345 | static struct omap_hwmod omap44xx_gpu_hwmod = { | |
1346 | .name = "gpu", | |
1347 | .class = &omap44xx_gpu_hwmod_class, | |
1348 | .clkdm_name = "l3_gfx_clkdm", | |
1349 | .mpu_irqs = omap44xx_gpu_irqs, | |
1350 | .main_clk = "gpu_fck", | |
1351 | .prcm = { | |
1352 | .omap4 = { | |
1353 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1354 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1355 | .modulemode = MODULEMODE_SWCTRL, | |
1356 | }, | |
1357 | }, | |
1358 | }; | |
1359 | ||
a091c08e PW |
1360 | /* |
1361 | * 'hdq1w' class | |
1362 | * hdq / 1-wire serial interface controller | |
1363 | */ | |
1364 | ||
1365 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1366 | .rev_offs = 0x0000, | |
1367 | .sysc_offs = 0x0014, | |
1368 | .syss_offs = 0x0018, | |
1369 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1370 | SYSS_HAS_RESET_STATUS), | |
1371 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1372 | }; | |
1373 | ||
1374 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1375 | .name = "hdq1w", | |
1376 | .sysc = &omap44xx_hdq1w_sysc, | |
1377 | }; | |
1378 | ||
1379 | /* hdq1w */ | |
1380 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1381 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1382 | { .irq = -1 } | |
1383 | }; | |
1384 | ||
1385 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1386 | .name = "hdq1w", | |
1387 | .class = &omap44xx_hdq1w_hwmod_class, | |
1388 | .clkdm_name = "l4_per_clkdm", | |
1389 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1390 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
1391 | .main_clk = "hdq1w_fck", | |
1392 | .prcm = { | |
1393 | .omap4 = { | |
1394 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1395 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1396 | .modulemode = MODULEMODE_SWCTRL, | |
1397 | }, | |
1398 | }, | |
1399 | }; | |
1400 | ||
407a6888 BC |
1401 | /* |
1402 | * 'hsi' class | |
1403 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1404 | * serial if) | |
1405 | */ | |
1406 | ||
1407 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1408 | .rev_offs = 0x0000, | |
1409 | .sysc_offs = 0x0010, | |
1410 | .syss_offs = 0x0014, | |
1411 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1412 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1413 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1414 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1415 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1416 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1417 | .sysc_fields = &omap_hwmod_sysc_type1, |
1418 | }; | |
1419 | ||
1420 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1421 | .name = "hsi", | |
1422 | .sysc = &omap44xx_hsi_sysc, | |
1423 | }; | |
1424 | ||
1425 | /* hsi */ | |
1426 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1427 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1428 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1429 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1430 | { .irq = -1 } |
407a6888 BC |
1431 | }; |
1432 | ||
407a6888 BC |
1433 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1434 | .name = "hsi", | |
1435 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1436 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1437 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1438 | .main_clk = "hsi_fck", |
00fe610b | 1439 | .prcm = { |
407a6888 | 1440 | .omap4 = { |
d0f0631d | 1441 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1442 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1443 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1444 | }, |
1445 | }, | |
407a6888 BC |
1446 | }; |
1447 | ||
3b54baad BC |
1448 | /* |
1449 | * 'i2c' class | |
1450 | * multimaster high-speed i2c controller | |
1451 | */ | |
db12ba53 | 1452 | |
3b54baad BC |
1453 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1454 | .sysc_offs = 0x0010, | |
1455 | .syss_offs = 0x0090, | |
1456 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1457 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1458 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1459 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1460 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1461 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1462 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1463 | }; |
1464 | ||
3b54baad | 1465 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1466 | .name = "i2c", |
1467 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1468 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1469 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1470 | }; |
1471 | ||
4d4441a6 AG |
1472 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
1473 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
1474 | }; | |
1475 | ||
3b54baad | 1476 | /* i2c1 */ |
3b54baad BC |
1477 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1478 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1479 | { .irq = -1 } |
db12ba53 BC |
1480 | }; |
1481 | ||
3b54baad BC |
1482 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1483 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1484 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1485 | { .dma_req = -1 } |
db12ba53 BC |
1486 | }; |
1487 | ||
3b54baad BC |
1488 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1489 | .name = "i2c1", | |
1490 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1491 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1492 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1493 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1494 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 1495 | .main_clk = "i2c1_fck", |
92b18d1c BC |
1496 | .prcm = { |
1497 | .omap4 = { | |
d0f0631d | 1498 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1499 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1500 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1501 | }, |
1502 | }, | |
4d4441a6 | 1503 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1504 | }; |
1505 | ||
3b54baad | 1506 | /* i2c2 */ |
3b54baad BC |
1507 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1508 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1509 | { .irq = -1 } |
92b18d1c BC |
1510 | }; |
1511 | ||
3b54baad BC |
1512 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1513 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1514 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1515 | { .dma_req = -1 } |
3b54baad BC |
1516 | }; |
1517 | ||
3b54baad BC |
1518 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1519 | .name = "i2c2", | |
1520 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1521 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1522 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1523 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1524 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 1525 | .main_clk = "i2c2_fck", |
db12ba53 BC |
1526 | .prcm = { |
1527 | .omap4 = { | |
d0f0631d | 1528 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1529 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1530 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1531 | }, |
1532 | }, | |
4d4441a6 | 1533 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1534 | }; |
1535 | ||
3b54baad | 1536 | /* i2c3 */ |
3b54baad BC |
1537 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1538 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1539 | { .irq = -1 } |
db12ba53 BC |
1540 | }; |
1541 | ||
3b54baad BC |
1542 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1543 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1544 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1545 | { .dma_req = -1 } |
92b18d1c BC |
1546 | }; |
1547 | ||
3b54baad BC |
1548 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1549 | .name = "i2c3", | |
1550 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1551 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1552 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1553 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1554 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 1555 | .main_clk = "i2c3_fck", |
db12ba53 BC |
1556 | .prcm = { |
1557 | .omap4 = { | |
d0f0631d | 1558 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1559 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1560 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1561 | }, |
1562 | }, | |
4d4441a6 | 1563 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1564 | }; |
1565 | ||
3b54baad | 1566 | /* i2c4 */ |
3b54baad BC |
1567 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1568 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1569 | { .irq = -1 } |
db12ba53 BC |
1570 | }; |
1571 | ||
3b54baad BC |
1572 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1573 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1574 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1575 | { .dma_req = -1 } |
db12ba53 BC |
1576 | }; |
1577 | ||
3b54baad BC |
1578 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1579 | .name = "i2c4", | |
1580 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1581 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1582 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1583 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1584 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 1585 | .main_clk = "i2c4_fck", |
92b18d1c BC |
1586 | .prcm = { |
1587 | .omap4 = { | |
d0f0631d | 1588 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1589 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1590 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1591 | }, |
1592 | }, | |
4d4441a6 | 1593 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1594 | }; |
1595 | ||
407a6888 BC |
1596 | /* |
1597 | * 'ipu' class | |
1598 | * imaging processor unit | |
1599 | */ | |
1600 | ||
1601 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1602 | .name = "ipu", | |
1603 | }; | |
1604 | ||
1605 | /* ipu */ | |
1606 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1607 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1608 | { .irq = -1 } |
407a6888 BC |
1609 | }; |
1610 | ||
f2f5736c | 1611 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1612 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1613 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1614 | { .name = "mmu_cache", .rst_shift = 2 }, |
1615 | }; | |
1616 | ||
407a6888 BC |
1617 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1618 | .name = "ipu", | |
1619 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1620 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1621 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1622 | .rst_lines = omap44xx_ipu_resets, |
1623 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
1624 | .main_clk = "ipu_fck", | |
00fe610b | 1625 | .prcm = { |
407a6888 | 1626 | .omap4 = { |
d0f0631d | 1627 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1628 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1629 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1630 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1631 | }, |
1632 | }, | |
407a6888 BC |
1633 | }; |
1634 | ||
1635 | /* | |
1636 | * 'iss' class | |
1637 | * external images sensor pixel data processor | |
1638 | */ | |
1639 | ||
1640 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1641 | .rev_offs = 0x0000, | |
1642 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1643 | /* |
1644 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1645 | * accessing sysconfig again. | |
1646 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1647 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1648 | * | |
1649 | * TODO: Indicate errata when available. | |
1650 | */ | |
1651 | .srst_udelay = 2, | |
407a6888 BC |
1652 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1653 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1654 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1655 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1656 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1657 | .sysc_fields = &omap_hwmod_sysc_type2, |
1658 | }; | |
1659 | ||
1660 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1661 | .name = "iss", | |
1662 | .sysc = &omap44xx_iss_sysc, | |
1663 | }; | |
1664 | ||
1665 | /* iss */ | |
1666 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1667 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1668 | { .irq = -1 } |
407a6888 BC |
1669 | }; |
1670 | ||
1671 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1672 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1673 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1674 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1675 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1676 | { .dma_req = -1 } |
407a6888 BC |
1677 | }; |
1678 | ||
407a6888 BC |
1679 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1680 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1681 | }; | |
1682 | ||
1683 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1684 | .name = "iss", | |
1685 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1686 | .clkdm_name = "iss_clkdm", |
407a6888 | 1687 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1688 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 1689 | .main_clk = "iss_fck", |
00fe610b | 1690 | .prcm = { |
407a6888 | 1691 | .omap4 = { |
d0f0631d | 1692 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1693 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1694 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1695 | }, |
1696 | }, | |
1697 | .opt_clks = iss_opt_clks, | |
1698 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1699 | }; |
1700 | ||
8f25bdc5 BC |
1701 | /* |
1702 | * 'iva' class | |
1703 | * multi-standard video encoder/decoder hardware accelerator | |
1704 | */ | |
1705 | ||
1706 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1707 | .name = "iva", |
8f25bdc5 BC |
1708 | }; |
1709 | ||
1710 | /* iva */ | |
1711 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1712 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1713 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1714 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1715 | { .irq = -1 } |
8f25bdc5 BC |
1716 | }; |
1717 | ||
1718 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1719 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1720 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1721 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1722 | }; |
1723 | ||
8f25bdc5 BC |
1724 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1725 | .name = "iva", | |
1726 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1727 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1728 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1729 | .rst_lines = omap44xx_iva_resets, |
1730 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1731 | .main_clk = "iva_fck", | |
1732 | .prcm = { | |
1733 | .omap4 = { | |
d0f0631d | 1734 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1735 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1736 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1737 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1738 | }, |
1739 | }, | |
8f25bdc5 BC |
1740 | }; |
1741 | ||
407a6888 BC |
1742 | /* |
1743 | * 'kbd' class | |
1744 | * keyboard controller | |
1745 | */ | |
1746 | ||
1747 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1748 | .rev_offs = 0x0000, | |
1749 | .sysc_offs = 0x0010, | |
1750 | .syss_offs = 0x0014, | |
1751 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1752 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1753 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1754 | SYSS_HAS_RESET_STATUS), | |
1755 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1756 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1757 | }; | |
1758 | ||
1759 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1760 | .name = "kbd", | |
1761 | .sysc = &omap44xx_kbd_sysc, | |
1762 | }; | |
1763 | ||
1764 | /* kbd */ | |
407a6888 BC |
1765 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1766 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1767 | { .irq = -1 } |
407a6888 BC |
1768 | }; |
1769 | ||
407a6888 BC |
1770 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1771 | .name = "kbd", | |
1772 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1773 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1774 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 1775 | .main_clk = "kbd_fck", |
00fe610b | 1776 | .prcm = { |
407a6888 | 1777 | .omap4 = { |
d0f0631d | 1778 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1779 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1780 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1781 | }, |
1782 | }, | |
407a6888 BC |
1783 | }; |
1784 | ||
ec5df927 BC |
1785 | /* |
1786 | * 'mailbox' class | |
1787 | * mailbox module allowing communication between the on-chip processors using a | |
1788 | * queued mailbox-interrupt mechanism. | |
1789 | */ | |
1790 | ||
1791 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1792 | .rev_offs = 0x0000, | |
1793 | .sysc_offs = 0x0010, | |
1794 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1795 | SYSC_HAS_SOFTRESET), | |
1796 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1797 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1798 | }; | |
1799 | ||
1800 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1801 | .name = "mailbox", | |
1802 | .sysc = &omap44xx_mailbox_sysc, | |
1803 | }; | |
1804 | ||
1805 | /* mailbox */ | |
ec5df927 BC |
1806 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1807 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1808 | { .irq = -1 } |
ec5df927 BC |
1809 | }; |
1810 | ||
ec5df927 BC |
1811 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1812 | .name = "mailbox", | |
1813 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1814 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1815 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1816 | .prcm = { |
ec5df927 | 1817 | .omap4 = { |
d0f0631d | 1818 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1819 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1820 | }, |
1821 | }, | |
ec5df927 BC |
1822 | }; |
1823 | ||
896d4e98 BC |
1824 | /* |
1825 | * 'mcasp' class | |
1826 | * multi-channel audio serial port controller | |
1827 | */ | |
1828 | ||
1829 | /* The IP is not compliant to type1 / type2 scheme */ | |
1830 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1831 | .sidle_shift = 0, | |
1832 | }; | |
1833 | ||
1834 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1835 | .sysc_offs = 0x0004, | |
1836 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1837 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1838 | SIDLE_SMART_WKUP), | |
1839 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1840 | }; | |
1841 | ||
1842 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1843 | .name = "mcasp", | |
1844 | .sysc = &omap44xx_mcasp_sysc, | |
1845 | }; | |
1846 | ||
1847 | /* mcasp */ | |
1848 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | |
1849 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | |
1850 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | |
1851 | { .irq = -1 } | |
1852 | }; | |
1853 | ||
1854 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | |
1855 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | |
1856 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | |
1857 | { .dma_req = -1 } | |
1858 | }; | |
1859 | ||
1860 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | |
1861 | .name = "mcasp", | |
1862 | .class = &omap44xx_mcasp_hwmod_class, | |
1863 | .clkdm_name = "abe_clkdm", | |
1864 | .mpu_irqs = omap44xx_mcasp_irqs, | |
1865 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | |
1866 | .main_clk = "mcasp_fck", | |
1867 | .prcm = { | |
1868 | .omap4 = { | |
1869 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1870 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1871 | .modulemode = MODULEMODE_SWCTRL, | |
1872 | }, | |
1873 | }, | |
1874 | }; | |
1875 | ||
4ddff493 BC |
1876 | /* |
1877 | * 'mcbsp' class | |
1878 | * multi channel buffered serial port controller | |
1879 | */ | |
1880 | ||
1881 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1882 | .sysc_offs = 0x008c, | |
1883 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1884 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1885 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1886 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1887 | }; | |
1888 | ||
1889 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1890 | .name = "mcbsp", | |
1891 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1892 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1893 | }; |
1894 | ||
1895 | /* mcbsp1 */ | |
4ddff493 BC |
1896 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
1897 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1898 | { .irq = -1 } |
4ddff493 BC |
1899 | }; |
1900 | ||
1901 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1902 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1903 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1904 | { .dma_req = -1 } |
4ddff493 BC |
1905 | }; |
1906 | ||
503d0ea2 PW |
1907 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1908 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1909 | { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, | |
1910 | }; | |
1911 | ||
4ddff493 BC |
1912 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1913 | .name = "mcbsp1", | |
1914 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1915 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1916 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1917 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
1918 | .main_clk = "mcbsp1_fck", |
1919 | .prcm = { | |
1920 | .omap4 = { | |
d0f0631d | 1921 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1922 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1923 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1924 | }, |
1925 | }, | |
503d0ea2 PW |
1926 | .opt_clks = mcbsp1_opt_clks, |
1927 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1928 | }; |
1929 | ||
1930 | /* mcbsp2 */ | |
4ddff493 BC |
1931 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
1932 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1933 | { .irq = -1 } |
4ddff493 BC |
1934 | }; |
1935 | ||
1936 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1937 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1938 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1939 | { .dma_req = -1 } |
4ddff493 BC |
1940 | }; |
1941 | ||
844a3b63 PW |
1942 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1943 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1944 | { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, | |
503d0ea2 PW |
1945 | }; |
1946 | ||
4ddff493 BC |
1947 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1948 | .name = "mcbsp2", | |
1949 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1950 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1951 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 1952 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
1953 | .main_clk = "mcbsp2_fck", |
1954 | .prcm = { | |
1955 | .omap4 = { | |
d0f0631d | 1956 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1957 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1958 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1959 | }, |
1960 | }, | |
503d0ea2 PW |
1961 | .opt_clks = mcbsp2_opt_clks, |
1962 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1963 | }; |
1964 | ||
1965 | /* mcbsp3 */ | |
4ddff493 BC |
1966 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
1967 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1968 | { .irq = -1 } |
4ddff493 BC |
1969 | }; |
1970 | ||
1971 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
1972 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
1973 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1974 | { .dma_req = -1 } |
4ddff493 BC |
1975 | }; |
1976 | ||
503d0ea2 PW |
1977 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1978 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1979 | { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, | |
1980 | }; | |
1981 | ||
4ddff493 BC |
1982 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1983 | .name = "mcbsp3", | |
1984 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1985 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1986 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 1987 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
1988 | .main_clk = "mcbsp3_fck", |
1989 | .prcm = { | |
1990 | .omap4 = { | |
d0f0631d | 1991 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1992 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1993 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1994 | }, |
1995 | }, | |
503d0ea2 PW |
1996 | .opt_clks = mcbsp3_opt_clks, |
1997 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1998 | }; |
1999 | ||
2000 | /* mcbsp4 */ | |
4ddff493 BC |
2001 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
2002 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2003 | { .irq = -1 } |
4ddff493 BC |
2004 | }; |
2005 | ||
2006 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
2007 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
2008 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2009 | { .dma_req = -1 } |
4ddff493 BC |
2010 | }; |
2011 | ||
503d0ea2 PW |
2012 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
2013 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
2014 | { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, | |
2015 | }; | |
2016 | ||
4ddff493 BC |
2017 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
2018 | .name = "mcbsp4", | |
2019 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2020 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 2021 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 2022 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
2023 | .main_clk = "mcbsp4_fck", |
2024 | .prcm = { | |
2025 | .omap4 = { | |
d0f0631d | 2026 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 2027 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 2028 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2029 | }, |
2030 | }, | |
503d0ea2 PW |
2031 | .opt_clks = mcbsp4_opt_clks, |
2032 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
2033 | }; |
2034 | ||
407a6888 BC |
2035 | /* |
2036 | * 'mcpdm' class | |
2037 | * multi channel pdm controller (proprietary interface with phoenix power | |
2038 | * ic) | |
2039 | */ | |
2040 | ||
2041 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
2042 | .rev_offs = 0x0000, | |
2043 | .sysc_offs = 0x0010, | |
2044 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2045 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2046 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2047 | SIDLE_SMART_WKUP), | |
2048 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2049 | }; | |
2050 | ||
2051 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
2052 | .name = "mcpdm", | |
2053 | .sysc = &omap44xx_mcpdm_sysc, | |
2054 | }; | |
2055 | ||
2056 | /* mcpdm */ | |
407a6888 BC |
2057 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
2058 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2059 | { .irq = -1 } |
407a6888 BC |
2060 | }; |
2061 | ||
2062 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
2063 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
2064 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2065 | { .dma_req = -1 } |
407a6888 BC |
2066 | }; |
2067 | ||
407a6888 BC |
2068 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
2069 | .name = "mcpdm", | |
2070 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 2071 | .clkdm_name = "abe_clkdm", |
407a6888 | 2072 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 2073 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 2074 | .main_clk = "mcpdm_fck", |
00fe610b | 2075 | .prcm = { |
407a6888 | 2076 | .omap4 = { |
d0f0631d | 2077 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 2078 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 2079 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2080 | }, |
2081 | }, | |
407a6888 BC |
2082 | }; |
2083 | ||
9bcbd7f0 BC |
2084 | /* |
2085 | * 'mcspi' class | |
2086 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2087 | * bus | |
2088 | */ | |
2089 | ||
2090 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
2091 | .rev_offs = 0x0000, | |
2092 | .sysc_offs = 0x0010, | |
2093 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2094 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2095 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2096 | SIDLE_SMART_WKUP), | |
2097 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2098 | }; | |
2099 | ||
2100 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
2101 | .name = "mcspi", | |
2102 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 2103 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
2104 | }; |
2105 | ||
2106 | /* mcspi1 */ | |
9bcbd7f0 BC |
2107 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
2108 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2109 | { .irq = -1 } |
9bcbd7f0 BC |
2110 | }; |
2111 | ||
2112 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
2113 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
2114 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
2115 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
2116 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
2117 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
2118 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
2119 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
2120 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2121 | { .dma_req = -1 } |
9bcbd7f0 BC |
2122 | }; |
2123 | ||
905a74d9 BC |
2124 | /* mcspi1 dev_attr */ |
2125 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
2126 | .num_chipselect = 4, | |
2127 | }; | |
2128 | ||
9bcbd7f0 BC |
2129 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
2130 | .name = "mcspi1", | |
2131 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2132 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2133 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 2134 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
2135 | .main_clk = "mcspi1_fck", |
2136 | .prcm = { | |
2137 | .omap4 = { | |
d0f0631d | 2138 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 2139 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 2140 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2141 | }, |
2142 | }, | |
905a74d9 | 2143 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
2144 | }; |
2145 | ||
2146 | /* mcspi2 */ | |
9bcbd7f0 BC |
2147 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
2148 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2149 | { .irq = -1 } |
9bcbd7f0 BC |
2150 | }; |
2151 | ||
2152 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
2153 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
2154 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
2155 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
2156 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2157 | { .dma_req = -1 } |
9bcbd7f0 BC |
2158 | }; |
2159 | ||
905a74d9 BC |
2160 | /* mcspi2 dev_attr */ |
2161 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
2162 | .num_chipselect = 2, | |
2163 | }; | |
2164 | ||
9bcbd7f0 BC |
2165 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
2166 | .name = "mcspi2", | |
2167 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2168 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2169 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 2170 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
2171 | .main_clk = "mcspi2_fck", |
2172 | .prcm = { | |
2173 | .omap4 = { | |
d0f0631d | 2174 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 2175 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 2176 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2177 | }, |
2178 | }, | |
905a74d9 | 2179 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
2180 | }; |
2181 | ||
2182 | /* mcspi3 */ | |
9bcbd7f0 BC |
2183 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
2184 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2185 | { .irq = -1 } |
9bcbd7f0 BC |
2186 | }; |
2187 | ||
2188 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
2189 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
2190 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
2191 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
2192 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2193 | { .dma_req = -1 } |
9bcbd7f0 BC |
2194 | }; |
2195 | ||
905a74d9 BC |
2196 | /* mcspi3 dev_attr */ |
2197 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
2198 | .num_chipselect = 2, | |
2199 | }; | |
2200 | ||
9bcbd7f0 BC |
2201 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
2202 | .name = "mcspi3", | |
2203 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2204 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2205 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 2206 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
2207 | .main_clk = "mcspi3_fck", |
2208 | .prcm = { | |
2209 | .omap4 = { | |
d0f0631d | 2210 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 2211 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 2212 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2213 | }, |
2214 | }, | |
905a74d9 | 2215 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2216 | }; |
2217 | ||
2218 | /* mcspi4 */ | |
9bcbd7f0 BC |
2219 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
2220 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2221 | { .irq = -1 } |
9bcbd7f0 BC |
2222 | }; |
2223 | ||
2224 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
2225 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2226 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2227 | { .dma_req = -1 } |
9bcbd7f0 BC |
2228 | }; |
2229 | ||
905a74d9 BC |
2230 | /* mcspi4 dev_attr */ |
2231 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2232 | .num_chipselect = 1, | |
2233 | }; | |
2234 | ||
9bcbd7f0 BC |
2235 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2236 | .name = "mcspi4", | |
2237 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2238 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2239 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 2240 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
2241 | .main_clk = "mcspi4_fck", |
2242 | .prcm = { | |
2243 | .omap4 = { | |
d0f0631d | 2244 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2245 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2246 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2247 | }, |
2248 | }, | |
905a74d9 | 2249 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2250 | }; |
2251 | ||
407a6888 BC |
2252 | /* |
2253 | * 'mmc' class | |
2254 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2255 | */ | |
2256 | ||
2257 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2258 | .rev_offs = 0x0000, | |
2259 | .sysc_offs = 0x0010, | |
2260 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2261 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2262 | SYSC_HAS_SOFTRESET), | |
2263 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2264 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2265 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2266 | .sysc_fields = &omap_hwmod_sysc_type2, |
2267 | }; | |
2268 | ||
2269 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2270 | .name = "mmc", | |
2271 | .sysc = &omap44xx_mmc_sysc, | |
2272 | }; | |
2273 | ||
2274 | /* mmc1 */ | |
2275 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
2276 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2277 | { .irq = -1 } |
407a6888 BC |
2278 | }; |
2279 | ||
2280 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
2281 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2282 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2283 | { .dma_req = -1 } |
407a6888 BC |
2284 | }; |
2285 | ||
6ab8946f KK |
2286 | /* mmc1 dev_attr */ |
2287 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
2288 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2289 | }; | |
2290 | ||
407a6888 BC |
2291 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2292 | .name = "mmc1", | |
2293 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2294 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2295 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 2296 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 2297 | .main_clk = "mmc1_fck", |
00fe610b | 2298 | .prcm = { |
407a6888 | 2299 | .omap4 = { |
d0f0631d | 2300 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2301 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2302 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2303 | }, |
2304 | }, | |
6ab8946f | 2305 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2306 | }; |
2307 | ||
2308 | /* mmc2 */ | |
2309 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2310 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2311 | { .irq = -1 } |
407a6888 BC |
2312 | }; |
2313 | ||
2314 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2315 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2316 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2317 | { .dma_req = -1 } |
407a6888 BC |
2318 | }; |
2319 | ||
407a6888 BC |
2320 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2321 | .name = "mmc2", | |
2322 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2323 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2324 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2325 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 2326 | .main_clk = "mmc2_fck", |
00fe610b | 2327 | .prcm = { |
407a6888 | 2328 | .omap4 = { |
d0f0631d | 2329 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2330 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2331 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2332 | }, |
2333 | }, | |
407a6888 BC |
2334 | }; |
2335 | ||
2336 | /* mmc3 */ | |
407a6888 BC |
2337 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2338 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2339 | { .irq = -1 } |
407a6888 BC |
2340 | }; |
2341 | ||
2342 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2343 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2344 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2345 | { .dma_req = -1 } |
407a6888 BC |
2346 | }; |
2347 | ||
407a6888 BC |
2348 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2349 | .name = "mmc3", | |
2350 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2351 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2352 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2353 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 2354 | .main_clk = "mmc3_fck", |
00fe610b | 2355 | .prcm = { |
407a6888 | 2356 | .omap4 = { |
d0f0631d | 2357 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2358 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2359 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2360 | }, |
2361 | }, | |
407a6888 BC |
2362 | }; |
2363 | ||
2364 | /* mmc4 */ | |
407a6888 BC |
2365 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2366 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2367 | { .irq = -1 } |
407a6888 BC |
2368 | }; |
2369 | ||
2370 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2371 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2372 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2373 | { .dma_req = -1 } |
407a6888 BC |
2374 | }; |
2375 | ||
407a6888 BC |
2376 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2377 | .name = "mmc4", | |
2378 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2379 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2380 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2381 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 2382 | .main_clk = "mmc4_fck", |
00fe610b | 2383 | .prcm = { |
407a6888 | 2384 | .omap4 = { |
d0f0631d | 2385 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2386 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2387 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2388 | }, |
2389 | }, | |
407a6888 BC |
2390 | }; |
2391 | ||
2392 | /* mmc5 */ | |
407a6888 BC |
2393 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2394 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2395 | { .irq = -1 } |
407a6888 BC |
2396 | }; |
2397 | ||
2398 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2399 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2400 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2401 | { .dma_req = -1 } |
407a6888 BC |
2402 | }; |
2403 | ||
407a6888 BC |
2404 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2405 | .name = "mmc5", | |
2406 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2407 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2408 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2409 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 2410 | .main_clk = "mmc5_fck", |
00fe610b | 2411 | .prcm = { |
407a6888 | 2412 | .omap4 = { |
d0f0631d | 2413 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2414 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2415 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2416 | }, |
2417 | }, | |
407a6888 BC |
2418 | }; |
2419 | ||
3b54baad BC |
2420 | /* |
2421 | * 'mpu' class | |
2422 | * mpu sub-system | |
2423 | */ | |
2424 | ||
2425 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2426 | .name = "mpu", |
db12ba53 BC |
2427 | }; |
2428 | ||
3b54baad BC |
2429 | /* mpu */ |
2430 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
2431 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
2432 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2433 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2434 | { .irq = -1 } |
db12ba53 BC |
2435 | }; |
2436 | ||
3b54baad BC |
2437 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2438 | .name = "mpu", | |
2439 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2440 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2441 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2442 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2443 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2444 | .prcm = { |
2445 | .omap4 = { | |
d0f0631d | 2446 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2447 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2448 | }, |
2449 | }, | |
db12ba53 BC |
2450 | }; |
2451 | ||
e17f18c0 PW |
2452 | /* |
2453 | * 'ocmc_ram' class | |
2454 | * top-level core on-chip ram | |
2455 | */ | |
2456 | ||
2457 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2458 | .name = "ocmc_ram", | |
2459 | }; | |
2460 | ||
2461 | /* ocmc_ram */ | |
2462 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2463 | .name = "ocmc_ram", | |
2464 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2465 | .clkdm_name = "l3_2_clkdm", | |
2466 | .prcm = { | |
2467 | .omap4 = { | |
2468 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2469 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2470 | }, | |
2471 | }, | |
2472 | }; | |
2473 | ||
0c668875 BC |
2474 | /* |
2475 | * 'ocp2scp' class | |
2476 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2477 | * protocol | |
2478 | */ | |
2479 | ||
2480 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { | |
2481 | .name = "ocp2scp", | |
2482 | }; | |
2483 | ||
2484 | /* ocp2scp_usb_phy */ | |
2485 | static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { | |
2486 | { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, | |
2487 | }; | |
2488 | ||
2489 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | |
2490 | .name = "ocp2scp_usb_phy", | |
2491 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2492 | .clkdm_name = "l3_init_clkdm", | |
2493 | .prcm = { | |
2494 | .omap4 = { | |
2495 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2496 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2497 | .modulemode = MODULEMODE_HWCTRL, | |
2498 | }, | |
2499 | }, | |
2500 | .opt_clks = ocp2scp_usb_phy_opt_clks, | |
2501 | .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), | |
2502 | }; | |
2503 | ||
794b480a PW |
2504 | /* |
2505 | * 'prcm' class | |
2506 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2507 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2508 | */ | |
2509 | ||
2510 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2511 | .name = "prcm", | |
2512 | }; | |
2513 | ||
2514 | /* prcm_mpu */ | |
2515 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2516 | .name = "prcm_mpu", | |
2517 | .class = &omap44xx_prcm_hwmod_class, | |
2518 | .clkdm_name = "l4_wkup_clkdm", | |
2519 | }; | |
2520 | ||
2521 | /* cm_core_aon */ | |
2522 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2523 | .name = "cm_core_aon", | |
2524 | .class = &omap44xx_prcm_hwmod_class, | |
2525 | .clkdm_name = "cm_clkdm", | |
2526 | }; | |
2527 | ||
2528 | /* cm_core */ | |
2529 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2530 | .name = "cm_core", | |
2531 | .class = &omap44xx_prcm_hwmod_class, | |
2532 | .clkdm_name = "cm_clkdm", | |
2533 | }; | |
2534 | ||
2535 | /* prm */ | |
2536 | static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { | |
2537 | { .irq = 11 + OMAP44XX_IRQ_GIC_START }, | |
2538 | { .irq = -1 } | |
2539 | }; | |
2540 | ||
2541 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |
2542 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2543 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2544 | }; | |
2545 | ||
2546 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2547 | .name = "prm", | |
2548 | .class = &omap44xx_prcm_hwmod_class, | |
2549 | .clkdm_name = "prm_clkdm", | |
2550 | .mpu_irqs = omap44xx_prm_irqs, | |
2551 | .rst_lines = omap44xx_prm_resets, | |
2552 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2553 | }; | |
2554 | ||
2555 | /* | |
2556 | * 'scrm' class | |
2557 | * system clock and reset manager | |
2558 | */ | |
2559 | ||
2560 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2561 | .name = "scrm", | |
2562 | }; | |
2563 | ||
2564 | /* scrm */ | |
2565 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2566 | .name = "scrm", | |
2567 | .class = &omap44xx_scrm_hwmod_class, | |
2568 | .clkdm_name = "l4_wkup_clkdm", | |
2569 | }; | |
2570 | ||
42b9e387 PW |
2571 | /* |
2572 | * 'sl2if' class | |
2573 | * shared level 2 memory interface | |
2574 | */ | |
2575 | ||
2576 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2577 | .name = "sl2if", | |
2578 | }; | |
2579 | ||
2580 | /* sl2if */ | |
2581 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2582 | .name = "sl2if", | |
2583 | .class = &omap44xx_sl2if_hwmod_class, | |
2584 | .clkdm_name = "ivahd_clkdm", | |
2585 | .prcm = { | |
2586 | .omap4 = { | |
2587 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2588 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2589 | .modulemode = MODULEMODE_HWCTRL, | |
2590 | }, | |
2591 | }, | |
2592 | }; | |
2593 | ||
1e3b5e59 BC |
2594 | /* |
2595 | * 'slimbus' class | |
2596 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2597 | * the device and external components | |
2598 | */ | |
2599 | ||
2600 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2601 | .rev_offs = 0x0000, | |
2602 | .sysc_offs = 0x0010, | |
2603 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2604 | SYSC_HAS_SOFTRESET), | |
2605 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2606 | SIDLE_SMART_WKUP), | |
2607 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2608 | }; | |
2609 | ||
2610 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2611 | .name = "slimbus", | |
2612 | .sysc = &omap44xx_slimbus_sysc, | |
2613 | }; | |
2614 | ||
2615 | /* slimbus1 */ | |
2616 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | |
2617 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | |
2618 | { .irq = -1 } | |
2619 | }; | |
2620 | ||
2621 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | |
2622 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | |
2623 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | |
2624 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | |
2625 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | |
2626 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | |
2627 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | |
2628 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | |
2629 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | |
2630 | { .dma_req = -1 } | |
2631 | }; | |
2632 | ||
2633 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | |
2634 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2635 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2636 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2637 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2638 | }; | |
2639 | ||
2640 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2641 | .name = "slimbus1", | |
2642 | .class = &omap44xx_slimbus_hwmod_class, | |
2643 | .clkdm_name = "abe_clkdm", | |
2644 | .mpu_irqs = omap44xx_slimbus1_irqs, | |
2645 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | |
2646 | .prcm = { | |
2647 | .omap4 = { | |
2648 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2649 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2650 | .modulemode = MODULEMODE_SWCTRL, | |
2651 | }, | |
2652 | }, | |
2653 | .opt_clks = slimbus1_opt_clks, | |
2654 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2655 | }; | |
2656 | ||
2657 | /* slimbus2 */ | |
2658 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | |
2659 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | |
2660 | { .irq = -1 } | |
2661 | }; | |
2662 | ||
2663 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | |
2664 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | |
2665 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | |
2666 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | |
2667 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | |
2668 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | |
2669 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | |
2670 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | |
2671 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | |
2672 | { .dma_req = -1 } | |
2673 | }; | |
2674 | ||
2675 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | |
2676 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2677 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2678 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2679 | }; | |
2680 | ||
2681 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2682 | .name = "slimbus2", | |
2683 | .class = &omap44xx_slimbus_hwmod_class, | |
2684 | .clkdm_name = "l4_per_clkdm", | |
2685 | .mpu_irqs = omap44xx_slimbus2_irqs, | |
2686 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | |
2687 | .prcm = { | |
2688 | .omap4 = { | |
2689 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2690 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2691 | .modulemode = MODULEMODE_SWCTRL, | |
2692 | }, | |
2693 | }, | |
2694 | .opt_clks = slimbus2_opt_clks, | |
2695 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2696 | }; | |
2697 | ||
1f6a717f BC |
2698 | /* |
2699 | * 'smartreflex' class | |
2700 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2701 | * performance error) | |
2702 | */ | |
2703 | ||
2704 | /* The IP is not compliant to type1 / type2 scheme */ | |
2705 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2706 | .sidle_shift = 24, | |
2707 | .enwkup_shift = 26, | |
2708 | }; | |
2709 | ||
2710 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2711 | .sysc_offs = 0x0038, | |
2712 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2713 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2714 | SIDLE_SMART_WKUP), | |
2715 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2716 | }; | |
2717 | ||
2718 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2719 | .name = "smartreflex", |
2720 | .sysc = &omap44xx_smartreflex_sysc, | |
2721 | .rev = 2, | |
1f6a717f BC |
2722 | }; |
2723 | ||
2724 | /* smartreflex_core */ | |
cea6b942 SG |
2725 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2726 | .sensor_voltdm_name = "core", | |
2727 | }; | |
2728 | ||
1f6a717f BC |
2729 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2730 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2731 | { .irq = -1 } |
1f6a717f BC |
2732 | }; |
2733 | ||
1f6a717f BC |
2734 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2735 | .name = "smartreflex_core", | |
2736 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2737 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2738 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2739 | |
1f6a717f | 2740 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2741 | .prcm = { |
2742 | .omap4 = { | |
d0f0631d | 2743 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2744 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2745 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2746 | }, |
2747 | }, | |
cea6b942 | 2748 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2749 | }; |
2750 | ||
2751 | /* smartreflex_iva */ | |
cea6b942 SG |
2752 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2753 | .sensor_voltdm_name = "iva", | |
2754 | }; | |
2755 | ||
1f6a717f BC |
2756 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
2757 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2758 | { .irq = -1 } |
1f6a717f BC |
2759 | }; |
2760 | ||
1f6a717f BC |
2761 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2762 | .name = "smartreflex_iva", | |
2763 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2764 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2765 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 2766 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2767 | .prcm = { |
2768 | .omap4 = { | |
d0f0631d | 2769 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2770 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2771 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2772 | }, |
2773 | }, | |
cea6b942 | 2774 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2775 | }; |
2776 | ||
2777 | /* smartreflex_mpu */ | |
cea6b942 SG |
2778 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2779 | .sensor_voltdm_name = "mpu", | |
2780 | }; | |
2781 | ||
1f6a717f BC |
2782 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
2783 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2784 | { .irq = -1 } |
1f6a717f BC |
2785 | }; |
2786 | ||
1f6a717f BC |
2787 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2788 | .name = "smartreflex_mpu", | |
2789 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2790 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2791 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 2792 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2793 | .prcm = { |
2794 | .omap4 = { | |
d0f0631d | 2795 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2796 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2797 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2798 | }, |
2799 | }, | |
cea6b942 | 2800 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2801 | }; |
2802 | ||
d11c217f BC |
2803 | /* |
2804 | * 'spinlock' class | |
2805 | * spinlock provides hardware assistance for synchronizing the processes | |
2806 | * running on multiple processors | |
2807 | */ | |
2808 | ||
2809 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2810 | .rev_offs = 0x0000, | |
2811 | .sysc_offs = 0x0010, | |
2812 | .syss_offs = 0x0014, | |
2813 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2814 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2815 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2816 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2817 | SIDLE_SMART_WKUP), | |
2818 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2819 | }; | |
2820 | ||
2821 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2822 | .name = "spinlock", | |
2823 | .sysc = &omap44xx_spinlock_sysc, | |
2824 | }; | |
2825 | ||
2826 | /* spinlock */ | |
d11c217f BC |
2827 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2828 | .name = "spinlock", | |
2829 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2830 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2831 | .prcm = { |
2832 | .omap4 = { | |
d0f0631d | 2833 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2834 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2835 | }, |
2836 | }, | |
d11c217f BC |
2837 | }; |
2838 | ||
35d1a66a BC |
2839 | /* |
2840 | * 'timer' class | |
2841 | * general purpose timer module with accurate 1ms tick | |
2842 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2843 | */ | |
2844 | ||
2845 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2846 | .rev_offs = 0x0000, | |
2847 | .sysc_offs = 0x0010, | |
2848 | .syss_offs = 0x0014, | |
2849 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2850 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2851 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2852 | SYSS_HAS_RESET_STATUS), | |
2853 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2854 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2855 | }; | |
2856 | ||
2857 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2858 | .name = "timer", | |
2859 | .sysc = &omap44xx_timer_1ms_sysc, | |
2860 | }; | |
2861 | ||
2862 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2863 | .rev_offs = 0x0000, | |
2864 | .sysc_offs = 0x0010, | |
2865 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2866 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2867 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2868 | SIDLE_SMART_WKUP), | |
2869 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2870 | }; | |
2871 | ||
2872 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2873 | .name = "timer", | |
2874 | .sysc = &omap44xx_timer_sysc, | |
2875 | }; | |
2876 | ||
c345c8b0 TKD |
2877 | /* always-on timers dev attribute */ |
2878 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2879 | .timer_capability = OMAP_TIMER_ALWON, | |
2880 | }; | |
2881 | ||
2882 | /* pwm timers dev attribute */ | |
2883 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2884 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2885 | }; | |
2886 | ||
35d1a66a | 2887 | /* timer1 */ |
35d1a66a BC |
2888 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
2889 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2890 | { .irq = -1 } |
35d1a66a BC |
2891 | }; |
2892 | ||
35d1a66a BC |
2893 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2894 | .name = "timer1", | |
2895 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2896 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 2897 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
2898 | .main_clk = "timer1_fck", |
2899 | .prcm = { | |
2900 | .omap4 = { | |
d0f0631d | 2901 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2902 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2903 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2904 | }, |
2905 | }, | |
c345c8b0 | 2906 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2907 | }; |
2908 | ||
2909 | /* timer2 */ | |
35d1a66a BC |
2910 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
2911 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2912 | { .irq = -1 } |
35d1a66a BC |
2913 | }; |
2914 | ||
35d1a66a BC |
2915 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2916 | .name = "timer2", | |
2917 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2918 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2919 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
2920 | .main_clk = "timer2_fck", |
2921 | .prcm = { | |
2922 | .omap4 = { | |
d0f0631d | 2923 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2924 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2925 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2926 | }, |
2927 | }, | |
c345c8b0 | 2928 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2929 | }; |
2930 | ||
2931 | /* timer3 */ | |
35d1a66a BC |
2932 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
2933 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2934 | { .irq = -1 } |
35d1a66a BC |
2935 | }; |
2936 | ||
35d1a66a BC |
2937 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2938 | .name = "timer3", | |
2939 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2940 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2941 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
2942 | .main_clk = "timer3_fck", |
2943 | .prcm = { | |
2944 | .omap4 = { | |
d0f0631d | 2945 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2946 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2947 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2948 | }, |
2949 | }, | |
c345c8b0 | 2950 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2951 | }; |
2952 | ||
2953 | /* timer4 */ | |
35d1a66a BC |
2954 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
2955 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2956 | { .irq = -1 } |
35d1a66a BC |
2957 | }; |
2958 | ||
35d1a66a BC |
2959 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2960 | .name = "timer4", | |
2961 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2962 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2963 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
2964 | .main_clk = "timer4_fck", |
2965 | .prcm = { | |
2966 | .omap4 = { | |
d0f0631d | 2967 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2968 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2969 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2970 | }, |
2971 | }, | |
c345c8b0 | 2972 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2973 | }; |
2974 | ||
2975 | /* timer5 */ | |
35d1a66a BC |
2976 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
2977 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2978 | { .irq = -1 } |
35d1a66a BC |
2979 | }; |
2980 | ||
35d1a66a BC |
2981 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2982 | .name = "timer5", | |
2983 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2984 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2985 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
2986 | .main_clk = "timer5_fck", |
2987 | .prcm = { | |
2988 | .omap4 = { | |
d0f0631d | 2989 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2990 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2991 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2992 | }, |
2993 | }, | |
c345c8b0 | 2994 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2995 | }; |
2996 | ||
2997 | /* timer6 */ | |
35d1a66a BC |
2998 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
2999 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3000 | { .irq = -1 } |
35d1a66a BC |
3001 | }; |
3002 | ||
35d1a66a BC |
3003 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
3004 | .name = "timer6", | |
3005 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3006 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3007 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 3008 | |
35d1a66a BC |
3009 | .main_clk = "timer6_fck", |
3010 | .prcm = { | |
3011 | .omap4 = { | |
d0f0631d | 3012 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 3013 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 3014 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3015 | }, |
3016 | }, | |
c345c8b0 | 3017 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
3018 | }; |
3019 | ||
3020 | /* timer7 */ | |
35d1a66a BC |
3021 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
3022 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3023 | { .irq = -1 } |
35d1a66a BC |
3024 | }; |
3025 | ||
35d1a66a BC |
3026 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
3027 | .name = "timer7", | |
3028 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3029 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3030 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
3031 | .main_clk = "timer7_fck", |
3032 | .prcm = { | |
3033 | .omap4 = { | |
d0f0631d | 3034 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 3035 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 3036 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3037 | }, |
3038 | }, | |
c345c8b0 | 3039 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
3040 | }; |
3041 | ||
3042 | /* timer8 */ | |
35d1a66a BC |
3043 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
3044 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3045 | { .irq = -1 } |
35d1a66a BC |
3046 | }; |
3047 | ||
35d1a66a BC |
3048 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
3049 | .name = "timer8", | |
3050 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3051 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3052 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
3053 | .main_clk = "timer8_fck", |
3054 | .prcm = { | |
3055 | .omap4 = { | |
d0f0631d | 3056 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 3057 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 3058 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3059 | }, |
3060 | }, | |
c345c8b0 | 3061 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3062 | }; |
3063 | ||
3064 | /* timer9 */ | |
35d1a66a BC |
3065 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
3066 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3067 | { .irq = -1 } |
35d1a66a BC |
3068 | }; |
3069 | ||
35d1a66a BC |
3070 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
3071 | .name = "timer9", | |
3072 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3073 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3074 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
3075 | .main_clk = "timer9_fck", |
3076 | .prcm = { | |
3077 | .omap4 = { | |
d0f0631d | 3078 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 3079 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 3080 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3081 | }, |
3082 | }, | |
c345c8b0 | 3083 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3084 | }; |
3085 | ||
3086 | /* timer10 */ | |
35d1a66a BC |
3087 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
3088 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3089 | { .irq = -1 } |
35d1a66a BC |
3090 | }; |
3091 | ||
35d1a66a BC |
3092 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
3093 | .name = "timer10", | |
3094 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3095 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3096 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
3097 | .main_clk = "timer10_fck", |
3098 | .prcm = { | |
3099 | .omap4 = { | |
d0f0631d | 3100 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 3101 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 3102 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3103 | }, |
3104 | }, | |
c345c8b0 | 3105 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3106 | }; |
3107 | ||
3108 | /* timer11 */ | |
35d1a66a BC |
3109 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
3110 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3111 | { .irq = -1 } |
35d1a66a BC |
3112 | }; |
3113 | ||
35d1a66a BC |
3114 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
3115 | .name = "timer11", | |
3116 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3117 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3118 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
3119 | .main_clk = "timer11_fck", |
3120 | .prcm = { | |
3121 | .omap4 = { | |
d0f0631d | 3122 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 3123 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 3124 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3125 | }, |
3126 | }, | |
c345c8b0 | 3127 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3128 | }; |
3129 | ||
9780a9cf | 3130 | /* |
3b54baad BC |
3131 | * 'uart' class |
3132 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
3133 | */ |
3134 | ||
3b54baad BC |
3135 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
3136 | .rev_offs = 0x0050, | |
3137 | .sysc_offs = 0x0054, | |
3138 | .syss_offs = 0x0058, | |
3139 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
3140 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
3141 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
3142 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3143 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
3144 | .sysc_fields = &omap_hwmod_sysc_type1, |
3145 | }; | |
3146 | ||
3b54baad | 3147 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
3148 | .name = "uart", |
3149 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
3150 | }; |
3151 | ||
3b54baad | 3152 | /* uart1 */ |
3b54baad BC |
3153 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
3154 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3155 | { .irq = -1 } |
9780a9cf BC |
3156 | }; |
3157 | ||
3b54baad BC |
3158 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
3159 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
3160 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3161 | { .dma_req = -1 } |
9780a9cf BC |
3162 | }; |
3163 | ||
3b54baad BC |
3164 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
3165 | .name = "uart1", | |
3166 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3167 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3168 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 3169 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 3170 | .main_clk = "uart1_fck", |
9780a9cf BC |
3171 | .prcm = { |
3172 | .omap4 = { | |
d0f0631d | 3173 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 3174 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 3175 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3176 | }, |
3177 | }, | |
9780a9cf BC |
3178 | }; |
3179 | ||
3b54baad | 3180 | /* uart2 */ |
3b54baad BC |
3181 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
3182 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3183 | { .irq = -1 } |
9780a9cf BC |
3184 | }; |
3185 | ||
3b54baad BC |
3186 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
3187 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
3188 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3189 | { .dma_req = -1 } |
3b54baad BC |
3190 | }; |
3191 | ||
3b54baad BC |
3192 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
3193 | .name = "uart2", | |
3194 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3195 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3196 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 3197 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 3198 | .main_clk = "uart2_fck", |
9780a9cf BC |
3199 | .prcm = { |
3200 | .omap4 = { | |
d0f0631d | 3201 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 3202 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 3203 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3204 | }, |
3205 | }, | |
9780a9cf BC |
3206 | }; |
3207 | ||
3b54baad | 3208 | /* uart3 */ |
3b54baad BC |
3209 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
3210 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3211 | { .irq = -1 } |
9780a9cf BC |
3212 | }; |
3213 | ||
3b54baad BC |
3214 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
3215 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
3216 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3217 | { .dma_req = -1 } |
3b54baad BC |
3218 | }; |
3219 | ||
3b54baad BC |
3220 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
3221 | .name = "uart3", | |
3222 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3223 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 3224 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3225 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 3226 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 3227 | .main_clk = "uart3_fck", |
9780a9cf BC |
3228 | .prcm = { |
3229 | .omap4 = { | |
d0f0631d | 3230 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 3231 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 3232 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3233 | }, |
3234 | }, | |
9780a9cf BC |
3235 | }; |
3236 | ||
3b54baad | 3237 | /* uart4 */ |
3b54baad BC |
3238 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
3239 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3240 | { .irq = -1 } |
9780a9cf BC |
3241 | }; |
3242 | ||
3b54baad BC |
3243 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
3244 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
3245 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3246 | { .dma_req = -1 } |
3b54baad BC |
3247 | }; |
3248 | ||
3b54baad BC |
3249 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
3250 | .name = "uart4", | |
3251 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3252 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3253 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 3254 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 3255 | .main_clk = "uart4_fck", |
9780a9cf BC |
3256 | .prcm = { |
3257 | .omap4 = { | |
d0f0631d | 3258 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 3259 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 3260 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3261 | }, |
3262 | }, | |
9780a9cf BC |
3263 | }; |
3264 | ||
0c668875 BC |
3265 | /* |
3266 | * 'usb_host_fs' class | |
3267 | * full-speed usb host controller | |
3268 | */ | |
3269 | ||
3270 | /* The IP is not compliant to type1 / type2 scheme */ | |
3271 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
3272 | .midle_shift = 4, | |
3273 | .sidle_shift = 2, | |
3274 | .srst_shift = 1, | |
3275 | }; | |
3276 | ||
3277 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
3278 | .rev_offs = 0x0000, | |
3279 | .sysc_offs = 0x0210, | |
3280 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3281 | SYSC_HAS_SOFTRESET), | |
3282 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3283 | SIDLE_SMART_WKUP), | |
3284 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
3285 | }; | |
3286 | ||
3287 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
3288 | .name = "usb_host_fs", | |
3289 | .sysc = &omap44xx_usb_host_fs_sysc, | |
3290 | }; | |
3291 | ||
3292 | /* usb_host_fs */ | |
3293 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | |
3294 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | |
3295 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | |
3296 | { .irq = -1 } | |
3297 | }; | |
3298 | ||
3299 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | |
3300 | .name = "usb_host_fs", | |
3301 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
3302 | .clkdm_name = "l3_init_clkdm", | |
3303 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | |
3304 | .main_clk = "usb_host_fs_fck", | |
3305 | .prcm = { | |
3306 | .omap4 = { | |
3307 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
3308 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
3309 | .modulemode = MODULEMODE_SWCTRL, | |
3310 | }, | |
3311 | }, | |
3312 | }; | |
3313 | ||
5844c4ea | 3314 | /* |
844a3b63 PW |
3315 | * 'usb_host_hs' class |
3316 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3317 | */ |
3318 | ||
844a3b63 PW |
3319 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3320 | .rev_offs = 0x0000, | |
3321 | .sysc_offs = 0x0010, | |
3322 | .syss_offs = 0x0014, | |
3323 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3324 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
3325 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3326 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3327 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3328 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3329 | }; |
3330 | ||
844a3b63 PW |
3331 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3332 | .name = "usb_host_hs", | |
3333 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3334 | }; |
3335 | ||
844a3b63 PW |
3336 | /* usb_host_hs */ |
3337 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
3338 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
3339 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3340 | { .irq = -1 } |
5844c4ea BC |
3341 | }; |
3342 | ||
844a3b63 PW |
3343 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3344 | .name = "usb_host_hs", | |
3345 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3346 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3347 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3348 | .prcm = { |
3349 | .omap4 = { | |
844a3b63 PW |
3350 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3351 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3352 | .modulemode = MODULEMODE_SWCTRL, | |
3353 | }, | |
3354 | }, | |
3355 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
3356 | ||
3357 | /* | |
3358 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3359 | * id: i660 | |
3360 | * | |
3361 | * Description: | |
3362 | * In the following configuration : | |
3363 | * - USBHOST module is set to smart-idle mode | |
3364 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3365 | * happens when the system is going to a low power mode : all ports | |
3366 | * have been suspended, the master part of the USBHOST module has | |
3367 | * entered the standby state, and SW has cut the functional clocks) | |
3368 | * - an USBHOST interrupt occurs before the module is able to answer | |
3369 | * idle_ack, typically a remote wakeup IRQ. | |
3370 | * Then the USB HOST module will enter a deadlock situation where it | |
3371 | * is no more accessible nor functional. | |
3372 | * | |
3373 | * Workaround: | |
3374 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3375 | */ | |
3376 | ||
3377 | /* | |
3378 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3379 | * Id: i571 | |
3380 | * | |
3381 | * Description: | |
3382 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3383 | * ready to enter the standby state (i.e. all ports are suspended and | |
3384 | * all attached devices are in suspend mode), then it can wrongly assert | |
3385 | * the Mstandby signal too early while there are still some residual OCP | |
3386 | * transactions ongoing. If this condition occurs, the internal state | |
3387 | * machine may go to an undefined state and the USB link may be stuck | |
3388 | * upon the next resume. | |
3389 | * | |
3390 | * Workaround: | |
3391 | * Don't use smart standby; use only force standby, | |
3392 | * hence HWMOD_SWSUP_MSTANDBY | |
3393 | */ | |
3394 | ||
3395 | /* | |
3396 | * During system boot; If the hwmod framework resets the module | |
3397 | * the module will have smart idle settings; which can lead to deadlock | |
3398 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3399 | * Use HWMOD_INIT_NO_RESET. | |
3400 | */ | |
3401 | ||
3402 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3403 | HWMOD_INIT_NO_RESET, | |
3404 | }; | |
3405 | ||
3406 | /* | |
3407 | * 'usb_otg_hs' class | |
3408 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3409 | */ | |
3410 | ||
3411 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3412 | .rev_offs = 0x0400, | |
3413 | .sysc_offs = 0x0404, | |
3414 | .syss_offs = 0x0408, | |
3415 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3416 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3417 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3418 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3419 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3420 | MSTANDBY_SMART), | |
3421 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3422 | }; | |
3423 | ||
3424 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3425 | .name = "usb_otg_hs", | |
3426 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3427 | }; | |
3428 | ||
3429 | /* usb_otg_hs */ | |
3430 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
3431 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
3432 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
3433 | { .irq = -1 } | |
3434 | }; | |
3435 | ||
3436 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
3437 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3438 | }; | |
3439 | ||
3440 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3441 | .name = "usb_otg_hs", | |
3442 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3443 | .clkdm_name = "l3_init_clkdm", | |
3444 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
3445 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
3446 | .main_clk = "usb_otg_hs_ick", | |
3447 | .prcm = { | |
3448 | .omap4 = { | |
3449 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3450 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3451 | .modulemode = MODULEMODE_HWCTRL, | |
3452 | }, | |
3453 | }, | |
3454 | .opt_clks = usb_otg_hs_opt_clks, | |
3455 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3456 | }; | |
3457 | ||
3458 | /* | |
3459 | * 'usb_tll_hs' class | |
3460 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3461 | */ | |
3462 | ||
3463 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3464 | .rev_offs = 0x0000, | |
3465 | .sysc_offs = 0x0010, | |
3466 | .syss_offs = 0x0014, | |
3467 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3468 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3469 | SYSC_HAS_AUTOIDLE), | |
3470 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3471 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3472 | }; | |
3473 | ||
3474 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3475 | .name = "usb_tll_hs", | |
3476 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3477 | }; | |
3478 | ||
3479 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
3480 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
3481 | { .irq = -1 } | |
3482 | }; | |
3483 | ||
3484 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
3485 | .name = "usb_tll_hs", | |
3486 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3487 | .clkdm_name = "l3_init_clkdm", | |
3488 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
3489 | .main_clk = "usb_tll_hs_ick", | |
3490 | .prcm = { | |
3491 | .omap4 = { | |
3492 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3493 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3494 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3495 | }, |
3496 | }, | |
5844c4ea BC |
3497 | }; |
3498 | ||
3b54baad BC |
3499 | /* |
3500 | * 'wd_timer' class | |
3501 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3502 | * overflow condition | |
3503 | */ | |
3504 | ||
3505 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3506 | .rev_offs = 0x0000, | |
3507 | .sysc_offs = 0x0010, | |
3508 | .syss_offs = 0x0014, | |
3509 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3510 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3511 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3512 | SIDLE_SMART_WKUP), | |
3b54baad | 3513 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3514 | }; |
3515 | ||
3b54baad BC |
3516 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3517 | .name = "wd_timer", | |
3518 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3519 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
3520 | }; |
3521 | ||
3522 | /* wd_timer2 */ | |
3b54baad BC |
3523 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
3524 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3525 | { .irq = -1 } |
3b54baad BC |
3526 | }; |
3527 | ||
3b54baad BC |
3528 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3529 | .name = "wd_timer2", | |
3530 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3531 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 3532 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 3533 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
3534 | .prcm = { |
3535 | .omap4 = { | |
d0f0631d | 3536 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3537 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3538 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3539 | }, |
3540 | }, | |
9780a9cf BC |
3541 | }; |
3542 | ||
3b54baad | 3543 | /* wd_timer3 */ |
3b54baad BC |
3544 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
3545 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3546 | { .irq = -1 } |
9780a9cf BC |
3547 | }; |
3548 | ||
3b54baad BC |
3549 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3550 | .name = "wd_timer3", | |
3551 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3552 | .clkdm_name = "abe_clkdm", |
3b54baad | 3553 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 3554 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
3555 | .prcm = { |
3556 | .omap4 = { | |
d0f0631d | 3557 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3558 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3559 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3560 | }, |
3561 | }, | |
9780a9cf | 3562 | }; |
531ce0d5 | 3563 | |
844a3b63 | 3564 | |
af88fa9a | 3565 | /* |
844a3b63 | 3566 | * interfaces |
af88fa9a | 3567 | */ |
af88fa9a | 3568 | |
42b9e387 PW |
3569 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { |
3570 | { | |
3571 | .pa_start = 0x4a204000, | |
3572 | .pa_end = 0x4a2040ff, | |
3573 | .flags = ADDR_TYPE_RT | |
3574 | }, | |
3575 | { } | |
3576 | }; | |
3577 | ||
3578 | /* c2c -> c2c_target_fw */ | |
3579 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | |
3580 | .master = &omap44xx_c2c_hwmod, | |
3581 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3582 | .clk = "div_core_ck", | |
3583 | .addr = omap44xx_c2c_target_fw_addrs, | |
3584 | .user = OCP_USER_MPU, | |
3585 | }; | |
3586 | ||
3587 | /* l4_cfg -> c2c_target_fw */ | |
3588 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | |
3589 | .master = &omap44xx_l4_cfg_hwmod, | |
3590 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3591 | .clk = "l4_div_ck", | |
3592 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3593 | }; | |
3594 | ||
844a3b63 PW |
3595 | /* l3_main_1 -> dmm */ |
3596 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3597 | .master = &omap44xx_l3_main_1_hwmod, | |
3598 | .slave = &omap44xx_dmm_hwmod, | |
3599 | .clk = "l3_div_ck", | |
3600 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3601 | }; |
3602 | ||
844a3b63 | 3603 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 3604 | { |
844a3b63 PW |
3605 | .pa_start = 0x4e000000, |
3606 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
3607 | .flags = ADDR_TYPE_RT |
3608 | }, | |
844a3b63 | 3609 | { } |
af88fa9a BC |
3610 | }; |
3611 | ||
844a3b63 PW |
3612 | /* mpu -> dmm */ |
3613 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3614 | .master = &omap44xx_mpu_hwmod, | |
3615 | .slave = &omap44xx_dmm_hwmod, | |
3616 | .clk = "l3_div_ck", | |
3617 | .addr = omap44xx_dmm_addrs, | |
3618 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3619 | }; |
3620 | ||
42b9e387 PW |
3621 | /* c2c -> emif_fw */ |
3622 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | |
3623 | .master = &omap44xx_c2c_hwmod, | |
3624 | .slave = &omap44xx_emif_fw_hwmod, | |
3625 | .clk = "div_core_ck", | |
3626 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3627 | }; | |
3628 | ||
844a3b63 PW |
3629 | /* dmm -> emif_fw */ |
3630 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3631 | .master = &omap44xx_dmm_hwmod, | |
3632 | .slave = &omap44xx_emif_fw_hwmod, | |
3633 | .clk = "l3_div_ck", | |
3634 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3635 | }; | |
3636 | ||
3637 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3638 | { | |
3639 | .pa_start = 0x4a20c000, | |
3640 | .pa_end = 0x4a20c0ff, | |
3641 | .flags = ADDR_TYPE_RT | |
3642 | }, | |
3643 | { } | |
3644 | }; | |
3645 | ||
3646 | /* l4_cfg -> emif_fw */ | |
3647 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3648 | .master = &omap44xx_l4_cfg_hwmod, | |
3649 | .slave = &omap44xx_emif_fw_hwmod, | |
3650 | .clk = "l4_div_ck", | |
3651 | .addr = omap44xx_emif_fw_addrs, | |
3652 | .user = OCP_USER_MPU, | |
3653 | }; | |
3654 | ||
3655 | /* iva -> l3_instr */ | |
3656 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3657 | .master = &omap44xx_iva_hwmod, | |
3658 | .slave = &omap44xx_l3_instr_hwmod, | |
3659 | .clk = "l3_div_ck", | |
3660 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3661 | }; | |
3662 | ||
3663 | /* l3_main_3 -> l3_instr */ | |
3664 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3665 | .master = &omap44xx_l3_main_3_hwmod, | |
3666 | .slave = &omap44xx_l3_instr_hwmod, | |
3667 | .clk = "l3_div_ck", | |
3668 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3669 | }; | |
3670 | ||
9a817bc8 BC |
3671 | /* ocp_wp_noc -> l3_instr */ |
3672 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3673 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3674 | .slave = &omap44xx_l3_instr_hwmod, | |
3675 | .clk = "l3_div_ck", | |
3676 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3677 | }; | |
3678 | ||
844a3b63 PW |
3679 | /* dsp -> l3_main_1 */ |
3680 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3681 | .master = &omap44xx_dsp_hwmod, | |
3682 | .slave = &omap44xx_l3_main_1_hwmod, | |
3683 | .clk = "l3_div_ck", | |
3684 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3685 | }; | |
3686 | ||
3687 | /* dss -> l3_main_1 */ | |
3688 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3689 | .master = &omap44xx_dss_hwmod, | |
3690 | .slave = &omap44xx_l3_main_1_hwmod, | |
3691 | .clk = "l3_div_ck", | |
3692 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3693 | }; | |
3694 | ||
3695 | /* l3_main_2 -> l3_main_1 */ | |
3696 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3697 | .master = &omap44xx_l3_main_2_hwmod, | |
3698 | .slave = &omap44xx_l3_main_1_hwmod, | |
3699 | .clk = "l3_div_ck", | |
3700 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3701 | }; | |
3702 | ||
3703 | /* l4_cfg -> l3_main_1 */ | |
3704 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3705 | .master = &omap44xx_l4_cfg_hwmod, | |
3706 | .slave = &omap44xx_l3_main_1_hwmod, | |
3707 | .clk = "l4_div_ck", | |
3708 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3709 | }; | |
3710 | ||
3711 | /* mmc1 -> l3_main_1 */ | |
3712 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3713 | .master = &omap44xx_mmc1_hwmod, | |
3714 | .slave = &omap44xx_l3_main_1_hwmod, | |
3715 | .clk = "l3_div_ck", | |
3716 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3717 | }; | |
3718 | ||
3719 | /* mmc2 -> l3_main_1 */ | |
3720 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3721 | .master = &omap44xx_mmc2_hwmod, | |
3722 | .slave = &omap44xx_l3_main_1_hwmod, | |
3723 | .clk = "l3_div_ck", | |
3724 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3725 | }; | |
3726 | ||
3727 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3728 | { | |
3729 | .pa_start = 0x44000000, | |
3730 | .pa_end = 0x44000fff, | |
3731 | .flags = ADDR_TYPE_RT | |
3732 | }, | |
3733 | { } | |
3734 | }; | |
3735 | ||
3736 | /* mpu -> l3_main_1 */ | |
3737 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3738 | .master = &omap44xx_mpu_hwmod, | |
3739 | .slave = &omap44xx_l3_main_1_hwmod, | |
3740 | .clk = "l3_div_ck", | |
3741 | .addr = omap44xx_l3_main_1_addrs, | |
3742 | .user = OCP_USER_MPU, | |
3743 | }; | |
3744 | ||
42b9e387 PW |
3745 | /* c2c_target_fw -> l3_main_2 */ |
3746 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | |
3747 | .master = &omap44xx_c2c_target_fw_hwmod, | |
3748 | .slave = &omap44xx_l3_main_2_hwmod, | |
3749 | .clk = "l3_div_ck", | |
3750 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3751 | }; | |
3752 | ||
844a3b63 PW |
3753 | /* dma_system -> l3_main_2 */ |
3754 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3755 | .master = &omap44xx_dma_system_hwmod, | |
3756 | .slave = &omap44xx_l3_main_2_hwmod, | |
3757 | .clk = "l3_div_ck", | |
3758 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3759 | }; | |
3760 | ||
b050f688 ML |
3761 | /* fdif -> l3_main_2 */ |
3762 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3763 | .master = &omap44xx_fdif_hwmod, | |
3764 | .slave = &omap44xx_l3_main_2_hwmod, | |
3765 | .clk = "l3_div_ck", | |
3766 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3767 | }; | |
3768 | ||
9def390e PW |
3769 | /* gpu -> l3_main_2 */ |
3770 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3771 | .master = &omap44xx_gpu_hwmod, | |
3772 | .slave = &omap44xx_l3_main_2_hwmod, | |
3773 | .clk = "l3_div_ck", | |
3774 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3775 | }; | |
3776 | ||
844a3b63 PW |
3777 | /* hsi -> l3_main_2 */ |
3778 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3779 | .master = &omap44xx_hsi_hwmod, | |
3780 | .slave = &omap44xx_l3_main_2_hwmod, | |
3781 | .clk = "l3_div_ck", | |
3782 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3783 | }; | |
3784 | ||
3785 | /* ipu -> l3_main_2 */ | |
3786 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3787 | .master = &omap44xx_ipu_hwmod, | |
3788 | .slave = &omap44xx_l3_main_2_hwmod, | |
3789 | .clk = "l3_div_ck", | |
3790 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3791 | }; | |
3792 | ||
3793 | /* iss -> l3_main_2 */ | |
3794 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3795 | .master = &omap44xx_iss_hwmod, | |
3796 | .slave = &omap44xx_l3_main_2_hwmod, | |
3797 | .clk = "l3_div_ck", | |
3798 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3799 | }; | |
3800 | ||
3801 | /* iva -> l3_main_2 */ | |
3802 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3803 | .master = &omap44xx_iva_hwmod, | |
3804 | .slave = &omap44xx_l3_main_2_hwmod, | |
3805 | .clk = "l3_div_ck", | |
3806 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3807 | }; | |
3808 | ||
3809 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
3810 | { | |
3811 | .pa_start = 0x44800000, | |
3812 | .pa_end = 0x44801fff, | |
3813 | .flags = ADDR_TYPE_RT | |
3814 | }, | |
3815 | { } | |
3816 | }; | |
3817 | ||
3818 | /* l3_main_1 -> l3_main_2 */ | |
3819 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3820 | .master = &omap44xx_l3_main_1_hwmod, | |
3821 | .slave = &omap44xx_l3_main_2_hwmod, | |
3822 | .clk = "l3_div_ck", | |
3823 | .addr = omap44xx_l3_main_2_addrs, | |
3824 | .user = OCP_USER_MPU, | |
3825 | }; | |
3826 | ||
3827 | /* l4_cfg -> l3_main_2 */ | |
3828 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3829 | .master = &omap44xx_l4_cfg_hwmod, | |
3830 | .slave = &omap44xx_l3_main_2_hwmod, | |
3831 | .clk = "l4_div_ck", | |
3832 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3833 | }; | |
3834 | ||
0c668875 BC |
3835 | /* usb_host_fs -> l3_main_2 */ |
3836 | static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = { | |
3837 | .master = &omap44xx_usb_host_fs_hwmod, | |
3838 | .slave = &omap44xx_l3_main_2_hwmod, | |
3839 | .clk = "l3_div_ck", | |
3840 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3841 | }; | |
3842 | ||
844a3b63 PW |
3843 | /* usb_host_hs -> l3_main_2 */ |
3844 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3845 | .master = &omap44xx_usb_host_hs_hwmod, | |
3846 | .slave = &omap44xx_l3_main_2_hwmod, | |
3847 | .clk = "l3_div_ck", | |
3848 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3849 | }; | |
3850 | ||
3851 | /* usb_otg_hs -> l3_main_2 */ | |
3852 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3853 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3854 | .slave = &omap44xx_l3_main_2_hwmod, | |
3855 | .clk = "l3_div_ck", | |
3856 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3857 | }; | |
3858 | ||
3859 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
3860 | { | |
3861 | .pa_start = 0x45000000, | |
3862 | .pa_end = 0x45000fff, | |
3863 | .flags = ADDR_TYPE_RT | |
3864 | }, | |
3865 | { } | |
3866 | }; | |
3867 | ||
3868 | /* l3_main_1 -> l3_main_3 */ | |
3869 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3870 | .master = &omap44xx_l3_main_1_hwmod, | |
3871 | .slave = &omap44xx_l3_main_3_hwmod, | |
3872 | .clk = "l3_div_ck", | |
3873 | .addr = omap44xx_l3_main_3_addrs, | |
3874 | .user = OCP_USER_MPU, | |
3875 | }; | |
3876 | ||
3877 | /* l3_main_2 -> l3_main_3 */ | |
3878 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3879 | .master = &omap44xx_l3_main_2_hwmod, | |
3880 | .slave = &omap44xx_l3_main_3_hwmod, | |
3881 | .clk = "l3_div_ck", | |
3882 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3883 | }; | |
3884 | ||
3885 | /* l4_cfg -> l3_main_3 */ | |
3886 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3887 | .master = &omap44xx_l4_cfg_hwmod, | |
3888 | .slave = &omap44xx_l3_main_3_hwmod, | |
3889 | .clk = "l4_div_ck", | |
3890 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3891 | }; | |
3892 | ||
3893 | /* aess -> l4_abe */ | |
3894 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { | |
3895 | .master = &omap44xx_aess_hwmod, | |
3896 | .slave = &omap44xx_l4_abe_hwmod, | |
3897 | .clk = "ocp_abe_iclk", | |
3898 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3899 | }; | |
3900 | ||
3901 | /* dsp -> l4_abe */ | |
3902 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3903 | .master = &omap44xx_dsp_hwmod, | |
3904 | .slave = &omap44xx_l4_abe_hwmod, | |
3905 | .clk = "ocp_abe_iclk", | |
3906 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3907 | }; | |
3908 | ||
3909 | /* l3_main_1 -> l4_abe */ | |
3910 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3911 | .master = &omap44xx_l3_main_1_hwmod, | |
3912 | .slave = &omap44xx_l4_abe_hwmod, | |
3913 | .clk = "l3_div_ck", | |
3914 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3915 | }; | |
3916 | ||
3917 | /* mpu -> l4_abe */ | |
3918 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3919 | .master = &omap44xx_mpu_hwmod, | |
3920 | .slave = &omap44xx_l4_abe_hwmod, | |
3921 | .clk = "ocp_abe_iclk", | |
3922 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3923 | }; | |
3924 | ||
3925 | /* l3_main_1 -> l4_cfg */ | |
3926 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3927 | .master = &omap44xx_l3_main_1_hwmod, | |
3928 | .slave = &omap44xx_l4_cfg_hwmod, | |
3929 | .clk = "l3_div_ck", | |
3930 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3931 | }; | |
3932 | ||
3933 | /* l3_main_2 -> l4_per */ | |
3934 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3935 | .master = &omap44xx_l3_main_2_hwmod, | |
3936 | .slave = &omap44xx_l4_per_hwmod, | |
3937 | .clk = "l3_div_ck", | |
3938 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3939 | }; | |
3940 | ||
3941 | /* l4_cfg -> l4_wkup */ | |
3942 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3943 | .master = &omap44xx_l4_cfg_hwmod, | |
3944 | .slave = &omap44xx_l4_wkup_hwmod, | |
3945 | .clk = "l4_div_ck", | |
3946 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3947 | }; | |
3948 | ||
3949 | /* mpu -> mpu_private */ | |
3950 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3951 | .master = &omap44xx_mpu_hwmod, | |
3952 | .slave = &omap44xx_mpu_private_hwmod, | |
3953 | .clk = "l3_div_ck", | |
3954 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3955 | }; | |
3956 | ||
9a817bc8 BC |
3957 | static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { |
3958 | { | |
3959 | .pa_start = 0x4a102000, | |
3960 | .pa_end = 0x4a10207f, | |
3961 | .flags = ADDR_TYPE_RT | |
3962 | }, | |
3963 | { } | |
3964 | }; | |
3965 | ||
3966 | /* l4_cfg -> ocp_wp_noc */ | |
3967 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
3968 | .master = &omap44xx_l4_cfg_hwmod, | |
3969 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
3970 | .clk = "l4_div_ck", | |
3971 | .addr = omap44xx_ocp_wp_noc_addrs, | |
3972 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3973 | }; | |
3974 | ||
844a3b63 PW |
3975 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
3976 | { | |
3977 | .pa_start = 0x401f1000, | |
3978 | .pa_end = 0x401f13ff, | |
3979 | .flags = ADDR_TYPE_RT | |
3980 | }, | |
3981 | { } | |
3982 | }; | |
3983 | ||
3984 | /* l4_abe -> aess */ | |
3985 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { | |
3986 | .master = &omap44xx_l4_abe_hwmod, | |
3987 | .slave = &omap44xx_aess_hwmod, | |
3988 | .clk = "ocp_abe_iclk", | |
3989 | .addr = omap44xx_aess_addrs, | |
3990 | .user = OCP_USER_MPU, | |
3991 | }; | |
3992 | ||
3993 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
3994 | { | |
3995 | .pa_start = 0x490f1000, | |
3996 | .pa_end = 0x490f13ff, | |
3997 | .flags = ADDR_TYPE_RT | |
3998 | }, | |
3999 | { } | |
4000 | }; | |
4001 | ||
4002 | /* l4_abe -> aess (dma) */ | |
4003 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { | |
4004 | .master = &omap44xx_l4_abe_hwmod, | |
4005 | .slave = &omap44xx_aess_hwmod, | |
4006 | .clk = "ocp_abe_iclk", | |
4007 | .addr = omap44xx_aess_dma_addrs, | |
4008 | .user = OCP_USER_SDMA, | |
4009 | }; | |
4010 | ||
42b9e387 PW |
4011 | /* l3_main_2 -> c2c */ |
4012 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
4013 | .master = &omap44xx_l3_main_2_hwmod, | |
4014 | .slave = &omap44xx_c2c_hwmod, | |
4015 | .clk = "l3_div_ck", | |
4016 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4017 | }; | |
4018 | ||
844a3b63 PW |
4019 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
4020 | { | |
4021 | .pa_start = 0x4a304000, | |
4022 | .pa_end = 0x4a30401f, | |
4023 | .flags = ADDR_TYPE_RT | |
4024 | }, | |
4025 | { } | |
4026 | }; | |
4027 | ||
4028 | /* l4_wkup -> counter_32k */ | |
4029 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
4030 | .master = &omap44xx_l4_wkup_hwmod, | |
4031 | .slave = &omap44xx_counter_32k_hwmod, | |
4032 | .clk = "l4_wkup_clk_mux_ck", | |
4033 | .addr = omap44xx_counter_32k_addrs, | |
4034 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4035 | }; | |
4036 | ||
a0b5d813 PW |
4037 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
4038 | { | |
4039 | .pa_start = 0x4a002000, | |
4040 | .pa_end = 0x4a0027ff, | |
4041 | .flags = ADDR_TYPE_RT | |
4042 | }, | |
4043 | { } | |
4044 | }; | |
4045 | ||
4046 | /* l4_cfg -> ctrl_module_core */ | |
4047 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
4048 | .master = &omap44xx_l4_cfg_hwmod, | |
4049 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
4050 | .clk = "l4_div_ck", | |
4051 | .addr = omap44xx_ctrl_module_core_addrs, | |
4052 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4053 | }; | |
4054 | ||
4055 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
4056 | { | |
4057 | .pa_start = 0x4a100000, | |
4058 | .pa_end = 0x4a1007ff, | |
4059 | .flags = ADDR_TYPE_RT | |
4060 | }, | |
4061 | { } | |
4062 | }; | |
4063 | ||
4064 | /* l4_cfg -> ctrl_module_pad_core */ | |
4065 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
4066 | .master = &omap44xx_l4_cfg_hwmod, | |
4067 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
4068 | .clk = "l4_div_ck", | |
4069 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
4070 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4071 | }; | |
4072 | ||
4073 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
4074 | { | |
4075 | .pa_start = 0x4a30c000, | |
4076 | .pa_end = 0x4a30c7ff, | |
4077 | .flags = ADDR_TYPE_RT | |
4078 | }, | |
4079 | { } | |
4080 | }; | |
4081 | ||
4082 | /* l4_wkup -> ctrl_module_wkup */ | |
4083 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
4084 | .master = &omap44xx_l4_wkup_hwmod, | |
4085 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
4086 | .clk = "l4_wkup_clk_mux_ck", | |
4087 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
4088 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4089 | }; | |
4090 | ||
4091 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
4092 | { | |
4093 | .pa_start = 0x4a31e000, | |
4094 | .pa_end = 0x4a31e7ff, | |
4095 | .flags = ADDR_TYPE_RT | |
4096 | }, | |
4097 | { } | |
4098 | }; | |
4099 | ||
4100 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
4101 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
4102 | .master = &omap44xx_l4_wkup_hwmod, | |
4103 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
4104 | .clk = "l4_wkup_clk_mux_ck", | |
4105 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
4106 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4107 | }; | |
4108 | ||
844a3b63 PW |
4109 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
4110 | { | |
4111 | .pa_start = 0x4a056000, | |
4112 | .pa_end = 0x4a056fff, | |
4113 | .flags = ADDR_TYPE_RT | |
4114 | }, | |
4115 | { } | |
4116 | }; | |
4117 | ||
4118 | /* l4_cfg -> dma_system */ | |
4119 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
4120 | .master = &omap44xx_l4_cfg_hwmod, | |
4121 | .slave = &omap44xx_dma_system_hwmod, | |
4122 | .clk = "l4_div_ck", | |
4123 | .addr = omap44xx_dma_system_addrs, | |
4124 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4125 | }; | |
4126 | ||
4127 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
4128 | { | |
4129 | .name = "mpu", | |
4130 | .pa_start = 0x4012e000, | |
4131 | .pa_end = 0x4012e07f, | |
4132 | .flags = ADDR_TYPE_RT | |
4133 | }, | |
4134 | { } | |
4135 | }; | |
4136 | ||
4137 | /* l4_abe -> dmic */ | |
4138 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
4139 | .master = &omap44xx_l4_abe_hwmod, | |
4140 | .slave = &omap44xx_dmic_hwmod, | |
4141 | .clk = "ocp_abe_iclk", | |
4142 | .addr = omap44xx_dmic_addrs, | |
4143 | .user = OCP_USER_MPU, | |
4144 | }; | |
4145 | ||
4146 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
4147 | { | |
4148 | .name = "dma", | |
4149 | .pa_start = 0x4902e000, | |
4150 | .pa_end = 0x4902e07f, | |
4151 | .flags = ADDR_TYPE_RT | |
4152 | }, | |
4153 | { } | |
4154 | }; | |
4155 | ||
4156 | /* l4_abe -> dmic (dma) */ | |
4157 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
4158 | .master = &omap44xx_l4_abe_hwmod, | |
4159 | .slave = &omap44xx_dmic_hwmod, | |
4160 | .clk = "ocp_abe_iclk", | |
4161 | .addr = omap44xx_dmic_dma_addrs, | |
4162 | .user = OCP_USER_SDMA, | |
4163 | }; | |
4164 | ||
4165 | /* dsp -> iva */ | |
4166 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
4167 | .master = &omap44xx_dsp_hwmod, | |
4168 | .slave = &omap44xx_iva_hwmod, | |
4169 | .clk = "dpll_iva_m5x2_ck", | |
4170 | .user = OCP_USER_DSP, | |
4171 | }; | |
4172 | ||
42b9e387 PW |
4173 | /* dsp -> sl2if */ |
4174 | static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { | |
4175 | .master = &omap44xx_dsp_hwmod, | |
4176 | .slave = &omap44xx_sl2if_hwmod, | |
4177 | .clk = "dpll_iva_m5x2_ck", | |
4178 | .user = OCP_USER_DSP, | |
4179 | }; | |
4180 | ||
844a3b63 PW |
4181 | /* l4_cfg -> dsp */ |
4182 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
4183 | .master = &omap44xx_l4_cfg_hwmod, | |
4184 | .slave = &omap44xx_dsp_hwmod, | |
4185 | .clk = "l4_div_ck", | |
4186 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4187 | }; | |
4188 | ||
4189 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
4190 | { | |
4191 | .pa_start = 0x58000000, | |
4192 | .pa_end = 0x5800007f, | |
4193 | .flags = ADDR_TYPE_RT | |
4194 | }, | |
4195 | { } | |
4196 | }; | |
4197 | ||
4198 | /* l3_main_2 -> dss */ | |
4199 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
4200 | .master = &omap44xx_l3_main_2_hwmod, | |
4201 | .slave = &omap44xx_dss_hwmod, | |
4202 | .clk = "dss_fck", | |
4203 | .addr = omap44xx_dss_dma_addrs, | |
4204 | .user = OCP_USER_SDMA, | |
4205 | }; | |
4206 | ||
4207 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
4208 | { | |
4209 | .pa_start = 0x48040000, | |
4210 | .pa_end = 0x4804007f, | |
4211 | .flags = ADDR_TYPE_RT | |
4212 | }, | |
4213 | { } | |
4214 | }; | |
4215 | ||
4216 | /* l4_per -> dss */ | |
4217 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
4218 | .master = &omap44xx_l4_per_hwmod, | |
4219 | .slave = &omap44xx_dss_hwmod, | |
4220 | .clk = "l4_div_ck", | |
4221 | .addr = omap44xx_dss_addrs, | |
4222 | .user = OCP_USER_MPU, | |
4223 | }; | |
4224 | ||
4225 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
4226 | { | |
4227 | .pa_start = 0x58001000, | |
4228 | .pa_end = 0x58001fff, | |
4229 | .flags = ADDR_TYPE_RT | |
4230 | }, | |
4231 | { } | |
4232 | }; | |
4233 | ||
4234 | /* l3_main_2 -> dss_dispc */ | |
4235 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
4236 | .master = &omap44xx_l3_main_2_hwmod, | |
4237 | .slave = &omap44xx_dss_dispc_hwmod, | |
4238 | .clk = "dss_fck", | |
4239 | .addr = omap44xx_dss_dispc_dma_addrs, | |
4240 | .user = OCP_USER_SDMA, | |
4241 | }; | |
4242 | ||
4243 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
4244 | { | |
4245 | .pa_start = 0x48041000, | |
4246 | .pa_end = 0x48041fff, | |
4247 | .flags = ADDR_TYPE_RT | |
4248 | }, | |
4249 | { } | |
4250 | }; | |
4251 | ||
4252 | /* l4_per -> dss_dispc */ | |
4253 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
4254 | .master = &omap44xx_l4_per_hwmod, | |
4255 | .slave = &omap44xx_dss_dispc_hwmod, | |
4256 | .clk = "l4_div_ck", | |
4257 | .addr = omap44xx_dss_dispc_addrs, | |
4258 | .user = OCP_USER_MPU, | |
4259 | }; | |
4260 | ||
4261 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
4262 | { | |
4263 | .pa_start = 0x58004000, | |
4264 | .pa_end = 0x580041ff, | |
4265 | .flags = ADDR_TYPE_RT | |
4266 | }, | |
4267 | { } | |
4268 | }; | |
4269 | ||
4270 | /* l3_main_2 -> dss_dsi1 */ | |
4271 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
4272 | .master = &omap44xx_l3_main_2_hwmod, | |
4273 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4274 | .clk = "dss_fck", | |
4275 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
4276 | .user = OCP_USER_SDMA, | |
4277 | }; | |
4278 | ||
4279 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
4280 | { | |
4281 | .pa_start = 0x48044000, | |
4282 | .pa_end = 0x480441ff, | |
4283 | .flags = ADDR_TYPE_RT | |
4284 | }, | |
4285 | { } | |
4286 | }; | |
4287 | ||
4288 | /* l4_per -> dss_dsi1 */ | |
4289 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
4290 | .master = &omap44xx_l4_per_hwmod, | |
4291 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4292 | .clk = "l4_div_ck", | |
4293 | .addr = omap44xx_dss_dsi1_addrs, | |
4294 | .user = OCP_USER_MPU, | |
4295 | }; | |
4296 | ||
4297 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
4298 | { | |
4299 | .pa_start = 0x58005000, | |
4300 | .pa_end = 0x580051ff, | |
4301 | .flags = ADDR_TYPE_RT | |
4302 | }, | |
4303 | { } | |
4304 | }; | |
4305 | ||
4306 | /* l3_main_2 -> dss_dsi2 */ | |
4307 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
4308 | .master = &omap44xx_l3_main_2_hwmod, | |
4309 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4310 | .clk = "dss_fck", | |
4311 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
4312 | .user = OCP_USER_SDMA, | |
4313 | }; | |
4314 | ||
4315 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
4316 | { | |
4317 | .pa_start = 0x48045000, | |
4318 | .pa_end = 0x480451ff, | |
4319 | .flags = ADDR_TYPE_RT | |
4320 | }, | |
4321 | { } | |
4322 | }; | |
4323 | ||
4324 | /* l4_per -> dss_dsi2 */ | |
4325 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
4326 | .master = &omap44xx_l4_per_hwmod, | |
4327 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4328 | .clk = "l4_div_ck", | |
4329 | .addr = omap44xx_dss_dsi2_addrs, | |
4330 | .user = OCP_USER_MPU, | |
4331 | }; | |
4332 | ||
4333 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
4334 | { | |
4335 | .pa_start = 0x58006000, | |
4336 | .pa_end = 0x58006fff, | |
4337 | .flags = ADDR_TYPE_RT | |
4338 | }, | |
4339 | { } | |
4340 | }; | |
4341 | ||
4342 | /* l3_main_2 -> dss_hdmi */ | |
4343 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
4344 | .master = &omap44xx_l3_main_2_hwmod, | |
4345 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4346 | .clk = "dss_fck", | |
4347 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
4348 | .user = OCP_USER_SDMA, | |
4349 | }; | |
4350 | ||
4351 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
4352 | { | |
4353 | .pa_start = 0x48046000, | |
4354 | .pa_end = 0x48046fff, | |
4355 | .flags = ADDR_TYPE_RT | |
4356 | }, | |
4357 | { } | |
4358 | }; | |
4359 | ||
4360 | /* l4_per -> dss_hdmi */ | |
4361 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
4362 | .master = &omap44xx_l4_per_hwmod, | |
4363 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4364 | .clk = "l4_div_ck", | |
4365 | .addr = omap44xx_dss_hdmi_addrs, | |
4366 | .user = OCP_USER_MPU, | |
4367 | }; | |
4368 | ||
4369 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
4370 | { | |
4371 | .pa_start = 0x58002000, | |
4372 | .pa_end = 0x580020ff, | |
4373 | .flags = ADDR_TYPE_RT | |
4374 | }, | |
4375 | { } | |
4376 | }; | |
4377 | ||
4378 | /* l3_main_2 -> dss_rfbi */ | |
4379 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
4380 | .master = &omap44xx_l3_main_2_hwmod, | |
4381 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4382 | .clk = "dss_fck", | |
4383 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
4384 | .user = OCP_USER_SDMA, | |
4385 | }; | |
4386 | ||
4387 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
4388 | { | |
4389 | .pa_start = 0x48042000, | |
4390 | .pa_end = 0x480420ff, | |
4391 | .flags = ADDR_TYPE_RT | |
4392 | }, | |
4393 | { } | |
4394 | }; | |
4395 | ||
4396 | /* l4_per -> dss_rfbi */ | |
4397 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
4398 | .master = &omap44xx_l4_per_hwmod, | |
4399 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4400 | .clk = "l4_div_ck", | |
4401 | .addr = omap44xx_dss_rfbi_addrs, | |
4402 | .user = OCP_USER_MPU, | |
4403 | }; | |
4404 | ||
4405 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
4406 | { | |
4407 | .pa_start = 0x58003000, | |
4408 | .pa_end = 0x580030ff, | |
4409 | .flags = ADDR_TYPE_RT | |
4410 | }, | |
4411 | { } | |
4412 | }; | |
4413 | ||
4414 | /* l3_main_2 -> dss_venc */ | |
4415 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
4416 | .master = &omap44xx_l3_main_2_hwmod, | |
4417 | .slave = &omap44xx_dss_venc_hwmod, | |
4418 | .clk = "dss_fck", | |
4419 | .addr = omap44xx_dss_venc_dma_addrs, | |
4420 | .user = OCP_USER_SDMA, | |
4421 | }; | |
4422 | ||
4423 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
4424 | { | |
4425 | .pa_start = 0x48043000, | |
4426 | .pa_end = 0x480430ff, | |
4427 | .flags = ADDR_TYPE_RT | |
4428 | }, | |
4429 | { } | |
4430 | }; | |
4431 | ||
4432 | /* l4_per -> dss_venc */ | |
4433 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
4434 | .master = &omap44xx_l4_per_hwmod, | |
4435 | .slave = &omap44xx_dss_venc_hwmod, | |
4436 | .clk = "l4_div_ck", | |
4437 | .addr = omap44xx_dss_venc_addrs, | |
4438 | .user = OCP_USER_MPU, | |
4439 | }; | |
4440 | ||
42b9e387 PW |
4441 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
4442 | { | |
4443 | .pa_start = 0x48078000, | |
4444 | .pa_end = 0x48078fff, | |
4445 | .flags = ADDR_TYPE_RT | |
4446 | }, | |
4447 | { } | |
4448 | }; | |
4449 | ||
4450 | /* l4_per -> elm */ | |
4451 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
4452 | .master = &omap44xx_l4_per_hwmod, | |
4453 | .slave = &omap44xx_elm_hwmod, | |
4454 | .clk = "l4_div_ck", | |
4455 | .addr = omap44xx_elm_addrs, | |
4456 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4457 | }; | |
4458 | ||
bf30f950 PW |
4459 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
4460 | { | |
4461 | .pa_start = 0x4c000000, | |
4462 | .pa_end = 0x4c0000ff, | |
4463 | .flags = ADDR_TYPE_RT | |
4464 | }, | |
4465 | { } | |
4466 | }; | |
4467 | ||
4468 | /* emif_fw -> emif1 */ | |
4469 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | |
4470 | .master = &omap44xx_emif_fw_hwmod, | |
4471 | .slave = &omap44xx_emif1_hwmod, | |
4472 | .clk = "l3_div_ck", | |
4473 | .addr = omap44xx_emif1_addrs, | |
4474 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4475 | }; | |
4476 | ||
4477 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | |
4478 | { | |
4479 | .pa_start = 0x4d000000, | |
4480 | .pa_end = 0x4d0000ff, | |
4481 | .flags = ADDR_TYPE_RT | |
4482 | }, | |
4483 | { } | |
4484 | }; | |
4485 | ||
4486 | /* emif_fw -> emif2 */ | |
4487 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | |
4488 | .master = &omap44xx_emif_fw_hwmod, | |
4489 | .slave = &omap44xx_emif2_hwmod, | |
4490 | .clk = "l3_div_ck", | |
4491 | .addr = omap44xx_emif2_addrs, | |
4492 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4493 | }; | |
4494 | ||
b050f688 ML |
4495 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
4496 | { | |
4497 | .pa_start = 0x4a10a000, | |
4498 | .pa_end = 0x4a10a1ff, | |
4499 | .flags = ADDR_TYPE_RT | |
4500 | }, | |
4501 | { } | |
4502 | }; | |
4503 | ||
4504 | /* l4_cfg -> fdif */ | |
4505 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4506 | .master = &omap44xx_l4_cfg_hwmod, | |
4507 | .slave = &omap44xx_fdif_hwmod, | |
4508 | .clk = "l4_div_ck", | |
4509 | .addr = omap44xx_fdif_addrs, | |
4510 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4511 | }; | |
4512 | ||
844a3b63 PW |
4513 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
4514 | { | |
4515 | .pa_start = 0x4a310000, | |
4516 | .pa_end = 0x4a3101ff, | |
4517 | .flags = ADDR_TYPE_RT | |
4518 | }, | |
4519 | { } | |
4520 | }; | |
4521 | ||
4522 | /* l4_wkup -> gpio1 */ | |
4523 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4524 | .master = &omap44xx_l4_wkup_hwmod, | |
4525 | .slave = &omap44xx_gpio1_hwmod, | |
4526 | .clk = "l4_wkup_clk_mux_ck", | |
4527 | .addr = omap44xx_gpio1_addrs, | |
4528 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4529 | }; | |
4530 | ||
4531 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
4532 | { | |
4533 | .pa_start = 0x48055000, | |
4534 | .pa_end = 0x480551ff, | |
4535 | .flags = ADDR_TYPE_RT | |
4536 | }, | |
4537 | { } | |
4538 | }; | |
4539 | ||
4540 | /* l4_per -> gpio2 */ | |
4541 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4542 | .master = &omap44xx_l4_per_hwmod, | |
4543 | .slave = &omap44xx_gpio2_hwmod, | |
4544 | .clk = "l4_div_ck", | |
4545 | .addr = omap44xx_gpio2_addrs, | |
4546 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4547 | }; | |
4548 | ||
4549 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
4550 | { | |
4551 | .pa_start = 0x48057000, | |
4552 | .pa_end = 0x480571ff, | |
4553 | .flags = ADDR_TYPE_RT | |
4554 | }, | |
4555 | { } | |
4556 | }; | |
4557 | ||
4558 | /* l4_per -> gpio3 */ | |
4559 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4560 | .master = &omap44xx_l4_per_hwmod, | |
4561 | .slave = &omap44xx_gpio3_hwmod, | |
4562 | .clk = "l4_div_ck", | |
4563 | .addr = omap44xx_gpio3_addrs, | |
4564 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4565 | }; | |
4566 | ||
4567 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
4568 | { | |
4569 | .pa_start = 0x48059000, | |
4570 | .pa_end = 0x480591ff, | |
4571 | .flags = ADDR_TYPE_RT | |
4572 | }, | |
4573 | { } | |
4574 | }; | |
4575 | ||
4576 | /* l4_per -> gpio4 */ | |
4577 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4578 | .master = &omap44xx_l4_per_hwmod, | |
4579 | .slave = &omap44xx_gpio4_hwmod, | |
4580 | .clk = "l4_div_ck", | |
4581 | .addr = omap44xx_gpio4_addrs, | |
4582 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4583 | }; | |
4584 | ||
4585 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
4586 | { | |
4587 | .pa_start = 0x4805b000, | |
4588 | .pa_end = 0x4805b1ff, | |
4589 | .flags = ADDR_TYPE_RT | |
4590 | }, | |
4591 | { } | |
4592 | }; | |
4593 | ||
4594 | /* l4_per -> gpio5 */ | |
4595 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4596 | .master = &omap44xx_l4_per_hwmod, | |
4597 | .slave = &omap44xx_gpio5_hwmod, | |
4598 | .clk = "l4_div_ck", | |
4599 | .addr = omap44xx_gpio5_addrs, | |
4600 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4601 | }; | |
4602 | ||
4603 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
4604 | { | |
4605 | .pa_start = 0x4805d000, | |
4606 | .pa_end = 0x4805d1ff, | |
4607 | .flags = ADDR_TYPE_RT | |
4608 | }, | |
4609 | { } | |
4610 | }; | |
4611 | ||
4612 | /* l4_per -> gpio6 */ | |
4613 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4614 | .master = &omap44xx_l4_per_hwmod, | |
4615 | .slave = &omap44xx_gpio6_hwmod, | |
4616 | .clk = "l4_div_ck", | |
4617 | .addr = omap44xx_gpio6_addrs, | |
4618 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4619 | }; | |
4620 | ||
eb42b5d3 BC |
4621 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
4622 | { | |
4623 | .pa_start = 0x50000000, | |
4624 | .pa_end = 0x500003ff, | |
4625 | .flags = ADDR_TYPE_RT | |
4626 | }, | |
4627 | { } | |
4628 | }; | |
4629 | ||
4630 | /* l3_main_2 -> gpmc */ | |
4631 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4632 | .master = &omap44xx_l3_main_2_hwmod, | |
4633 | .slave = &omap44xx_gpmc_hwmod, | |
4634 | .clk = "l3_div_ck", | |
4635 | .addr = omap44xx_gpmc_addrs, | |
4636 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4637 | }; | |
4638 | ||
9def390e PW |
4639 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4640 | { | |
4641 | .pa_start = 0x56000000, | |
4642 | .pa_end = 0x5600ffff, | |
4643 | .flags = ADDR_TYPE_RT | |
4644 | }, | |
4645 | { } | |
4646 | }; | |
4647 | ||
4648 | /* l3_main_2 -> gpu */ | |
4649 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4650 | .master = &omap44xx_l3_main_2_hwmod, | |
4651 | .slave = &omap44xx_gpu_hwmod, | |
4652 | .clk = "l3_div_ck", | |
4653 | .addr = omap44xx_gpu_addrs, | |
4654 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4655 | }; | |
4656 | ||
a091c08e PW |
4657 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4658 | { | |
4659 | .pa_start = 0x480b2000, | |
4660 | .pa_end = 0x480b201f, | |
4661 | .flags = ADDR_TYPE_RT | |
4662 | }, | |
4663 | { } | |
4664 | }; | |
4665 | ||
4666 | /* l4_per -> hdq1w */ | |
4667 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4668 | .master = &omap44xx_l4_per_hwmod, | |
4669 | .slave = &omap44xx_hdq1w_hwmod, | |
4670 | .clk = "l4_div_ck", | |
4671 | .addr = omap44xx_hdq1w_addrs, | |
4672 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4673 | }; | |
4674 | ||
844a3b63 PW |
4675 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4676 | { | |
4677 | .pa_start = 0x4a058000, | |
4678 | .pa_end = 0x4a05bfff, | |
4679 | .flags = ADDR_TYPE_RT | |
4680 | }, | |
4681 | { } | |
4682 | }; | |
4683 | ||
4684 | /* l4_cfg -> hsi */ | |
4685 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4686 | .master = &omap44xx_l4_cfg_hwmod, | |
4687 | .slave = &omap44xx_hsi_hwmod, | |
4688 | .clk = "l4_div_ck", | |
4689 | .addr = omap44xx_hsi_addrs, | |
4690 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4691 | }; | |
4692 | ||
4693 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
4694 | { | |
4695 | .pa_start = 0x48070000, | |
4696 | .pa_end = 0x480700ff, | |
4697 | .flags = ADDR_TYPE_RT | |
4698 | }, | |
4699 | { } | |
4700 | }; | |
4701 | ||
4702 | /* l4_per -> i2c1 */ | |
4703 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4704 | .master = &omap44xx_l4_per_hwmod, | |
4705 | .slave = &omap44xx_i2c1_hwmod, | |
4706 | .clk = "l4_div_ck", | |
4707 | .addr = omap44xx_i2c1_addrs, | |
4708 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4709 | }; | |
4710 | ||
4711 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
4712 | { | |
4713 | .pa_start = 0x48072000, | |
4714 | .pa_end = 0x480720ff, | |
4715 | .flags = ADDR_TYPE_RT | |
4716 | }, | |
4717 | { } | |
4718 | }; | |
4719 | ||
4720 | /* l4_per -> i2c2 */ | |
4721 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4722 | .master = &omap44xx_l4_per_hwmod, | |
4723 | .slave = &omap44xx_i2c2_hwmod, | |
4724 | .clk = "l4_div_ck", | |
4725 | .addr = omap44xx_i2c2_addrs, | |
4726 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4727 | }; | |
4728 | ||
4729 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
4730 | { | |
4731 | .pa_start = 0x48060000, | |
4732 | .pa_end = 0x480600ff, | |
4733 | .flags = ADDR_TYPE_RT | |
4734 | }, | |
4735 | { } | |
4736 | }; | |
4737 | ||
4738 | /* l4_per -> i2c3 */ | |
4739 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4740 | .master = &omap44xx_l4_per_hwmod, | |
4741 | .slave = &omap44xx_i2c3_hwmod, | |
4742 | .clk = "l4_div_ck", | |
4743 | .addr = omap44xx_i2c3_addrs, | |
4744 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4745 | }; | |
4746 | ||
4747 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
4748 | { | |
4749 | .pa_start = 0x48350000, | |
4750 | .pa_end = 0x483500ff, | |
4751 | .flags = ADDR_TYPE_RT | |
4752 | }, | |
4753 | { } | |
4754 | }; | |
4755 | ||
4756 | /* l4_per -> i2c4 */ | |
4757 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4758 | .master = &omap44xx_l4_per_hwmod, | |
4759 | .slave = &omap44xx_i2c4_hwmod, | |
4760 | .clk = "l4_div_ck", | |
4761 | .addr = omap44xx_i2c4_addrs, | |
4762 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4763 | }; | |
4764 | ||
4765 | /* l3_main_2 -> ipu */ | |
4766 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4767 | .master = &omap44xx_l3_main_2_hwmod, | |
4768 | .slave = &omap44xx_ipu_hwmod, | |
4769 | .clk = "l3_div_ck", | |
4770 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4771 | }; | |
4772 | ||
4773 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
4774 | { | |
4775 | .pa_start = 0x52000000, | |
4776 | .pa_end = 0x520000ff, | |
4777 | .flags = ADDR_TYPE_RT | |
4778 | }, | |
4779 | { } | |
4780 | }; | |
4781 | ||
4782 | /* l3_main_2 -> iss */ | |
4783 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
4784 | .master = &omap44xx_l3_main_2_hwmod, | |
4785 | .slave = &omap44xx_iss_hwmod, | |
4786 | .clk = "l3_div_ck", | |
4787 | .addr = omap44xx_iss_addrs, | |
4788 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4789 | }; | |
4790 | ||
42b9e387 PW |
4791 | /* iva -> sl2if */ |
4792 | static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { | |
4793 | .master = &omap44xx_iva_hwmod, | |
4794 | .slave = &omap44xx_sl2if_hwmod, | |
4795 | .clk = "dpll_iva_m5x2_ck", | |
4796 | .user = OCP_USER_IVA, | |
4797 | }; | |
4798 | ||
844a3b63 PW |
4799 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
4800 | { | |
4801 | .pa_start = 0x5a000000, | |
4802 | .pa_end = 0x5a07ffff, | |
4803 | .flags = ADDR_TYPE_RT | |
4804 | }, | |
4805 | { } | |
4806 | }; | |
4807 | ||
4808 | /* l3_main_2 -> iva */ | |
4809 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
4810 | .master = &omap44xx_l3_main_2_hwmod, | |
4811 | .slave = &omap44xx_iva_hwmod, | |
4812 | .clk = "l3_div_ck", | |
4813 | .addr = omap44xx_iva_addrs, | |
4814 | .user = OCP_USER_MPU, | |
4815 | }; | |
4816 | ||
4817 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
4818 | { | |
4819 | .pa_start = 0x4a31c000, | |
4820 | .pa_end = 0x4a31c07f, | |
4821 | .flags = ADDR_TYPE_RT | |
4822 | }, | |
4823 | { } | |
4824 | }; | |
4825 | ||
4826 | /* l4_wkup -> kbd */ | |
4827 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
4828 | .master = &omap44xx_l4_wkup_hwmod, | |
4829 | .slave = &omap44xx_kbd_hwmod, | |
4830 | .clk = "l4_wkup_clk_mux_ck", | |
4831 | .addr = omap44xx_kbd_addrs, | |
4832 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4833 | }; | |
4834 | ||
4835 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
4836 | { | |
4837 | .pa_start = 0x4a0f4000, | |
4838 | .pa_end = 0x4a0f41ff, | |
4839 | .flags = ADDR_TYPE_RT | |
4840 | }, | |
4841 | { } | |
4842 | }; | |
4843 | ||
4844 | /* l4_cfg -> mailbox */ | |
4845 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4846 | .master = &omap44xx_l4_cfg_hwmod, | |
4847 | .slave = &omap44xx_mailbox_hwmod, | |
4848 | .clk = "l4_div_ck", | |
4849 | .addr = omap44xx_mailbox_addrs, | |
4850 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4851 | }; | |
4852 | ||
896d4e98 BC |
4853 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
4854 | { | |
4855 | .pa_start = 0x40128000, | |
4856 | .pa_end = 0x401283ff, | |
4857 | .flags = ADDR_TYPE_RT | |
4858 | }, | |
4859 | { } | |
4860 | }; | |
4861 | ||
4862 | /* l4_abe -> mcasp */ | |
4863 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
4864 | .master = &omap44xx_l4_abe_hwmod, | |
4865 | .slave = &omap44xx_mcasp_hwmod, | |
4866 | .clk = "ocp_abe_iclk", | |
4867 | .addr = omap44xx_mcasp_addrs, | |
4868 | .user = OCP_USER_MPU, | |
4869 | }; | |
4870 | ||
4871 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
4872 | { | |
4873 | .pa_start = 0x49028000, | |
4874 | .pa_end = 0x490283ff, | |
4875 | .flags = ADDR_TYPE_RT | |
4876 | }, | |
4877 | { } | |
4878 | }; | |
4879 | ||
4880 | /* l4_abe -> mcasp (dma) */ | |
4881 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
4882 | .master = &omap44xx_l4_abe_hwmod, | |
4883 | .slave = &omap44xx_mcasp_hwmod, | |
4884 | .clk = "ocp_abe_iclk", | |
4885 | .addr = omap44xx_mcasp_dma_addrs, | |
4886 | .user = OCP_USER_SDMA, | |
4887 | }; | |
4888 | ||
844a3b63 PW |
4889 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
4890 | { | |
4891 | .name = "mpu", | |
4892 | .pa_start = 0x40122000, | |
4893 | .pa_end = 0x401220ff, | |
4894 | .flags = ADDR_TYPE_RT | |
4895 | }, | |
4896 | { } | |
4897 | }; | |
4898 | ||
4899 | /* l4_abe -> mcbsp1 */ | |
4900 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4901 | .master = &omap44xx_l4_abe_hwmod, | |
4902 | .slave = &omap44xx_mcbsp1_hwmod, | |
4903 | .clk = "ocp_abe_iclk", | |
4904 | .addr = omap44xx_mcbsp1_addrs, | |
4905 | .user = OCP_USER_MPU, | |
4906 | }; | |
4907 | ||
4908 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
4909 | { | |
4910 | .name = "dma", | |
4911 | .pa_start = 0x49022000, | |
4912 | .pa_end = 0x490220ff, | |
4913 | .flags = ADDR_TYPE_RT | |
4914 | }, | |
4915 | { } | |
4916 | }; | |
4917 | ||
4918 | /* l4_abe -> mcbsp1 (dma) */ | |
4919 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
4920 | .master = &omap44xx_l4_abe_hwmod, | |
4921 | .slave = &omap44xx_mcbsp1_hwmod, | |
4922 | .clk = "ocp_abe_iclk", | |
4923 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4924 | .user = OCP_USER_SDMA, | |
4925 | }; | |
4926 | ||
4927 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
4928 | { | |
4929 | .name = "mpu", | |
4930 | .pa_start = 0x40124000, | |
4931 | .pa_end = 0x401240ff, | |
4932 | .flags = ADDR_TYPE_RT | |
4933 | }, | |
4934 | { } | |
4935 | }; | |
4936 | ||
4937 | /* l4_abe -> mcbsp2 */ | |
4938 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4939 | .master = &omap44xx_l4_abe_hwmod, | |
4940 | .slave = &omap44xx_mcbsp2_hwmod, | |
4941 | .clk = "ocp_abe_iclk", | |
4942 | .addr = omap44xx_mcbsp2_addrs, | |
4943 | .user = OCP_USER_MPU, | |
4944 | }; | |
4945 | ||
4946 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
4947 | { | |
4948 | .name = "dma", | |
4949 | .pa_start = 0x49024000, | |
4950 | .pa_end = 0x490240ff, | |
4951 | .flags = ADDR_TYPE_RT | |
4952 | }, | |
4953 | { } | |
4954 | }; | |
4955 | ||
4956 | /* l4_abe -> mcbsp2 (dma) */ | |
4957 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
4958 | .master = &omap44xx_l4_abe_hwmod, | |
4959 | .slave = &omap44xx_mcbsp2_hwmod, | |
4960 | .clk = "ocp_abe_iclk", | |
4961 | .addr = omap44xx_mcbsp2_dma_addrs, | |
4962 | .user = OCP_USER_SDMA, | |
4963 | }; | |
4964 | ||
4965 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
4966 | { | |
4967 | .name = "mpu", | |
4968 | .pa_start = 0x40126000, | |
4969 | .pa_end = 0x401260ff, | |
4970 | .flags = ADDR_TYPE_RT | |
4971 | }, | |
4972 | { } | |
4973 | }; | |
4974 | ||
4975 | /* l4_abe -> mcbsp3 */ | |
4976 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
4977 | .master = &omap44xx_l4_abe_hwmod, | |
4978 | .slave = &omap44xx_mcbsp3_hwmod, | |
4979 | .clk = "ocp_abe_iclk", | |
4980 | .addr = omap44xx_mcbsp3_addrs, | |
4981 | .user = OCP_USER_MPU, | |
4982 | }; | |
4983 | ||
4984 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
4985 | { | |
4986 | .name = "dma", | |
4987 | .pa_start = 0x49026000, | |
4988 | .pa_end = 0x490260ff, | |
4989 | .flags = ADDR_TYPE_RT | |
4990 | }, | |
4991 | { } | |
4992 | }; | |
4993 | ||
4994 | /* l4_abe -> mcbsp3 (dma) */ | |
4995 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
4996 | .master = &omap44xx_l4_abe_hwmod, | |
4997 | .slave = &omap44xx_mcbsp3_hwmod, | |
4998 | .clk = "ocp_abe_iclk", | |
4999 | .addr = omap44xx_mcbsp3_dma_addrs, | |
5000 | .user = OCP_USER_SDMA, | |
5001 | }; | |
5002 | ||
5003 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
5004 | { | |
5005 | .pa_start = 0x48096000, | |
5006 | .pa_end = 0x480960ff, | |
5007 | .flags = ADDR_TYPE_RT | |
5008 | }, | |
5009 | { } | |
5010 | }; | |
5011 | ||
5012 | /* l4_per -> mcbsp4 */ | |
5013 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
5014 | .master = &omap44xx_l4_per_hwmod, | |
5015 | .slave = &omap44xx_mcbsp4_hwmod, | |
5016 | .clk = "l4_div_ck", | |
5017 | .addr = omap44xx_mcbsp4_addrs, | |
5018 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5019 | }; | |
5020 | ||
5021 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
5022 | { | |
5023 | .pa_start = 0x40132000, | |
5024 | .pa_end = 0x4013207f, | |
5025 | .flags = ADDR_TYPE_RT | |
5026 | }, | |
5027 | { } | |
5028 | }; | |
5029 | ||
5030 | /* l4_abe -> mcpdm */ | |
5031 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
5032 | .master = &omap44xx_l4_abe_hwmod, | |
5033 | .slave = &omap44xx_mcpdm_hwmod, | |
5034 | .clk = "ocp_abe_iclk", | |
5035 | .addr = omap44xx_mcpdm_addrs, | |
5036 | .user = OCP_USER_MPU, | |
5037 | }; | |
5038 | ||
5039 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
5040 | { | |
5041 | .pa_start = 0x49032000, | |
5042 | .pa_end = 0x4903207f, | |
5043 | .flags = ADDR_TYPE_RT | |
5044 | }, | |
5045 | { } | |
5046 | }; | |
5047 | ||
5048 | /* l4_abe -> mcpdm (dma) */ | |
5049 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
5050 | .master = &omap44xx_l4_abe_hwmod, | |
5051 | .slave = &omap44xx_mcpdm_hwmod, | |
5052 | .clk = "ocp_abe_iclk", | |
5053 | .addr = omap44xx_mcpdm_dma_addrs, | |
5054 | .user = OCP_USER_SDMA, | |
5055 | }; | |
5056 | ||
5057 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
5058 | { | |
5059 | .pa_start = 0x48098000, | |
5060 | .pa_end = 0x480981ff, | |
5061 | .flags = ADDR_TYPE_RT | |
5062 | }, | |
5063 | { } | |
5064 | }; | |
5065 | ||
5066 | /* l4_per -> mcspi1 */ | |
5067 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
5068 | .master = &omap44xx_l4_per_hwmod, | |
5069 | .slave = &omap44xx_mcspi1_hwmod, | |
5070 | .clk = "l4_div_ck", | |
5071 | .addr = omap44xx_mcspi1_addrs, | |
5072 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5073 | }; | |
5074 | ||
5075 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
5076 | { | |
5077 | .pa_start = 0x4809a000, | |
5078 | .pa_end = 0x4809a1ff, | |
5079 | .flags = ADDR_TYPE_RT | |
5080 | }, | |
5081 | { } | |
5082 | }; | |
5083 | ||
5084 | /* l4_per -> mcspi2 */ | |
5085 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
5086 | .master = &omap44xx_l4_per_hwmod, | |
5087 | .slave = &omap44xx_mcspi2_hwmod, | |
5088 | .clk = "l4_div_ck", | |
5089 | .addr = omap44xx_mcspi2_addrs, | |
5090 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5091 | }; | |
5092 | ||
5093 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
5094 | { | |
5095 | .pa_start = 0x480b8000, | |
5096 | .pa_end = 0x480b81ff, | |
5097 | .flags = ADDR_TYPE_RT | |
5098 | }, | |
5099 | { } | |
5100 | }; | |
5101 | ||
5102 | /* l4_per -> mcspi3 */ | |
5103 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
5104 | .master = &omap44xx_l4_per_hwmod, | |
5105 | .slave = &omap44xx_mcspi3_hwmod, | |
5106 | .clk = "l4_div_ck", | |
5107 | .addr = omap44xx_mcspi3_addrs, | |
5108 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5109 | }; | |
5110 | ||
5111 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
5112 | { | |
5113 | .pa_start = 0x480ba000, | |
5114 | .pa_end = 0x480ba1ff, | |
5115 | .flags = ADDR_TYPE_RT | |
5116 | }, | |
5117 | { } | |
5118 | }; | |
5119 | ||
5120 | /* l4_per -> mcspi4 */ | |
5121 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
5122 | .master = &omap44xx_l4_per_hwmod, | |
5123 | .slave = &omap44xx_mcspi4_hwmod, | |
5124 | .clk = "l4_div_ck", | |
5125 | .addr = omap44xx_mcspi4_addrs, | |
5126 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5127 | }; | |
5128 | ||
5129 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
5130 | { | |
5131 | .pa_start = 0x4809c000, | |
5132 | .pa_end = 0x4809c3ff, | |
5133 | .flags = ADDR_TYPE_RT | |
5134 | }, | |
5135 | { } | |
5136 | }; | |
5137 | ||
5138 | /* l4_per -> mmc1 */ | |
5139 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
5140 | .master = &omap44xx_l4_per_hwmod, | |
5141 | .slave = &omap44xx_mmc1_hwmod, | |
5142 | .clk = "l4_div_ck", | |
5143 | .addr = omap44xx_mmc1_addrs, | |
5144 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5145 | }; | |
5146 | ||
5147 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
5148 | { | |
5149 | .pa_start = 0x480b4000, | |
5150 | .pa_end = 0x480b43ff, | |
5151 | .flags = ADDR_TYPE_RT | |
5152 | }, | |
5153 | { } | |
5154 | }; | |
5155 | ||
5156 | /* l4_per -> mmc2 */ | |
5157 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
5158 | .master = &omap44xx_l4_per_hwmod, | |
5159 | .slave = &omap44xx_mmc2_hwmod, | |
5160 | .clk = "l4_div_ck", | |
5161 | .addr = omap44xx_mmc2_addrs, | |
5162 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5163 | }; | |
5164 | ||
5165 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
5166 | { | |
5167 | .pa_start = 0x480ad000, | |
5168 | .pa_end = 0x480ad3ff, | |
5169 | .flags = ADDR_TYPE_RT | |
5170 | }, | |
5171 | { } | |
5172 | }; | |
5173 | ||
5174 | /* l4_per -> mmc3 */ | |
5175 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
5176 | .master = &omap44xx_l4_per_hwmod, | |
5177 | .slave = &omap44xx_mmc3_hwmod, | |
5178 | .clk = "l4_div_ck", | |
5179 | .addr = omap44xx_mmc3_addrs, | |
5180 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5181 | }; | |
5182 | ||
5183 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
5184 | { | |
5185 | .pa_start = 0x480d1000, | |
5186 | .pa_end = 0x480d13ff, | |
5187 | .flags = ADDR_TYPE_RT | |
5188 | }, | |
5189 | { } | |
5190 | }; | |
5191 | ||
5192 | /* l4_per -> mmc4 */ | |
5193 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
5194 | .master = &omap44xx_l4_per_hwmod, | |
5195 | .slave = &omap44xx_mmc4_hwmod, | |
5196 | .clk = "l4_div_ck", | |
5197 | .addr = omap44xx_mmc4_addrs, | |
5198 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5199 | }; | |
5200 | ||
5201 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
5202 | { | |
5203 | .pa_start = 0x480d5000, | |
5204 | .pa_end = 0x480d53ff, | |
5205 | .flags = ADDR_TYPE_RT | |
5206 | }, | |
5207 | { } | |
5208 | }; | |
5209 | ||
5210 | /* l4_per -> mmc5 */ | |
5211 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
5212 | .master = &omap44xx_l4_per_hwmod, | |
5213 | .slave = &omap44xx_mmc5_hwmod, | |
5214 | .clk = "l4_div_ck", | |
5215 | .addr = omap44xx_mmc5_addrs, | |
5216 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5217 | }; | |
5218 | ||
e17f18c0 PW |
5219 | /* l3_main_2 -> ocmc_ram */ |
5220 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
5221 | .master = &omap44xx_l3_main_2_hwmod, | |
5222 | .slave = &omap44xx_ocmc_ram_hwmod, | |
5223 | .clk = "l3_div_ck", | |
5224 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5225 | }; | |
5226 | ||
0c668875 BC |
5227 | /* l4_cfg -> ocp2scp_usb_phy */ |
5228 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
5229 | .master = &omap44xx_l4_cfg_hwmod, | |
5230 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
5231 | .clk = "l4_div_ck", | |
5232 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5233 | }; | |
5234 | ||
794b480a PW |
5235 | static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { |
5236 | { | |
5237 | .pa_start = 0x48243000, | |
5238 | .pa_end = 0x48243fff, | |
5239 | .flags = ADDR_TYPE_RT | |
5240 | }, | |
5241 | { } | |
5242 | }; | |
5243 | ||
5244 | /* mpu_private -> prcm_mpu */ | |
5245 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
5246 | .master = &omap44xx_mpu_private_hwmod, | |
5247 | .slave = &omap44xx_prcm_mpu_hwmod, | |
5248 | .clk = "l3_div_ck", | |
5249 | .addr = omap44xx_prcm_mpu_addrs, | |
5250 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5251 | }; | |
5252 | ||
5253 | static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { | |
5254 | { | |
5255 | .pa_start = 0x4a004000, | |
5256 | .pa_end = 0x4a004fff, | |
5257 | .flags = ADDR_TYPE_RT | |
5258 | }, | |
5259 | { } | |
5260 | }; | |
5261 | ||
5262 | /* l4_wkup -> cm_core_aon */ | |
5263 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
5264 | .master = &omap44xx_l4_wkup_hwmod, | |
5265 | .slave = &omap44xx_cm_core_aon_hwmod, | |
5266 | .clk = "l4_wkup_clk_mux_ck", | |
5267 | .addr = omap44xx_cm_core_aon_addrs, | |
5268 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5269 | }; | |
5270 | ||
5271 | static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { | |
5272 | { | |
5273 | .pa_start = 0x4a008000, | |
5274 | .pa_end = 0x4a009fff, | |
5275 | .flags = ADDR_TYPE_RT | |
5276 | }, | |
5277 | { } | |
5278 | }; | |
5279 | ||
5280 | /* l4_cfg -> cm_core */ | |
5281 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
5282 | .master = &omap44xx_l4_cfg_hwmod, | |
5283 | .slave = &omap44xx_cm_core_hwmod, | |
5284 | .clk = "l4_div_ck", | |
5285 | .addr = omap44xx_cm_core_addrs, | |
5286 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5287 | }; | |
5288 | ||
5289 | static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { | |
5290 | { | |
5291 | .pa_start = 0x4a306000, | |
5292 | .pa_end = 0x4a307fff, | |
5293 | .flags = ADDR_TYPE_RT | |
5294 | }, | |
5295 | { } | |
5296 | }; | |
5297 | ||
5298 | /* l4_wkup -> prm */ | |
5299 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
5300 | .master = &omap44xx_l4_wkup_hwmod, | |
5301 | .slave = &omap44xx_prm_hwmod, | |
5302 | .clk = "l4_wkup_clk_mux_ck", | |
5303 | .addr = omap44xx_prm_addrs, | |
5304 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5305 | }; | |
5306 | ||
5307 | static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { | |
5308 | { | |
5309 | .pa_start = 0x4a30a000, | |
5310 | .pa_end = 0x4a30a7ff, | |
5311 | .flags = ADDR_TYPE_RT | |
5312 | }, | |
5313 | { } | |
5314 | }; | |
5315 | ||
5316 | /* l4_wkup -> scrm */ | |
5317 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
5318 | .master = &omap44xx_l4_wkup_hwmod, | |
5319 | .slave = &omap44xx_scrm_hwmod, | |
5320 | .clk = "l4_wkup_clk_mux_ck", | |
5321 | .addr = omap44xx_scrm_addrs, | |
5322 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5323 | }; | |
5324 | ||
42b9e387 PW |
5325 | /* l3_main_2 -> sl2if */ |
5326 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { | |
5327 | .master = &omap44xx_l3_main_2_hwmod, | |
5328 | .slave = &omap44xx_sl2if_hwmod, | |
5329 | .clk = "l3_div_ck", | |
5330 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5331 | }; | |
5332 | ||
1e3b5e59 BC |
5333 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
5334 | { | |
5335 | .pa_start = 0x4012c000, | |
5336 | .pa_end = 0x4012c3ff, | |
5337 | .flags = ADDR_TYPE_RT | |
5338 | }, | |
5339 | { } | |
5340 | }; | |
5341 | ||
5342 | /* l4_abe -> slimbus1 */ | |
5343 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
5344 | .master = &omap44xx_l4_abe_hwmod, | |
5345 | .slave = &omap44xx_slimbus1_hwmod, | |
5346 | .clk = "ocp_abe_iclk", | |
5347 | .addr = omap44xx_slimbus1_addrs, | |
5348 | .user = OCP_USER_MPU, | |
5349 | }; | |
5350 | ||
5351 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
5352 | { | |
5353 | .pa_start = 0x4902c000, | |
5354 | .pa_end = 0x4902c3ff, | |
5355 | .flags = ADDR_TYPE_RT | |
5356 | }, | |
5357 | { } | |
5358 | }; | |
5359 | ||
5360 | /* l4_abe -> slimbus1 (dma) */ | |
5361 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
5362 | .master = &omap44xx_l4_abe_hwmod, | |
5363 | .slave = &omap44xx_slimbus1_hwmod, | |
5364 | .clk = "ocp_abe_iclk", | |
5365 | .addr = omap44xx_slimbus1_dma_addrs, | |
5366 | .user = OCP_USER_SDMA, | |
5367 | }; | |
5368 | ||
5369 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
5370 | { | |
5371 | .pa_start = 0x48076000, | |
5372 | .pa_end = 0x480763ff, | |
5373 | .flags = ADDR_TYPE_RT | |
5374 | }, | |
5375 | { } | |
5376 | }; | |
5377 | ||
5378 | /* l4_per -> slimbus2 */ | |
5379 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
5380 | .master = &omap44xx_l4_per_hwmod, | |
5381 | .slave = &omap44xx_slimbus2_hwmod, | |
5382 | .clk = "l4_div_ck", | |
5383 | .addr = omap44xx_slimbus2_addrs, | |
5384 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5385 | }; | |
5386 | ||
844a3b63 PW |
5387 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
5388 | { | |
5389 | .pa_start = 0x4a0dd000, | |
5390 | .pa_end = 0x4a0dd03f, | |
5391 | .flags = ADDR_TYPE_RT | |
5392 | }, | |
5393 | { } | |
5394 | }; | |
5395 | ||
5396 | /* l4_cfg -> smartreflex_core */ | |
5397 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
5398 | .master = &omap44xx_l4_cfg_hwmod, | |
5399 | .slave = &omap44xx_smartreflex_core_hwmod, | |
5400 | .clk = "l4_div_ck", | |
5401 | .addr = omap44xx_smartreflex_core_addrs, | |
5402 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5403 | }; | |
5404 | ||
5405 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
5406 | { | |
5407 | .pa_start = 0x4a0db000, | |
5408 | .pa_end = 0x4a0db03f, | |
5409 | .flags = ADDR_TYPE_RT | |
5410 | }, | |
5411 | { } | |
5412 | }; | |
5413 | ||
5414 | /* l4_cfg -> smartreflex_iva */ | |
5415 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
5416 | .master = &omap44xx_l4_cfg_hwmod, | |
5417 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
5418 | .clk = "l4_div_ck", | |
5419 | .addr = omap44xx_smartreflex_iva_addrs, | |
5420 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5421 | }; | |
5422 | ||
5423 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
5424 | { | |
5425 | .pa_start = 0x4a0d9000, | |
5426 | .pa_end = 0x4a0d903f, | |
5427 | .flags = ADDR_TYPE_RT | |
5428 | }, | |
5429 | { } | |
5430 | }; | |
5431 | ||
5432 | /* l4_cfg -> smartreflex_mpu */ | |
5433 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
5434 | .master = &omap44xx_l4_cfg_hwmod, | |
5435 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
5436 | .clk = "l4_div_ck", | |
5437 | .addr = omap44xx_smartreflex_mpu_addrs, | |
5438 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5439 | }; | |
5440 | ||
5441 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
5442 | { | |
5443 | .pa_start = 0x4a0f6000, | |
5444 | .pa_end = 0x4a0f6fff, | |
5445 | .flags = ADDR_TYPE_RT | |
5446 | }, | |
5447 | { } | |
5448 | }; | |
5449 | ||
5450 | /* l4_cfg -> spinlock */ | |
5451 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
5452 | .master = &omap44xx_l4_cfg_hwmod, | |
5453 | .slave = &omap44xx_spinlock_hwmod, | |
5454 | .clk = "l4_div_ck", | |
5455 | .addr = omap44xx_spinlock_addrs, | |
5456 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5457 | }; | |
5458 | ||
5459 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
5460 | { | |
5461 | .pa_start = 0x4a318000, | |
5462 | .pa_end = 0x4a31807f, | |
5463 | .flags = ADDR_TYPE_RT | |
5464 | }, | |
5465 | { } | |
5466 | }; | |
5467 | ||
5468 | /* l4_wkup -> timer1 */ | |
5469 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
5470 | .master = &omap44xx_l4_wkup_hwmod, | |
5471 | .slave = &omap44xx_timer1_hwmod, | |
5472 | .clk = "l4_wkup_clk_mux_ck", | |
5473 | .addr = omap44xx_timer1_addrs, | |
5474 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5475 | }; | |
5476 | ||
5477 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
5478 | { | |
5479 | .pa_start = 0x48032000, | |
5480 | .pa_end = 0x4803207f, | |
5481 | .flags = ADDR_TYPE_RT | |
5482 | }, | |
5483 | { } | |
5484 | }; | |
5485 | ||
5486 | /* l4_per -> timer2 */ | |
5487 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
5488 | .master = &omap44xx_l4_per_hwmod, | |
5489 | .slave = &omap44xx_timer2_hwmod, | |
5490 | .clk = "l4_div_ck", | |
5491 | .addr = omap44xx_timer2_addrs, | |
5492 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5493 | }; | |
5494 | ||
5495 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
5496 | { | |
5497 | .pa_start = 0x48034000, | |
5498 | .pa_end = 0x4803407f, | |
5499 | .flags = ADDR_TYPE_RT | |
5500 | }, | |
5501 | { } | |
5502 | }; | |
5503 | ||
5504 | /* l4_per -> timer3 */ | |
5505 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
5506 | .master = &omap44xx_l4_per_hwmod, | |
5507 | .slave = &omap44xx_timer3_hwmod, | |
5508 | .clk = "l4_div_ck", | |
5509 | .addr = omap44xx_timer3_addrs, | |
5510 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5511 | }; | |
5512 | ||
5513 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
5514 | { | |
5515 | .pa_start = 0x48036000, | |
5516 | .pa_end = 0x4803607f, | |
5517 | .flags = ADDR_TYPE_RT | |
5518 | }, | |
5519 | { } | |
5520 | }; | |
5521 | ||
5522 | /* l4_per -> timer4 */ | |
5523 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
5524 | .master = &omap44xx_l4_per_hwmod, | |
5525 | .slave = &omap44xx_timer4_hwmod, | |
5526 | .clk = "l4_div_ck", | |
5527 | .addr = omap44xx_timer4_addrs, | |
5528 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5529 | }; | |
5530 | ||
5531 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
5532 | { | |
5533 | .pa_start = 0x40138000, | |
5534 | .pa_end = 0x4013807f, | |
5535 | .flags = ADDR_TYPE_RT | |
5536 | }, | |
5537 | { } | |
5538 | }; | |
5539 | ||
5540 | /* l4_abe -> timer5 */ | |
5541 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
5542 | .master = &omap44xx_l4_abe_hwmod, | |
5543 | .slave = &omap44xx_timer5_hwmod, | |
5544 | .clk = "ocp_abe_iclk", | |
5545 | .addr = omap44xx_timer5_addrs, | |
5546 | .user = OCP_USER_MPU, | |
5547 | }; | |
5548 | ||
5549 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
5550 | { | |
5551 | .pa_start = 0x49038000, | |
5552 | .pa_end = 0x4903807f, | |
5553 | .flags = ADDR_TYPE_RT | |
5554 | }, | |
5555 | { } | |
5556 | }; | |
5557 | ||
5558 | /* l4_abe -> timer5 (dma) */ | |
5559 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
5560 | .master = &omap44xx_l4_abe_hwmod, | |
5561 | .slave = &omap44xx_timer5_hwmod, | |
5562 | .clk = "ocp_abe_iclk", | |
5563 | .addr = omap44xx_timer5_dma_addrs, | |
5564 | .user = OCP_USER_SDMA, | |
5565 | }; | |
5566 | ||
5567 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
5568 | { | |
5569 | .pa_start = 0x4013a000, | |
5570 | .pa_end = 0x4013a07f, | |
5571 | .flags = ADDR_TYPE_RT | |
5572 | }, | |
5573 | { } | |
5574 | }; | |
5575 | ||
5576 | /* l4_abe -> timer6 */ | |
5577 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
5578 | .master = &omap44xx_l4_abe_hwmod, | |
5579 | .slave = &omap44xx_timer6_hwmod, | |
5580 | .clk = "ocp_abe_iclk", | |
5581 | .addr = omap44xx_timer6_addrs, | |
5582 | .user = OCP_USER_MPU, | |
5583 | }; | |
5584 | ||
5585 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
5586 | { | |
5587 | .pa_start = 0x4903a000, | |
5588 | .pa_end = 0x4903a07f, | |
5589 | .flags = ADDR_TYPE_RT | |
5590 | }, | |
5591 | { } | |
5592 | }; | |
5593 | ||
5594 | /* l4_abe -> timer6 (dma) */ | |
5595 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
5596 | .master = &omap44xx_l4_abe_hwmod, | |
5597 | .slave = &omap44xx_timer6_hwmod, | |
5598 | .clk = "ocp_abe_iclk", | |
5599 | .addr = omap44xx_timer6_dma_addrs, | |
5600 | .user = OCP_USER_SDMA, | |
5601 | }; | |
5602 | ||
5603 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
5604 | { | |
5605 | .pa_start = 0x4013c000, | |
5606 | .pa_end = 0x4013c07f, | |
5607 | .flags = ADDR_TYPE_RT | |
5608 | }, | |
5609 | { } | |
5610 | }; | |
5611 | ||
5612 | /* l4_abe -> timer7 */ | |
5613 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
5614 | .master = &omap44xx_l4_abe_hwmod, | |
5615 | .slave = &omap44xx_timer7_hwmod, | |
5616 | .clk = "ocp_abe_iclk", | |
5617 | .addr = omap44xx_timer7_addrs, | |
5618 | .user = OCP_USER_MPU, | |
5619 | }; | |
5620 | ||
5621 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
5622 | { | |
5623 | .pa_start = 0x4903c000, | |
5624 | .pa_end = 0x4903c07f, | |
5625 | .flags = ADDR_TYPE_RT | |
5626 | }, | |
5627 | { } | |
5628 | }; | |
5629 | ||
5630 | /* l4_abe -> timer7 (dma) */ | |
5631 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
5632 | .master = &omap44xx_l4_abe_hwmod, | |
5633 | .slave = &omap44xx_timer7_hwmod, | |
5634 | .clk = "ocp_abe_iclk", | |
5635 | .addr = omap44xx_timer7_dma_addrs, | |
5636 | .user = OCP_USER_SDMA, | |
5637 | }; | |
5638 | ||
5639 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
5640 | { | |
5641 | .pa_start = 0x4013e000, | |
5642 | .pa_end = 0x4013e07f, | |
5643 | .flags = ADDR_TYPE_RT | |
5644 | }, | |
5645 | { } | |
5646 | }; | |
5647 | ||
5648 | /* l4_abe -> timer8 */ | |
5649 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
5650 | .master = &omap44xx_l4_abe_hwmod, | |
5651 | .slave = &omap44xx_timer8_hwmod, | |
5652 | .clk = "ocp_abe_iclk", | |
5653 | .addr = omap44xx_timer8_addrs, | |
5654 | .user = OCP_USER_MPU, | |
5655 | }; | |
5656 | ||
5657 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
5658 | { | |
5659 | .pa_start = 0x4903e000, | |
5660 | .pa_end = 0x4903e07f, | |
5661 | .flags = ADDR_TYPE_RT | |
5662 | }, | |
5663 | { } | |
5664 | }; | |
5665 | ||
5666 | /* l4_abe -> timer8 (dma) */ | |
5667 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
5668 | .master = &omap44xx_l4_abe_hwmod, | |
5669 | .slave = &omap44xx_timer8_hwmod, | |
5670 | .clk = "ocp_abe_iclk", | |
5671 | .addr = omap44xx_timer8_dma_addrs, | |
5672 | .user = OCP_USER_SDMA, | |
5673 | }; | |
5674 | ||
5675 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
5676 | { | |
5677 | .pa_start = 0x4803e000, | |
5678 | .pa_end = 0x4803e07f, | |
5679 | .flags = ADDR_TYPE_RT | |
5680 | }, | |
5681 | { } | |
5682 | }; | |
5683 | ||
5684 | /* l4_per -> timer9 */ | |
5685 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
5686 | .master = &omap44xx_l4_per_hwmod, | |
5687 | .slave = &omap44xx_timer9_hwmod, | |
5688 | .clk = "l4_div_ck", | |
5689 | .addr = omap44xx_timer9_addrs, | |
5690 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5691 | }; | |
5692 | ||
5693 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
5694 | { | |
5695 | .pa_start = 0x48086000, | |
5696 | .pa_end = 0x4808607f, | |
5697 | .flags = ADDR_TYPE_RT | |
5698 | }, | |
5699 | { } | |
5700 | }; | |
5701 | ||
5702 | /* l4_per -> timer10 */ | |
5703 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
5704 | .master = &omap44xx_l4_per_hwmod, | |
5705 | .slave = &omap44xx_timer10_hwmod, | |
5706 | .clk = "l4_div_ck", | |
5707 | .addr = omap44xx_timer10_addrs, | |
5708 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5709 | }; | |
5710 | ||
5711 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
5712 | { | |
5713 | .pa_start = 0x48088000, | |
5714 | .pa_end = 0x4808807f, | |
5715 | .flags = ADDR_TYPE_RT | |
5716 | }, | |
5717 | { } | |
5718 | }; | |
5719 | ||
5720 | /* l4_per -> timer11 */ | |
5721 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
5722 | .master = &omap44xx_l4_per_hwmod, | |
5723 | .slave = &omap44xx_timer11_hwmod, | |
5724 | .clk = "l4_div_ck", | |
5725 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
5726 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5727 | }; | |
5728 | ||
844a3b63 PW |
5729 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
5730 | { | |
5731 | .pa_start = 0x4806a000, | |
5732 | .pa_end = 0x4806a0ff, | |
5733 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5734 | }, |
844a3b63 PW |
5735 | { } |
5736 | }; | |
af88fa9a | 5737 | |
844a3b63 PW |
5738 | /* l4_per -> uart1 */ |
5739 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
5740 | .master = &omap44xx_l4_per_hwmod, | |
5741 | .slave = &omap44xx_uart1_hwmod, | |
5742 | .clk = "l4_div_ck", | |
5743 | .addr = omap44xx_uart1_addrs, | |
5744 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5745 | }; | |
af88fa9a | 5746 | |
844a3b63 PW |
5747 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
5748 | { | |
5749 | .pa_start = 0x4806c000, | |
5750 | .pa_end = 0x4806c0ff, | |
5751 | .flags = ADDR_TYPE_RT | |
5752 | }, | |
5753 | { } | |
5754 | }; | |
af88fa9a | 5755 | |
844a3b63 PW |
5756 | /* l4_per -> uart2 */ |
5757 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
5758 | .master = &omap44xx_l4_per_hwmod, | |
5759 | .slave = &omap44xx_uart2_hwmod, | |
5760 | .clk = "l4_div_ck", | |
5761 | .addr = omap44xx_uart2_addrs, | |
5762 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5763 | }; | |
af88fa9a | 5764 | |
844a3b63 PW |
5765 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
5766 | { | |
5767 | .pa_start = 0x48020000, | |
5768 | .pa_end = 0x480200ff, | |
5769 | .flags = ADDR_TYPE_RT | |
5770 | }, | |
5771 | { } | |
af88fa9a BC |
5772 | }; |
5773 | ||
844a3b63 PW |
5774 | /* l4_per -> uart3 */ |
5775 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
5776 | .master = &omap44xx_l4_per_hwmod, | |
5777 | .slave = &omap44xx_uart3_hwmod, | |
5778 | .clk = "l4_div_ck", | |
5779 | .addr = omap44xx_uart3_addrs, | |
5780 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5781 | }; |
5782 | ||
844a3b63 PW |
5783 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
5784 | { | |
5785 | .pa_start = 0x4806e000, | |
5786 | .pa_end = 0x4806e0ff, | |
5787 | .flags = ADDR_TYPE_RT | |
5788 | }, | |
5789 | { } | |
af88fa9a BC |
5790 | }; |
5791 | ||
844a3b63 PW |
5792 | /* l4_per -> uart4 */ |
5793 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
5794 | .master = &omap44xx_l4_per_hwmod, | |
5795 | .slave = &omap44xx_uart4_hwmod, | |
5796 | .clk = "l4_div_ck", | |
5797 | .addr = omap44xx_uart4_addrs, | |
5798 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5799 | }; | |
5800 | ||
0c668875 BC |
5801 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { |
5802 | { | |
5803 | .pa_start = 0x4a0a9000, | |
5804 | .pa_end = 0x4a0a93ff, | |
5805 | .flags = ADDR_TYPE_RT | |
5806 | }, | |
5807 | { } | |
5808 | }; | |
5809 | ||
5810 | /* l4_cfg -> usb_host_fs */ | |
5811 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = { | |
5812 | .master = &omap44xx_l4_cfg_hwmod, | |
5813 | .slave = &omap44xx_usb_host_fs_hwmod, | |
5814 | .clk = "l4_div_ck", | |
5815 | .addr = omap44xx_usb_host_fs_addrs, | |
5816 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5817 | }; | |
5818 | ||
844a3b63 PW |
5819 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
5820 | { | |
5821 | .name = "uhh", | |
5822 | .pa_start = 0x4a064000, | |
5823 | .pa_end = 0x4a0647ff, | |
5824 | .flags = ADDR_TYPE_RT | |
5825 | }, | |
5826 | { | |
5827 | .name = "ohci", | |
5828 | .pa_start = 0x4a064800, | |
5829 | .pa_end = 0x4a064bff, | |
5830 | }, | |
5831 | { | |
5832 | .name = "ehci", | |
5833 | .pa_start = 0x4a064c00, | |
5834 | .pa_end = 0x4a064fff, | |
5835 | }, | |
5836 | {} | |
5837 | }; | |
5838 | ||
5839 | /* l4_cfg -> usb_host_hs */ | |
5840 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
5841 | .master = &omap44xx_l4_cfg_hwmod, | |
5842 | .slave = &omap44xx_usb_host_hs_hwmod, | |
5843 | .clk = "l4_div_ck", | |
5844 | .addr = omap44xx_usb_host_hs_addrs, | |
5845 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5846 | }; | |
5847 | ||
5848 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
5849 | { | |
5850 | .pa_start = 0x4a0ab000, | |
5851 | .pa_end = 0x4a0ab003, | |
5852 | .flags = ADDR_TYPE_RT | |
5853 | }, | |
5854 | { } | |
5855 | }; | |
5856 | ||
5857 | /* l4_cfg -> usb_otg_hs */ | |
5858 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
5859 | .master = &omap44xx_l4_cfg_hwmod, | |
5860 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
5861 | .clk = "l4_div_ck", | |
5862 | .addr = omap44xx_usb_otg_hs_addrs, | |
5863 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5864 | }; |
5865 | ||
5866 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
5867 | { | |
5868 | .name = "tll", | |
5869 | .pa_start = 0x4a062000, | |
5870 | .pa_end = 0x4a063fff, | |
5871 | .flags = ADDR_TYPE_RT | |
5872 | }, | |
5873 | {} | |
5874 | }; | |
5875 | ||
844a3b63 | 5876 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
5877 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
5878 | .master = &omap44xx_l4_cfg_hwmod, | |
5879 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
5880 | .clk = "l4_div_ck", | |
5881 | .addr = omap44xx_usb_tll_hs_addrs, | |
5882 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5883 | }; | |
5884 | ||
844a3b63 PW |
5885 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
5886 | { | |
5887 | .pa_start = 0x4a314000, | |
5888 | .pa_end = 0x4a31407f, | |
5889 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5890 | }, |
844a3b63 PW |
5891 | { } |
5892 | }; | |
5893 | ||
5894 | /* l4_wkup -> wd_timer2 */ | |
5895 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
5896 | .master = &omap44xx_l4_wkup_hwmod, | |
5897 | .slave = &omap44xx_wd_timer2_hwmod, | |
5898 | .clk = "l4_wkup_clk_mux_ck", | |
5899 | .addr = omap44xx_wd_timer2_addrs, | |
5900 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5901 | }; | |
5902 | ||
5903 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
5904 | { | |
5905 | .pa_start = 0x40130000, | |
5906 | .pa_end = 0x4013007f, | |
5907 | .flags = ADDR_TYPE_RT | |
5908 | }, | |
5909 | { } | |
5910 | }; | |
5911 | ||
5912 | /* l4_abe -> wd_timer3 */ | |
5913 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
5914 | .master = &omap44xx_l4_abe_hwmod, | |
5915 | .slave = &omap44xx_wd_timer3_hwmod, | |
5916 | .clk = "ocp_abe_iclk", | |
5917 | .addr = omap44xx_wd_timer3_addrs, | |
5918 | .user = OCP_USER_MPU, | |
5919 | }; | |
5920 | ||
5921 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
5922 | { | |
5923 | .pa_start = 0x49030000, | |
5924 | .pa_end = 0x4903007f, | |
5925 | .flags = ADDR_TYPE_RT | |
5926 | }, | |
5927 | { } | |
5928 | }; | |
5929 | ||
5930 | /* l4_abe -> wd_timer3 (dma) */ | |
5931 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
5932 | .master = &omap44xx_l4_abe_hwmod, | |
5933 | .slave = &omap44xx_wd_timer3_hwmod, | |
5934 | .clk = "ocp_abe_iclk", | |
5935 | .addr = omap44xx_wd_timer3_dma_addrs, | |
5936 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
5937 | }; |
5938 | ||
0a78c5c5 | 5939 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
42b9e387 PW |
5940 | &omap44xx_c2c__c2c_target_fw, |
5941 | &omap44xx_l4_cfg__c2c_target_fw, | |
0a78c5c5 PW |
5942 | &omap44xx_l3_main_1__dmm, |
5943 | &omap44xx_mpu__dmm, | |
42b9e387 | 5944 | &omap44xx_c2c__emif_fw, |
0a78c5c5 PW |
5945 | &omap44xx_dmm__emif_fw, |
5946 | &omap44xx_l4_cfg__emif_fw, | |
5947 | &omap44xx_iva__l3_instr, | |
5948 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 5949 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
5950 | &omap44xx_dsp__l3_main_1, |
5951 | &omap44xx_dss__l3_main_1, | |
5952 | &omap44xx_l3_main_2__l3_main_1, | |
5953 | &omap44xx_l4_cfg__l3_main_1, | |
5954 | &omap44xx_mmc1__l3_main_1, | |
5955 | &omap44xx_mmc2__l3_main_1, | |
5956 | &omap44xx_mpu__l3_main_1, | |
42b9e387 | 5957 | &omap44xx_c2c_target_fw__l3_main_2, |
0a78c5c5 | 5958 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 5959 | &omap44xx_fdif__l3_main_2, |
9def390e | 5960 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
5961 | &omap44xx_hsi__l3_main_2, |
5962 | &omap44xx_ipu__l3_main_2, | |
5963 | &omap44xx_iss__l3_main_2, | |
5964 | &omap44xx_iva__l3_main_2, | |
5965 | &omap44xx_l3_main_1__l3_main_2, | |
5966 | &omap44xx_l4_cfg__l3_main_2, | |
0c668875 | 5967 | &omap44xx_usb_host_fs__l3_main_2, |
0a78c5c5 PW |
5968 | &omap44xx_usb_host_hs__l3_main_2, |
5969 | &omap44xx_usb_otg_hs__l3_main_2, | |
5970 | &omap44xx_l3_main_1__l3_main_3, | |
5971 | &omap44xx_l3_main_2__l3_main_3, | |
5972 | &omap44xx_l4_cfg__l3_main_3, | |
5973 | &omap44xx_aess__l4_abe, | |
5974 | &omap44xx_dsp__l4_abe, | |
5975 | &omap44xx_l3_main_1__l4_abe, | |
5976 | &omap44xx_mpu__l4_abe, | |
5977 | &omap44xx_l3_main_1__l4_cfg, | |
5978 | &omap44xx_l3_main_2__l4_per, | |
5979 | &omap44xx_l4_cfg__l4_wkup, | |
5980 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 5981 | &omap44xx_l4_cfg__ocp_wp_noc, |
0a78c5c5 PW |
5982 | &omap44xx_l4_abe__aess, |
5983 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 5984 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 5985 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
5986 | &omap44xx_l4_cfg__ctrl_module_core, |
5987 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
5988 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
5989 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
0a78c5c5 PW |
5990 | &omap44xx_l4_cfg__dma_system, |
5991 | &omap44xx_l4_abe__dmic, | |
5992 | &omap44xx_l4_abe__dmic_dma, | |
5993 | &omap44xx_dsp__iva, | |
42b9e387 | 5994 | &omap44xx_dsp__sl2if, |
0a78c5c5 PW |
5995 | &omap44xx_l4_cfg__dsp, |
5996 | &omap44xx_l3_main_2__dss, | |
5997 | &omap44xx_l4_per__dss, | |
5998 | &omap44xx_l3_main_2__dss_dispc, | |
5999 | &omap44xx_l4_per__dss_dispc, | |
6000 | &omap44xx_l3_main_2__dss_dsi1, | |
6001 | &omap44xx_l4_per__dss_dsi1, | |
6002 | &omap44xx_l3_main_2__dss_dsi2, | |
6003 | &omap44xx_l4_per__dss_dsi2, | |
6004 | &omap44xx_l3_main_2__dss_hdmi, | |
6005 | &omap44xx_l4_per__dss_hdmi, | |
6006 | &omap44xx_l3_main_2__dss_rfbi, | |
6007 | &omap44xx_l4_per__dss_rfbi, | |
6008 | &omap44xx_l3_main_2__dss_venc, | |
6009 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 6010 | &omap44xx_l4_per__elm, |
bf30f950 PW |
6011 | &omap44xx_emif_fw__emif1, |
6012 | &omap44xx_emif_fw__emif2, | |
b050f688 | 6013 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
6014 | &omap44xx_l4_wkup__gpio1, |
6015 | &omap44xx_l4_per__gpio2, | |
6016 | &omap44xx_l4_per__gpio3, | |
6017 | &omap44xx_l4_per__gpio4, | |
6018 | &omap44xx_l4_per__gpio5, | |
6019 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 6020 | &omap44xx_l3_main_2__gpmc, |
9def390e | 6021 | &omap44xx_l3_main_2__gpu, |
a091c08e | 6022 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
6023 | &omap44xx_l4_cfg__hsi, |
6024 | &omap44xx_l4_per__i2c1, | |
6025 | &omap44xx_l4_per__i2c2, | |
6026 | &omap44xx_l4_per__i2c3, | |
6027 | &omap44xx_l4_per__i2c4, | |
6028 | &omap44xx_l3_main_2__ipu, | |
6029 | &omap44xx_l3_main_2__iss, | |
42b9e387 | 6030 | &omap44xx_iva__sl2if, |
0a78c5c5 PW |
6031 | &omap44xx_l3_main_2__iva, |
6032 | &omap44xx_l4_wkup__kbd, | |
6033 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
6034 | &omap44xx_l4_abe__mcasp, |
6035 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 PW |
6036 | &omap44xx_l4_abe__mcbsp1, |
6037 | &omap44xx_l4_abe__mcbsp1_dma, | |
6038 | &omap44xx_l4_abe__mcbsp2, | |
6039 | &omap44xx_l4_abe__mcbsp2_dma, | |
6040 | &omap44xx_l4_abe__mcbsp3, | |
6041 | &omap44xx_l4_abe__mcbsp3_dma, | |
6042 | &omap44xx_l4_per__mcbsp4, | |
6043 | &omap44xx_l4_abe__mcpdm, | |
6044 | &omap44xx_l4_abe__mcpdm_dma, | |
6045 | &omap44xx_l4_per__mcspi1, | |
6046 | &omap44xx_l4_per__mcspi2, | |
6047 | &omap44xx_l4_per__mcspi3, | |
6048 | &omap44xx_l4_per__mcspi4, | |
6049 | &omap44xx_l4_per__mmc1, | |
6050 | &omap44xx_l4_per__mmc2, | |
6051 | &omap44xx_l4_per__mmc3, | |
6052 | &omap44xx_l4_per__mmc4, | |
6053 | &omap44xx_l4_per__mmc5, | |
e17f18c0 | 6054 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 6055 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
6056 | &omap44xx_mpu_private__prcm_mpu, |
6057 | &omap44xx_l4_wkup__cm_core_aon, | |
6058 | &omap44xx_l4_cfg__cm_core, | |
6059 | &omap44xx_l4_wkup__prm, | |
6060 | &omap44xx_l4_wkup__scrm, | |
42b9e387 | 6061 | &omap44xx_l3_main_2__sl2if, |
1e3b5e59 BC |
6062 | &omap44xx_l4_abe__slimbus1, |
6063 | &omap44xx_l4_abe__slimbus1_dma, | |
6064 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
6065 | &omap44xx_l4_cfg__smartreflex_core, |
6066 | &omap44xx_l4_cfg__smartreflex_iva, | |
6067 | &omap44xx_l4_cfg__smartreflex_mpu, | |
6068 | &omap44xx_l4_cfg__spinlock, | |
6069 | &omap44xx_l4_wkup__timer1, | |
6070 | &omap44xx_l4_per__timer2, | |
6071 | &omap44xx_l4_per__timer3, | |
6072 | &omap44xx_l4_per__timer4, | |
6073 | &omap44xx_l4_abe__timer5, | |
6074 | &omap44xx_l4_abe__timer5_dma, | |
6075 | &omap44xx_l4_abe__timer6, | |
6076 | &omap44xx_l4_abe__timer6_dma, | |
6077 | &omap44xx_l4_abe__timer7, | |
6078 | &omap44xx_l4_abe__timer7_dma, | |
6079 | &omap44xx_l4_abe__timer8, | |
6080 | &omap44xx_l4_abe__timer8_dma, | |
6081 | &omap44xx_l4_per__timer9, | |
6082 | &omap44xx_l4_per__timer10, | |
6083 | &omap44xx_l4_per__timer11, | |
6084 | &omap44xx_l4_per__uart1, | |
6085 | &omap44xx_l4_per__uart2, | |
6086 | &omap44xx_l4_per__uart3, | |
6087 | &omap44xx_l4_per__uart4, | |
0c668875 | 6088 | &omap44xx_l4_cfg__usb_host_fs, |
0a78c5c5 PW |
6089 | &omap44xx_l4_cfg__usb_host_hs, |
6090 | &omap44xx_l4_cfg__usb_otg_hs, | |
6091 | &omap44xx_l4_cfg__usb_tll_hs, | |
6092 | &omap44xx_l4_wkup__wd_timer2, | |
6093 | &omap44xx_l4_abe__wd_timer3, | |
6094 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
6095 | NULL, |
6096 | }; | |
6097 | ||
6098 | int __init omap44xx_hwmod_init(void) | |
6099 | { | |
0a78c5c5 | 6100 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
6101 | } |
6102 |