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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
6d3c55fd | 25 | #include <plat/i2c.h> |
9780a9cf | 26 | #include <plat/gpio.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
c345c8b0 | 31 | #include <plat/dmtimer.h> |
13662dc5 | 32 | #include <plat/common.h> |
55d2cb08 BC |
33 | |
34 | #include "omap_hwmod_common_data.h" | |
35 | ||
cea6b942 | 36 | #include "smartreflex.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
ff2516fb | 41 | #include "wd_timer.h" |
55d2cb08 BC |
42 | |
43 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
44 | #define OMAP44XX_IRQ_GIC_START 32 | |
45 | ||
46 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 47 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
48 | |
49 | /* | |
844a3b63 | 50 | * IP blocks |
55d2cb08 BC |
51 | */ |
52 | ||
42b9e387 PW |
53 | /* |
54 | * 'c2c_target_fw' class | |
55 | * instance(s): c2c_target_fw | |
56 | */ | |
57 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | |
58 | .name = "c2c_target_fw", | |
59 | }; | |
60 | ||
61 | /* c2c_target_fw */ | |
62 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | |
63 | .name = "c2c_target_fw", | |
64 | .class = &omap44xx_c2c_target_fw_hwmod_class, | |
65 | .clkdm_name = "d2d_clkdm", | |
66 | .prcm = { | |
67 | .omap4 = { | |
68 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | |
69 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | |
70 | }, | |
71 | }, | |
72 | }; | |
73 | ||
55d2cb08 BC |
74 | /* |
75 | * 'dmm' class | |
76 | * instance(s): dmm | |
77 | */ | |
78 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 79 | .name = "dmm", |
55d2cb08 BC |
80 | }; |
81 | ||
7e69ed97 BC |
82 | /* dmm */ |
83 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
84 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
85 | { .irq = -1 } | |
86 | }; | |
87 | ||
55d2cb08 BC |
88 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
89 | .name = "dmm", | |
90 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 91 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 92 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
93 | .prcm = { |
94 | .omap4 = { | |
95 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 96 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
97 | }, |
98 | }, | |
55d2cb08 BC |
99 | }; |
100 | ||
101 | /* | |
102 | * 'emif_fw' class | |
103 | * instance(s): emif_fw | |
104 | */ | |
105 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 106 | .name = "emif_fw", |
55d2cb08 BC |
107 | }; |
108 | ||
7e69ed97 | 109 | /* emif_fw */ |
55d2cb08 BC |
110 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
111 | .name = "emif_fw", | |
112 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 113 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
114 | .prcm = { |
115 | .omap4 = { | |
116 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 117 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
118 | }, |
119 | }, | |
55d2cb08 BC |
120 | }; |
121 | ||
122 | /* | |
123 | * 'l3' class | |
124 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
125 | */ | |
126 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 127 | .name = "l3", |
55d2cb08 BC |
128 | }; |
129 | ||
7e69ed97 | 130 | /* l3_instr */ |
55d2cb08 BC |
131 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
132 | .name = "l3_instr", | |
133 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 134 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
135 | .prcm = { |
136 | .omap4 = { | |
137 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 138 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 139 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
140 | }, |
141 | }, | |
55d2cb08 BC |
142 | }; |
143 | ||
7e69ed97 | 144 | /* l3_main_1 */ |
9b4021be BC |
145 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
146 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
147 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
148 | { .irq = -1 } | |
149 | }; | |
150 | ||
55d2cb08 BC |
151 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
152 | .name = "l3_main_1", | |
153 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 154 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 155 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
156 | .prcm = { |
157 | .omap4 = { | |
158 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 159 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
160 | }, |
161 | }, | |
55d2cb08 BC |
162 | }; |
163 | ||
7e69ed97 | 164 | /* l3_main_2 */ |
55d2cb08 BC |
165 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
166 | .name = "l3_main_2", | |
167 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 168 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
169 | .prcm = { |
170 | .omap4 = { | |
171 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 172 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
173 | }, |
174 | }, | |
55d2cb08 BC |
175 | }; |
176 | ||
7e69ed97 | 177 | /* l3_main_3 */ |
55d2cb08 BC |
178 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
179 | .name = "l3_main_3", | |
180 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 181 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
182 | .prcm = { |
183 | .omap4 = { | |
184 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 185 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 186 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
187 | }, |
188 | }, | |
55d2cb08 BC |
189 | }; |
190 | ||
191 | /* | |
192 | * 'l4' class | |
193 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
194 | */ | |
195 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 196 | .name = "l4", |
55d2cb08 BC |
197 | }; |
198 | ||
7e69ed97 | 199 | /* l4_abe */ |
55d2cb08 BC |
200 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
201 | .name = "l4_abe", | |
202 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 203 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
204 | .prcm = { |
205 | .omap4 = { | |
206 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
207 | }, | |
208 | }, | |
55d2cb08 BC |
209 | }; |
210 | ||
7e69ed97 | 211 | /* l4_cfg */ |
55d2cb08 BC |
212 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
213 | .name = "l4_cfg", | |
214 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 215 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
216 | .prcm = { |
217 | .omap4 = { | |
218 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 219 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
220 | }, |
221 | }, | |
55d2cb08 BC |
222 | }; |
223 | ||
7e69ed97 | 224 | /* l4_per */ |
55d2cb08 BC |
225 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
226 | .name = "l4_per", | |
227 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 228 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
229 | .prcm = { |
230 | .omap4 = { | |
231 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 232 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
233 | }, |
234 | }, | |
55d2cb08 BC |
235 | }; |
236 | ||
7e69ed97 | 237 | /* l4_wkup */ |
55d2cb08 BC |
238 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
239 | .name = "l4_wkup", | |
240 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 241 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
242 | .prcm = { |
243 | .omap4 = { | |
244 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 245 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
246 | }, |
247 | }, | |
55d2cb08 BC |
248 | }; |
249 | ||
f776471f | 250 | /* |
3b54baad BC |
251 | * 'mpu_bus' class |
252 | * instance(s): mpu_private | |
f776471f | 253 | */ |
3b54baad | 254 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 255 | .name = "mpu_bus", |
3b54baad | 256 | }; |
f776471f | 257 | |
7e69ed97 | 258 | /* mpu_private */ |
3b54baad BC |
259 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
260 | .name = "mpu_private", | |
261 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 262 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
263 | }; |
264 | ||
9a817bc8 BC |
265 | /* |
266 | * 'ocp_wp_noc' class | |
267 | * instance(s): ocp_wp_noc | |
268 | */ | |
269 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
270 | .name = "ocp_wp_noc", | |
271 | }; | |
272 | ||
273 | /* ocp_wp_noc */ | |
274 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
275 | .name = "ocp_wp_noc", | |
276 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
277 | .clkdm_name = "l3_instr_clkdm", | |
278 | .prcm = { | |
279 | .omap4 = { | |
280 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
281 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
282 | .modulemode = MODULEMODE_HWCTRL, | |
283 | }, | |
284 | }, | |
285 | }; | |
286 | ||
3b54baad BC |
287 | /* |
288 | * Modules omap_hwmod structures | |
289 | * | |
290 | * The following IPs are excluded for the moment because: | |
291 | * - They do not need an explicit SW control using omap_hwmod API. | |
292 | * - They still need to be validated with the driver | |
293 | * properly adapted to omap_hwmod / omap_device | |
294 | * | |
3b54baad BC |
295 | * cm_core |
296 | * cm_core_aon | |
3b54baad BC |
297 | * ctrl_module_core |
298 | * ctrl_module_pad_core | |
299 | * ctrl_module_pad_wkup | |
300 | * ctrl_module_wkup | |
301 | * debugss | |
3b54baad BC |
302 | * efuse_ctrl_cust |
303 | * efuse_ctrl_std | |
00fe610b BC |
304 | * mpu_c0 |
305 | * mpu_c1 | |
3b54baad BC |
306 | * prcm_mpu |
307 | * prm | |
308 | * scrm | |
3b54baad | 309 | * usb_phy_cm |
3b54baad BC |
310 | * usim |
311 | */ | |
312 | ||
407a6888 BC |
313 | /* |
314 | * 'aess' class | |
315 | * audio engine sub system | |
316 | */ | |
317 | ||
318 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
319 | .rev_offs = 0x0000, | |
320 | .sysc_offs = 0x0010, | |
321 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
322 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
323 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
324 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
325 | .sysc_fields = &omap_hwmod_sysc_type2, |
326 | }; | |
327 | ||
328 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
329 | .name = "aess", | |
330 | .sysc = &omap44xx_aess_sysc, | |
331 | }; | |
332 | ||
333 | /* aess */ | |
334 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
335 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 336 | { .irq = -1 } |
407a6888 BC |
337 | }; |
338 | ||
339 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
340 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
341 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
342 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
343 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
344 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
345 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
346 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
347 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 348 | { .dma_req = -1 } |
407a6888 BC |
349 | }; |
350 | ||
407a6888 BC |
351 | static struct omap_hwmod omap44xx_aess_hwmod = { |
352 | .name = "aess", | |
353 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 354 | .clkdm_name = "abe_clkdm", |
407a6888 | 355 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 356 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 357 | .main_clk = "aess_fck", |
00fe610b | 358 | .prcm = { |
407a6888 | 359 | .omap4 = { |
d0f0631d | 360 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 361 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 362 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
363 | }, |
364 | }, | |
407a6888 BC |
365 | }; |
366 | ||
42b9e387 PW |
367 | /* |
368 | * 'c2c' class | |
369 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
370 | * soc | |
371 | */ | |
372 | ||
373 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
374 | .name = "c2c", | |
375 | }; | |
376 | ||
377 | /* c2c */ | |
378 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | |
379 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | |
380 | { .irq = -1 } | |
381 | }; | |
382 | ||
383 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | |
384 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | |
385 | { .dma_req = -1 } | |
386 | }; | |
387 | ||
388 | static struct omap_hwmod omap44xx_c2c_hwmod = { | |
389 | .name = "c2c", | |
390 | .class = &omap44xx_c2c_hwmod_class, | |
391 | .clkdm_name = "d2d_clkdm", | |
392 | .mpu_irqs = omap44xx_c2c_irqs, | |
393 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | |
394 | .prcm = { | |
395 | .omap4 = { | |
396 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
397 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
398 | }, | |
399 | }, | |
400 | }; | |
401 | ||
407a6888 BC |
402 | /* |
403 | * 'counter' class | |
404 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
405 | */ | |
406 | ||
407 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
408 | .rev_offs = 0x0000, | |
409 | .sysc_offs = 0x0004, | |
410 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
411 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
412 | SIDLE_SMART_WKUP), | |
413 | .sysc_fields = &omap_hwmod_sysc_type1, | |
414 | }; | |
415 | ||
416 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
417 | .name = "counter", | |
418 | .sysc = &omap44xx_counter_sysc, | |
419 | }; | |
420 | ||
421 | /* counter_32k */ | |
407a6888 BC |
422 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
423 | .name = "counter_32k", | |
424 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 425 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
426 | .flags = HWMOD_SWSUP_SIDLE, |
427 | .main_clk = "sys_32k_ck", | |
00fe610b | 428 | .prcm = { |
407a6888 | 429 | .omap4 = { |
d0f0631d | 430 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 431 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
432 | }, |
433 | }, | |
407a6888 BC |
434 | }; |
435 | ||
d7cf5f33 BC |
436 | /* |
437 | * 'dma' class | |
438 | * dma controller for data exchange between memory to memory (i.e. internal or | |
439 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
440 | */ | |
441 | ||
442 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
443 | .rev_offs = 0x0000, | |
444 | .sysc_offs = 0x002c, | |
445 | .syss_offs = 0x0028, | |
446 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
447 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
448 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
449 | SYSS_HAS_RESET_STATUS), | |
450 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
451 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
452 | .sysc_fields = &omap_hwmod_sysc_type1, | |
453 | }; | |
454 | ||
455 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
456 | .name = "dma", | |
457 | .sysc = &omap44xx_dma_sysc, | |
458 | }; | |
459 | ||
460 | /* dma dev_attr */ | |
461 | static struct omap_dma_dev_attr dma_dev_attr = { | |
462 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
463 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
464 | .lch_count = 32, | |
465 | }; | |
466 | ||
467 | /* dma_system */ | |
468 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
469 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
470 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
471 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
472 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 473 | { .irq = -1 } |
d7cf5f33 BC |
474 | }; |
475 | ||
d7cf5f33 BC |
476 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
477 | .name = "dma_system", | |
478 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 479 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 480 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
481 | .main_clk = "l3_div_ck", |
482 | .prcm = { | |
483 | .omap4 = { | |
d0f0631d | 484 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 485 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
486 | }, |
487 | }, | |
488 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
489 | }; |
490 | ||
8ca476da BC |
491 | /* |
492 | * 'dmic' class | |
493 | * digital microphone controller | |
494 | */ | |
495 | ||
496 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
497 | .rev_offs = 0x0000, | |
498 | .sysc_offs = 0x0010, | |
499 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
500 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
501 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
502 | SIDLE_SMART_WKUP), | |
503 | .sysc_fields = &omap_hwmod_sysc_type2, | |
504 | }; | |
505 | ||
506 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
507 | .name = "dmic", | |
508 | .sysc = &omap44xx_dmic_sysc, | |
509 | }; | |
510 | ||
511 | /* dmic */ | |
8ca476da BC |
512 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
513 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 514 | { .irq = -1 } |
8ca476da BC |
515 | }; |
516 | ||
517 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
518 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 519 | { .dma_req = -1 } |
8ca476da BC |
520 | }; |
521 | ||
8ca476da BC |
522 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
523 | .name = "dmic", | |
524 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 525 | .clkdm_name = "abe_clkdm", |
8ca476da | 526 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 527 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 528 | .main_clk = "dmic_fck", |
00fe610b | 529 | .prcm = { |
8ca476da | 530 | .omap4 = { |
d0f0631d | 531 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 532 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 533 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
534 | }, |
535 | }, | |
8ca476da BC |
536 | }; |
537 | ||
8f25bdc5 BC |
538 | /* |
539 | * 'dsp' class | |
540 | * dsp sub-system | |
541 | */ | |
542 | ||
543 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 544 | .name = "dsp", |
8f25bdc5 BC |
545 | }; |
546 | ||
547 | /* dsp */ | |
548 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
549 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 550 | { .irq = -1 } |
8f25bdc5 BC |
551 | }; |
552 | ||
553 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 | 554 | { .name = "dsp", .rst_shift = 0 }, |
f2f5736c | 555 | { .name = "mmu_cache", .rst_shift = 1 }, |
8f25bdc5 BC |
556 | }; |
557 | ||
8f25bdc5 BC |
558 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
559 | .name = "dsp", | |
560 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 561 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 562 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
563 | .rst_lines = omap44xx_dsp_resets, |
564 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
565 | .main_clk = "dsp_fck", | |
566 | .prcm = { | |
567 | .omap4 = { | |
d0f0631d | 568 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 569 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 570 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 571 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
572 | }, |
573 | }, | |
8f25bdc5 BC |
574 | }; |
575 | ||
d63bd74f BC |
576 | /* |
577 | * 'dss' class | |
578 | * display sub-system | |
579 | */ | |
580 | ||
581 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
582 | .rev_offs = 0x0000, | |
583 | .syss_offs = 0x0014, | |
584 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
585 | }; | |
586 | ||
587 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
588 | .name = "dss", | |
589 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 590 | .reset = omap_dss_reset, |
d63bd74f BC |
591 | }; |
592 | ||
593 | /* dss */ | |
d63bd74f BC |
594 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
595 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
596 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 597 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
598 | }; |
599 | ||
600 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
601 | .name = "dss_core", | |
37ad0855 | 602 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 603 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 604 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 605 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
606 | .prcm = { |
607 | .omap4 = { | |
d0f0631d | 608 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 609 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
610 | }, |
611 | }, | |
612 | .opt_clks = dss_opt_clks, | |
613 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
614 | }; |
615 | ||
616 | /* | |
617 | * 'dispc' class | |
618 | * display controller | |
619 | */ | |
620 | ||
621 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
622 | .rev_offs = 0x0000, | |
623 | .sysc_offs = 0x0010, | |
624 | .syss_offs = 0x0014, | |
625 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
626 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
627 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
628 | SYSS_HAS_RESET_STATUS), | |
629 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
630 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
631 | .sysc_fields = &omap_hwmod_sysc_type1, | |
632 | }; | |
633 | ||
634 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
635 | .name = "dispc", | |
636 | .sysc = &omap44xx_dispc_sysc, | |
637 | }; | |
638 | ||
639 | /* dss_dispc */ | |
d63bd74f BC |
640 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
641 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 642 | { .irq = -1 } |
d63bd74f BC |
643 | }; |
644 | ||
645 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
646 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 647 | { .dma_req = -1 } |
d63bd74f BC |
648 | }; |
649 | ||
b923d40d AT |
650 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
651 | .manager_count = 3, | |
652 | .has_framedonetv_irq = 1 | |
653 | }; | |
654 | ||
d63bd74f BC |
655 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
656 | .name = "dss_dispc", | |
657 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 658 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 659 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 660 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 661 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
662 | .prcm = { |
663 | .omap4 = { | |
d0f0631d | 664 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 665 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
666 | }, |
667 | }, | |
b923d40d | 668 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
669 | }; |
670 | ||
671 | /* | |
672 | * 'dsi' class | |
673 | * display serial interface controller | |
674 | */ | |
675 | ||
676 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
677 | .rev_offs = 0x0000, | |
678 | .sysc_offs = 0x0010, | |
679 | .syss_offs = 0x0014, | |
680 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
681 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
682 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
683 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
684 | .sysc_fields = &omap_hwmod_sysc_type1, | |
685 | }; | |
686 | ||
687 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
688 | .name = "dsi", | |
689 | .sysc = &omap44xx_dsi_sysc, | |
690 | }; | |
691 | ||
692 | /* dss_dsi1 */ | |
d63bd74f BC |
693 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
694 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 695 | { .irq = -1 } |
d63bd74f BC |
696 | }; |
697 | ||
698 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
699 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 700 | { .dma_req = -1 } |
d63bd74f BC |
701 | }; |
702 | ||
3a23aafc TV |
703 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
704 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
705 | }; | |
706 | ||
d63bd74f BC |
707 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
708 | .name = "dss_dsi1", | |
709 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 710 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 711 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 712 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 713 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
714 | .prcm = { |
715 | .omap4 = { | |
d0f0631d | 716 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 717 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
718 | }, |
719 | }, | |
3a23aafc TV |
720 | .opt_clks = dss_dsi1_opt_clks, |
721 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
722 | }; |
723 | ||
724 | /* dss_dsi2 */ | |
d63bd74f BC |
725 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
726 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 727 | { .irq = -1 } |
d63bd74f BC |
728 | }; |
729 | ||
730 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
731 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 732 | { .dma_req = -1 } |
d63bd74f BC |
733 | }; |
734 | ||
3a23aafc TV |
735 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
736 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
737 | }; | |
738 | ||
d63bd74f BC |
739 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
740 | .name = "dss_dsi2", | |
741 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 742 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 743 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 744 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 745 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
746 | .prcm = { |
747 | .omap4 = { | |
d0f0631d | 748 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 749 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
750 | }, |
751 | }, | |
3a23aafc TV |
752 | .opt_clks = dss_dsi2_opt_clks, |
753 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
754 | }; |
755 | ||
756 | /* | |
757 | * 'hdmi' class | |
758 | * hdmi controller | |
759 | */ | |
760 | ||
761 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
762 | .rev_offs = 0x0000, | |
763 | .sysc_offs = 0x0010, | |
764 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
765 | SYSC_HAS_SOFTRESET), | |
766 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
767 | SIDLE_SMART_WKUP), | |
768 | .sysc_fields = &omap_hwmod_sysc_type2, | |
769 | }; | |
770 | ||
771 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
772 | .name = "hdmi", | |
773 | .sysc = &omap44xx_hdmi_sysc, | |
774 | }; | |
775 | ||
776 | /* dss_hdmi */ | |
d63bd74f BC |
777 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
778 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 779 | { .irq = -1 } |
d63bd74f BC |
780 | }; |
781 | ||
782 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
783 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 784 | { .dma_req = -1 } |
d63bd74f BC |
785 | }; |
786 | ||
3a23aafc TV |
787 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
788 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
789 | }; | |
790 | ||
d63bd74f BC |
791 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
792 | .name = "dss_hdmi", | |
793 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 794 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 795 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 796 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 797 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
798 | .prcm = { |
799 | .omap4 = { | |
d0f0631d | 800 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 801 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
802 | }, |
803 | }, | |
3a23aafc TV |
804 | .opt_clks = dss_hdmi_opt_clks, |
805 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
806 | }; |
807 | ||
808 | /* | |
809 | * 'rfbi' class | |
810 | * remote frame buffer interface | |
811 | */ | |
812 | ||
813 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
814 | .rev_offs = 0x0000, | |
815 | .sysc_offs = 0x0010, | |
816 | .syss_offs = 0x0014, | |
817 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
818 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
819 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
820 | .sysc_fields = &omap_hwmod_sysc_type1, | |
821 | }; | |
822 | ||
823 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
824 | .name = "rfbi", | |
825 | .sysc = &omap44xx_rfbi_sysc, | |
826 | }; | |
827 | ||
828 | /* dss_rfbi */ | |
d63bd74f BC |
829 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
830 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 831 | { .dma_req = -1 } |
d63bd74f BC |
832 | }; |
833 | ||
3a23aafc TV |
834 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
835 | { .role = "ick", .clk = "dss_fck" }, | |
836 | }; | |
837 | ||
d63bd74f BC |
838 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
839 | .name = "dss_rfbi", | |
840 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 841 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 842 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 843 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
844 | .prcm = { |
845 | .omap4 = { | |
d0f0631d | 846 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 847 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
848 | }, |
849 | }, | |
3a23aafc TV |
850 | .opt_clks = dss_rfbi_opt_clks, |
851 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
852 | }; |
853 | ||
854 | /* | |
855 | * 'venc' class | |
856 | * video encoder | |
857 | */ | |
858 | ||
859 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
860 | .name = "venc", | |
861 | }; | |
862 | ||
863 | /* dss_venc */ | |
d63bd74f BC |
864 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
865 | .name = "dss_venc", | |
866 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 867 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 868 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
869 | .prcm = { |
870 | .omap4 = { | |
d0f0631d | 871 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 872 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
873 | }, |
874 | }, | |
d63bd74f BC |
875 | }; |
876 | ||
42b9e387 PW |
877 | /* |
878 | * 'elm' class | |
879 | * bch error location module | |
880 | */ | |
881 | ||
882 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
883 | .rev_offs = 0x0000, | |
884 | .sysc_offs = 0x0010, | |
885 | .syss_offs = 0x0014, | |
886 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
887 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
888 | SYSS_HAS_RESET_STATUS), | |
889 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
890 | .sysc_fields = &omap_hwmod_sysc_type1, | |
891 | }; | |
892 | ||
893 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
894 | .name = "elm", | |
895 | .sysc = &omap44xx_elm_sysc, | |
896 | }; | |
897 | ||
898 | /* elm */ | |
899 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | |
900 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | |
901 | { .irq = -1 } | |
902 | }; | |
903 | ||
904 | static struct omap_hwmod omap44xx_elm_hwmod = { | |
905 | .name = "elm", | |
906 | .class = &omap44xx_elm_hwmod_class, | |
907 | .clkdm_name = "l4_per_clkdm", | |
908 | .mpu_irqs = omap44xx_elm_irqs, | |
909 | .prcm = { | |
910 | .omap4 = { | |
911 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
912 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
913 | }, | |
914 | }, | |
915 | }; | |
916 | ||
bf30f950 PW |
917 | /* |
918 | * 'emif' class | |
919 | * external memory interface no1 | |
920 | */ | |
921 | ||
922 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
923 | .rev_offs = 0x0000, | |
924 | }; | |
925 | ||
926 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
927 | .name = "emif", | |
928 | .sysc = &omap44xx_emif_sysc, | |
929 | }; | |
930 | ||
931 | /* emif1 */ | |
932 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | |
933 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | |
934 | { .irq = -1 } | |
935 | }; | |
936 | ||
937 | static struct omap_hwmod omap44xx_emif1_hwmod = { | |
938 | .name = "emif1", | |
939 | .class = &omap44xx_emif_hwmod_class, | |
940 | .clkdm_name = "l3_emif_clkdm", | |
941 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
942 | .mpu_irqs = omap44xx_emif1_irqs, | |
943 | .main_clk = "ddrphy_ck", | |
944 | .prcm = { | |
945 | .omap4 = { | |
946 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
947 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
948 | .modulemode = MODULEMODE_HWCTRL, | |
949 | }, | |
950 | }, | |
951 | }; | |
952 | ||
953 | /* emif2 */ | |
954 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | |
955 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | |
956 | { .irq = -1 } | |
957 | }; | |
958 | ||
959 | static struct omap_hwmod omap44xx_emif2_hwmod = { | |
960 | .name = "emif2", | |
961 | .class = &omap44xx_emif_hwmod_class, | |
962 | .clkdm_name = "l3_emif_clkdm", | |
963 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
964 | .mpu_irqs = omap44xx_emif2_irqs, | |
965 | .main_clk = "ddrphy_ck", | |
966 | .prcm = { | |
967 | .omap4 = { | |
968 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
969 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
970 | .modulemode = MODULEMODE_HWCTRL, | |
971 | }, | |
972 | }, | |
973 | }; | |
974 | ||
b050f688 ML |
975 | /* |
976 | * 'fdif' class | |
977 | * face detection hw accelerator module | |
978 | */ | |
979 | ||
980 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
981 | .rev_offs = 0x0000, | |
982 | .sysc_offs = 0x0010, | |
983 | /* | |
984 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
985 | * accessing sysconfig again. | |
986 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
987 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
988 | * | |
989 | * TODO: Indicate errata when available. | |
990 | */ | |
991 | .srst_udelay = 2, | |
992 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
993 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
994 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
995 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
996 | .sysc_fields = &omap_hwmod_sysc_type2, | |
997 | }; | |
998 | ||
999 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1000 | .name = "fdif", | |
1001 | .sysc = &omap44xx_fdif_sysc, | |
1002 | }; | |
1003 | ||
1004 | /* fdif */ | |
1005 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
1006 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
1007 | { .irq = -1 } | |
1008 | }; | |
1009 | ||
1010 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
1011 | .name = "fdif", | |
1012 | .class = &omap44xx_fdif_hwmod_class, | |
1013 | .clkdm_name = "iss_clkdm", | |
1014 | .mpu_irqs = omap44xx_fdif_irqs, | |
1015 | .main_clk = "fdif_fck", | |
1016 | .prcm = { | |
1017 | .omap4 = { | |
1018 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1019 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1020 | .modulemode = MODULEMODE_SWCTRL, | |
1021 | }, | |
1022 | }, | |
1023 | }; | |
1024 | ||
3b54baad BC |
1025 | /* |
1026 | * 'gpio' class | |
1027 | * general purpose io module | |
1028 | */ | |
1029 | ||
1030 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1031 | .rev_offs = 0x0000, | |
f776471f | 1032 | .sysc_offs = 0x0010, |
3b54baad | 1033 | .syss_offs = 0x0114, |
0cfe8751 BC |
1034 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1035 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1036 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1037 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1038 | SIDLE_SMART_WKUP), | |
f776471f BC |
1039 | .sysc_fields = &omap_hwmod_sysc_type1, |
1040 | }; | |
1041 | ||
3b54baad | 1042 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1043 | .name = "gpio", |
1044 | .sysc = &omap44xx_gpio_sysc, | |
1045 | .rev = 2, | |
f776471f BC |
1046 | }; |
1047 | ||
3b54baad BC |
1048 | /* gpio dev_attr */ |
1049 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1050 | .bank_width = 32, |
1051 | .dbck_flag = true, | |
f776471f BC |
1052 | }; |
1053 | ||
3b54baad | 1054 | /* gpio1 */ |
3b54baad BC |
1055 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1056 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1057 | { .irq = -1 } |
f776471f BC |
1058 | }; |
1059 | ||
3b54baad | 1060 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1061 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1062 | }; |
1063 | ||
1064 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1065 | .name = "gpio1", | |
1066 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1067 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1068 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1069 | .main_clk = "gpio1_ick", |
f776471f BC |
1070 | .prcm = { |
1071 | .omap4 = { | |
d0f0631d | 1072 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1073 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1074 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1075 | }, |
1076 | }, | |
3b54baad BC |
1077 | .opt_clks = gpio1_opt_clks, |
1078 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1079 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1080 | }; |
1081 | ||
3b54baad | 1082 | /* gpio2 */ |
3b54baad BC |
1083 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1084 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1085 | { .irq = -1 } |
f776471f BC |
1086 | }; |
1087 | ||
3b54baad | 1088 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1089 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1090 | }; |
1091 | ||
1092 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1093 | .name = "gpio2", | |
1094 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1095 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1096 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1097 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1098 | .main_clk = "gpio2_ick", |
f776471f BC |
1099 | .prcm = { |
1100 | .omap4 = { | |
d0f0631d | 1101 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1102 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1103 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1104 | }, |
1105 | }, | |
3b54baad BC |
1106 | .opt_clks = gpio2_opt_clks, |
1107 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1108 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1109 | }; |
1110 | ||
3b54baad | 1111 | /* gpio3 */ |
3b54baad BC |
1112 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1113 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1114 | { .irq = -1 } |
f776471f BC |
1115 | }; |
1116 | ||
3b54baad | 1117 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1118 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1119 | }; |
1120 | ||
1121 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1122 | .name = "gpio3", | |
1123 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1124 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1125 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1126 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1127 | .main_clk = "gpio3_ick", |
f776471f BC |
1128 | .prcm = { |
1129 | .omap4 = { | |
d0f0631d | 1130 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1131 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1132 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1133 | }, |
1134 | }, | |
3b54baad BC |
1135 | .opt_clks = gpio3_opt_clks, |
1136 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1137 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1138 | }; |
1139 | ||
3b54baad | 1140 | /* gpio4 */ |
3b54baad BC |
1141 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1142 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1143 | { .irq = -1 } |
f776471f BC |
1144 | }; |
1145 | ||
3b54baad | 1146 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1147 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1148 | }; |
1149 | ||
1150 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1151 | .name = "gpio4", | |
1152 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1153 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1154 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1155 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 1156 | .main_clk = "gpio4_ick", |
f776471f BC |
1157 | .prcm = { |
1158 | .omap4 = { | |
d0f0631d | 1159 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1160 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1161 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1162 | }, |
1163 | }, | |
3b54baad BC |
1164 | .opt_clks = gpio4_opt_clks, |
1165 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1166 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1167 | }; |
1168 | ||
3b54baad | 1169 | /* gpio5 */ |
3b54baad BC |
1170 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1171 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1172 | { .irq = -1 } |
55d2cb08 BC |
1173 | }; |
1174 | ||
844a3b63 PW |
1175 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1176 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1177 | }; |
1178 | ||
3b54baad BC |
1179 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1180 | .name = "gpio5", | |
1181 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1182 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1183 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1184 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 1185 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
1186 | .prcm = { |
1187 | .omap4 = { | |
d0f0631d | 1188 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1189 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1190 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1191 | }, |
1192 | }, | |
3b54baad BC |
1193 | .opt_clks = gpio5_opt_clks, |
1194 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1195 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1196 | }; |
1197 | ||
3b54baad | 1198 | /* gpio6 */ |
3b54baad BC |
1199 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1200 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1201 | { .irq = -1 } |
92b18d1c BC |
1202 | }; |
1203 | ||
3b54baad | 1204 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1205 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1206 | }; |
1207 | ||
3b54baad BC |
1208 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1209 | .name = "gpio6", | |
1210 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1211 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1212 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1213 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
1214 | .main_clk = "gpio6_ick", |
1215 | .prcm = { | |
1216 | .omap4 = { | |
d0f0631d | 1217 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1218 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1219 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1220 | }, |
db12ba53 | 1221 | }, |
3b54baad BC |
1222 | .opt_clks = gpio6_opt_clks, |
1223 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1224 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1225 | }; |
1226 | ||
eb42b5d3 BC |
1227 | /* |
1228 | * 'gpmc' class | |
1229 | * general purpose memory controller | |
1230 | */ | |
1231 | ||
1232 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1233 | .rev_offs = 0x0000, | |
1234 | .sysc_offs = 0x0010, | |
1235 | .syss_offs = 0x0014, | |
1236 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1237 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1238 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1239 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1240 | }; | |
1241 | ||
1242 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1243 | .name = "gpmc", | |
1244 | .sysc = &omap44xx_gpmc_sysc, | |
1245 | }; | |
1246 | ||
1247 | /* gpmc */ | |
1248 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1249 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1250 | { .irq = -1 } | |
1251 | }; | |
1252 | ||
1253 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1254 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1255 | { .dma_req = -1 } | |
1256 | }; | |
1257 | ||
1258 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1259 | .name = "gpmc", | |
1260 | .class = &omap44xx_gpmc_hwmod_class, | |
1261 | .clkdm_name = "l3_2_clkdm", | |
1262 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1263 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1264 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1265 | .prcm = { | |
1266 | .omap4 = { | |
1267 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1268 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1269 | .modulemode = MODULEMODE_HWCTRL, | |
1270 | }, | |
1271 | }, | |
1272 | }; | |
1273 | ||
9def390e PW |
1274 | /* |
1275 | * 'gpu' class | |
1276 | * 2d/3d graphics accelerator | |
1277 | */ | |
1278 | ||
1279 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1280 | .rev_offs = 0x1fc00, | |
1281 | .sysc_offs = 0x1fc10, | |
1282 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1283 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1284 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1285 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1286 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1287 | }; | |
1288 | ||
1289 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1290 | .name = "gpu", | |
1291 | .sysc = &omap44xx_gpu_sysc, | |
1292 | }; | |
1293 | ||
1294 | /* gpu */ | |
1295 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | |
1296 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | |
1297 | { .irq = -1 } | |
1298 | }; | |
1299 | ||
1300 | static struct omap_hwmod omap44xx_gpu_hwmod = { | |
1301 | .name = "gpu", | |
1302 | .class = &omap44xx_gpu_hwmod_class, | |
1303 | .clkdm_name = "l3_gfx_clkdm", | |
1304 | .mpu_irqs = omap44xx_gpu_irqs, | |
1305 | .main_clk = "gpu_fck", | |
1306 | .prcm = { | |
1307 | .omap4 = { | |
1308 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1309 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1310 | .modulemode = MODULEMODE_SWCTRL, | |
1311 | }, | |
1312 | }, | |
1313 | }; | |
1314 | ||
a091c08e PW |
1315 | /* |
1316 | * 'hdq1w' class | |
1317 | * hdq / 1-wire serial interface controller | |
1318 | */ | |
1319 | ||
1320 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1321 | .rev_offs = 0x0000, | |
1322 | .sysc_offs = 0x0014, | |
1323 | .syss_offs = 0x0018, | |
1324 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1325 | SYSS_HAS_RESET_STATUS), | |
1326 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1327 | }; | |
1328 | ||
1329 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1330 | .name = "hdq1w", | |
1331 | .sysc = &omap44xx_hdq1w_sysc, | |
1332 | }; | |
1333 | ||
1334 | /* hdq1w */ | |
1335 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1336 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1337 | { .irq = -1 } | |
1338 | }; | |
1339 | ||
1340 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1341 | .name = "hdq1w", | |
1342 | .class = &omap44xx_hdq1w_hwmod_class, | |
1343 | .clkdm_name = "l4_per_clkdm", | |
1344 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1345 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
1346 | .main_clk = "hdq1w_fck", | |
1347 | .prcm = { | |
1348 | .omap4 = { | |
1349 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1350 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1351 | .modulemode = MODULEMODE_SWCTRL, | |
1352 | }, | |
1353 | }, | |
1354 | }; | |
1355 | ||
407a6888 BC |
1356 | /* |
1357 | * 'hsi' class | |
1358 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1359 | * serial if) | |
1360 | */ | |
1361 | ||
1362 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1363 | .rev_offs = 0x0000, | |
1364 | .sysc_offs = 0x0010, | |
1365 | .syss_offs = 0x0014, | |
1366 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1367 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1368 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1369 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1370 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1371 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1372 | .sysc_fields = &omap_hwmod_sysc_type1, |
1373 | }; | |
1374 | ||
1375 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1376 | .name = "hsi", | |
1377 | .sysc = &omap44xx_hsi_sysc, | |
1378 | }; | |
1379 | ||
1380 | /* hsi */ | |
1381 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1382 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1383 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1384 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1385 | { .irq = -1 } |
407a6888 BC |
1386 | }; |
1387 | ||
407a6888 BC |
1388 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1389 | .name = "hsi", | |
1390 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1391 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1392 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1393 | .main_clk = "hsi_fck", |
00fe610b | 1394 | .prcm = { |
407a6888 | 1395 | .omap4 = { |
d0f0631d | 1396 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1397 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1398 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1399 | }, |
1400 | }, | |
407a6888 BC |
1401 | }; |
1402 | ||
3b54baad BC |
1403 | /* |
1404 | * 'i2c' class | |
1405 | * multimaster high-speed i2c controller | |
1406 | */ | |
db12ba53 | 1407 | |
3b54baad BC |
1408 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1409 | .sysc_offs = 0x0010, | |
1410 | .syss_offs = 0x0090, | |
1411 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1412 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1413 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1414 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1415 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1416 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1417 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1418 | }; |
1419 | ||
3b54baad | 1420 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1421 | .name = "i2c", |
1422 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1423 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1424 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1425 | }; |
1426 | ||
4d4441a6 AG |
1427 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
1428 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
1429 | }; | |
1430 | ||
3b54baad | 1431 | /* i2c1 */ |
3b54baad BC |
1432 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1433 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1434 | { .irq = -1 } |
db12ba53 BC |
1435 | }; |
1436 | ||
3b54baad BC |
1437 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1438 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1439 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1440 | { .dma_req = -1 } |
db12ba53 BC |
1441 | }; |
1442 | ||
3b54baad BC |
1443 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1444 | .name = "i2c1", | |
1445 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1446 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1447 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1448 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1449 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 1450 | .main_clk = "i2c1_fck", |
92b18d1c BC |
1451 | .prcm = { |
1452 | .omap4 = { | |
d0f0631d | 1453 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1454 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1455 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1456 | }, |
1457 | }, | |
4d4441a6 | 1458 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1459 | }; |
1460 | ||
3b54baad | 1461 | /* i2c2 */ |
3b54baad BC |
1462 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1463 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1464 | { .irq = -1 } |
92b18d1c BC |
1465 | }; |
1466 | ||
3b54baad BC |
1467 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1468 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1469 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1470 | { .dma_req = -1 } |
3b54baad BC |
1471 | }; |
1472 | ||
3b54baad BC |
1473 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1474 | .name = "i2c2", | |
1475 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1476 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1477 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1478 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1479 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 1480 | .main_clk = "i2c2_fck", |
db12ba53 BC |
1481 | .prcm = { |
1482 | .omap4 = { | |
d0f0631d | 1483 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1484 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1485 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1486 | }, |
1487 | }, | |
4d4441a6 | 1488 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1489 | }; |
1490 | ||
3b54baad | 1491 | /* i2c3 */ |
3b54baad BC |
1492 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1493 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1494 | { .irq = -1 } |
db12ba53 BC |
1495 | }; |
1496 | ||
3b54baad BC |
1497 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1498 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1499 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1500 | { .dma_req = -1 } |
92b18d1c BC |
1501 | }; |
1502 | ||
3b54baad BC |
1503 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1504 | .name = "i2c3", | |
1505 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1506 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1507 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1508 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1509 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 1510 | .main_clk = "i2c3_fck", |
db12ba53 BC |
1511 | .prcm = { |
1512 | .omap4 = { | |
d0f0631d | 1513 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1514 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1515 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1516 | }, |
1517 | }, | |
4d4441a6 | 1518 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1519 | }; |
1520 | ||
3b54baad | 1521 | /* i2c4 */ |
3b54baad BC |
1522 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1523 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1524 | { .irq = -1 } |
db12ba53 BC |
1525 | }; |
1526 | ||
3b54baad BC |
1527 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1528 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1529 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1530 | { .dma_req = -1 } |
db12ba53 BC |
1531 | }; |
1532 | ||
3b54baad BC |
1533 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1534 | .name = "i2c4", | |
1535 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1536 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1537 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1538 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1539 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 1540 | .main_clk = "i2c4_fck", |
92b18d1c BC |
1541 | .prcm = { |
1542 | .omap4 = { | |
d0f0631d | 1543 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1544 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1545 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1546 | }, |
1547 | }, | |
4d4441a6 | 1548 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1549 | }; |
1550 | ||
407a6888 BC |
1551 | /* |
1552 | * 'ipu' class | |
1553 | * imaging processor unit | |
1554 | */ | |
1555 | ||
1556 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1557 | .name = "ipu", | |
1558 | }; | |
1559 | ||
1560 | /* ipu */ | |
1561 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1562 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1563 | { .irq = -1 } |
407a6888 BC |
1564 | }; |
1565 | ||
f2f5736c | 1566 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1567 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1568 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1569 | { .name = "mmu_cache", .rst_shift = 2 }, |
1570 | }; | |
1571 | ||
407a6888 BC |
1572 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1573 | .name = "ipu", | |
1574 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1575 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1576 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1577 | .rst_lines = omap44xx_ipu_resets, |
1578 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
1579 | .main_clk = "ipu_fck", | |
00fe610b | 1580 | .prcm = { |
407a6888 | 1581 | .omap4 = { |
d0f0631d | 1582 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1583 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1584 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1585 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1586 | }, |
1587 | }, | |
407a6888 BC |
1588 | }; |
1589 | ||
1590 | /* | |
1591 | * 'iss' class | |
1592 | * external images sensor pixel data processor | |
1593 | */ | |
1594 | ||
1595 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1596 | .rev_offs = 0x0000, | |
1597 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1598 | /* |
1599 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1600 | * accessing sysconfig again. | |
1601 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1602 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1603 | * | |
1604 | * TODO: Indicate errata when available. | |
1605 | */ | |
1606 | .srst_udelay = 2, | |
407a6888 BC |
1607 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1608 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1609 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1610 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1611 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1612 | .sysc_fields = &omap_hwmod_sysc_type2, |
1613 | }; | |
1614 | ||
1615 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1616 | .name = "iss", | |
1617 | .sysc = &omap44xx_iss_sysc, | |
1618 | }; | |
1619 | ||
1620 | /* iss */ | |
1621 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1622 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1623 | { .irq = -1 } |
407a6888 BC |
1624 | }; |
1625 | ||
1626 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1627 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1628 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1629 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1630 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1631 | { .dma_req = -1 } |
407a6888 BC |
1632 | }; |
1633 | ||
407a6888 BC |
1634 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1635 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1636 | }; | |
1637 | ||
1638 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1639 | .name = "iss", | |
1640 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1641 | .clkdm_name = "iss_clkdm", |
407a6888 | 1642 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1643 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 1644 | .main_clk = "iss_fck", |
00fe610b | 1645 | .prcm = { |
407a6888 | 1646 | .omap4 = { |
d0f0631d | 1647 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1648 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1649 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1650 | }, |
1651 | }, | |
1652 | .opt_clks = iss_opt_clks, | |
1653 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1654 | }; |
1655 | ||
8f25bdc5 BC |
1656 | /* |
1657 | * 'iva' class | |
1658 | * multi-standard video encoder/decoder hardware accelerator | |
1659 | */ | |
1660 | ||
1661 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1662 | .name = "iva", |
8f25bdc5 BC |
1663 | }; |
1664 | ||
1665 | /* iva */ | |
1666 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1667 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1668 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1669 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1670 | { .irq = -1 } |
8f25bdc5 BC |
1671 | }; |
1672 | ||
1673 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1674 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1675 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1676 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1677 | }; |
1678 | ||
8f25bdc5 BC |
1679 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1680 | .name = "iva", | |
1681 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1682 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1683 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1684 | .rst_lines = omap44xx_iva_resets, |
1685 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1686 | .main_clk = "iva_fck", | |
1687 | .prcm = { | |
1688 | .omap4 = { | |
d0f0631d | 1689 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1690 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1691 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1692 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1693 | }, |
1694 | }, | |
8f25bdc5 BC |
1695 | }; |
1696 | ||
407a6888 BC |
1697 | /* |
1698 | * 'kbd' class | |
1699 | * keyboard controller | |
1700 | */ | |
1701 | ||
1702 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1703 | .rev_offs = 0x0000, | |
1704 | .sysc_offs = 0x0010, | |
1705 | .syss_offs = 0x0014, | |
1706 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1707 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1708 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1709 | SYSS_HAS_RESET_STATUS), | |
1710 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1711 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1712 | }; | |
1713 | ||
1714 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1715 | .name = "kbd", | |
1716 | .sysc = &omap44xx_kbd_sysc, | |
1717 | }; | |
1718 | ||
1719 | /* kbd */ | |
407a6888 BC |
1720 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1721 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1722 | { .irq = -1 } |
407a6888 BC |
1723 | }; |
1724 | ||
407a6888 BC |
1725 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1726 | .name = "kbd", | |
1727 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1728 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1729 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 1730 | .main_clk = "kbd_fck", |
00fe610b | 1731 | .prcm = { |
407a6888 | 1732 | .omap4 = { |
d0f0631d | 1733 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1734 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1735 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1736 | }, |
1737 | }, | |
407a6888 BC |
1738 | }; |
1739 | ||
ec5df927 BC |
1740 | /* |
1741 | * 'mailbox' class | |
1742 | * mailbox module allowing communication between the on-chip processors using a | |
1743 | * queued mailbox-interrupt mechanism. | |
1744 | */ | |
1745 | ||
1746 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1747 | .rev_offs = 0x0000, | |
1748 | .sysc_offs = 0x0010, | |
1749 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1750 | SYSC_HAS_SOFTRESET), | |
1751 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1752 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1753 | }; | |
1754 | ||
1755 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1756 | .name = "mailbox", | |
1757 | .sysc = &omap44xx_mailbox_sysc, | |
1758 | }; | |
1759 | ||
1760 | /* mailbox */ | |
ec5df927 BC |
1761 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1762 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1763 | { .irq = -1 } |
ec5df927 BC |
1764 | }; |
1765 | ||
ec5df927 BC |
1766 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1767 | .name = "mailbox", | |
1768 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1769 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1770 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1771 | .prcm = { |
ec5df927 | 1772 | .omap4 = { |
d0f0631d | 1773 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1774 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1775 | }, |
1776 | }, | |
ec5df927 BC |
1777 | }; |
1778 | ||
896d4e98 BC |
1779 | /* |
1780 | * 'mcasp' class | |
1781 | * multi-channel audio serial port controller | |
1782 | */ | |
1783 | ||
1784 | /* The IP is not compliant to type1 / type2 scheme */ | |
1785 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1786 | .sidle_shift = 0, | |
1787 | }; | |
1788 | ||
1789 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1790 | .sysc_offs = 0x0004, | |
1791 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1792 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1793 | SIDLE_SMART_WKUP), | |
1794 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1795 | }; | |
1796 | ||
1797 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1798 | .name = "mcasp", | |
1799 | .sysc = &omap44xx_mcasp_sysc, | |
1800 | }; | |
1801 | ||
1802 | /* mcasp */ | |
1803 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | |
1804 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | |
1805 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | |
1806 | { .irq = -1 } | |
1807 | }; | |
1808 | ||
1809 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | |
1810 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | |
1811 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | |
1812 | { .dma_req = -1 } | |
1813 | }; | |
1814 | ||
1815 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | |
1816 | .name = "mcasp", | |
1817 | .class = &omap44xx_mcasp_hwmod_class, | |
1818 | .clkdm_name = "abe_clkdm", | |
1819 | .mpu_irqs = omap44xx_mcasp_irqs, | |
1820 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | |
1821 | .main_clk = "mcasp_fck", | |
1822 | .prcm = { | |
1823 | .omap4 = { | |
1824 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1825 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1826 | .modulemode = MODULEMODE_SWCTRL, | |
1827 | }, | |
1828 | }, | |
1829 | }; | |
1830 | ||
4ddff493 BC |
1831 | /* |
1832 | * 'mcbsp' class | |
1833 | * multi channel buffered serial port controller | |
1834 | */ | |
1835 | ||
1836 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1837 | .sysc_offs = 0x008c, | |
1838 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1839 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1840 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1841 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1842 | }; | |
1843 | ||
1844 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1845 | .name = "mcbsp", | |
1846 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1847 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1848 | }; |
1849 | ||
1850 | /* mcbsp1 */ | |
4ddff493 BC |
1851 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
1852 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1853 | { .irq = -1 } |
4ddff493 BC |
1854 | }; |
1855 | ||
1856 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1857 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1858 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1859 | { .dma_req = -1 } |
4ddff493 BC |
1860 | }; |
1861 | ||
503d0ea2 PW |
1862 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1863 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1864 | { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, | |
1865 | }; | |
1866 | ||
4ddff493 BC |
1867 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1868 | .name = "mcbsp1", | |
1869 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1870 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1871 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1872 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
1873 | .main_clk = "mcbsp1_fck", |
1874 | .prcm = { | |
1875 | .omap4 = { | |
d0f0631d | 1876 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1877 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1878 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1879 | }, |
1880 | }, | |
503d0ea2 PW |
1881 | .opt_clks = mcbsp1_opt_clks, |
1882 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1883 | }; |
1884 | ||
1885 | /* mcbsp2 */ | |
4ddff493 BC |
1886 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
1887 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1888 | { .irq = -1 } |
4ddff493 BC |
1889 | }; |
1890 | ||
1891 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1892 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1893 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1894 | { .dma_req = -1 } |
4ddff493 BC |
1895 | }; |
1896 | ||
844a3b63 PW |
1897 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1898 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1899 | { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, | |
503d0ea2 PW |
1900 | }; |
1901 | ||
4ddff493 BC |
1902 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1903 | .name = "mcbsp2", | |
1904 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1905 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1906 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 1907 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
1908 | .main_clk = "mcbsp2_fck", |
1909 | .prcm = { | |
1910 | .omap4 = { | |
d0f0631d | 1911 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1912 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1913 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1914 | }, |
1915 | }, | |
503d0ea2 PW |
1916 | .opt_clks = mcbsp2_opt_clks, |
1917 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1918 | }; |
1919 | ||
1920 | /* mcbsp3 */ | |
4ddff493 BC |
1921 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
1922 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1923 | { .irq = -1 } |
4ddff493 BC |
1924 | }; |
1925 | ||
1926 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
1927 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
1928 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1929 | { .dma_req = -1 } |
4ddff493 BC |
1930 | }; |
1931 | ||
503d0ea2 PW |
1932 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1933 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1934 | { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, | |
1935 | }; | |
1936 | ||
4ddff493 BC |
1937 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1938 | .name = "mcbsp3", | |
1939 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1940 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1941 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 1942 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
1943 | .main_clk = "mcbsp3_fck", |
1944 | .prcm = { | |
1945 | .omap4 = { | |
d0f0631d | 1946 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1947 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1948 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1949 | }, |
1950 | }, | |
503d0ea2 PW |
1951 | .opt_clks = mcbsp3_opt_clks, |
1952 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1953 | }; |
1954 | ||
1955 | /* mcbsp4 */ | |
4ddff493 BC |
1956 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
1957 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1958 | { .irq = -1 } |
4ddff493 BC |
1959 | }; |
1960 | ||
1961 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
1962 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
1963 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1964 | { .dma_req = -1 } |
4ddff493 BC |
1965 | }; |
1966 | ||
503d0ea2 PW |
1967 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
1968 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1969 | { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, | |
1970 | }; | |
1971 | ||
4ddff493 BC |
1972 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
1973 | .name = "mcbsp4", | |
1974 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1975 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 1976 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 1977 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
1978 | .main_clk = "mcbsp4_fck", |
1979 | .prcm = { | |
1980 | .omap4 = { | |
d0f0631d | 1981 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 1982 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 1983 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1984 | }, |
1985 | }, | |
503d0ea2 PW |
1986 | .opt_clks = mcbsp4_opt_clks, |
1987 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
1988 | }; |
1989 | ||
407a6888 BC |
1990 | /* |
1991 | * 'mcpdm' class | |
1992 | * multi channel pdm controller (proprietary interface with phoenix power | |
1993 | * ic) | |
1994 | */ | |
1995 | ||
1996 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
1997 | .rev_offs = 0x0000, | |
1998 | .sysc_offs = 0x0010, | |
1999 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2000 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2001 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2002 | SIDLE_SMART_WKUP), | |
2003 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2004 | }; | |
2005 | ||
2006 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
2007 | .name = "mcpdm", | |
2008 | .sysc = &omap44xx_mcpdm_sysc, | |
2009 | }; | |
2010 | ||
2011 | /* mcpdm */ | |
407a6888 BC |
2012 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
2013 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2014 | { .irq = -1 } |
407a6888 BC |
2015 | }; |
2016 | ||
2017 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
2018 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
2019 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2020 | { .dma_req = -1 } |
407a6888 BC |
2021 | }; |
2022 | ||
407a6888 BC |
2023 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
2024 | .name = "mcpdm", | |
2025 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 2026 | .clkdm_name = "abe_clkdm", |
407a6888 | 2027 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 2028 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 2029 | .main_clk = "mcpdm_fck", |
00fe610b | 2030 | .prcm = { |
407a6888 | 2031 | .omap4 = { |
d0f0631d | 2032 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 2033 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 2034 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2035 | }, |
2036 | }, | |
407a6888 BC |
2037 | }; |
2038 | ||
9bcbd7f0 BC |
2039 | /* |
2040 | * 'mcspi' class | |
2041 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2042 | * bus | |
2043 | */ | |
2044 | ||
2045 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
2046 | .rev_offs = 0x0000, | |
2047 | .sysc_offs = 0x0010, | |
2048 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2049 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2050 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2051 | SIDLE_SMART_WKUP), | |
2052 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2053 | }; | |
2054 | ||
2055 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
2056 | .name = "mcspi", | |
2057 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 2058 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
2059 | }; |
2060 | ||
2061 | /* mcspi1 */ | |
9bcbd7f0 BC |
2062 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
2063 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2064 | { .irq = -1 } |
9bcbd7f0 BC |
2065 | }; |
2066 | ||
2067 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
2068 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
2069 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
2070 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
2071 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
2072 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
2073 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
2074 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
2075 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2076 | { .dma_req = -1 } |
9bcbd7f0 BC |
2077 | }; |
2078 | ||
905a74d9 BC |
2079 | /* mcspi1 dev_attr */ |
2080 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
2081 | .num_chipselect = 4, | |
2082 | }; | |
2083 | ||
9bcbd7f0 BC |
2084 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
2085 | .name = "mcspi1", | |
2086 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2087 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2088 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 2089 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
2090 | .main_clk = "mcspi1_fck", |
2091 | .prcm = { | |
2092 | .omap4 = { | |
d0f0631d | 2093 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 2094 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 2095 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2096 | }, |
2097 | }, | |
905a74d9 | 2098 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
2099 | }; |
2100 | ||
2101 | /* mcspi2 */ | |
9bcbd7f0 BC |
2102 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
2103 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2104 | { .irq = -1 } |
9bcbd7f0 BC |
2105 | }; |
2106 | ||
2107 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
2108 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
2109 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
2110 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
2111 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2112 | { .dma_req = -1 } |
9bcbd7f0 BC |
2113 | }; |
2114 | ||
905a74d9 BC |
2115 | /* mcspi2 dev_attr */ |
2116 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
2117 | .num_chipselect = 2, | |
2118 | }; | |
2119 | ||
9bcbd7f0 BC |
2120 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
2121 | .name = "mcspi2", | |
2122 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2123 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2124 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 2125 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
2126 | .main_clk = "mcspi2_fck", |
2127 | .prcm = { | |
2128 | .omap4 = { | |
d0f0631d | 2129 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 2130 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 2131 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2132 | }, |
2133 | }, | |
905a74d9 | 2134 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
2135 | }; |
2136 | ||
2137 | /* mcspi3 */ | |
9bcbd7f0 BC |
2138 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
2139 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2140 | { .irq = -1 } |
9bcbd7f0 BC |
2141 | }; |
2142 | ||
2143 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
2144 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
2145 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
2146 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
2147 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2148 | { .dma_req = -1 } |
9bcbd7f0 BC |
2149 | }; |
2150 | ||
905a74d9 BC |
2151 | /* mcspi3 dev_attr */ |
2152 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
2153 | .num_chipselect = 2, | |
2154 | }; | |
2155 | ||
9bcbd7f0 BC |
2156 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
2157 | .name = "mcspi3", | |
2158 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2159 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2160 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 2161 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
2162 | .main_clk = "mcspi3_fck", |
2163 | .prcm = { | |
2164 | .omap4 = { | |
d0f0631d | 2165 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 2166 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 2167 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2168 | }, |
2169 | }, | |
905a74d9 | 2170 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2171 | }; |
2172 | ||
2173 | /* mcspi4 */ | |
9bcbd7f0 BC |
2174 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
2175 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2176 | { .irq = -1 } |
9bcbd7f0 BC |
2177 | }; |
2178 | ||
2179 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
2180 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2181 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2182 | { .dma_req = -1 } |
9bcbd7f0 BC |
2183 | }; |
2184 | ||
905a74d9 BC |
2185 | /* mcspi4 dev_attr */ |
2186 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2187 | .num_chipselect = 1, | |
2188 | }; | |
2189 | ||
9bcbd7f0 BC |
2190 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2191 | .name = "mcspi4", | |
2192 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2193 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2194 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 2195 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
2196 | .main_clk = "mcspi4_fck", |
2197 | .prcm = { | |
2198 | .omap4 = { | |
d0f0631d | 2199 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2200 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2201 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2202 | }, |
2203 | }, | |
905a74d9 | 2204 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2205 | }; |
2206 | ||
407a6888 BC |
2207 | /* |
2208 | * 'mmc' class | |
2209 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2210 | */ | |
2211 | ||
2212 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2213 | .rev_offs = 0x0000, | |
2214 | .sysc_offs = 0x0010, | |
2215 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2216 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2217 | SYSC_HAS_SOFTRESET), | |
2218 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2219 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2220 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2221 | .sysc_fields = &omap_hwmod_sysc_type2, |
2222 | }; | |
2223 | ||
2224 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2225 | .name = "mmc", | |
2226 | .sysc = &omap44xx_mmc_sysc, | |
2227 | }; | |
2228 | ||
2229 | /* mmc1 */ | |
2230 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
2231 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2232 | { .irq = -1 } |
407a6888 BC |
2233 | }; |
2234 | ||
2235 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
2236 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2237 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2238 | { .dma_req = -1 } |
407a6888 BC |
2239 | }; |
2240 | ||
6ab8946f KK |
2241 | /* mmc1 dev_attr */ |
2242 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
2243 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2244 | }; | |
2245 | ||
407a6888 BC |
2246 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2247 | .name = "mmc1", | |
2248 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2249 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2250 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 2251 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 2252 | .main_clk = "mmc1_fck", |
00fe610b | 2253 | .prcm = { |
407a6888 | 2254 | .omap4 = { |
d0f0631d | 2255 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2256 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2257 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2258 | }, |
2259 | }, | |
6ab8946f | 2260 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2261 | }; |
2262 | ||
2263 | /* mmc2 */ | |
2264 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2265 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2266 | { .irq = -1 } |
407a6888 BC |
2267 | }; |
2268 | ||
2269 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2270 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2271 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2272 | { .dma_req = -1 } |
407a6888 BC |
2273 | }; |
2274 | ||
407a6888 BC |
2275 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2276 | .name = "mmc2", | |
2277 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2278 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2279 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2280 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 2281 | .main_clk = "mmc2_fck", |
00fe610b | 2282 | .prcm = { |
407a6888 | 2283 | .omap4 = { |
d0f0631d | 2284 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2285 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2286 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2287 | }, |
2288 | }, | |
407a6888 BC |
2289 | }; |
2290 | ||
2291 | /* mmc3 */ | |
407a6888 BC |
2292 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2293 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2294 | { .irq = -1 } |
407a6888 BC |
2295 | }; |
2296 | ||
2297 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2298 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2299 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2300 | { .dma_req = -1 } |
407a6888 BC |
2301 | }; |
2302 | ||
407a6888 BC |
2303 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2304 | .name = "mmc3", | |
2305 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2306 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2307 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2308 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 2309 | .main_clk = "mmc3_fck", |
00fe610b | 2310 | .prcm = { |
407a6888 | 2311 | .omap4 = { |
d0f0631d | 2312 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2313 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2314 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2315 | }, |
2316 | }, | |
407a6888 BC |
2317 | }; |
2318 | ||
2319 | /* mmc4 */ | |
407a6888 BC |
2320 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2321 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2322 | { .irq = -1 } |
407a6888 BC |
2323 | }; |
2324 | ||
2325 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2326 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2327 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2328 | { .dma_req = -1 } |
407a6888 BC |
2329 | }; |
2330 | ||
407a6888 BC |
2331 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2332 | .name = "mmc4", | |
2333 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2334 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2335 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2336 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 2337 | .main_clk = "mmc4_fck", |
00fe610b | 2338 | .prcm = { |
407a6888 | 2339 | .omap4 = { |
d0f0631d | 2340 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2341 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2342 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2343 | }, |
2344 | }, | |
407a6888 BC |
2345 | }; |
2346 | ||
2347 | /* mmc5 */ | |
407a6888 BC |
2348 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2349 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2350 | { .irq = -1 } |
407a6888 BC |
2351 | }; |
2352 | ||
2353 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2354 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2355 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2356 | { .dma_req = -1 } |
407a6888 BC |
2357 | }; |
2358 | ||
407a6888 BC |
2359 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2360 | .name = "mmc5", | |
2361 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2362 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2363 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2364 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 2365 | .main_clk = "mmc5_fck", |
00fe610b | 2366 | .prcm = { |
407a6888 | 2367 | .omap4 = { |
d0f0631d | 2368 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2369 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2370 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2371 | }, |
2372 | }, | |
407a6888 BC |
2373 | }; |
2374 | ||
3b54baad BC |
2375 | /* |
2376 | * 'mpu' class | |
2377 | * mpu sub-system | |
2378 | */ | |
2379 | ||
2380 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2381 | .name = "mpu", |
db12ba53 BC |
2382 | }; |
2383 | ||
3b54baad BC |
2384 | /* mpu */ |
2385 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
2386 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
2387 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2388 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2389 | { .irq = -1 } |
db12ba53 BC |
2390 | }; |
2391 | ||
3b54baad BC |
2392 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2393 | .name = "mpu", | |
2394 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2395 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2396 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2397 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2398 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2399 | .prcm = { |
2400 | .omap4 = { | |
d0f0631d | 2401 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2402 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2403 | }, |
2404 | }, | |
db12ba53 BC |
2405 | }; |
2406 | ||
e17f18c0 PW |
2407 | /* |
2408 | * 'ocmc_ram' class | |
2409 | * top-level core on-chip ram | |
2410 | */ | |
2411 | ||
2412 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2413 | .name = "ocmc_ram", | |
2414 | }; | |
2415 | ||
2416 | /* ocmc_ram */ | |
2417 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2418 | .name = "ocmc_ram", | |
2419 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2420 | .clkdm_name = "l3_2_clkdm", | |
2421 | .prcm = { | |
2422 | .omap4 = { | |
2423 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2424 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2425 | }, | |
2426 | }, | |
2427 | }; | |
2428 | ||
0c668875 BC |
2429 | /* |
2430 | * 'ocp2scp' class | |
2431 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2432 | * protocol | |
2433 | */ | |
2434 | ||
2435 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { | |
2436 | .name = "ocp2scp", | |
2437 | }; | |
2438 | ||
2439 | /* ocp2scp_usb_phy */ | |
2440 | static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { | |
2441 | { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, | |
2442 | }; | |
2443 | ||
2444 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | |
2445 | .name = "ocp2scp_usb_phy", | |
2446 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2447 | .clkdm_name = "l3_init_clkdm", | |
2448 | .prcm = { | |
2449 | .omap4 = { | |
2450 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2451 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2452 | .modulemode = MODULEMODE_HWCTRL, | |
2453 | }, | |
2454 | }, | |
2455 | .opt_clks = ocp2scp_usb_phy_opt_clks, | |
2456 | .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), | |
2457 | }; | |
2458 | ||
42b9e387 PW |
2459 | /* |
2460 | * 'sl2if' class | |
2461 | * shared level 2 memory interface | |
2462 | */ | |
2463 | ||
2464 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2465 | .name = "sl2if", | |
2466 | }; | |
2467 | ||
2468 | /* sl2if */ | |
2469 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2470 | .name = "sl2if", | |
2471 | .class = &omap44xx_sl2if_hwmod_class, | |
2472 | .clkdm_name = "ivahd_clkdm", | |
2473 | .prcm = { | |
2474 | .omap4 = { | |
2475 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2476 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2477 | .modulemode = MODULEMODE_HWCTRL, | |
2478 | }, | |
2479 | }, | |
2480 | }; | |
2481 | ||
1e3b5e59 BC |
2482 | /* |
2483 | * 'slimbus' class | |
2484 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2485 | * the device and external components | |
2486 | */ | |
2487 | ||
2488 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2489 | .rev_offs = 0x0000, | |
2490 | .sysc_offs = 0x0010, | |
2491 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2492 | SYSC_HAS_SOFTRESET), | |
2493 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2494 | SIDLE_SMART_WKUP), | |
2495 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2496 | }; | |
2497 | ||
2498 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2499 | .name = "slimbus", | |
2500 | .sysc = &omap44xx_slimbus_sysc, | |
2501 | }; | |
2502 | ||
2503 | /* slimbus1 */ | |
2504 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | |
2505 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | |
2506 | { .irq = -1 } | |
2507 | }; | |
2508 | ||
2509 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | |
2510 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | |
2511 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | |
2512 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | |
2513 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | |
2514 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | |
2515 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | |
2516 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | |
2517 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | |
2518 | { .dma_req = -1 } | |
2519 | }; | |
2520 | ||
2521 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | |
2522 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2523 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2524 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2525 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2526 | }; | |
2527 | ||
2528 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2529 | .name = "slimbus1", | |
2530 | .class = &omap44xx_slimbus_hwmod_class, | |
2531 | .clkdm_name = "abe_clkdm", | |
2532 | .mpu_irqs = omap44xx_slimbus1_irqs, | |
2533 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | |
2534 | .prcm = { | |
2535 | .omap4 = { | |
2536 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2537 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2538 | .modulemode = MODULEMODE_SWCTRL, | |
2539 | }, | |
2540 | }, | |
2541 | .opt_clks = slimbus1_opt_clks, | |
2542 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2543 | }; | |
2544 | ||
2545 | /* slimbus2 */ | |
2546 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | |
2547 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | |
2548 | { .irq = -1 } | |
2549 | }; | |
2550 | ||
2551 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | |
2552 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | |
2553 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | |
2554 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | |
2555 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | |
2556 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | |
2557 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | |
2558 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | |
2559 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | |
2560 | { .dma_req = -1 } | |
2561 | }; | |
2562 | ||
2563 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | |
2564 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2565 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2566 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2567 | }; | |
2568 | ||
2569 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2570 | .name = "slimbus2", | |
2571 | .class = &omap44xx_slimbus_hwmod_class, | |
2572 | .clkdm_name = "l4_per_clkdm", | |
2573 | .mpu_irqs = omap44xx_slimbus2_irqs, | |
2574 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | |
2575 | .prcm = { | |
2576 | .omap4 = { | |
2577 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2578 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2579 | .modulemode = MODULEMODE_SWCTRL, | |
2580 | }, | |
2581 | }, | |
2582 | .opt_clks = slimbus2_opt_clks, | |
2583 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2584 | }; | |
2585 | ||
1f6a717f BC |
2586 | /* |
2587 | * 'smartreflex' class | |
2588 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2589 | * performance error) | |
2590 | */ | |
2591 | ||
2592 | /* The IP is not compliant to type1 / type2 scheme */ | |
2593 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2594 | .sidle_shift = 24, | |
2595 | .enwkup_shift = 26, | |
2596 | }; | |
2597 | ||
2598 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2599 | .sysc_offs = 0x0038, | |
2600 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2601 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2602 | SIDLE_SMART_WKUP), | |
2603 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2604 | }; | |
2605 | ||
2606 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2607 | .name = "smartreflex", |
2608 | .sysc = &omap44xx_smartreflex_sysc, | |
2609 | .rev = 2, | |
1f6a717f BC |
2610 | }; |
2611 | ||
2612 | /* smartreflex_core */ | |
cea6b942 SG |
2613 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2614 | .sensor_voltdm_name = "core", | |
2615 | }; | |
2616 | ||
1f6a717f BC |
2617 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2618 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2619 | { .irq = -1 } |
1f6a717f BC |
2620 | }; |
2621 | ||
1f6a717f BC |
2622 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2623 | .name = "smartreflex_core", | |
2624 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2625 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2626 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2627 | |
1f6a717f | 2628 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2629 | .prcm = { |
2630 | .omap4 = { | |
d0f0631d | 2631 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2632 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2633 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2634 | }, |
2635 | }, | |
cea6b942 | 2636 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2637 | }; |
2638 | ||
2639 | /* smartreflex_iva */ | |
cea6b942 SG |
2640 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2641 | .sensor_voltdm_name = "iva", | |
2642 | }; | |
2643 | ||
1f6a717f BC |
2644 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
2645 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2646 | { .irq = -1 } |
1f6a717f BC |
2647 | }; |
2648 | ||
1f6a717f BC |
2649 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2650 | .name = "smartreflex_iva", | |
2651 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2652 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2653 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 2654 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2655 | .prcm = { |
2656 | .omap4 = { | |
d0f0631d | 2657 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2658 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2659 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2660 | }, |
2661 | }, | |
cea6b942 | 2662 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2663 | }; |
2664 | ||
2665 | /* smartreflex_mpu */ | |
cea6b942 SG |
2666 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2667 | .sensor_voltdm_name = "mpu", | |
2668 | }; | |
2669 | ||
1f6a717f BC |
2670 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
2671 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2672 | { .irq = -1 } |
1f6a717f BC |
2673 | }; |
2674 | ||
1f6a717f BC |
2675 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2676 | .name = "smartreflex_mpu", | |
2677 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2678 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2679 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 2680 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2681 | .prcm = { |
2682 | .omap4 = { | |
d0f0631d | 2683 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2684 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2685 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2686 | }, |
2687 | }, | |
cea6b942 | 2688 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2689 | }; |
2690 | ||
d11c217f BC |
2691 | /* |
2692 | * 'spinlock' class | |
2693 | * spinlock provides hardware assistance for synchronizing the processes | |
2694 | * running on multiple processors | |
2695 | */ | |
2696 | ||
2697 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2698 | .rev_offs = 0x0000, | |
2699 | .sysc_offs = 0x0010, | |
2700 | .syss_offs = 0x0014, | |
2701 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2702 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2703 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2704 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2705 | SIDLE_SMART_WKUP), | |
2706 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2707 | }; | |
2708 | ||
2709 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2710 | .name = "spinlock", | |
2711 | .sysc = &omap44xx_spinlock_sysc, | |
2712 | }; | |
2713 | ||
2714 | /* spinlock */ | |
d11c217f BC |
2715 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2716 | .name = "spinlock", | |
2717 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2718 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2719 | .prcm = { |
2720 | .omap4 = { | |
d0f0631d | 2721 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2722 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2723 | }, |
2724 | }, | |
d11c217f BC |
2725 | }; |
2726 | ||
35d1a66a BC |
2727 | /* |
2728 | * 'timer' class | |
2729 | * general purpose timer module with accurate 1ms tick | |
2730 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2731 | */ | |
2732 | ||
2733 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2734 | .rev_offs = 0x0000, | |
2735 | .sysc_offs = 0x0010, | |
2736 | .syss_offs = 0x0014, | |
2737 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2738 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2739 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2740 | SYSS_HAS_RESET_STATUS), | |
2741 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2742 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2743 | }; | |
2744 | ||
2745 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2746 | .name = "timer", | |
2747 | .sysc = &omap44xx_timer_1ms_sysc, | |
2748 | }; | |
2749 | ||
2750 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2751 | .rev_offs = 0x0000, | |
2752 | .sysc_offs = 0x0010, | |
2753 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2754 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2755 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2756 | SIDLE_SMART_WKUP), | |
2757 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2758 | }; | |
2759 | ||
2760 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2761 | .name = "timer", | |
2762 | .sysc = &omap44xx_timer_sysc, | |
2763 | }; | |
2764 | ||
c345c8b0 TKD |
2765 | /* always-on timers dev attribute */ |
2766 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2767 | .timer_capability = OMAP_TIMER_ALWON, | |
2768 | }; | |
2769 | ||
2770 | /* pwm timers dev attribute */ | |
2771 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2772 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2773 | }; | |
2774 | ||
35d1a66a | 2775 | /* timer1 */ |
35d1a66a BC |
2776 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
2777 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2778 | { .irq = -1 } |
35d1a66a BC |
2779 | }; |
2780 | ||
35d1a66a BC |
2781 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2782 | .name = "timer1", | |
2783 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2784 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 2785 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
2786 | .main_clk = "timer1_fck", |
2787 | .prcm = { | |
2788 | .omap4 = { | |
d0f0631d | 2789 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2790 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2791 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2792 | }, |
2793 | }, | |
c345c8b0 | 2794 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2795 | }; |
2796 | ||
2797 | /* timer2 */ | |
35d1a66a BC |
2798 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
2799 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2800 | { .irq = -1 } |
35d1a66a BC |
2801 | }; |
2802 | ||
35d1a66a BC |
2803 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2804 | .name = "timer2", | |
2805 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2806 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2807 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
2808 | .main_clk = "timer2_fck", |
2809 | .prcm = { | |
2810 | .omap4 = { | |
d0f0631d | 2811 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2812 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2813 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2814 | }, |
2815 | }, | |
c345c8b0 | 2816 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2817 | }; |
2818 | ||
2819 | /* timer3 */ | |
35d1a66a BC |
2820 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
2821 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2822 | { .irq = -1 } |
35d1a66a BC |
2823 | }; |
2824 | ||
35d1a66a BC |
2825 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2826 | .name = "timer3", | |
2827 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2828 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2829 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
2830 | .main_clk = "timer3_fck", |
2831 | .prcm = { | |
2832 | .omap4 = { | |
d0f0631d | 2833 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2834 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2835 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2836 | }, |
2837 | }, | |
c345c8b0 | 2838 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2839 | }; |
2840 | ||
2841 | /* timer4 */ | |
35d1a66a BC |
2842 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
2843 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2844 | { .irq = -1 } |
35d1a66a BC |
2845 | }; |
2846 | ||
35d1a66a BC |
2847 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2848 | .name = "timer4", | |
2849 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2850 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2851 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
2852 | .main_clk = "timer4_fck", |
2853 | .prcm = { | |
2854 | .omap4 = { | |
d0f0631d | 2855 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2856 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2857 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2858 | }, |
2859 | }, | |
c345c8b0 | 2860 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2861 | }; |
2862 | ||
2863 | /* timer5 */ | |
35d1a66a BC |
2864 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
2865 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2866 | { .irq = -1 } |
35d1a66a BC |
2867 | }; |
2868 | ||
35d1a66a BC |
2869 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2870 | .name = "timer5", | |
2871 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2872 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2873 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
2874 | .main_clk = "timer5_fck", |
2875 | .prcm = { | |
2876 | .omap4 = { | |
d0f0631d | 2877 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2878 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2879 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2880 | }, |
2881 | }, | |
c345c8b0 | 2882 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2883 | }; |
2884 | ||
2885 | /* timer6 */ | |
35d1a66a BC |
2886 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
2887 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2888 | { .irq = -1 } |
35d1a66a BC |
2889 | }; |
2890 | ||
35d1a66a BC |
2891 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
2892 | .name = "timer6", | |
2893 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2894 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2895 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 2896 | |
35d1a66a BC |
2897 | .main_clk = "timer6_fck", |
2898 | .prcm = { | |
2899 | .omap4 = { | |
d0f0631d | 2900 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 2901 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 2902 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2903 | }, |
2904 | }, | |
c345c8b0 | 2905 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2906 | }; |
2907 | ||
2908 | /* timer7 */ | |
35d1a66a BC |
2909 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
2910 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2911 | { .irq = -1 } |
35d1a66a BC |
2912 | }; |
2913 | ||
35d1a66a BC |
2914 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
2915 | .name = "timer7", | |
2916 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2917 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2918 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
2919 | .main_clk = "timer7_fck", |
2920 | .prcm = { | |
2921 | .omap4 = { | |
d0f0631d | 2922 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 2923 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 2924 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2925 | }, |
2926 | }, | |
c345c8b0 | 2927 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2928 | }; |
2929 | ||
2930 | /* timer8 */ | |
35d1a66a BC |
2931 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
2932 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2933 | { .irq = -1 } |
35d1a66a BC |
2934 | }; |
2935 | ||
35d1a66a BC |
2936 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
2937 | .name = "timer8", | |
2938 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2939 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2940 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
2941 | .main_clk = "timer8_fck", |
2942 | .prcm = { | |
2943 | .omap4 = { | |
d0f0631d | 2944 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 2945 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 2946 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2947 | }, |
2948 | }, | |
c345c8b0 | 2949 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2950 | }; |
2951 | ||
2952 | /* timer9 */ | |
35d1a66a BC |
2953 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
2954 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2955 | { .irq = -1 } |
35d1a66a BC |
2956 | }; |
2957 | ||
35d1a66a BC |
2958 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
2959 | .name = "timer9", | |
2960 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2961 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2962 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
2963 | .main_clk = "timer9_fck", |
2964 | .prcm = { | |
2965 | .omap4 = { | |
d0f0631d | 2966 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 2967 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 2968 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2969 | }, |
2970 | }, | |
c345c8b0 | 2971 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2972 | }; |
2973 | ||
2974 | /* timer10 */ | |
35d1a66a BC |
2975 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
2976 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2977 | { .irq = -1 } |
35d1a66a BC |
2978 | }; |
2979 | ||
35d1a66a BC |
2980 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
2981 | .name = "timer10", | |
2982 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2983 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2984 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
2985 | .main_clk = "timer10_fck", |
2986 | .prcm = { | |
2987 | .omap4 = { | |
d0f0631d | 2988 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 2989 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 2990 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2991 | }, |
2992 | }, | |
c345c8b0 | 2993 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2994 | }; |
2995 | ||
2996 | /* timer11 */ | |
35d1a66a BC |
2997 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
2998 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2999 | { .irq = -1 } |
35d1a66a BC |
3000 | }; |
3001 | ||
35d1a66a BC |
3002 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
3003 | .name = "timer11", | |
3004 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3005 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3006 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
3007 | .main_clk = "timer11_fck", |
3008 | .prcm = { | |
3009 | .omap4 = { | |
d0f0631d | 3010 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 3011 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 3012 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3013 | }, |
3014 | }, | |
c345c8b0 | 3015 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3016 | }; |
3017 | ||
9780a9cf | 3018 | /* |
3b54baad BC |
3019 | * 'uart' class |
3020 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
3021 | */ |
3022 | ||
3b54baad BC |
3023 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
3024 | .rev_offs = 0x0050, | |
3025 | .sysc_offs = 0x0054, | |
3026 | .syss_offs = 0x0058, | |
3027 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
3028 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
3029 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
3030 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3031 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
3032 | .sysc_fields = &omap_hwmod_sysc_type1, |
3033 | }; | |
3034 | ||
3b54baad | 3035 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
3036 | .name = "uart", |
3037 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
3038 | }; |
3039 | ||
3b54baad | 3040 | /* uart1 */ |
3b54baad BC |
3041 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
3042 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3043 | { .irq = -1 } |
9780a9cf BC |
3044 | }; |
3045 | ||
3b54baad BC |
3046 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
3047 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
3048 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3049 | { .dma_req = -1 } |
9780a9cf BC |
3050 | }; |
3051 | ||
3b54baad BC |
3052 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
3053 | .name = "uart1", | |
3054 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3055 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3056 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 3057 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 3058 | .main_clk = "uart1_fck", |
9780a9cf BC |
3059 | .prcm = { |
3060 | .omap4 = { | |
d0f0631d | 3061 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 3062 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 3063 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3064 | }, |
3065 | }, | |
9780a9cf BC |
3066 | }; |
3067 | ||
3b54baad | 3068 | /* uart2 */ |
3b54baad BC |
3069 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
3070 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3071 | { .irq = -1 } |
9780a9cf BC |
3072 | }; |
3073 | ||
3b54baad BC |
3074 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
3075 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
3076 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3077 | { .dma_req = -1 } |
3b54baad BC |
3078 | }; |
3079 | ||
3b54baad BC |
3080 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
3081 | .name = "uart2", | |
3082 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3083 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3084 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 3085 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 3086 | .main_clk = "uart2_fck", |
9780a9cf BC |
3087 | .prcm = { |
3088 | .omap4 = { | |
d0f0631d | 3089 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 3090 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 3091 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3092 | }, |
3093 | }, | |
9780a9cf BC |
3094 | }; |
3095 | ||
3b54baad | 3096 | /* uart3 */ |
3b54baad BC |
3097 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
3098 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3099 | { .irq = -1 } |
9780a9cf BC |
3100 | }; |
3101 | ||
3b54baad BC |
3102 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
3103 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
3104 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3105 | { .dma_req = -1 } |
3b54baad BC |
3106 | }; |
3107 | ||
3b54baad BC |
3108 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
3109 | .name = "uart3", | |
3110 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3111 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 3112 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3113 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 3114 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 3115 | .main_clk = "uart3_fck", |
9780a9cf BC |
3116 | .prcm = { |
3117 | .omap4 = { | |
d0f0631d | 3118 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 3119 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 3120 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3121 | }, |
3122 | }, | |
9780a9cf BC |
3123 | }; |
3124 | ||
3b54baad | 3125 | /* uart4 */ |
3b54baad BC |
3126 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
3127 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3128 | { .irq = -1 } |
9780a9cf BC |
3129 | }; |
3130 | ||
3b54baad BC |
3131 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
3132 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
3133 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3134 | { .dma_req = -1 } |
3b54baad BC |
3135 | }; |
3136 | ||
3b54baad BC |
3137 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
3138 | .name = "uart4", | |
3139 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3140 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3141 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 3142 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 3143 | .main_clk = "uart4_fck", |
9780a9cf BC |
3144 | .prcm = { |
3145 | .omap4 = { | |
d0f0631d | 3146 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 3147 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 3148 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3149 | }, |
3150 | }, | |
9780a9cf BC |
3151 | }; |
3152 | ||
0c668875 BC |
3153 | /* |
3154 | * 'usb_host_fs' class | |
3155 | * full-speed usb host controller | |
3156 | */ | |
3157 | ||
3158 | /* The IP is not compliant to type1 / type2 scheme */ | |
3159 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
3160 | .midle_shift = 4, | |
3161 | .sidle_shift = 2, | |
3162 | .srst_shift = 1, | |
3163 | }; | |
3164 | ||
3165 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
3166 | .rev_offs = 0x0000, | |
3167 | .sysc_offs = 0x0210, | |
3168 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3169 | SYSC_HAS_SOFTRESET), | |
3170 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3171 | SIDLE_SMART_WKUP), | |
3172 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
3173 | }; | |
3174 | ||
3175 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
3176 | .name = "usb_host_fs", | |
3177 | .sysc = &omap44xx_usb_host_fs_sysc, | |
3178 | }; | |
3179 | ||
3180 | /* usb_host_fs */ | |
3181 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | |
3182 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | |
3183 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | |
3184 | { .irq = -1 } | |
3185 | }; | |
3186 | ||
3187 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | |
3188 | .name = "usb_host_fs", | |
3189 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
3190 | .clkdm_name = "l3_init_clkdm", | |
3191 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | |
3192 | .main_clk = "usb_host_fs_fck", | |
3193 | .prcm = { | |
3194 | .omap4 = { | |
3195 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
3196 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
3197 | .modulemode = MODULEMODE_SWCTRL, | |
3198 | }, | |
3199 | }, | |
3200 | }; | |
3201 | ||
5844c4ea | 3202 | /* |
844a3b63 PW |
3203 | * 'usb_host_hs' class |
3204 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3205 | */ |
3206 | ||
844a3b63 PW |
3207 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3208 | .rev_offs = 0x0000, | |
3209 | .sysc_offs = 0x0010, | |
3210 | .syss_offs = 0x0014, | |
3211 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3212 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
3213 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3214 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3215 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3216 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3217 | }; |
3218 | ||
844a3b63 PW |
3219 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3220 | .name = "usb_host_hs", | |
3221 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3222 | }; |
3223 | ||
844a3b63 PW |
3224 | /* usb_host_hs */ |
3225 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
3226 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
3227 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3228 | { .irq = -1 } |
5844c4ea BC |
3229 | }; |
3230 | ||
844a3b63 PW |
3231 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3232 | .name = "usb_host_hs", | |
3233 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3234 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3235 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3236 | .prcm = { |
3237 | .omap4 = { | |
844a3b63 PW |
3238 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3239 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3240 | .modulemode = MODULEMODE_SWCTRL, | |
3241 | }, | |
3242 | }, | |
3243 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
3244 | ||
3245 | /* | |
3246 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3247 | * id: i660 | |
3248 | * | |
3249 | * Description: | |
3250 | * In the following configuration : | |
3251 | * - USBHOST module is set to smart-idle mode | |
3252 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3253 | * happens when the system is going to a low power mode : all ports | |
3254 | * have been suspended, the master part of the USBHOST module has | |
3255 | * entered the standby state, and SW has cut the functional clocks) | |
3256 | * - an USBHOST interrupt occurs before the module is able to answer | |
3257 | * idle_ack, typically a remote wakeup IRQ. | |
3258 | * Then the USB HOST module will enter a deadlock situation where it | |
3259 | * is no more accessible nor functional. | |
3260 | * | |
3261 | * Workaround: | |
3262 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3263 | */ | |
3264 | ||
3265 | /* | |
3266 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3267 | * Id: i571 | |
3268 | * | |
3269 | * Description: | |
3270 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3271 | * ready to enter the standby state (i.e. all ports are suspended and | |
3272 | * all attached devices are in suspend mode), then it can wrongly assert | |
3273 | * the Mstandby signal too early while there are still some residual OCP | |
3274 | * transactions ongoing. If this condition occurs, the internal state | |
3275 | * machine may go to an undefined state and the USB link may be stuck | |
3276 | * upon the next resume. | |
3277 | * | |
3278 | * Workaround: | |
3279 | * Don't use smart standby; use only force standby, | |
3280 | * hence HWMOD_SWSUP_MSTANDBY | |
3281 | */ | |
3282 | ||
3283 | /* | |
3284 | * During system boot; If the hwmod framework resets the module | |
3285 | * the module will have smart idle settings; which can lead to deadlock | |
3286 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3287 | * Use HWMOD_INIT_NO_RESET. | |
3288 | */ | |
3289 | ||
3290 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3291 | HWMOD_INIT_NO_RESET, | |
3292 | }; | |
3293 | ||
3294 | /* | |
3295 | * 'usb_otg_hs' class | |
3296 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3297 | */ | |
3298 | ||
3299 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3300 | .rev_offs = 0x0400, | |
3301 | .sysc_offs = 0x0404, | |
3302 | .syss_offs = 0x0408, | |
3303 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3304 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3305 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3306 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3307 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3308 | MSTANDBY_SMART), | |
3309 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3310 | }; | |
3311 | ||
3312 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3313 | .name = "usb_otg_hs", | |
3314 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3315 | }; | |
3316 | ||
3317 | /* usb_otg_hs */ | |
3318 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
3319 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
3320 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
3321 | { .irq = -1 } | |
3322 | }; | |
3323 | ||
3324 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
3325 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3326 | }; | |
3327 | ||
3328 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3329 | .name = "usb_otg_hs", | |
3330 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3331 | .clkdm_name = "l3_init_clkdm", | |
3332 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
3333 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
3334 | .main_clk = "usb_otg_hs_ick", | |
3335 | .prcm = { | |
3336 | .omap4 = { | |
3337 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3338 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3339 | .modulemode = MODULEMODE_HWCTRL, | |
3340 | }, | |
3341 | }, | |
3342 | .opt_clks = usb_otg_hs_opt_clks, | |
3343 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3344 | }; | |
3345 | ||
3346 | /* | |
3347 | * 'usb_tll_hs' class | |
3348 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3349 | */ | |
3350 | ||
3351 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3352 | .rev_offs = 0x0000, | |
3353 | .sysc_offs = 0x0010, | |
3354 | .syss_offs = 0x0014, | |
3355 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3356 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3357 | SYSC_HAS_AUTOIDLE), | |
3358 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3359 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3360 | }; | |
3361 | ||
3362 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3363 | .name = "usb_tll_hs", | |
3364 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3365 | }; | |
3366 | ||
3367 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
3368 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
3369 | { .irq = -1 } | |
3370 | }; | |
3371 | ||
3372 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
3373 | .name = "usb_tll_hs", | |
3374 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3375 | .clkdm_name = "l3_init_clkdm", | |
3376 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
3377 | .main_clk = "usb_tll_hs_ick", | |
3378 | .prcm = { | |
3379 | .omap4 = { | |
3380 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3381 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3382 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3383 | }, |
3384 | }, | |
5844c4ea BC |
3385 | }; |
3386 | ||
3b54baad BC |
3387 | /* |
3388 | * 'wd_timer' class | |
3389 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3390 | * overflow condition | |
3391 | */ | |
3392 | ||
3393 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3394 | .rev_offs = 0x0000, | |
3395 | .sysc_offs = 0x0010, | |
3396 | .syss_offs = 0x0014, | |
3397 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3398 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3399 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3400 | SIDLE_SMART_WKUP), | |
3b54baad | 3401 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3402 | }; |
3403 | ||
3b54baad BC |
3404 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3405 | .name = "wd_timer", | |
3406 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3407 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
3408 | }; |
3409 | ||
3410 | /* wd_timer2 */ | |
3b54baad BC |
3411 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
3412 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3413 | { .irq = -1 } |
3b54baad BC |
3414 | }; |
3415 | ||
3b54baad BC |
3416 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3417 | .name = "wd_timer2", | |
3418 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3419 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 3420 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 3421 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
3422 | .prcm = { |
3423 | .omap4 = { | |
d0f0631d | 3424 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3425 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3426 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3427 | }, |
3428 | }, | |
9780a9cf BC |
3429 | }; |
3430 | ||
3b54baad | 3431 | /* wd_timer3 */ |
3b54baad BC |
3432 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
3433 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3434 | { .irq = -1 } |
9780a9cf BC |
3435 | }; |
3436 | ||
3b54baad BC |
3437 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3438 | .name = "wd_timer3", | |
3439 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3440 | .clkdm_name = "abe_clkdm", |
3b54baad | 3441 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 3442 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
3443 | .prcm = { |
3444 | .omap4 = { | |
d0f0631d | 3445 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3446 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3447 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3448 | }, |
3449 | }, | |
9780a9cf | 3450 | }; |
531ce0d5 | 3451 | |
844a3b63 | 3452 | |
af88fa9a | 3453 | /* |
844a3b63 | 3454 | * interfaces |
af88fa9a | 3455 | */ |
af88fa9a | 3456 | |
42b9e387 PW |
3457 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { |
3458 | { | |
3459 | .pa_start = 0x4a204000, | |
3460 | .pa_end = 0x4a2040ff, | |
3461 | .flags = ADDR_TYPE_RT | |
3462 | }, | |
3463 | { } | |
3464 | }; | |
3465 | ||
3466 | /* c2c -> c2c_target_fw */ | |
3467 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | |
3468 | .master = &omap44xx_c2c_hwmod, | |
3469 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3470 | .clk = "div_core_ck", | |
3471 | .addr = omap44xx_c2c_target_fw_addrs, | |
3472 | .user = OCP_USER_MPU, | |
3473 | }; | |
3474 | ||
3475 | /* l4_cfg -> c2c_target_fw */ | |
3476 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | |
3477 | .master = &omap44xx_l4_cfg_hwmod, | |
3478 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3479 | .clk = "l4_div_ck", | |
3480 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3481 | }; | |
3482 | ||
844a3b63 PW |
3483 | /* l3_main_1 -> dmm */ |
3484 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3485 | .master = &omap44xx_l3_main_1_hwmod, | |
3486 | .slave = &omap44xx_dmm_hwmod, | |
3487 | .clk = "l3_div_ck", | |
3488 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3489 | }; |
3490 | ||
844a3b63 | 3491 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 3492 | { |
844a3b63 PW |
3493 | .pa_start = 0x4e000000, |
3494 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
3495 | .flags = ADDR_TYPE_RT |
3496 | }, | |
844a3b63 | 3497 | { } |
af88fa9a BC |
3498 | }; |
3499 | ||
844a3b63 PW |
3500 | /* mpu -> dmm */ |
3501 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3502 | .master = &omap44xx_mpu_hwmod, | |
3503 | .slave = &omap44xx_dmm_hwmod, | |
3504 | .clk = "l3_div_ck", | |
3505 | .addr = omap44xx_dmm_addrs, | |
3506 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3507 | }; |
3508 | ||
42b9e387 PW |
3509 | /* c2c -> emif_fw */ |
3510 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | |
3511 | .master = &omap44xx_c2c_hwmod, | |
3512 | .slave = &omap44xx_emif_fw_hwmod, | |
3513 | .clk = "div_core_ck", | |
3514 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3515 | }; | |
3516 | ||
844a3b63 PW |
3517 | /* dmm -> emif_fw */ |
3518 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3519 | .master = &omap44xx_dmm_hwmod, | |
3520 | .slave = &omap44xx_emif_fw_hwmod, | |
3521 | .clk = "l3_div_ck", | |
3522 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3523 | }; | |
3524 | ||
3525 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3526 | { | |
3527 | .pa_start = 0x4a20c000, | |
3528 | .pa_end = 0x4a20c0ff, | |
3529 | .flags = ADDR_TYPE_RT | |
3530 | }, | |
3531 | { } | |
3532 | }; | |
3533 | ||
3534 | /* l4_cfg -> emif_fw */ | |
3535 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3536 | .master = &omap44xx_l4_cfg_hwmod, | |
3537 | .slave = &omap44xx_emif_fw_hwmod, | |
3538 | .clk = "l4_div_ck", | |
3539 | .addr = omap44xx_emif_fw_addrs, | |
3540 | .user = OCP_USER_MPU, | |
3541 | }; | |
3542 | ||
3543 | /* iva -> l3_instr */ | |
3544 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3545 | .master = &omap44xx_iva_hwmod, | |
3546 | .slave = &omap44xx_l3_instr_hwmod, | |
3547 | .clk = "l3_div_ck", | |
3548 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3549 | }; | |
3550 | ||
3551 | /* l3_main_3 -> l3_instr */ | |
3552 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3553 | .master = &omap44xx_l3_main_3_hwmod, | |
3554 | .slave = &omap44xx_l3_instr_hwmod, | |
3555 | .clk = "l3_div_ck", | |
3556 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3557 | }; | |
3558 | ||
9a817bc8 BC |
3559 | /* ocp_wp_noc -> l3_instr */ |
3560 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3561 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3562 | .slave = &omap44xx_l3_instr_hwmod, | |
3563 | .clk = "l3_div_ck", | |
3564 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3565 | }; | |
3566 | ||
844a3b63 PW |
3567 | /* dsp -> l3_main_1 */ |
3568 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3569 | .master = &omap44xx_dsp_hwmod, | |
3570 | .slave = &omap44xx_l3_main_1_hwmod, | |
3571 | .clk = "l3_div_ck", | |
3572 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3573 | }; | |
3574 | ||
3575 | /* dss -> l3_main_1 */ | |
3576 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3577 | .master = &omap44xx_dss_hwmod, | |
3578 | .slave = &omap44xx_l3_main_1_hwmod, | |
3579 | .clk = "l3_div_ck", | |
3580 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3581 | }; | |
3582 | ||
3583 | /* l3_main_2 -> l3_main_1 */ | |
3584 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3585 | .master = &omap44xx_l3_main_2_hwmod, | |
3586 | .slave = &omap44xx_l3_main_1_hwmod, | |
3587 | .clk = "l3_div_ck", | |
3588 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3589 | }; | |
3590 | ||
3591 | /* l4_cfg -> l3_main_1 */ | |
3592 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3593 | .master = &omap44xx_l4_cfg_hwmod, | |
3594 | .slave = &omap44xx_l3_main_1_hwmod, | |
3595 | .clk = "l4_div_ck", | |
3596 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3597 | }; | |
3598 | ||
3599 | /* mmc1 -> l3_main_1 */ | |
3600 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3601 | .master = &omap44xx_mmc1_hwmod, | |
3602 | .slave = &omap44xx_l3_main_1_hwmod, | |
3603 | .clk = "l3_div_ck", | |
3604 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3605 | }; | |
3606 | ||
3607 | /* mmc2 -> l3_main_1 */ | |
3608 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3609 | .master = &omap44xx_mmc2_hwmod, | |
3610 | .slave = &omap44xx_l3_main_1_hwmod, | |
3611 | .clk = "l3_div_ck", | |
3612 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3613 | }; | |
3614 | ||
3615 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3616 | { | |
3617 | .pa_start = 0x44000000, | |
3618 | .pa_end = 0x44000fff, | |
3619 | .flags = ADDR_TYPE_RT | |
3620 | }, | |
3621 | { } | |
3622 | }; | |
3623 | ||
3624 | /* mpu -> l3_main_1 */ | |
3625 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3626 | .master = &omap44xx_mpu_hwmod, | |
3627 | .slave = &omap44xx_l3_main_1_hwmod, | |
3628 | .clk = "l3_div_ck", | |
3629 | .addr = omap44xx_l3_main_1_addrs, | |
3630 | .user = OCP_USER_MPU, | |
3631 | }; | |
3632 | ||
42b9e387 PW |
3633 | /* c2c_target_fw -> l3_main_2 */ |
3634 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | |
3635 | .master = &omap44xx_c2c_target_fw_hwmod, | |
3636 | .slave = &omap44xx_l3_main_2_hwmod, | |
3637 | .clk = "l3_div_ck", | |
3638 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3639 | }; | |
3640 | ||
844a3b63 PW |
3641 | /* dma_system -> l3_main_2 */ |
3642 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3643 | .master = &omap44xx_dma_system_hwmod, | |
3644 | .slave = &omap44xx_l3_main_2_hwmod, | |
3645 | .clk = "l3_div_ck", | |
3646 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3647 | }; | |
3648 | ||
b050f688 ML |
3649 | /* fdif -> l3_main_2 */ |
3650 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3651 | .master = &omap44xx_fdif_hwmod, | |
3652 | .slave = &omap44xx_l3_main_2_hwmod, | |
3653 | .clk = "l3_div_ck", | |
3654 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3655 | }; | |
3656 | ||
9def390e PW |
3657 | /* gpu -> l3_main_2 */ |
3658 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3659 | .master = &omap44xx_gpu_hwmod, | |
3660 | .slave = &omap44xx_l3_main_2_hwmod, | |
3661 | .clk = "l3_div_ck", | |
3662 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3663 | }; | |
3664 | ||
844a3b63 PW |
3665 | /* hsi -> l3_main_2 */ |
3666 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3667 | .master = &omap44xx_hsi_hwmod, | |
3668 | .slave = &omap44xx_l3_main_2_hwmod, | |
3669 | .clk = "l3_div_ck", | |
3670 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3671 | }; | |
3672 | ||
3673 | /* ipu -> l3_main_2 */ | |
3674 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3675 | .master = &omap44xx_ipu_hwmod, | |
3676 | .slave = &omap44xx_l3_main_2_hwmod, | |
3677 | .clk = "l3_div_ck", | |
3678 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3679 | }; | |
3680 | ||
3681 | /* iss -> l3_main_2 */ | |
3682 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3683 | .master = &omap44xx_iss_hwmod, | |
3684 | .slave = &omap44xx_l3_main_2_hwmod, | |
3685 | .clk = "l3_div_ck", | |
3686 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3687 | }; | |
3688 | ||
3689 | /* iva -> l3_main_2 */ | |
3690 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3691 | .master = &omap44xx_iva_hwmod, | |
3692 | .slave = &omap44xx_l3_main_2_hwmod, | |
3693 | .clk = "l3_div_ck", | |
3694 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3695 | }; | |
3696 | ||
3697 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
3698 | { | |
3699 | .pa_start = 0x44800000, | |
3700 | .pa_end = 0x44801fff, | |
3701 | .flags = ADDR_TYPE_RT | |
3702 | }, | |
3703 | { } | |
3704 | }; | |
3705 | ||
3706 | /* l3_main_1 -> l3_main_2 */ | |
3707 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3708 | .master = &omap44xx_l3_main_1_hwmod, | |
3709 | .slave = &omap44xx_l3_main_2_hwmod, | |
3710 | .clk = "l3_div_ck", | |
3711 | .addr = omap44xx_l3_main_2_addrs, | |
3712 | .user = OCP_USER_MPU, | |
3713 | }; | |
3714 | ||
3715 | /* l4_cfg -> l3_main_2 */ | |
3716 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3717 | .master = &omap44xx_l4_cfg_hwmod, | |
3718 | .slave = &omap44xx_l3_main_2_hwmod, | |
3719 | .clk = "l4_div_ck", | |
3720 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3721 | }; | |
3722 | ||
0c668875 BC |
3723 | /* usb_host_fs -> l3_main_2 */ |
3724 | static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = { | |
3725 | .master = &omap44xx_usb_host_fs_hwmod, | |
3726 | .slave = &omap44xx_l3_main_2_hwmod, | |
3727 | .clk = "l3_div_ck", | |
3728 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3729 | }; | |
3730 | ||
844a3b63 PW |
3731 | /* usb_host_hs -> l3_main_2 */ |
3732 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3733 | .master = &omap44xx_usb_host_hs_hwmod, | |
3734 | .slave = &omap44xx_l3_main_2_hwmod, | |
3735 | .clk = "l3_div_ck", | |
3736 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3737 | }; | |
3738 | ||
3739 | /* usb_otg_hs -> l3_main_2 */ | |
3740 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3741 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3742 | .slave = &omap44xx_l3_main_2_hwmod, | |
3743 | .clk = "l3_div_ck", | |
3744 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3745 | }; | |
3746 | ||
3747 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
3748 | { | |
3749 | .pa_start = 0x45000000, | |
3750 | .pa_end = 0x45000fff, | |
3751 | .flags = ADDR_TYPE_RT | |
3752 | }, | |
3753 | { } | |
3754 | }; | |
3755 | ||
3756 | /* l3_main_1 -> l3_main_3 */ | |
3757 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3758 | .master = &omap44xx_l3_main_1_hwmod, | |
3759 | .slave = &omap44xx_l3_main_3_hwmod, | |
3760 | .clk = "l3_div_ck", | |
3761 | .addr = omap44xx_l3_main_3_addrs, | |
3762 | .user = OCP_USER_MPU, | |
3763 | }; | |
3764 | ||
3765 | /* l3_main_2 -> l3_main_3 */ | |
3766 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3767 | .master = &omap44xx_l3_main_2_hwmod, | |
3768 | .slave = &omap44xx_l3_main_3_hwmod, | |
3769 | .clk = "l3_div_ck", | |
3770 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3771 | }; | |
3772 | ||
3773 | /* l4_cfg -> l3_main_3 */ | |
3774 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3775 | .master = &omap44xx_l4_cfg_hwmod, | |
3776 | .slave = &omap44xx_l3_main_3_hwmod, | |
3777 | .clk = "l4_div_ck", | |
3778 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3779 | }; | |
3780 | ||
3781 | /* aess -> l4_abe */ | |
3782 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { | |
3783 | .master = &omap44xx_aess_hwmod, | |
3784 | .slave = &omap44xx_l4_abe_hwmod, | |
3785 | .clk = "ocp_abe_iclk", | |
3786 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3787 | }; | |
3788 | ||
3789 | /* dsp -> l4_abe */ | |
3790 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3791 | .master = &omap44xx_dsp_hwmod, | |
3792 | .slave = &omap44xx_l4_abe_hwmod, | |
3793 | .clk = "ocp_abe_iclk", | |
3794 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3795 | }; | |
3796 | ||
3797 | /* l3_main_1 -> l4_abe */ | |
3798 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3799 | .master = &omap44xx_l3_main_1_hwmod, | |
3800 | .slave = &omap44xx_l4_abe_hwmod, | |
3801 | .clk = "l3_div_ck", | |
3802 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3803 | }; | |
3804 | ||
3805 | /* mpu -> l4_abe */ | |
3806 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3807 | .master = &omap44xx_mpu_hwmod, | |
3808 | .slave = &omap44xx_l4_abe_hwmod, | |
3809 | .clk = "ocp_abe_iclk", | |
3810 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3811 | }; | |
3812 | ||
3813 | /* l3_main_1 -> l4_cfg */ | |
3814 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3815 | .master = &omap44xx_l3_main_1_hwmod, | |
3816 | .slave = &omap44xx_l4_cfg_hwmod, | |
3817 | .clk = "l3_div_ck", | |
3818 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3819 | }; | |
3820 | ||
3821 | /* l3_main_2 -> l4_per */ | |
3822 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3823 | .master = &omap44xx_l3_main_2_hwmod, | |
3824 | .slave = &omap44xx_l4_per_hwmod, | |
3825 | .clk = "l3_div_ck", | |
3826 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3827 | }; | |
3828 | ||
3829 | /* l4_cfg -> l4_wkup */ | |
3830 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3831 | .master = &omap44xx_l4_cfg_hwmod, | |
3832 | .slave = &omap44xx_l4_wkup_hwmod, | |
3833 | .clk = "l4_div_ck", | |
3834 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3835 | }; | |
3836 | ||
3837 | /* mpu -> mpu_private */ | |
3838 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3839 | .master = &omap44xx_mpu_hwmod, | |
3840 | .slave = &omap44xx_mpu_private_hwmod, | |
3841 | .clk = "l3_div_ck", | |
3842 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3843 | }; | |
3844 | ||
9a817bc8 BC |
3845 | static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { |
3846 | { | |
3847 | .pa_start = 0x4a102000, | |
3848 | .pa_end = 0x4a10207f, | |
3849 | .flags = ADDR_TYPE_RT | |
3850 | }, | |
3851 | { } | |
3852 | }; | |
3853 | ||
3854 | /* l4_cfg -> ocp_wp_noc */ | |
3855 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
3856 | .master = &omap44xx_l4_cfg_hwmod, | |
3857 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
3858 | .clk = "l4_div_ck", | |
3859 | .addr = omap44xx_ocp_wp_noc_addrs, | |
3860 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3861 | }; | |
3862 | ||
844a3b63 PW |
3863 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
3864 | { | |
3865 | .pa_start = 0x401f1000, | |
3866 | .pa_end = 0x401f13ff, | |
3867 | .flags = ADDR_TYPE_RT | |
3868 | }, | |
3869 | { } | |
3870 | }; | |
3871 | ||
3872 | /* l4_abe -> aess */ | |
3873 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { | |
3874 | .master = &omap44xx_l4_abe_hwmod, | |
3875 | .slave = &omap44xx_aess_hwmod, | |
3876 | .clk = "ocp_abe_iclk", | |
3877 | .addr = omap44xx_aess_addrs, | |
3878 | .user = OCP_USER_MPU, | |
3879 | }; | |
3880 | ||
3881 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
3882 | { | |
3883 | .pa_start = 0x490f1000, | |
3884 | .pa_end = 0x490f13ff, | |
3885 | .flags = ADDR_TYPE_RT | |
3886 | }, | |
3887 | { } | |
3888 | }; | |
3889 | ||
3890 | /* l4_abe -> aess (dma) */ | |
3891 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { | |
3892 | .master = &omap44xx_l4_abe_hwmod, | |
3893 | .slave = &omap44xx_aess_hwmod, | |
3894 | .clk = "ocp_abe_iclk", | |
3895 | .addr = omap44xx_aess_dma_addrs, | |
3896 | .user = OCP_USER_SDMA, | |
3897 | }; | |
3898 | ||
42b9e387 PW |
3899 | /* l3_main_2 -> c2c */ |
3900 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
3901 | .master = &omap44xx_l3_main_2_hwmod, | |
3902 | .slave = &omap44xx_c2c_hwmod, | |
3903 | .clk = "l3_div_ck", | |
3904 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3905 | }; | |
3906 | ||
844a3b63 PW |
3907 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
3908 | { | |
3909 | .pa_start = 0x4a304000, | |
3910 | .pa_end = 0x4a30401f, | |
3911 | .flags = ADDR_TYPE_RT | |
3912 | }, | |
3913 | { } | |
3914 | }; | |
3915 | ||
3916 | /* l4_wkup -> counter_32k */ | |
3917 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
3918 | .master = &omap44xx_l4_wkup_hwmod, | |
3919 | .slave = &omap44xx_counter_32k_hwmod, | |
3920 | .clk = "l4_wkup_clk_mux_ck", | |
3921 | .addr = omap44xx_counter_32k_addrs, | |
3922 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3923 | }; | |
3924 | ||
3925 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
3926 | { | |
3927 | .pa_start = 0x4a056000, | |
3928 | .pa_end = 0x4a056fff, | |
3929 | .flags = ADDR_TYPE_RT | |
3930 | }, | |
3931 | { } | |
3932 | }; | |
3933 | ||
3934 | /* l4_cfg -> dma_system */ | |
3935 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
3936 | .master = &omap44xx_l4_cfg_hwmod, | |
3937 | .slave = &omap44xx_dma_system_hwmod, | |
3938 | .clk = "l4_div_ck", | |
3939 | .addr = omap44xx_dma_system_addrs, | |
3940 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3941 | }; | |
3942 | ||
3943 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
3944 | { | |
3945 | .name = "mpu", | |
3946 | .pa_start = 0x4012e000, | |
3947 | .pa_end = 0x4012e07f, | |
3948 | .flags = ADDR_TYPE_RT | |
3949 | }, | |
3950 | { } | |
3951 | }; | |
3952 | ||
3953 | /* l4_abe -> dmic */ | |
3954 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
3955 | .master = &omap44xx_l4_abe_hwmod, | |
3956 | .slave = &omap44xx_dmic_hwmod, | |
3957 | .clk = "ocp_abe_iclk", | |
3958 | .addr = omap44xx_dmic_addrs, | |
3959 | .user = OCP_USER_MPU, | |
3960 | }; | |
3961 | ||
3962 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
3963 | { | |
3964 | .name = "dma", | |
3965 | .pa_start = 0x4902e000, | |
3966 | .pa_end = 0x4902e07f, | |
3967 | .flags = ADDR_TYPE_RT | |
3968 | }, | |
3969 | { } | |
3970 | }; | |
3971 | ||
3972 | /* l4_abe -> dmic (dma) */ | |
3973 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
3974 | .master = &omap44xx_l4_abe_hwmod, | |
3975 | .slave = &omap44xx_dmic_hwmod, | |
3976 | .clk = "ocp_abe_iclk", | |
3977 | .addr = omap44xx_dmic_dma_addrs, | |
3978 | .user = OCP_USER_SDMA, | |
3979 | }; | |
3980 | ||
3981 | /* dsp -> iva */ | |
3982 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
3983 | .master = &omap44xx_dsp_hwmod, | |
3984 | .slave = &omap44xx_iva_hwmod, | |
3985 | .clk = "dpll_iva_m5x2_ck", | |
3986 | .user = OCP_USER_DSP, | |
3987 | }; | |
3988 | ||
42b9e387 PW |
3989 | /* dsp -> sl2if */ |
3990 | static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { | |
3991 | .master = &omap44xx_dsp_hwmod, | |
3992 | .slave = &omap44xx_sl2if_hwmod, | |
3993 | .clk = "dpll_iva_m5x2_ck", | |
3994 | .user = OCP_USER_DSP, | |
3995 | }; | |
3996 | ||
844a3b63 PW |
3997 | /* l4_cfg -> dsp */ |
3998 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
3999 | .master = &omap44xx_l4_cfg_hwmod, | |
4000 | .slave = &omap44xx_dsp_hwmod, | |
4001 | .clk = "l4_div_ck", | |
4002 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4003 | }; | |
4004 | ||
4005 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
4006 | { | |
4007 | .pa_start = 0x58000000, | |
4008 | .pa_end = 0x5800007f, | |
4009 | .flags = ADDR_TYPE_RT | |
4010 | }, | |
4011 | { } | |
4012 | }; | |
4013 | ||
4014 | /* l3_main_2 -> dss */ | |
4015 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
4016 | .master = &omap44xx_l3_main_2_hwmod, | |
4017 | .slave = &omap44xx_dss_hwmod, | |
4018 | .clk = "dss_fck", | |
4019 | .addr = omap44xx_dss_dma_addrs, | |
4020 | .user = OCP_USER_SDMA, | |
4021 | }; | |
4022 | ||
4023 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
4024 | { | |
4025 | .pa_start = 0x48040000, | |
4026 | .pa_end = 0x4804007f, | |
4027 | .flags = ADDR_TYPE_RT | |
4028 | }, | |
4029 | { } | |
4030 | }; | |
4031 | ||
4032 | /* l4_per -> dss */ | |
4033 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
4034 | .master = &omap44xx_l4_per_hwmod, | |
4035 | .slave = &omap44xx_dss_hwmod, | |
4036 | .clk = "l4_div_ck", | |
4037 | .addr = omap44xx_dss_addrs, | |
4038 | .user = OCP_USER_MPU, | |
4039 | }; | |
4040 | ||
4041 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
4042 | { | |
4043 | .pa_start = 0x58001000, | |
4044 | .pa_end = 0x58001fff, | |
4045 | .flags = ADDR_TYPE_RT | |
4046 | }, | |
4047 | { } | |
4048 | }; | |
4049 | ||
4050 | /* l3_main_2 -> dss_dispc */ | |
4051 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
4052 | .master = &omap44xx_l3_main_2_hwmod, | |
4053 | .slave = &omap44xx_dss_dispc_hwmod, | |
4054 | .clk = "dss_fck", | |
4055 | .addr = omap44xx_dss_dispc_dma_addrs, | |
4056 | .user = OCP_USER_SDMA, | |
4057 | }; | |
4058 | ||
4059 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
4060 | { | |
4061 | .pa_start = 0x48041000, | |
4062 | .pa_end = 0x48041fff, | |
4063 | .flags = ADDR_TYPE_RT | |
4064 | }, | |
4065 | { } | |
4066 | }; | |
4067 | ||
4068 | /* l4_per -> dss_dispc */ | |
4069 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
4070 | .master = &omap44xx_l4_per_hwmod, | |
4071 | .slave = &omap44xx_dss_dispc_hwmod, | |
4072 | .clk = "l4_div_ck", | |
4073 | .addr = omap44xx_dss_dispc_addrs, | |
4074 | .user = OCP_USER_MPU, | |
4075 | }; | |
4076 | ||
4077 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
4078 | { | |
4079 | .pa_start = 0x58004000, | |
4080 | .pa_end = 0x580041ff, | |
4081 | .flags = ADDR_TYPE_RT | |
4082 | }, | |
4083 | { } | |
4084 | }; | |
4085 | ||
4086 | /* l3_main_2 -> dss_dsi1 */ | |
4087 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
4088 | .master = &omap44xx_l3_main_2_hwmod, | |
4089 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4090 | .clk = "dss_fck", | |
4091 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
4092 | .user = OCP_USER_SDMA, | |
4093 | }; | |
4094 | ||
4095 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
4096 | { | |
4097 | .pa_start = 0x48044000, | |
4098 | .pa_end = 0x480441ff, | |
4099 | .flags = ADDR_TYPE_RT | |
4100 | }, | |
4101 | { } | |
4102 | }; | |
4103 | ||
4104 | /* l4_per -> dss_dsi1 */ | |
4105 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
4106 | .master = &omap44xx_l4_per_hwmod, | |
4107 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4108 | .clk = "l4_div_ck", | |
4109 | .addr = omap44xx_dss_dsi1_addrs, | |
4110 | .user = OCP_USER_MPU, | |
4111 | }; | |
4112 | ||
4113 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
4114 | { | |
4115 | .pa_start = 0x58005000, | |
4116 | .pa_end = 0x580051ff, | |
4117 | .flags = ADDR_TYPE_RT | |
4118 | }, | |
4119 | { } | |
4120 | }; | |
4121 | ||
4122 | /* l3_main_2 -> dss_dsi2 */ | |
4123 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
4124 | .master = &omap44xx_l3_main_2_hwmod, | |
4125 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4126 | .clk = "dss_fck", | |
4127 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
4128 | .user = OCP_USER_SDMA, | |
4129 | }; | |
4130 | ||
4131 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
4132 | { | |
4133 | .pa_start = 0x48045000, | |
4134 | .pa_end = 0x480451ff, | |
4135 | .flags = ADDR_TYPE_RT | |
4136 | }, | |
4137 | { } | |
4138 | }; | |
4139 | ||
4140 | /* l4_per -> dss_dsi2 */ | |
4141 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
4142 | .master = &omap44xx_l4_per_hwmod, | |
4143 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4144 | .clk = "l4_div_ck", | |
4145 | .addr = omap44xx_dss_dsi2_addrs, | |
4146 | .user = OCP_USER_MPU, | |
4147 | }; | |
4148 | ||
4149 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
4150 | { | |
4151 | .pa_start = 0x58006000, | |
4152 | .pa_end = 0x58006fff, | |
4153 | .flags = ADDR_TYPE_RT | |
4154 | }, | |
4155 | { } | |
4156 | }; | |
4157 | ||
4158 | /* l3_main_2 -> dss_hdmi */ | |
4159 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
4160 | .master = &omap44xx_l3_main_2_hwmod, | |
4161 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4162 | .clk = "dss_fck", | |
4163 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
4164 | .user = OCP_USER_SDMA, | |
4165 | }; | |
4166 | ||
4167 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
4168 | { | |
4169 | .pa_start = 0x48046000, | |
4170 | .pa_end = 0x48046fff, | |
4171 | .flags = ADDR_TYPE_RT | |
4172 | }, | |
4173 | { } | |
4174 | }; | |
4175 | ||
4176 | /* l4_per -> dss_hdmi */ | |
4177 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
4178 | .master = &omap44xx_l4_per_hwmod, | |
4179 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4180 | .clk = "l4_div_ck", | |
4181 | .addr = omap44xx_dss_hdmi_addrs, | |
4182 | .user = OCP_USER_MPU, | |
4183 | }; | |
4184 | ||
4185 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
4186 | { | |
4187 | .pa_start = 0x58002000, | |
4188 | .pa_end = 0x580020ff, | |
4189 | .flags = ADDR_TYPE_RT | |
4190 | }, | |
4191 | { } | |
4192 | }; | |
4193 | ||
4194 | /* l3_main_2 -> dss_rfbi */ | |
4195 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
4196 | .master = &omap44xx_l3_main_2_hwmod, | |
4197 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4198 | .clk = "dss_fck", | |
4199 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
4200 | .user = OCP_USER_SDMA, | |
4201 | }; | |
4202 | ||
4203 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
4204 | { | |
4205 | .pa_start = 0x48042000, | |
4206 | .pa_end = 0x480420ff, | |
4207 | .flags = ADDR_TYPE_RT | |
4208 | }, | |
4209 | { } | |
4210 | }; | |
4211 | ||
4212 | /* l4_per -> dss_rfbi */ | |
4213 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
4214 | .master = &omap44xx_l4_per_hwmod, | |
4215 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4216 | .clk = "l4_div_ck", | |
4217 | .addr = omap44xx_dss_rfbi_addrs, | |
4218 | .user = OCP_USER_MPU, | |
4219 | }; | |
4220 | ||
4221 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
4222 | { | |
4223 | .pa_start = 0x58003000, | |
4224 | .pa_end = 0x580030ff, | |
4225 | .flags = ADDR_TYPE_RT | |
4226 | }, | |
4227 | { } | |
4228 | }; | |
4229 | ||
4230 | /* l3_main_2 -> dss_venc */ | |
4231 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
4232 | .master = &omap44xx_l3_main_2_hwmod, | |
4233 | .slave = &omap44xx_dss_venc_hwmod, | |
4234 | .clk = "dss_fck", | |
4235 | .addr = omap44xx_dss_venc_dma_addrs, | |
4236 | .user = OCP_USER_SDMA, | |
4237 | }; | |
4238 | ||
4239 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
4240 | { | |
4241 | .pa_start = 0x48043000, | |
4242 | .pa_end = 0x480430ff, | |
4243 | .flags = ADDR_TYPE_RT | |
4244 | }, | |
4245 | { } | |
4246 | }; | |
4247 | ||
4248 | /* l4_per -> dss_venc */ | |
4249 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
4250 | .master = &omap44xx_l4_per_hwmod, | |
4251 | .slave = &omap44xx_dss_venc_hwmod, | |
4252 | .clk = "l4_div_ck", | |
4253 | .addr = omap44xx_dss_venc_addrs, | |
4254 | .user = OCP_USER_MPU, | |
4255 | }; | |
4256 | ||
42b9e387 PW |
4257 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
4258 | { | |
4259 | .pa_start = 0x48078000, | |
4260 | .pa_end = 0x48078fff, | |
4261 | .flags = ADDR_TYPE_RT | |
4262 | }, | |
4263 | { } | |
4264 | }; | |
4265 | ||
4266 | /* l4_per -> elm */ | |
4267 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
4268 | .master = &omap44xx_l4_per_hwmod, | |
4269 | .slave = &omap44xx_elm_hwmod, | |
4270 | .clk = "l4_div_ck", | |
4271 | .addr = omap44xx_elm_addrs, | |
4272 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4273 | }; | |
4274 | ||
bf30f950 PW |
4275 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
4276 | { | |
4277 | .pa_start = 0x4c000000, | |
4278 | .pa_end = 0x4c0000ff, | |
4279 | .flags = ADDR_TYPE_RT | |
4280 | }, | |
4281 | { } | |
4282 | }; | |
4283 | ||
4284 | /* emif_fw -> emif1 */ | |
4285 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | |
4286 | .master = &omap44xx_emif_fw_hwmod, | |
4287 | .slave = &omap44xx_emif1_hwmod, | |
4288 | .clk = "l3_div_ck", | |
4289 | .addr = omap44xx_emif1_addrs, | |
4290 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4291 | }; | |
4292 | ||
4293 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | |
4294 | { | |
4295 | .pa_start = 0x4d000000, | |
4296 | .pa_end = 0x4d0000ff, | |
4297 | .flags = ADDR_TYPE_RT | |
4298 | }, | |
4299 | { } | |
4300 | }; | |
4301 | ||
4302 | /* emif_fw -> emif2 */ | |
4303 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | |
4304 | .master = &omap44xx_emif_fw_hwmod, | |
4305 | .slave = &omap44xx_emif2_hwmod, | |
4306 | .clk = "l3_div_ck", | |
4307 | .addr = omap44xx_emif2_addrs, | |
4308 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4309 | }; | |
4310 | ||
b050f688 ML |
4311 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
4312 | { | |
4313 | .pa_start = 0x4a10a000, | |
4314 | .pa_end = 0x4a10a1ff, | |
4315 | .flags = ADDR_TYPE_RT | |
4316 | }, | |
4317 | { } | |
4318 | }; | |
4319 | ||
4320 | /* l4_cfg -> fdif */ | |
4321 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4322 | .master = &omap44xx_l4_cfg_hwmod, | |
4323 | .slave = &omap44xx_fdif_hwmod, | |
4324 | .clk = "l4_div_ck", | |
4325 | .addr = omap44xx_fdif_addrs, | |
4326 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4327 | }; | |
4328 | ||
844a3b63 PW |
4329 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
4330 | { | |
4331 | .pa_start = 0x4a310000, | |
4332 | .pa_end = 0x4a3101ff, | |
4333 | .flags = ADDR_TYPE_RT | |
4334 | }, | |
4335 | { } | |
4336 | }; | |
4337 | ||
4338 | /* l4_wkup -> gpio1 */ | |
4339 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4340 | .master = &omap44xx_l4_wkup_hwmod, | |
4341 | .slave = &omap44xx_gpio1_hwmod, | |
4342 | .clk = "l4_wkup_clk_mux_ck", | |
4343 | .addr = omap44xx_gpio1_addrs, | |
4344 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4345 | }; | |
4346 | ||
4347 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
4348 | { | |
4349 | .pa_start = 0x48055000, | |
4350 | .pa_end = 0x480551ff, | |
4351 | .flags = ADDR_TYPE_RT | |
4352 | }, | |
4353 | { } | |
4354 | }; | |
4355 | ||
4356 | /* l4_per -> gpio2 */ | |
4357 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4358 | .master = &omap44xx_l4_per_hwmod, | |
4359 | .slave = &omap44xx_gpio2_hwmod, | |
4360 | .clk = "l4_div_ck", | |
4361 | .addr = omap44xx_gpio2_addrs, | |
4362 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4363 | }; | |
4364 | ||
4365 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
4366 | { | |
4367 | .pa_start = 0x48057000, | |
4368 | .pa_end = 0x480571ff, | |
4369 | .flags = ADDR_TYPE_RT | |
4370 | }, | |
4371 | { } | |
4372 | }; | |
4373 | ||
4374 | /* l4_per -> gpio3 */ | |
4375 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4376 | .master = &omap44xx_l4_per_hwmod, | |
4377 | .slave = &omap44xx_gpio3_hwmod, | |
4378 | .clk = "l4_div_ck", | |
4379 | .addr = omap44xx_gpio3_addrs, | |
4380 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4381 | }; | |
4382 | ||
4383 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
4384 | { | |
4385 | .pa_start = 0x48059000, | |
4386 | .pa_end = 0x480591ff, | |
4387 | .flags = ADDR_TYPE_RT | |
4388 | }, | |
4389 | { } | |
4390 | }; | |
4391 | ||
4392 | /* l4_per -> gpio4 */ | |
4393 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4394 | .master = &omap44xx_l4_per_hwmod, | |
4395 | .slave = &omap44xx_gpio4_hwmod, | |
4396 | .clk = "l4_div_ck", | |
4397 | .addr = omap44xx_gpio4_addrs, | |
4398 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4399 | }; | |
4400 | ||
4401 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
4402 | { | |
4403 | .pa_start = 0x4805b000, | |
4404 | .pa_end = 0x4805b1ff, | |
4405 | .flags = ADDR_TYPE_RT | |
4406 | }, | |
4407 | { } | |
4408 | }; | |
4409 | ||
4410 | /* l4_per -> gpio5 */ | |
4411 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4412 | .master = &omap44xx_l4_per_hwmod, | |
4413 | .slave = &omap44xx_gpio5_hwmod, | |
4414 | .clk = "l4_div_ck", | |
4415 | .addr = omap44xx_gpio5_addrs, | |
4416 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4417 | }; | |
4418 | ||
4419 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
4420 | { | |
4421 | .pa_start = 0x4805d000, | |
4422 | .pa_end = 0x4805d1ff, | |
4423 | .flags = ADDR_TYPE_RT | |
4424 | }, | |
4425 | { } | |
4426 | }; | |
4427 | ||
4428 | /* l4_per -> gpio6 */ | |
4429 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4430 | .master = &omap44xx_l4_per_hwmod, | |
4431 | .slave = &omap44xx_gpio6_hwmod, | |
4432 | .clk = "l4_div_ck", | |
4433 | .addr = omap44xx_gpio6_addrs, | |
4434 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4435 | }; | |
4436 | ||
eb42b5d3 BC |
4437 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
4438 | { | |
4439 | .pa_start = 0x50000000, | |
4440 | .pa_end = 0x500003ff, | |
4441 | .flags = ADDR_TYPE_RT | |
4442 | }, | |
4443 | { } | |
4444 | }; | |
4445 | ||
4446 | /* l3_main_2 -> gpmc */ | |
4447 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4448 | .master = &omap44xx_l3_main_2_hwmod, | |
4449 | .slave = &omap44xx_gpmc_hwmod, | |
4450 | .clk = "l3_div_ck", | |
4451 | .addr = omap44xx_gpmc_addrs, | |
4452 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4453 | }; | |
4454 | ||
9def390e PW |
4455 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4456 | { | |
4457 | .pa_start = 0x56000000, | |
4458 | .pa_end = 0x5600ffff, | |
4459 | .flags = ADDR_TYPE_RT | |
4460 | }, | |
4461 | { } | |
4462 | }; | |
4463 | ||
4464 | /* l3_main_2 -> gpu */ | |
4465 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4466 | .master = &omap44xx_l3_main_2_hwmod, | |
4467 | .slave = &omap44xx_gpu_hwmod, | |
4468 | .clk = "l3_div_ck", | |
4469 | .addr = omap44xx_gpu_addrs, | |
4470 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4471 | }; | |
4472 | ||
a091c08e PW |
4473 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4474 | { | |
4475 | .pa_start = 0x480b2000, | |
4476 | .pa_end = 0x480b201f, | |
4477 | .flags = ADDR_TYPE_RT | |
4478 | }, | |
4479 | { } | |
4480 | }; | |
4481 | ||
4482 | /* l4_per -> hdq1w */ | |
4483 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4484 | .master = &omap44xx_l4_per_hwmod, | |
4485 | .slave = &omap44xx_hdq1w_hwmod, | |
4486 | .clk = "l4_div_ck", | |
4487 | .addr = omap44xx_hdq1w_addrs, | |
4488 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4489 | }; | |
4490 | ||
844a3b63 PW |
4491 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4492 | { | |
4493 | .pa_start = 0x4a058000, | |
4494 | .pa_end = 0x4a05bfff, | |
4495 | .flags = ADDR_TYPE_RT | |
4496 | }, | |
4497 | { } | |
4498 | }; | |
4499 | ||
4500 | /* l4_cfg -> hsi */ | |
4501 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4502 | .master = &omap44xx_l4_cfg_hwmod, | |
4503 | .slave = &omap44xx_hsi_hwmod, | |
4504 | .clk = "l4_div_ck", | |
4505 | .addr = omap44xx_hsi_addrs, | |
4506 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4507 | }; | |
4508 | ||
4509 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
4510 | { | |
4511 | .pa_start = 0x48070000, | |
4512 | .pa_end = 0x480700ff, | |
4513 | .flags = ADDR_TYPE_RT | |
4514 | }, | |
4515 | { } | |
4516 | }; | |
4517 | ||
4518 | /* l4_per -> i2c1 */ | |
4519 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4520 | .master = &omap44xx_l4_per_hwmod, | |
4521 | .slave = &omap44xx_i2c1_hwmod, | |
4522 | .clk = "l4_div_ck", | |
4523 | .addr = omap44xx_i2c1_addrs, | |
4524 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4525 | }; | |
4526 | ||
4527 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
4528 | { | |
4529 | .pa_start = 0x48072000, | |
4530 | .pa_end = 0x480720ff, | |
4531 | .flags = ADDR_TYPE_RT | |
4532 | }, | |
4533 | { } | |
4534 | }; | |
4535 | ||
4536 | /* l4_per -> i2c2 */ | |
4537 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4538 | .master = &omap44xx_l4_per_hwmod, | |
4539 | .slave = &omap44xx_i2c2_hwmod, | |
4540 | .clk = "l4_div_ck", | |
4541 | .addr = omap44xx_i2c2_addrs, | |
4542 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4543 | }; | |
4544 | ||
4545 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
4546 | { | |
4547 | .pa_start = 0x48060000, | |
4548 | .pa_end = 0x480600ff, | |
4549 | .flags = ADDR_TYPE_RT | |
4550 | }, | |
4551 | { } | |
4552 | }; | |
4553 | ||
4554 | /* l4_per -> i2c3 */ | |
4555 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4556 | .master = &omap44xx_l4_per_hwmod, | |
4557 | .slave = &omap44xx_i2c3_hwmod, | |
4558 | .clk = "l4_div_ck", | |
4559 | .addr = omap44xx_i2c3_addrs, | |
4560 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4561 | }; | |
4562 | ||
4563 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
4564 | { | |
4565 | .pa_start = 0x48350000, | |
4566 | .pa_end = 0x483500ff, | |
4567 | .flags = ADDR_TYPE_RT | |
4568 | }, | |
4569 | { } | |
4570 | }; | |
4571 | ||
4572 | /* l4_per -> i2c4 */ | |
4573 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4574 | .master = &omap44xx_l4_per_hwmod, | |
4575 | .slave = &omap44xx_i2c4_hwmod, | |
4576 | .clk = "l4_div_ck", | |
4577 | .addr = omap44xx_i2c4_addrs, | |
4578 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4579 | }; | |
4580 | ||
4581 | /* l3_main_2 -> ipu */ | |
4582 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4583 | .master = &omap44xx_l3_main_2_hwmod, | |
4584 | .slave = &omap44xx_ipu_hwmod, | |
4585 | .clk = "l3_div_ck", | |
4586 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4587 | }; | |
4588 | ||
4589 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
4590 | { | |
4591 | .pa_start = 0x52000000, | |
4592 | .pa_end = 0x520000ff, | |
4593 | .flags = ADDR_TYPE_RT | |
4594 | }, | |
4595 | { } | |
4596 | }; | |
4597 | ||
4598 | /* l3_main_2 -> iss */ | |
4599 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
4600 | .master = &omap44xx_l3_main_2_hwmod, | |
4601 | .slave = &omap44xx_iss_hwmod, | |
4602 | .clk = "l3_div_ck", | |
4603 | .addr = omap44xx_iss_addrs, | |
4604 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4605 | }; | |
4606 | ||
42b9e387 PW |
4607 | /* iva -> sl2if */ |
4608 | static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { | |
4609 | .master = &omap44xx_iva_hwmod, | |
4610 | .slave = &omap44xx_sl2if_hwmod, | |
4611 | .clk = "dpll_iva_m5x2_ck", | |
4612 | .user = OCP_USER_IVA, | |
4613 | }; | |
4614 | ||
844a3b63 PW |
4615 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
4616 | { | |
4617 | .pa_start = 0x5a000000, | |
4618 | .pa_end = 0x5a07ffff, | |
4619 | .flags = ADDR_TYPE_RT | |
4620 | }, | |
4621 | { } | |
4622 | }; | |
4623 | ||
4624 | /* l3_main_2 -> iva */ | |
4625 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
4626 | .master = &omap44xx_l3_main_2_hwmod, | |
4627 | .slave = &omap44xx_iva_hwmod, | |
4628 | .clk = "l3_div_ck", | |
4629 | .addr = omap44xx_iva_addrs, | |
4630 | .user = OCP_USER_MPU, | |
4631 | }; | |
4632 | ||
4633 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
4634 | { | |
4635 | .pa_start = 0x4a31c000, | |
4636 | .pa_end = 0x4a31c07f, | |
4637 | .flags = ADDR_TYPE_RT | |
4638 | }, | |
4639 | { } | |
4640 | }; | |
4641 | ||
4642 | /* l4_wkup -> kbd */ | |
4643 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
4644 | .master = &omap44xx_l4_wkup_hwmod, | |
4645 | .slave = &omap44xx_kbd_hwmod, | |
4646 | .clk = "l4_wkup_clk_mux_ck", | |
4647 | .addr = omap44xx_kbd_addrs, | |
4648 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4649 | }; | |
4650 | ||
4651 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
4652 | { | |
4653 | .pa_start = 0x4a0f4000, | |
4654 | .pa_end = 0x4a0f41ff, | |
4655 | .flags = ADDR_TYPE_RT | |
4656 | }, | |
4657 | { } | |
4658 | }; | |
4659 | ||
4660 | /* l4_cfg -> mailbox */ | |
4661 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4662 | .master = &omap44xx_l4_cfg_hwmod, | |
4663 | .slave = &omap44xx_mailbox_hwmod, | |
4664 | .clk = "l4_div_ck", | |
4665 | .addr = omap44xx_mailbox_addrs, | |
4666 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4667 | }; | |
4668 | ||
896d4e98 BC |
4669 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
4670 | { | |
4671 | .pa_start = 0x40128000, | |
4672 | .pa_end = 0x401283ff, | |
4673 | .flags = ADDR_TYPE_RT | |
4674 | }, | |
4675 | { } | |
4676 | }; | |
4677 | ||
4678 | /* l4_abe -> mcasp */ | |
4679 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
4680 | .master = &omap44xx_l4_abe_hwmod, | |
4681 | .slave = &omap44xx_mcasp_hwmod, | |
4682 | .clk = "ocp_abe_iclk", | |
4683 | .addr = omap44xx_mcasp_addrs, | |
4684 | .user = OCP_USER_MPU, | |
4685 | }; | |
4686 | ||
4687 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
4688 | { | |
4689 | .pa_start = 0x49028000, | |
4690 | .pa_end = 0x490283ff, | |
4691 | .flags = ADDR_TYPE_RT | |
4692 | }, | |
4693 | { } | |
4694 | }; | |
4695 | ||
4696 | /* l4_abe -> mcasp (dma) */ | |
4697 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
4698 | .master = &omap44xx_l4_abe_hwmod, | |
4699 | .slave = &omap44xx_mcasp_hwmod, | |
4700 | .clk = "ocp_abe_iclk", | |
4701 | .addr = omap44xx_mcasp_dma_addrs, | |
4702 | .user = OCP_USER_SDMA, | |
4703 | }; | |
4704 | ||
844a3b63 PW |
4705 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
4706 | { | |
4707 | .name = "mpu", | |
4708 | .pa_start = 0x40122000, | |
4709 | .pa_end = 0x401220ff, | |
4710 | .flags = ADDR_TYPE_RT | |
4711 | }, | |
4712 | { } | |
4713 | }; | |
4714 | ||
4715 | /* l4_abe -> mcbsp1 */ | |
4716 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4717 | .master = &omap44xx_l4_abe_hwmod, | |
4718 | .slave = &omap44xx_mcbsp1_hwmod, | |
4719 | .clk = "ocp_abe_iclk", | |
4720 | .addr = omap44xx_mcbsp1_addrs, | |
4721 | .user = OCP_USER_MPU, | |
4722 | }; | |
4723 | ||
4724 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
4725 | { | |
4726 | .name = "dma", | |
4727 | .pa_start = 0x49022000, | |
4728 | .pa_end = 0x490220ff, | |
4729 | .flags = ADDR_TYPE_RT | |
4730 | }, | |
4731 | { } | |
4732 | }; | |
4733 | ||
4734 | /* l4_abe -> mcbsp1 (dma) */ | |
4735 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
4736 | .master = &omap44xx_l4_abe_hwmod, | |
4737 | .slave = &omap44xx_mcbsp1_hwmod, | |
4738 | .clk = "ocp_abe_iclk", | |
4739 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4740 | .user = OCP_USER_SDMA, | |
4741 | }; | |
4742 | ||
4743 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
4744 | { | |
4745 | .name = "mpu", | |
4746 | .pa_start = 0x40124000, | |
4747 | .pa_end = 0x401240ff, | |
4748 | .flags = ADDR_TYPE_RT | |
4749 | }, | |
4750 | { } | |
4751 | }; | |
4752 | ||
4753 | /* l4_abe -> mcbsp2 */ | |
4754 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4755 | .master = &omap44xx_l4_abe_hwmod, | |
4756 | .slave = &omap44xx_mcbsp2_hwmod, | |
4757 | .clk = "ocp_abe_iclk", | |
4758 | .addr = omap44xx_mcbsp2_addrs, | |
4759 | .user = OCP_USER_MPU, | |
4760 | }; | |
4761 | ||
4762 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
4763 | { | |
4764 | .name = "dma", | |
4765 | .pa_start = 0x49024000, | |
4766 | .pa_end = 0x490240ff, | |
4767 | .flags = ADDR_TYPE_RT | |
4768 | }, | |
4769 | { } | |
4770 | }; | |
4771 | ||
4772 | /* l4_abe -> mcbsp2 (dma) */ | |
4773 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
4774 | .master = &omap44xx_l4_abe_hwmod, | |
4775 | .slave = &omap44xx_mcbsp2_hwmod, | |
4776 | .clk = "ocp_abe_iclk", | |
4777 | .addr = omap44xx_mcbsp2_dma_addrs, | |
4778 | .user = OCP_USER_SDMA, | |
4779 | }; | |
4780 | ||
4781 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
4782 | { | |
4783 | .name = "mpu", | |
4784 | .pa_start = 0x40126000, | |
4785 | .pa_end = 0x401260ff, | |
4786 | .flags = ADDR_TYPE_RT | |
4787 | }, | |
4788 | { } | |
4789 | }; | |
4790 | ||
4791 | /* l4_abe -> mcbsp3 */ | |
4792 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
4793 | .master = &omap44xx_l4_abe_hwmod, | |
4794 | .slave = &omap44xx_mcbsp3_hwmod, | |
4795 | .clk = "ocp_abe_iclk", | |
4796 | .addr = omap44xx_mcbsp3_addrs, | |
4797 | .user = OCP_USER_MPU, | |
4798 | }; | |
4799 | ||
4800 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
4801 | { | |
4802 | .name = "dma", | |
4803 | .pa_start = 0x49026000, | |
4804 | .pa_end = 0x490260ff, | |
4805 | .flags = ADDR_TYPE_RT | |
4806 | }, | |
4807 | { } | |
4808 | }; | |
4809 | ||
4810 | /* l4_abe -> mcbsp3 (dma) */ | |
4811 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
4812 | .master = &omap44xx_l4_abe_hwmod, | |
4813 | .slave = &omap44xx_mcbsp3_hwmod, | |
4814 | .clk = "ocp_abe_iclk", | |
4815 | .addr = omap44xx_mcbsp3_dma_addrs, | |
4816 | .user = OCP_USER_SDMA, | |
4817 | }; | |
4818 | ||
4819 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
4820 | { | |
4821 | .pa_start = 0x48096000, | |
4822 | .pa_end = 0x480960ff, | |
4823 | .flags = ADDR_TYPE_RT | |
4824 | }, | |
4825 | { } | |
4826 | }; | |
4827 | ||
4828 | /* l4_per -> mcbsp4 */ | |
4829 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
4830 | .master = &omap44xx_l4_per_hwmod, | |
4831 | .slave = &omap44xx_mcbsp4_hwmod, | |
4832 | .clk = "l4_div_ck", | |
4833 | .addr = omap44xx_mcbsp4_addrs, | |
4834 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4835 | }; | |
4836 | ||
4837 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
4838 | { | |
4839 | .pa_start = 0x40132000, | |
4840 | .pa_end = 0x4013207f, | |
4841 | .flags = ADDR_TYPE_RT | |
4842 | }, | |
4843 | { } | |
4844 | }; | |
4845 | ||
4846 | /* l4_abe -> mcpdm */ | |
4847 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
4848 | .master = &omap44xx_l4_abe_hwmod, | |
4849 | .slave = &omap44xx_mcpdm_hwmod, | |
4850 | .clk = "ocp_abe_iclk", | |
4851 | .addr = omap44xx_mcpdm_addrs, | |
4852 | .user = OCP_USER_MPU, | |
4853 | }; | |
4854 | ||
4855 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
4856 | { | |
4857 | .pa_start = 0x49032000, | |
4858 | .pa_end = 0x4903207f, | |
4859 | .flags = ADDR_TYPE_RT | |
4860 | }, | |
4861 | { } | |
4862 | }; | |
4863 | ||
4864 | /* l4_abe -> mcpdm (dma) */ | |
4865 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
4866 | .master = &omap44xx_l4_abe_hwmod, | |
4867 | .slave = &omap44xx_mcpdm_hwmod, | |
4868 | .clk = "ocp_abe_iclk", | |
4869 | .addr = omap44xx_mcpdm_dma_addrs, | |
4870 | .user = OCP_USER_SDMA, | |
4871 | }; | |
4872 | ||
4873 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
4874 | { | |
4875 | .pa_start = 0x48098000, | |
4876 | .pa_end = 0x480981ff, | |
4877 | .flags = ADDR_TYPE_RT | |
4878 | }, | |
4879 | { } | |
4880 | }; | |
4881 | ||
4882 | /* l4_per -> mcspi1 */ | |
4883 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
4884 | .master = &omap44xx_l4_per_hwmod, | |
4885 | .slave = &omap44xx_mcspi1_hwmod, | |
4886 | .clk = "l4_div_ck", | |
4887 | .addr = omap44xx_mcspi1_addrs, | |
4888 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4889 | }; | |
4890 | ||
4891 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
4892 | { | |
4893 | .pa_start = 0x4809a000, | |
4894 | .pa_end = 0x4809a1ff, | |
4895 | .flags = ADDR_TYPE_RT | |
4896 | }, | |
4897 | { } | |
4898 | }; | |
4899 | ||
4900 | /* l4_per -> mcspi2 */ | |
4901 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
4902 | .master = &omap44xx_l4_per_hwmod, | |
4903 | .slave = &omap44xx_mcspi2_hwmod, | |
4904 | .clk = "l4_div_ck", | |
4905 | .addr = omap44xx_mcspi2_addrs, | |
4906 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4907 | }; | |
4908 | ||
4909 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
4910 | { | |
4911 | .pa_start = 0x480b8000, | |
4912 | .pa_end = 0x480b81ff, | |
4913 | .flags = ADDR_TYPE_RT | |
4914 | }, | |
4915 | { } | |
4916 | }; | |
4917 | ||
4918 | /* l4_per -> mcspi3 */ | |
4919 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
4920 | .master = &omap44xx_l4_per_hwmod, | |
4921 | .slave = &omap44xx_mcspi3_hwmod, | |
4922 | .clk = "l4_div_ck", | |
4923 | .addr = omap44xx_mcspi3_addrs, | |
4924 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4925 | }; | |
4926 | ||
4927 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
4928 | { | |
4929 | .pa_start = 0x480ba000, | |
4930 | .pa_end = 0x480ba1ff, | |
4931 | .flags = ADDR_TYPE_RT | |
4932 | }, | |
4933 | { } | |
4934 | }; | |
4935 | ||
4936 | /* l4_per -> mcspi4 */ | |
4937 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
4938 | .master = &omap44xx_l4_per_hwmod, | |
4939 | .slave = &omap44xx_mcspi4_hwmod, | |
4940 | .clk = "l4_div_ck", | |
4941 | .addr = omap44xx_mcspi4_addrs, | |
4942 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4943 | }; | |
4944 | ||
4945 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
4946 | { | |
4947 | .pa_start = 0x4809c000, | |
4948 | .pa_end = 0x4809c3ff, | |
4949 | .flags = ADDR_TYPE_RT | |
4950 | }, | |
4951 | { } | |
4952 | }; | |
4953 | ||
4954 | /* l4_per -> mmc1 */ | |
4955 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
4956 | .master = &omap44xx_l4_per_hwmod, | |
4957 | .slave = &omap44xx_mmc1_hwmod, | |
4958 | .clk = "l4_div_ck", | |
4959 | .addr = omap44xx_mmc1_addrs, | |
4960 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4961 | }; | |
4962 | ||
4963 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
4964 | { | |
4965 | .pa_start = 0x480b4000, | |
4966 | .pa_end = 0x480b43ff, | |
4967 | .flags = ADDR_TYPE_RT | |
4968 | }, | |
4969 | { } | |
4970 | }; | |
4971 | ||
4972 | /* l4_per -> mmc2 */ | |
4973 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
4974 | .master = &omap44xx_l4_per_hwmod, | |
4975 | .slave = &omap44xx_mmc2_hwmod, | |
4976 | .clk = "l4_div_ck", | |
4977 | .addr = omap44xx_mmc2_addrs, | |
4978 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4979 | }; | |
4980 | ||
4981 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
4982 | { | |
4983 | .pa_start = 0x480ad000, | |
4984 | .pa_end = 0x480ad3ff, | |
4985 | .flags = ADDR_TYPE_RT | |
4986 | }, | |
4987 | { } | |
4988 | }; | |
4989 | ||
4990 | /* l4_per -> mmc3 */ | |
4991 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
4992 | .master = &omap44xx_l4_per_hwmod, | |
4993 | .slave = &omap44xx_mmc3_hwmod, | |
4994 | .clk = "l4_div_ck", | |
4995 | .addr = omap44xx_mmc3_addrs, | |
4996 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4997 | }; | |
4998 | ||
4999 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
5000 | { | |
5001 | .pa_start = 0x480d1000, | |
5002 | .pa_end = 0x480d13ff, | |
5003 | .flags = ADDR_TYPE_RT | |
5004 | }, | |
5005 | { } | |
5006 | }; | |
5007 | ||
5008 | /* l4_per -> mmc4 */ | |
5009 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
5010 | .master = &omap44xx_l4_per_hwmod, | |
5011 | .slave = &omap44xx_mmc4_hwmod, | |
5012 | .clk = "l4_div_ck", | |
5013 | .addr = omap44xx_mmc4_addrs, | |
5014 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5015 | }; | |
5016 | ||
5017 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
5018 | { | |
5019 | .pa_start = 0x480d5000, | |
5020 | .pa_end = 0x480d53ff, | |
5021 | .flags = ADDR_TYPE_RT | |
5022 | }, | |
5023 | { } | |
5024 | }; | |
5025 | ||
5026 | /* l4_per -> mmc5 */ | |
5027 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
5028 | .master = &omap44xx_l4_per_hwmod, | |
5029 | .slave = &omap44xx_mmc5_hwmod, | |
5030 | .clk = "l4_div_ck", | |
5031 | .addr = omap44xx_mmc5_addrs, | |
5032 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5033 | }; | |
5034 | ||
e17f18c0 PW |
5035 | /* l3_main_2 -> ocmc_ram */ |
5036 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
5037 | .master = &omap44xx_l3_main_2_hwmod, | |
5038 | .slave = &omap44xx_ocmc_ram_hwmod, | |
5039 | .clk = "l3_div_ck", | |
5040 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5041 | }; | |
5042 | ||
0c668875 BC |
5043 | /* l4_cfg -> ocp2scp_usb_phy */ |
5044 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
5045 | .master = &omap44xx_l4_cfg_hwmod, | |
5046 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
5047 | .clk = "l4_div_ck", | |
5048 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5049 | }; | |
5050 | ||
42b9e387 PW |
5051 | /* l3_main_2 -> sl2if */ |
5052 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { | |
5053 | .master = &omap44xx_l3_main_2_hwmod, | |
5054 | .slave = &omap44xx_sl2if_hwmod, | |
5055 | .clk = "l3_div_ck", | |
5056 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5057 | }; | |
5058 | ||
1e3b5e59 BC |
5059 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
5060 | { | |
5061 | .pa_start = 0x4012c000, | |
5062 | .pa_end = 0x4012c3ff, | |
5063 | .flags = ADDR_TYPE_RT | |
5064 | }, | |
5065 | { } | |
5066 | }; | |
5067 | ||
5068 | /* l4_abe -> slimbus1 */ | |
5069 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
5070 | .master = &omap44xx_l4_abe_hwmod, | |
5071 | .slave = &omap44xx_slimbus1_hwmod, | |
5072 | .clk = "ocp_abe_iclk", | |
5073 | .addr = omap44xx_slimbus1_addrs, | |
5074 | .user = OCP_USER_MPU, | |
5075 | }; | |
5076 | ||
5077 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
5078 | { | |
5079 | .pa_start = 0x4902c000, | |
5080 | .pa_end = 0x4902c3ff, | |
5081 | .flags = ADDR_TYPE_RT | |
5082 | }, | |
5083 | { } | |
5084 | }; | |
5085 | ||
5086 | /* l4_abe -> slimbus1 (dma) */ | |
5087 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
5088 | .master = &omap44xx_l4_abe_hwmod, | |
5089 | .slave = &omap44xx_slimbus1_hwmod, | |
5090 | .clk = "ocp_abe_iclk", | |
5091 | .addr = omap44xx_slimbus1_dma_addrs, | |
5092 | .user = OCP_USER_SDMA, | |
5093 | }; | |
5094 | ||
5095 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
5096 | { | |
5097 | .pa_start = 0x48076000, | |
5098 | .pa_end = 0x480763ff, | |
5099 | .flags = ADDR_TYPE_RT | |
5100 | }, | |
5101 | { } | |
5102 | }; | |
5103 | ||
5104 | /* l4_per -> slimbus2 */ | |
5105 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
5106 | .master = &omap44xx_l4_per_hwmod, | |
5107 | .slave = &omap44xx_slimbus2_hwmod, | |
5108 | .clk = "l4_div_ck", | |
5109 | .addr = omap44xx_slimbus2_addrs, | |
5110 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5111 | }; | |
5112 | ||
844a3b63 PW |
5113 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
5114 | { | |
5115 | .pa_start = 0x4a0dd000, | |
5116 | .pa_end = 0x4a0dd03f, | |
5117 | .flags = ADDR_TYPE_RT | |
5118 | }, | |
5119 | { } | |
5120 | }; | |
5121 | ||
5122 | /* l4_cfg -> smartreflex_core */ | |
5123 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
5124 | .master = &omap44xx_l4_cfg_hwmod, | |
5125 | .slave = &omap44xx_smartreflex_core_hwmod, | |
5126 | .clk = "l4_div_ck", | |
5127 | .addr = omap44xx_smartreflex_core_addrs, | |
5128 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5129 | }; | |
5130 | ||
5131 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
5132 | { | |
5133 | .pa_start = 0x4a0db000, | |
5134 | .pa_end = 0x4a0db03f, | |
5135 | .flags = ADDR_TYPE_RT | |
5136 | }, | |
5137 | { } | |
5138 | }; | |
5139 | ||
5140 | /* l4_cfg -> smartreflex_iva */ | |
5141 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
5142 | .master = &omap44xx_l4_cfg_hwmod, | |
5143 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
5144 | .clk = "l4_div_ck", | |
5145 | .addr = omap44xx_smartreflex_iva_addrs, | |
5146 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5147 | }; | |
5148 | ||
5149 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
5150 | { | |
5151 | .pa_start = 0x4a0d9000, | |
5152 | .pa_end = 0x4a0d903f, | |
5153 | .flags = ADDR_TYPE_RT | |
5154 | }, | |
5155 | { } | |
5156 | }; | |
5157 | ||
5158 | /* l4_cfg -> smartreflex_mpu */ | |
5159 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
5160 | .master = &omap44xx_l4_cfg_hwmod, | |
5161 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
5162 | .clk = "l4_div_ck", | |
5163 | .addr = omap44xx_smartreflex_mpu_addrs, | |
5164 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5165 | }; | |
5166 | ||
5167 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
5168 | { | |
5169 | .pa_start = 0x4a0f6000, | |
5170 | .pa_end = 0x4a0f6fff, | |
5171 | .flags = ADDR_TYPE_RT | |
5172 | }, | |
5173 | { } | |
5174 | }; | |
5175 | ||
5176 | /* l4_cfg -> spinlock */ | |
5177 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
5178 | .master = &omap44xx_l4_cfg_hwmod, | |
5179 | .slave = &omap44xx_spinlock_hwmod, | |
5180 | .clk = "l4_div_ck", | |
5181 | .addr = omap44xx_spinlock_addrs, | |
5182 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5183 | }; | |
5184 | ||
5185 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
5186 | { | |
5187 | .pa_start = 0x4a318000, | |
5188 | .pa_end = 0x4a31807f, | |
5189 | .flags = ADDR_TYPE_RT | |
5190 | }, | |
5191 | { } | |
5192 | }; | |
5193 | ||
5194 | /* l4_wkup -> timer1 */ | |
5195 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
5196 | .master = &omap44xx_l4_wkup_hwmod, | |
5197 | .slave = &omap44xx_timer1_hwmod, | |
5198 | .clk = "l4_wkup_clk_mux_ck", | |
5199 | .addr = omap44xx_timer1_addrs, | |
5200 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5201 | }; | |
5202 | ||
5203 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
5204 | { | |
5205 | .pa_start = 0x48032000, | |
5206 | .pa_end = 0x4803207f, | |
5207 | .flags = ADDR_TYPE_RT | |
5208 | }, | |
5209 | { } | |
5210 | }; | |
5211 | ||
5212 | /* l4_per -> timer2 */ | |
5213 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
5214 | .master = &omap44xx_l4_per_hwmod, | |
5215 | .slave = &omap44xx_timer2_hwmod, | |
5216 | .clk = "l4_div_ck", | |
5217 | .addr = omap44xx_timer2_addrs, | |
5218 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5219 | }; | |
5220 | ||
5221 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
5222 | { | |
5223 | .pa_start = 0x48034000, | |
5224 | .pa_end = 0x4803407f, | |
5225 | .flags = ADDR_TYPE_RT | |
5226 | }, | |
5227 | { } | |
5228 | }; | |
5229 | ||
5230 | /* l4_per -> timer3 */ | |
5231 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
5232 | .master = &omap44xx_l4_per_hwmod, | |
5233 | .slave = &omap44xx_timer3_hwmod, | |
5234 | .clk = "l4_div_ck", | |
5235 | .addr = omap44xx_timer3_addrs, | |
5236 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5237 | }; | |
5238 | ||
5239 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
5240 | { | |
5241 | .pa_start = 0x48036000, | |
5242 | .pa_end = 0x4803607f, | |
5243 | .flags = ADDR_TYPE_RT | |
5244 | }, | |
5245 | { } | |
5246 | }; | |
5247 | ||
5248 | /* l4_per -> timer4 */ | |
5249 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
5250 | .master = &omap44xx_l4_per_hwmod, | |
5251 | .slave = &omap44xx_timer4_hwmod, | |
5252 | .clk = "l4_div_ck", | |
5253 | .addr = omap44xx_timer4_addrs, | |
5254 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5255 | }; | |
5256 | ||
5257 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
5258 | { | |
5259 | .pa_start = 0x40138000, | |
5260 | .pa_end = 0x4013807f, | |
5261 | .flags = ADDR_TYPE_RT | |
5262 | }, | |
5263 | { } | |
5264 | }; | |
5265 | ||
5266 | /* l4_abe -> timer5 */ | |
5267 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
5268 | .master = &omap44xx_l4_abe_hwmod, | |
5269 | .slave = &omap44xx_timer5_hwmod, | |
5270 | .clk = "ocp_abe_iclk", | |
5271 | .addr = omap44xx_timer5_addrs, | |
5272 | .user = OCP_USER_MPU, | |
5273 | }; | |
5274 | ||
5275 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
5276 | { | |
5277 | .pa_start = 0x49038000, | |
5278 | .pa_end = 0x4903807f, | |
5279 | .flags = ADDR_TYPE_RT | |
5280 | }, | |
5281 | { } | |
5282 | }; | |
5283 | ||
5284 | /* l4_abe -> timer5 (dma) */ | |
5285 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
5286 | .master = &omap44xx_l4_abe_hwmod, | |
5287 | .slave = &omap44xx_timer5_hwmod, | |
5288 | .clk = "ocp_abe_iclk", | |
5289 | .addr = omap44xx_timer5_dma_addrs, | |
5290 | .user = OCP_USER_SDMA, | |
5291 | }; | |
5292 | ||
5293 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
5294 | { | |
5295 | .pa_start = 0x4013a000, | |
5296 | .pa_end = 0x4013a07f, | |
5297 | .flags = ADDR_TYPE_RT | |
5298 | }, | |
5299 | { } | |
5300 | }; | |
5301 | ||
5302 | /* l4_abe -> timer6 */ | |
5303 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
5304 | .master = &omap44xx_l4_abe_hwmod, | |
5305 | .slave = &omap44xx_timer6_hwmod, | |
5306 | .clk = "ocp_abe_iclk", | |
5307 | .addr = omap44xx_timer6_addrs, | |
5308 | .user = OCP_USER_MPU, | |
5309 | }; | |
5310 | ||
5311 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
5312 | { | |
5313 | .pa_start = 0x4903a000, | |
5314 | .pa_end = 0x4903a07f, | |
5315 | .flags = ADDR_TYPE_RT | |
5316 | }, | |
5317 | { } | |
5318 | }; | |
5319 | ||
5320 | /* l4_abe -> timer6 (dma) */ | |
5321 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
5322 | .master = &omap44xx_l4_abe_hwmod, | |
5323 | .slave = &omap44xx_timer6_hwmod, | |
5324 | .clk = "ocp_abe_iclk", | |
5325 | .addr = omap44xx_timer6_dma_addrs, | |
5326 | .user = OCP_USER_SDMA, | |
5327 | }; | |
5328 | ||
5329 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
5330 | { | |
5331 | .pa_start = 0x4013c000, | |
5332 | .pa_end = 0x4013c07f, | |
5333 | .flags = ADDR_TYPE_RT | |
5334 | }, | |
5335 | { } | |
5336 | }; | |
5337 | ||
5338 | /* l4_abe -> timer7 */ | |
5339 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
5340 | .master = &omap44xx_l4_abe_hwmod, | |
5341 | .slave = &omap44xx_timer7_hwmod, | |
5342 | .clk = "ocp_abe_iclk", | |
5343 | .addr = omap44xx_timer7_addrs, | |
5344 | .user = OCP_USER_MPU, | |
5345 | }; | |
5346 | ||
5347 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
5348 | { | |
5349 | .pa_start = 0x4903c000, | |
5350 | .pa_end = 0x4903c07f, | |
5351 | .flags = ADDR_TYPE_RT | |
5352 | }, | |
5353 | { } | |
5354 | }; | |
5355 | ||
5356 | /* l4_abe -> timer7 (dma) */ | |
5357 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
5358 | .master = &omap44xx_l4_abe_hwmod, | |
5359 | .slave = &omap44xx_timer7_hwmod, | |
5360 | .clk = "ocp_abe_iclk", | |
5361 | .addr = omap44xx_timer7_dma_addrs, | |
5362 | .user = OCP_USER_SDMA, | |
5363 | }; | |
5364 | ||
5365 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
5366 | { | |
5367 | .pa_start = 0x4013e000, | |
5368 | .pa_end = 0x4013e07f, | |
5369 | .flags = ADDR_TYPE_RT | |
5370 | }, | |
5371 | { } | |
5372 | }; | |
5373 | ||
5374 | /* l4_abe -> timer8 */ | |
5375 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
5376 | .master = &omap44xx_l4_abe_hwmod, | |
5377 | .slave = &omap44xx_timer8_hwmod, | |
5378 | .clk = "ocp_abe_iclk", | |
5379 | .addr = omap44xx_timer8_addrs, | |
5380 | .user = OCP_USER_MPU, | |
5381 | }; | |
5382 | ||
5383 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
5384 | { | |
5385 | .pa_start = 0x4903e000, | |
5386 | .pa_end = 0x4903e07f, | |
5387 | .flags = ADDR_TYPE_RT | |
5388 | }, | |
5389 | { } | |
5390 | }; | |
5391 | ||
5392 | /* l4_abe -> timer8 (dma) */ | |
5393 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
5394 | .master = &omap44xx_l4_abe_hwmod, | |
5395 | .slave = &omap44xx_timer8_hwmod, | |
5396 | .clk = "ocp_abe_iclk", | |
5397 | .addr = omap44xx_timer8_dma_addrs, | |
5398 | .user = OCP_USER_SDMA, | |
5399 | }; | |
5400 | ||
5401 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
5402 | { | |
5403 | .pa_start = 0x4803e000, | |
5404 | .pa_end = 0x4803e07f, | |
5405 | .flags = ADDR_TYPE_RT | |
5406 | }, | |
5407 | { } | |
5408 | }; | |
5409 | ||
5410 | /* l4_per -> timer9 */ | |
5411 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
5412 | .master = &omap44xx_l4_per_hwmod, | |
5413 | .slave = &omap44xx_timer9_hwmod, | |
5414 | .clk = "l4_div_ck", | |
5415 | .addr = omap44xx_timer9_addrs, | |
5416 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5417 | }; | |
5418 | ||
5419 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
5420 | { | |
5421 | .pa_start = 0x48086000, | |
5422 | .pa_end = 0x4808607f, | |
5423 | .flags = ADDR_TYPE_RT | |
5424 | }, | |
5425 | { } | |
5426 | }; | |
5427 | ||
5428 | /* l4_per -> timer10 */ | |
5429 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
5430 | .master = &omap44xx_l4_per_hwmod, | |
5431 | .slave = &omap44xx_timer10_hwmod, | |
5432 | .clk = "l4_div_ck", | |
5433 | .addr = omap44xx_timer10_addrs, | |
5434 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5435 | }; | |
5436 | ||
5437 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
5438 | { | |
5439 | .pa_start = 0x48088000, | |
5440 | .pa_end = 0x4808807f, | |
5441 | .flags = ADDR_TYPE_RT | |
5442 | }, | |
5443 | { } | |
5444 | }; | |
5445 | ||
5446 | /* l4_per -> timer11 */ | |
5447 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
5448 | .master = &omap44xx_l4_per_hwmod, | |
5449 | .slave = &omap44xx_timer11_hwmod, | |
5450 | .clk = "l4_div_ck", | |
5451 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
5452 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5453 | }; | |
5454 | ||
844a3b63 PW |
5455 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
5456 | { | |
5457 | .pa_start = 0x4806a000, | |
5458 | .pa_end = 0x4806a0ff, | |
5459 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5460 | }, |
844a3b63 PW |
5461 | { } |
5462 | }; | |
af88fa9a | 5463 | |
844a3b63 PW |
5464 | /* l4_per -> uart1 */ |
5465 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
5466 | .master = &omap44xx_l4_per_hwmod, | |
5467 | .slave = &omap44xx_uart1_hwmod, | |
5468 | .clk = "l4_div_ck", | |
5469 | .addr = omap44xx_uart1_addrs, | |
5470 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5471 | }; | |
af88fa9a | 5472 | |
844a3b63 PW |
5473 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
5474 | { | |
5475 | .pa_start = 0x4806c000, | |
5476 | .pa_end = 0x4806c0ff, | |
5477 | .flags = ADDR_TYPE_RT | |
5478 | }, | |
5479 | { } | |
5480 | }; | |
af88fa9a | 5481 | |
844a3b63 PW |
5482 | /* l4_per -> uart2 */ |
5483 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
5484 | .master = &omap44xx_l4_per_hwmod, | |
5485 | .slave = &omap44xx_uart2_hwmod, | |
5486 | .clk = "l4_div_ck", | |
5487 | .addr = omap44xx_uart2_addrs, | |
5488 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5489 | }; | |
af88fa9a | 5490 | |
844a3b63 PW |
5491 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
5492 | { | |
5493 | .pa_start = 0x48020000, | |
5494 | .pa_end = 0x480200ff, | |
5495 | .flags = ADDR_TYPE_RT | |
5496 | }, | |
5497 | { } | |
af88fa9a BC |
5498 | }; |
5499 | ||
844a3b63 PW |
5500 | /* l4_per -> uart3 */ |
5501 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
5502 | .master = &omap44xx_l4_per_hwmod, | |
5503 | .slave = &omap44xx_uart3_hwmod, | |
5504 | .clk = "l4_div_ck", | |
5505 | .addr = omap44xx_uart3_addrs, | |
5506 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5507 | }; |
5508 | ||
844a3b63 PW |
5509 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
5510 | { | |
5511 | .pa_start = 0x4806e000, | |
5512 | .pa_end = 0x4806e0ff, | |
5513 | .flags = ADDR_TYPE_RT | |
5514 | }, | |
5515 | { } | |
af88fa9a BC |
5516 | }; |
5517 | ||
844a3b63 PW |
5518 | /* l4_per -> uart4 */ |
5519 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
5520 | .master = &omap44xx_l4_per_hwmod, | |
5521 | .slave = &omap44xx_uart4_hwmod, | |
5522 | .clk = "l4_div_ck", | |
5523 | .addr = omap44xx_uart4_addrs, | |
5524 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5525 | }; | |
5526 | ||
0c668875 BC |
5527 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { |
5528 | { | |
5529 | .pa_start = 0x4a0a9000, | |
5530 | .pa_end = 0x4a0a93ff, | |
5531 | .flags = ADDR_TYPE_RT | |
5532 | }, | |
5533 | { } | |
5534 | }; | |
5535 | ||
5536 | /* l4_cfg -> usb_host_fs */ | |
5537 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = { | |
5538 | .master = &omap44xx_l4_cfg_hwmod, | |
5539 | .slave = &omap44xx_usb_host_fs_hwmod, | |
5540 | .clk = "l4_div_ck", | |
5541 | .addr = omap44xx_usb_host_fs_addrs, | |
5542 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5543 | }; | |
5544 | ||
844a3b63 PW |
5545 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
5546 | { | |
5547 | .name = "uhh", | |
5548 | .pa_start = 0x4a064000, | |
5549 | .pa_end = 0x4a0647ff, | |
5550 | .flags = ADDR_TYPE_RT | |
5551 | }, | |
5552 | { | |
5553 | .name = "ohci", | |
5554 | .pa_start = 0x4a064800, | |
5555 | .pa_end = 0x4a064bff, | |
5556 | }, | |
5557 | { | |
5558 | .name = "ehci", | |
5559 | .pa_start = 0x4a064c00, | |
5560 | .pa_end = 0x4a064fff, | |
5561 | }, | |
5562 | {} | |
5563 | }; | |
5564 | ||
5565 | /* l4_cfg -> usb_host_hs */ | |
5566 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
5567 | .master = &omap44xx_l4_cfg_hwmod, | |
5568 | .slave = &omap44xx_usb_host_hs_hwmod, | |
5569 | .clk = "l4_div_ck", | |
5570 | .addr = omap44xx_usb_host_hs_addrs, | |
5571 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5572 | }; | |
5573 | ||
5574 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
5575 | { | |
5576 | .pa_start = 0x4a0ab000, | |
5577 | .pa_end = 0x4a0ab003, | |
5578 | .flags = ADDR_TYPE_RT | |
5579 | }, | |
5580 | { } | |
5581 | }; | |
5582 | ||
5583 | /* l4_cfg -> usb_otg_hs */ | |
5584 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
5585 | .master = &omap44xx_l4_cfg_hwmod, | |
5586 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
5587 | .clk = "l4_div_ck", | |
5588 | .addr = omap44xx_usb_otg_hs_addrs, | |
5589 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5590 | }; |
5591 | ||
5592 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
5593 | { | |
5594 | .name = "tll", | |
5595 | .pa_start = 0x4a062000, | |
5596 | .pa_end = 0x4a063fff, | |
5597 | .flags = ADDR_TYPE_RT | |
5598 | }, | |
5599 | {} | |
5600 | }; | |
5601 | ||
844a3b63 | 5602 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
5603 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
5604 | .master = &omap44xx_l4_cfg_hwmod, | |
5605 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
5606 | .clk = "l4_div_ck", | |
5607 | .addr = omap44xx_usb_tll_hs_addrs, | |
5608 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5609 | }; | |
5610 | ||
844a3b63 PW |
5611 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
5612 | { | |
5613 | .pa_start = 0x4a314000, | |
5614 | .pa_end = 0x4a31407f, | |
5615 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5616 | }, |
844a3b63 PW |
5617 | { } |
5618 | }; | |
5619 | ||
5620 | /* l4_wkup -> wd_timer2 */ | |
5621 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
5622 | .master = &omap44xx_l4_wkup_hwmod, | |
5623 | .slave = &omap44xx_wd_timer2_hwmod, | |
5624 | .clk = "l4_wkup_clk_mux_ck", | |
5625 | .addr = omap44xx_wd_timer2_addrs, | |
5626 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5627 | }; | |
5628 | ||
5629 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
5630 | { | |
5631 | .pa_start = 0x40130000, | |
5632 | .pa_end = 0x4013007f, | |
5633 | .flags = ADDR_TYPE_RT | |
5634 | }, | |
5635 | { } | |
5636 | }; | |
5637 | ||
5638 | /* l4_abe -> wd_timer3 */ | |
5639 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
5640 | .master = &omap44xx_l4_abe_hwmod, | |
5641 | .slave = &omap44xx_wd_timer3_hwmod, | |
5642 | .clk = "ocp_abe_iclk", | |
5643 | .addr = omap44xx_wd_timer3_addrs, | |
5644 | .user = OCP_USER_MPU, | |
5645 | }; | |
5646 | ||
5647 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
5648 | { | |
5649 | .pa_start = 0x49030000, | |
5650 | .pa_end = 0x4903007f, | |
5651 | .flags = ADDR_TYPE_RT | |
5652 | }, | |
5653 | { } | |
5654 | }; | |
5655 | ||
5656 | /* l4_abe -> wd_timer3 (dma) */ | |
5657 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
5658 | .master = &omap44xx_l4_abe_hwmod, | |
5659 | .slave = &omap44xx_wd_timer3_hwmod, | |
5660 | .clk = "ocp_abe_iclk", | |
5661 | .addr = omap44xx_wd_timer3_dma_addrs, | |
5662 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
5663 | }; |
5664 | ||
0a78c5c5 | 5665 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
42b9e387 PW |
5666 | &omap44xx_c2c__c2c_target_fw, |
5667 | &omap44xx_l4_cfg__c2c_target_fw, | |
0a78c5c5 PW |
5668 | &omap44xx_l3_main_1__dmm, |
5669 | &omap44xx_mpu__dmm, | |
42b9e387 | 5670 | &omap44xx_c2c__emif_fw, |
0a78c5c5 PW |
5671 | &omap44xx_dmm__emif_fw, |
5672 | &omap44xx_l4_cfg__emif_fw, | |
5673 | &omap44xx_iva__l3_instr, | |
5674 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 5675 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
5676 | &omap44xx_dsp__l3_main_1, |
5677 | &omap44xx_dss__l3_main_1, | |
5678 | &omap44xx_l3_main_2__l3_main_1, | |
5679 | &omap44xx_l4_cfg__l3_main_1, | |
5680 | &omap44xx_mmc1__l3_main_1, | |
5681 | &omap44xx_mmc2__l3_main_1, | |
5682 | &omap44xx_mpu__l3_main_1, | |
42b9e387 | 5683 | &omap44xx_c2c_target_fw__l3_main_2, |
0a78c5c5 | 5684 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 5685 | &omap44xx_fdif__l3_main_2, |
9def390e | 5686 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
5687 | &omap44xx_hsi__l3_main_2, |
5688 | &omap44xx_ipu__l3_main_2, | |
5689 | &omap44xx_iss__l3_main_2, | |
5690 | &omap44xx_iva__l3_main_2, | |
5691 | &omap44xx_l3_main_1__l3_main_2, | |
5692 | &omap44xx_l4_cfg__l3_main_2, | |
0c668875 | 5693 | &omap44xx_usb_host_fs__l3_main_2, |
0a78c5c5 PW |
5694 | &omap44xx_usb_host_hs__l3_main_2, |
5695 | &omap44xx_usb_otg_hs__l3_main_2, | |
5696 | &omap44xx_l3_main_1__l3_main_3, | |
5697 | &omap44xx_l3_main_2__l3_main_3, | |
5698 | &omap44xx_l4_cfg__l3_main_3, | |
5699 | &omap44xx_aess__l4_abe, | |
5700 | &omap44xx_dsp__l4_abe, | |
5701 | &omap44xx_l3_main_1__l4_abe, | |
5702 | &omap44xx_mpu__l4_abe, | |
5703 | &omap44xx_l3_main_1__l4_cfg, | |
5704 | &omap44xx_l3_main_2__l4_per, | |
5705 | &omap44xx_l4_cfg__l4_wkup, | |
5706 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 5707 | &omap44xx_l4_cfg__ocp_wp_noc, |
0a78c5c5 PW |
5708 | &omap44xx_l4_abe__aess, |
5709 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 5710 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 PW |
5711 | &omap44xx_l4_wkup__counter_32k, |
5712 | &omap44xx_l4_cfg__dma_system, | |
5713 | &omap44xx_l4_abe__dmic, | |
5714 | &omap44xx_l4_abe__dmic_dma, | |
5715 | &omap44xx_dsp__iva, | |
42b9e387 | 5716 | &omap44xx_dsp__sl2if, |
0a78c5c5 PW |
5717 | &omap44xx_l4_cfg__dsp, |
5718 | &omap44xx_l3_main_2__dss, | |
5719 | &omap44xx_l4_per__dss, | |
5720 | &omap44xx_l3_main_2__dss_dispc, | |
5721 | &omap44xx_l4_per__dss_dispc, | |
5722 | &omap44xx_l3_main_2__dss_dsi1, | |
5723 | &omap44xx_l4_per__dss_dsi1, | |
5724 | &omap44xx_l3_main_2__dss_dsi2, | |
5725 | &omap44xx_l4_per__dss_dsi2, | |
5726 | &omap44xx_l3_main_2__dss_hdmi, | |
5727 | &omap44xx_l4_per__dss_hdmi, | |
5728 | &omap44xx_l3_main_2__dss_rfbi, | |
5729 | &omap44xx_l4_per__dss_rfbi, | |
5730 | &omap44xx_l3_main_2__dss_venc, | |
5731 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 5732 | &omap44xx_l4_per__elm, |
bf30f950 PW |
5733 | &omap44xx_emif_fw__emif1, |
5734 | &omap44xx_emif_fw__emif2, | |
b050f688 | 5735 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
5736 | &omap44xx_l4_wkup__gpio1, |
5737 | &omap44xx_l4_per__gpio2, | |
5738 | &omap44xx_l4_per__gpio3, | |
5739 | &omap44xx_l4_per__gpio4, | |
5740 | &omap44xx_l4_per__gpio5, | |
5741 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 5742 | &omap44xx_l3_main_2__gpmc, |
9def390e | 5743 | &omap44xx_l3_main_2__gpu, |
a091c08e | 5744 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
5745 | &omap44xx_l4_cfg__hsi, |
5746 | &omap44xx_l4_per__i2c1, | |
5747 | &omap44xx_l4_per__i2c2, | |
5748 | &omap44xx_l4_per__i2c3, | |
5749 | &omap44xx_l4_per__i2c4, | |
5750 | &omap44xx_l3_main_2__ipu, | |
5751 | &omap44xx_l3_main_2__iss, | |
42b9e387 | 5752 | &omap44xx_iva__sl2if, |
0a78c5c5 PW |
5753 | &omap44xx_l3_main_2__iva, |
5754 | &omap44xx_l4_wkup__kbd, | |
5755 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
5756 | &omap44xx_l4_abe__mcasp, |
5757 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 PW |
5758 | &omap44xx_l4_abe__mcbsp1, |
5759 | &omap44xx_l4_abe__mcbsp1_dma, | |
5760 | &omap44xx_l4_abe__mcbsp2, | |
5761 | &omap44xx_l4_abe__mcbsp2_dma, | |
5762 | &omap44xx_l4_abe__mcbsp3, | |
5763 | &omap44xx_l4_abe__mcbsp3_dma, | |
5764 | &omap44xx_l4_per__mcbsp4, | |
5765 | &omap44xx_l4_abe__mcpdm, | |
5766 | &omap44xx_l4_abe__mcpdm_dma, | |
5767 | &omap44xx_l4_per__mcspi1, | |
5768 | &omap44xx_l4_per__mcspi2, | |
5769 | &omap44xx_l4_per__mcspi3, | |
5770 | &omap44xx_l4_per__mcspi4, | |
5771 | &omap44xx_l4_per__mmc1, | |
5772 | &omap44xx_l4_per__mmc2, | |
5773 | &omap44xx_l4_per__mmc3, | |
5774 | &omap44xx_l4_per__mmc4, | |
5775 | &omap44xx_l4_per__mmc5, | |
e17f18c0 | 5776 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 5777 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
42b9e387 | 5778 | &omap44xx_l3_main_2__sl2if, |
1e3b5e59 BC |
5779 | &omap44xx_l4_abe__slimbus1, |
5780 | &omap44xx_l4_abe__slimbus1_dma, | |
5781 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
5782 | &omap44xx_l4_cfg__smartreflex_core, |
5783 | &omap44xx_l4_cfg__smartreflex_iva, | |
5784 | &omap44xx_l4_cfg__smartreflex_mpu, | |
5785 | &omap44xx_l4_cfg__spinlock, | |
5786 | &omap44xx_l4_wkup__timer1, | |
5787 | &omap44xx_l4_per__timer2, | |
5788 | &omap44xx_l4_per__timer3, | |
5789 | &omap44xx_l4_per__timer4, | |
5790 | &omap44xx_l4_abe__timer5, | |
5791 | &omap44xx_l4_abe__timer5_dma, | |
5792 | &omap44xx_l4_abe__timer6, | |
5793 | &omap44xx_l4_abe__timer6_dma, | |
5794 | &omap44xx_l4_abe__timer7, | |
5795 | &omap44xx_l4_abe__timer7_dma, | |
5796 | &omap44xx_l4_abe__timer8, | |
5797 | &omap44xx_l4_abe__timer8_dma, | |
5798 | &omap44xx_l4_per__timer9, | |
5799 | &omap44xx_l4_per__timer10, | |
5800 | &omap44xx_l4_per__timer11, | |
5801 | &omap44xx_l4_per__uart1, | |
5802 | &omap44xx_l4_per__uart2, | |
5803 | &omap44xx_l4_per__uart3, | |
5804 | &omap44xx_l4_per__uart4, | |
0c668875 | 5805 | &omap44xx_l4_cfg__usb_host_fs, |
0a78c5c5 PW |
5806 | &omap44xx_l4_cfg__usb_host_hs, |
5807 | &omap44xx_l4_cfg__usb_otg_hs, | |
5808 | &omap44xx_l4_cfg__usb_tll_hs, | |
5809 | &omap44xx_l4_wkup__wd_timer2, | |
5810 | &omap44xx_l4_abe__wd_timer3, | |
5811 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
5812 | NULL, |
5813 | }; | |
5814 | ||
5815 | int __init omap44xx_hwmod_init(void) | |
5816 | { | |
0a78c5c5 | 5817 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
5818 | } |
5819 |