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OMAP4: prm: Remove deprecated functions
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55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
d63bd74f 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
55d2cb08
BC		 5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
6d3c55fd 25#include <plat/i2c.h>
9780a9cf 26#include <plat/gpio.h>
531ce0d5 27#include <plat/dma.h>
905a74d9 28#include <plat/mcspi.h>
cb7e9ded 29#include <plat/mcbsp.h>
6ab8946f 30#include <plat/mmc.h>
4d4441a6 31#include <plat/i2c.h>
55d2cb08
BC		 32
33#include "omap_hwmod_common_data.h"
34
d198b514
PW		 35#include "cm1_44xx.h"
36#include "cm2_44xx.h"
37#include "prm44xx.h"
55d2cb08 38#include "prm-regbits-44xx.h"
ff2516fb 39#include "wd_timer.h"
55d2cb08
BC		 40
41/* Base offset for all OMAP4 interrupts external to MPUSS */
42#define OMAP44XX_IRQ_GIC_START 32
43
44/* Base offset for all OMAP4 dma requests */
45#define OMAP44XX_DMA_REQ_START 1
46
47/* Backward references (IPs with Bus Master capability) */
407a6888 48static struct omap_hwmod omap44xx_aess_hwmod;
531ce0d5 49static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 50static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 51static struct omap_hwmod omap44xx_dsp_hwmod;
d63bd74f 52static struct omap_hwmod omap44xx_dss_hwmod;
55d2cb08 53static struct omap_hwmod omap44xx_emif_fw_hwmod;
407a6888
BC		 54static struct omap_hwmod omap44xx_hsi_hwmod;
55static struct omap_hwmod omap44xx_ipu_hwmod;
56static struct omap_hwmod omap44xx_iss_hwmod;
8f25bdc5 57static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 58static struct omap_hwmod omap44xx_l3_instr_hwmod;
59static struct omap_hwmod omap44xx_l3_main_1_hwmod;
60static struct omap_hwmod omap44xx_l3_main_2_hwmod;
61static struct omap_hwmod omap44xx_l3_main_3_hwmod;
62static struct omap_hwmod omap44xx_l4_abe_hwmod;
63static struct omap_hwmod omap44xx_l4_cfg_hwmod;
64static struct omap_hwmod omap44xx_l4_per_hwmod;
65static struct omap_hwmod omap44xx_l4_wkup_hwmod;
407a6888
BC		 66static struct omap_hwmod omap44xx_mmc1_hwmod;
67static struct omap_hwmod omap44xx_mmc2_hwmod;
55d2cb08
BC		 68static struct omap_hwmod omap44xx_mpu_hwmod;
69static struct omap_hwmod omap44xx_mpu_private_hwmod;
5844c4ea 70static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
55d2cb08
BC		 71
72/*
73 * Interconnects omap_hwmod structures
74 * hwmods that compose the global OMAP interconnect
75 */
76
77/*
78 * 'dmm' class
79 * instance(s): dmm
80 */
81static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 82 .name = "dmm",
55d2cb08
BC		 83};
84
7e69ed97
BC		 85/* dmm */
86static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
87 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
88 { .irq = -1 }
89};
90
55d2cb08
BC		 91/* l3_main_1 -> dmm */
92static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
93 .master = &omap44xx_l3_main_1_hwmod,
94 .slave = &omap44xx_dmm_hwmod,
95 .clk = "l3_div_ck",
659fa822
BC		 96 .user = OCP_USER_SDMA,
97};
98
99static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
100 {
101 .pa_start = 0x4e000000,
102 .pa_end = 0x4e0007ff,
103 .flags = ADDR_TYPE_RT
104 },
78183f3f 105 { }
55d2cb08
BC		 106};
107
108/* mpu -> dmm */
109static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
110 .master = &omap44xx_mpu_hwmod,
111 .slave = &omap44xx_dmm_hwmod,
112 .clk = "l3_div_ck",
659fa822 113 .addr = omap44xx_dmm_addrs,
659fa822 114 .user = OCP_USER_MPU,
55d2cb08
BC		 115};
116
117/* dmm slave ports */
118static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
119 &omap44xx_l3_main_1__dmm,
120 &omap44xx_mpu__dmm,
121};
122
55d2cb08
BC		 123static struct omap_hwmod omap44xx_dmm_hwmod = {
124 .name = "dmm",
125 .class = &omap44xx_dmm_hwmod_class,
a5322c6f 126 .clkdm_name = "l3_emif_clkdm",
d0f0631d
BC		 127 .prcm = {
128 .omap4 = {
129 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
130 },
131 },
55d2cb08
BC		 132 .slaves = omap44xx_dmm_slaves,
133 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
a5322c6f 134 .mpu_irqs = omap44xx_dmm_irqs,
55d2cb08
BC		 135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
136};
137
138/*
139 * 'emif_fw' class
140 * instance(s): emif_fw
141 */
142static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 143 .name = "emif_fw",
55d2cb08
BC		 144};
145
7e69ed97 146/* emif_fw */
55d2cb08
BC		 147/* dmm -> emif_fw */
148static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
149 .master = &omap44xx_dmm_hwmod,
150 .slave = &omap44xx_emif_fw_hwmod,
151 .clk = "l3_div_ck",
152 .user = OCP_USER_MPU | OCP_USER_SDMA,
153};
154
659fa822
BC		 155static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
156 {
157 .pa_start = 0x4a20c000,
158 .pa_end = 0x4a20c0ff,
159 .flags = ADDR_TYPE_RT
160 },
78183f3f 161 { }
659fa822
BC		 162};
163
55d2cb08
BC		 164/* l4_cfg -> emif_fw */
165static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
166 .master = &omap44xx_l4_cfg_hwmod,
167 .slave = &omap44xx_emif_fw_hwmod,
168 .clk = "l4_div_ck",
659fa822 169 .addr = omap44xx_emif_fw_addrs,
659fa822 170 .user = OCP_USER_MPU,
55d2cb08
BC		 171};
172
173/* emif_fw slave ports */
174static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
175 &omap44xx_dmm__emif_fw,
176 &omap44xx_l4_cfg__emif_fw,
177};
178
179static struct omap_hwmod omap44xx_emif_fw_hwmod = {
180 .name = "emif_fw",
181 .class = &omap44xx_emif_fw_hwmod_class,
a5322c6f 182 .clkdm_name = "l3_emif_clkdm",
d0f0631d
BC		 183 .prcm = {
184 .omap4 = {
185 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
186 },
187 },
55d2cb08
BC		 188 .slaves = omap44xx_emif_fw_slaves,
189 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
191};
192
193/*
194 * 'l3' class
195 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
196 */
197static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 198 .name = "l3",
55d2cb08
BC		 199};
200
7e69ed97 201/* l3_instr */
8f25bdc5
BC		 202/* iva -> l3_instr */
203static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
204 .master = &omap44xx_iva_hwmod,
205 .slave = &omap44xx_l3_instr_hwmod,
206 .clk = "l3_div_ck",
207 .user = OCP_USER_MPU | OCP_USER_SDMA,
208};
209
55d2cb08
BC		 210/* l3_main_3 -> l3_instr */
211static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
212 .master = &omap44xx_l3_main_3_hwmod,
213 .slave = &omap44xx_l3_instr_hwmod,
214 .clk = "l3_div_ck",
215 .user = OCP_USER_MPU | OCP_USER_SDMA,
216};
217
218/* l3_instr slave ports */
219static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 220 &omap44xx_iva__l3_instr,
55d2cb08
BC		 221 &omap44xx_l3_main_3__l3_instr,
222};
223
224static struct omap_hwmod omap44xx_l3_instr_hwmod = {
225 .name = "l3_instr",
226 .class = &omap44xx_l3_hwmod_class,
a5322c6f 227 .clkdm_name = "l3_instr_clkdm",
d0f0631d
BC		 228 .prcm = {
229 .omap4 = {
230 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
231 },
232 },
55d2cb08
BC		 233 .slaves = omap44xx_l3_instr_slaves,
234 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
236};
237
7e69ed97 238/* l3_main_1 */
9b4021be
BC		 239static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
240 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
241 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
242 { .irq = -1 }
243};
244
8f25bdc5
BC		 245/* dsp -> l3_main_1 */
246static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
247 .master = &omap44xx_dsp_hwmod,
248 .slave = &omap44xx_l3_main_1_hwmod,
249 .clk = "l3_div_ck",
250 .user = OCP_USER_MPU | OCP_USER_SDMA,
251};
252
d63bd74f
BC		 253/* dss -> l3_main_1 */
254static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
255 .master = &omap44xx_dss_hwmod,
256 .slave = &omap44xx_l3_main_1_hwmod,
257 .clk = "l3_div_ck",
258 .user = OCP_USER_MPU | OCP_USER_SDMA,
259};
260
55d2cb08
BC		 261/* l3_main_2 -> l3_main_1 */
262static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
263 .master = &omap44xx_l3_main_2_hwmod,
264 .slave = &omap44xx_l3_main_1_hwmod,
265 .clk = "l3_div_ck",
266 .user = OCP_USER_MPU | OCP_USER_SDMA,
267};
268
269/* l4_cfg -> l3_main_1 */
270static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
271 .master = &omap44xx_l4_cfg_hwmod,
272 .slave = &omap44xx_l3_main_1_hwmod,
273 .clk = "l4_div_ck",
274 .user = OCP_USER_MPU | OCP_USER_SDMA,
275};
276
407a6888
BC		 277/* mmc1 -> l3_main_1 */
278static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
279 .master = &omap44xx_mmc1_hwmod,
280 .slave = &omap44xx_l3_main_1_hwmod,
281 .clk = "l3_div_ck",
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
283};
284
285/* mmc2 -> l3_main_1 */
286static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
287 .master = &omap44xx_mmc2_hwmod,
288 .slave = &omap44xx_l3_main_1_hwmod,
289 .clk = "l3_div_ck",
290 .user = OCP_USER_MPU | OCP_USER_SDMA,
291};
292
c4645234 293static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
294 {
295 .pa_start = 0x44000000,
296 .pa_end = 0x44000fff,
9b4021be 297 .flags = ADDR_TYPE_RT
c4645234 298 },
78183f3f 299 { }
c4645234 300};
301
55d2cb08
BC		 302/* mpu -> l3_main_1 */
303static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
304 .master = &omap44xx_mpu_hwmod,
305 .slave = &omap44xx_l3_main_1_hwmod,
306 .clk = "l3_div_ck",
c4645234 307 .addr = omap44xx_l3_main_1_addrs,
9b4021be 308 .user = OCP_USER_MPU,
55d2cb08
BC		 309};
310
311/* l3_main_1 slave ports */
312static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 313 &omap44xx_dsp__l3_main_1,
d63bd74f 314 &omap44xx_dss__l3_main_1,
55d2cb08
BC		 315 &omap44xx_l3_main_2__l3_main_1,
316 &omap44xx_l4_cfg__l3_main_1,
407a6888
BC		 317 &omap44xx_mmc1__l3_main_1,
318 &omap44xx_mmc2__l3_main_1,
55d2cb08
BC		 319 &omap44xx_mpu__l3_main_1,
320};
321
322static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
323 .name = "l3_main_1",
324 .class = &omap44xx_l3_hwmod_class,
a5322c6f 325 .clkdm_name = "l3_1_clkdm",
7e69ed97 326 .mpu_irqs = omap44xx_l3_main_1_irqs,
d0f0631d
BC		 327 .prcm = {
328 .omap4 = {
329 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
330 },
331 },
55d2cb08
BC		 332 .slaves = omap44xx_l3_main_1_slaves,
333 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
335};
336
7e69ed97 337/* l3_main_2 */
d7cf5f33
BC		 338/* dma_system -> l3_main_2 */
339static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
340 .master = &omap44xx_dma_system_hwmod,
341 .slave = &omap44xx_l3_main_2_hwmod,
342 .clk = "l3_div_ck",
343 .user = OCP_USER_MPU | OCP_USER_SDMA,
344};
345
407a6888
BC		 346/* hsi -> l3_main_2 */
347static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
348 .master = &omap44xx_hsi_hwmod,
349 .slave = &omap44xx_l3_main_2_hwmod,
350 .clk = "l3_div_ck",
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
352};
353
354/* ipu -> l3_main_2 */
355static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
356 .master = &omap44xx_ipu_hwmod,
357 .slave = &omap44xx_l3_main_2_hwmod,
358 .clk = "l3_div_ck",
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
360};
361
362/* iss -> l3_main_2 */
363static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
364 .master = &omap44xx_iss_hwmod,
365 .slave = &omap44xx_l3_main_2_hwmod,
366 .clk = "l3_div_ck",
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
368};
369
8f25bdc5
BC		 370/* iva -> l3_main_2 */
371static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
372 .master = &omap44xx_iva_hwmod,
373 .slave = &omap44xx_l3_main_2_hwmod,
374 .clk = "l3_div_ck",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
376};
377
c4645234 378static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
379 {
380 .pa_start = 0x44800000,
381 .pa_end = 0x44801fff,
9b4021be 382 .flags = ADDR_TYPE_RT
c4645234 383 },
78183f3f 384 { }
c4645234 385};
386
55d2cb08
BC		 387/* l3_main_1 -> l3_main_2 */
388static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
389 .master = &omap44xx_l3_main_1_hwmod,
390 .slave = &omap44xx_l3_main_2_hwmod,
391 .clk = "l3_div_ck",
c4645234 392 .addr = omap44xx_l3_main_2_addrs,
9b4021be 393 .user = OCP_USER_MPU,
55d2cb08
BC		 394};
395
396/* l4_cfg -> l3_main_2 */
397static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
398 .master = &omap44xx_l4_cfg_hwmod,
399 .slave = &omap44xx_l3_main_2_hwmod,
400 .clk = "l4_div_ck",
401 .user = OCP_USER_MPU | OCP_USER_SDMA,
402};
403
5844c4ea
BC		 404/* usb_otg_hs -> l3_main_2 */
405static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
406 .master = &omap44xx_usb_otg_hs_hwmod,
407 .slave = &omap44xx_l3_main_2_hwmod,
408 .clk = "l3_div_ck",
409 .user = OCP_USER_MPU | OCP_USER_SDMA,
410};
411
55d2cb08
BC		 412/* l3_main_2 slave ports */
413static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 414 &omap44xx_dma_system__l3_main_2,
407a6888
BC		 415 &omap44xx_hsi__l3_main_2,
416 &omap44xx_ipu__l3_main_2,
417 &omap44xx_iss__l3_main_2,
8f25bdc5 418 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 419 &omap44xx_l3_main_1__l3_main_2,
420 &omap44xx_l4_cfg__l3_main_2,
5844c4ea 421 &omap44xx_usb_otg_hs__l3_main_2,
55d2cb08
BC		 422};
423
424static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
425 .name = "l3_main_2",
426 .class = &omap44xx_l3_hwmod_class,
a5322c6f 427 .clkdm_name = "l3_2_clkdm",
d0f0631d
BC		 428 .prcm = {
429 .omap4 = {
430 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
431 },
432 },
55d2cb08
BC		 433 .slaves = omap44xx_l3_main_2_slaves,
434 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
435 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
436};
437
7e69ed97 438/* l3_main_3 */
c4645234 439static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
440 {
441 .pa_start = 0x45000000,
442 .pa_end = 0x45000fff,
9b4021be 443 .flags = ADDR_TYPE_RT
c4645234 444 },
78183f3f 445 { }
c4645234 446};
447
55d2cb08
BC		 448/* l3_main_1 -> l3_main_3 */
449static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
450 .master = &omap44xx_l3_main_1_hwmod,
451 .slave = &omap44xx_l3_main_3_hwmod,
452 .clk = "l3_div_ck",
c4645234 453 .addr = omap44xx_l3_main_3_addrs,
9b4021be 454 .user = OCP_USER_MPU,
55d2cb08
BC		 455};
456
457/* l3_main_2 -> l3_main_3 */
458static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
459 .master = &omap44xx_l3_main_2_hwmod,
460 .slave = &omap44xx_l3_main_3_hwmod,
461 .clk = "l3_div_ck",
462 .user = OCP_USER_MPU | OCP_USER_SDMA,
463};
464
465/* l4_cfg -> l3_main_3 */
466static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
467 .master = &omap44xx_l4_cfg_hwmod,
468 .slave = &omap44xx_l3_main_3_hwmod,
469 .clk = "l4_div_ck",
470 .user = OCP_USER_MPU | OCP_USER_SDMA,
471};
472
473/* l3_main_3 slave ports */
474static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
475 &omap44xx_l3_main_1__l3_main_3,
476 &omap44xx_l3_main_2__l3_main_3,
477 &omap44xx_l4_cfg__l3_main_3,
478};
479
480static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
481 .name = "l3_main_3",
482 .class = &omap44xx_l3_hwmod_class,
a5322c6f 483 .clkdm_name = "l3_instr_clkdm",
d0f0631d
BC		 484 .prcm = {
485 .omap4 = {
486 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
487 },
488 },
55d2cb08
BC		 489 .slaves = omap44xx_l3_main_3_slaves,
490 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
491 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
492};
493
494/*
495 * 'l4' class
496 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
497 */
498static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 499 .name = "l4",
55d2cb08
BC		 500};
501
7e69ed97 502/* l4_abe */
407a6888
BC		 503/* aess -> l4_abe */
504static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
505 .master = &omap44xx_aess_hwmod,
506 .slave = &omap44xx_l4_abe_hwmod,
507 .clk = "ocp_abe_iclk",
508 .user = OCP_USER_MPU | OCP_USER_SDMA,
509};
510
8f25bdc5
BC		 511/* dsp -> l4_abe */
512static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
513 .master = &omap44xx_dsp_hwmod,
514 .slave = &omap44xx_l4_abe_hwmod,
515 .clk = "ocp_abe_iclk",
516 .user = OCP_USER_MPU | OCP_USER_SDMA,
517};
518
55d2cb08
BC		 519/* l3_main_1 -> l4_abe */
520static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
521 .master = &omap44xx_l3_main_1_hwmod,
522 .slave = &omap44xx_l4_abe_hwmod,
523 .clk = "l3_div_ck",
524 .user = OCP_USER_MPU | OCP_USER_SDMA,
525};
526
527/* mpu -> l4_abe */
528static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
529 .master = &omap44xx_mpu_hwmod,
530 .slave = &omap44xx_l4_abe_hwmod,
531 .clk = "ocp_abe_iclk",
532 .user = OCP_USER_MPU | OCP_USER_SDMA,
533};
534
535/* l4_abe slave ports */
536static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
407a6888 537 &omap44xx_aess__l4_abe,
8f25bdc5 538 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 539 &omap44xx_l3_main_1__l4_abe,
540 &omap44xx_mpu__l4_abe,
541};
542
543static struct omap_hwmod omap44xx_l4_abe_hwmod = {
544 .name = "l4_abe",
545 .class = &omap44xx_l4_hwmod_class,
a5322c6f 546 .clkdm_name = "abe_clkdm",
d0f0631d
BC		 547 .prcm = {
548 .omap4 = {
549 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
550 },
551 },
55d2cb08
BC		 552 .slaves = omap44xx_l4_abe_slaves,
553 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
554 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
555};
556
7e69ed97 557/* l4_cfg */
55d2cb08
BC		 558/* l3_main_1 -> l4_cfg */
559static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
560 .master = &omap44xx_l3_main_1_hwmod,
561 .slave = &omap44xx_l4_cfg_hwmod,
562 .clk = "l3_div_ck",
563 .user = OCP_USER_MPU | OCP_USER_SDMA,
564};
565
566/* l4_cfg slave ports */
567static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
568 &omap44xx_l3_main_1__l4_cfg,
569};
570
571static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
572 .name = "l4_cfg",
573 .class = &omap44xx_l4_hwmod_class,
a5322c6f 574 .clkdm_name = "l4_cfg_clkdm",
d0f0631d
BC		 575 .prcm = {
576 .omap4 = {
577 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
578 },
579 },
55d2cb08
BC		 580 .slaves = omap44xx_l4_cfg_slaves,
581 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
582 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
583};
584
7e69ed97 585/* l4_per */
55d2cb08
BC		 586/* l3_main_2 -> l4_per */
587static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
588 .master = &omap44xx_l3_main_2_hwmod,
589 .slave = &omap44xx_l4_per_hwmod,
590 .clk = "l3_div_ck",
591 .user = OCP_USER_MPU | OCP_USER_SDMA,
592};
593
594/* l4_per slave ports */
595static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
596 &omap44xx_l3_main_2__l4_per,
597};
598
599static struct omap_hwmod omap44xx_l4_per_hwmod = {
600 .name = "l4_per",
601 .class = &omap44xx_l4_hwmod_class,
a5322c6f 602 .clkdm_name = "l4_per_clkdm",
d0f0631d
BC		 603 .prcm = {
604 .omap4 = {
605 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
606 },
607 },
55d2cb08
BC		 608 .slaves = omap44xx_l4_per_slaves,
609 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
610 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
611};
612
7e69ed97 613/* l4_wkup */
55d2cb08
BC		 614/* l4_cfg -> l4_wkup */
615static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
616 .master = &omap44xx_l4_cfg_hwmod,
617 .slave = &omap44xx_l4_wkup_hwmod,
618 .clk = "l4_div_ck",
619 .user = OCP_USER_MPU | OCP_USER_SDMA,
620};
621
622/* l4_wkup slave ports */
623static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
624 &omap44xx_l4_cfg__l4_wkup,
625};
626
627static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
628 .name = "l4_wkup",
629 .class = &omap44xx_l4_hwmod_class,
a5322c6f 630 .clkdm_name = "l4_wkup_clkdm",
d0f0631d
BC		 631 .prcm = {
632 .omap4 = {
633 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
634 },
635 },
55d2cb08
BC		 636 .slaves = omap44xx_l4_wkup_slaves,
637 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
638 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
639};
640
f776471f 641/*
3b54baad
BC		 642 * 'mpu_bus' class
643 * instance(s): mpu_private
f776471f 644 */
3b54baad 645static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 646 .name = "mpu_bus",
3b54baad 647};
f776471f 648
7e69ed97 649/* mpu_private */
3b54baad
BC		 650/* mpu -> mpu_private */
651static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
652 .master = &omap44xx_mpu_hwmod,
653 .slave = &omap44xx_mpu_private_hwmod,
654 .clk = "l3_div_ck",
655 .user = OCP_USER_MPU | OCP_USER_SDMA,
656};
657
658/* mpu_private slave ports */
659static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
660 &omap44xx_mpu__mpu_private,
661};
662
663static struct omap_hwmod omap44xx_mpu_private_hwmod = {
664 .name = "mpu_private",
665 .class = &omap44xx_mpu_bus_hwmod_class,
a5322c6f 666 .clkdm_name = "mpuss_clkdm",
3b54baad
BC		 667 .slaves = omap44xx_mpu_private_slaves,
668 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
669 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
670};
671
672/*
673 * Modules omap_hwmod structures
674 *
675 * The following IPs are excluded for the moment because:
676 * - They do not need an explicit SW control using omap_hwmod API.
677 * - They still need to be validated with the driver
678 * properly adapted to omap_hwmod / omap_device
679 *
3b54baad
BC		 680 * c2c
681 * c2c_target_fw
682 * cm_core
683 * cm_core_aon
3b54baad
BC		 684 * ctrl_module_core
685 * ctrl_module_pad_core
686 * ctrl_module_pad_wkup
687 * ctrl_module_wkup
688 * debugss
3b54baad
BC		 689 * efuse_ctrl_cust
690 * efuse_ctrl_std
691 * elm
692 * emif1
693 * emif2
694 * fdif
695 * gpmc
696 * gpu
697 * hdq1w
00fe610b
BC		 698 * mcasp
699 * mpu_c0
700 * mpu_c1
3b54baad
BC		 701 * ocmc_ram
702 * ocp2scp_usb_phy
703 * ocp_wp_noc
3b54baad
BC		 704 * prcm_mpu
705 * prm
706 * scrm
707 * sl2if
708 * slimbus1
709 * slimbus2
3b54baad
BC		 710 * usb_host_fs
711 * usb_host_hs
3b54baad
BC		 712 * usb_phy_cm
713 * usb_tll_hs
714 * usim
715 */
716
407a6888
BC		 717/*
718 * 'aess' class
719 * audio engine sub system
720 */
721
722static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
723 .rev_offs = 0x0000,
724 .sysc_offs = 0x0010,
725 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
726 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
c614ebf6
BC		 727 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
728 MSTANDBY_SMART_WKUP),
407a6888
BC		 729 .sysc_fields = &omap_hwmod_sysc_type2,
730};
731
732static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
733 .name = "aess",
734 .sysc = &omap44xx_aess_sysc,
735};
736
737/* aess */
738static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
739 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
212738a4 740 { .irq = -1 }
407a6888
BC		 741};
742
743static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
744 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
745 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
746 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
747 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
748 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
749 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
750 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
751 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
bc614958 752 { .dma_req = -1 }
407a6888
BC		 753};
754
755/* aess master ports */
756static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
757 &omap44xx_aess__l4_abe,
758};
759
760static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
761 {
762 .pa_start = 0x401f1000,
763 .pa_end = 0x401f13ff,
764 .flags = ADDR_TYPE_RT
765 },
78183f3f 766 { }
407a6888
BC		 767};
768
769/* l4_abe -> aess */
770static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
771 .master = &omap44xx_l4_abe_hwmod,
772 .slave = &omap44xx_aess_hwmod,
773 .clk = "ocp_abe_iclk",
774 .addr = omap44xx_aess_addrs,
407a6888
BC		 775 .user = OCP_USER_MPU,
776};
777
778static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
779 {
780 .pa_start = 0x490f1000,
781 .pa_end = 0x490f13ff,
782 .flags = ADDR_TYPE_RT
783 },
78183f3f 784 { }
407a6888
BC		 785};
786
787/* l4_abe -> aess (dma) */
788static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
789 .master = &omap44xx_l4_abe_hwmod,
790 .slave = &omap44xx_aess_hwmod,
791 .clk = "ocp_abe_iclk",
792 .addr = omap44xx_aess_dma_addrs,
407a6888
BC		 793 .user = OCP_USER_SDMA,
794};
795
796/* aess slave ports */
797static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
798 &omap44xx_l4_abe__aess,
799 &omap44xx_l4_abe__aess_dma,
800};
801
802static struct omap_hwmod omap44xx_aess_hwmod = {
803 .name = "aess",
804 .class = &omap44xx_aess_hwmod_class,
a5322c6f 805 .clkdm_name = "abe_clkdm",
407a6888 806 .mpu_irqs = omap44xx_aess_irqs,
407a6888 807 .sdma_reqs = omap44xx_aess_sdma_reqs,
407a6888 808 .main_clk = "aess_fck",
00fe610b 809 .prcm = {
407a6888 810 .omap4 = {
d0f0631d 811 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
407a6888
BC		 812 },
813 },
814 .slaves = omap44xx_aess_slaves,
815 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
816 .masters = omap44xx_aess_masters,
817 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
818 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
819};
820
821/*
822 * 'bandgap' class
823 * bangap reference for ldo regulators
824 */
825
826static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
827 .name = "bandgap",
828};
829
830/* bandgap */
831static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
832 { .role = "fclk", .clk = "bandgap_fclk" },
833};
834
835static struct omap_hwmod omap44xx_bandgap_hwmod = {
836 .name = "bandgap",
837 .class = &omap44xx_bandgap_hwmod_class,
a5322c6f 838 .clkdm_name = "l4_wkup_clkdm",
00fe610b 839 .prcm = {
407a6888 840 .omap4 = {
d0f0631d 841 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
407a6888
BC		 842 },
843 },
844 .opt_clks = bandgap_opt_clks,
845 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
846 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
847};
848
849/*
850 * 'counter' class
851 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
852 */
853
854static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
855 .rev_offs = 0x0000,
856 .sysc_offs = 0x0004,
857 .sysc_flags = SYSC_HAS_SIDLEMODE,
858 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
859 SIDLE_SMART_WKUP),
860 .sysc_fields = &omap_hwmod_sysc_type1,
861};
862
863static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
864 .name = "counter",
865 .sysc = &omap44xx_counter_sysc,
866};
867
868/* counter_32k */
869static struct omap_hwmod omap44xx_counter_32k_hwmod;
870static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
871 {
872 .pa_start = 0x4a304000,
873 .pa_end = 0x4a30401f,
874 .flags = ADDR_TYPE_RT
875 },
78183f3f 876 { }
407a6888
BC		 877};
878
879/* l4_wkup -> counter_32k */
880static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
881 .master = &omap44xx_l4_wkup_hwmod,
882 .slave = &omap44xx_counter_32k_hwmod,
883 .clk = "l4_wkup_clk_mux_ck",
884 .addr = omap44xx_counter_32k_addrs,
407a6888
BC		 885 .user = OCP_USER_MPU | OCP_USER_SDMA,
886};
887
888/* counter_32k slave ports */
889static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
890 &omap44xx_l4_wkup__counter_32k,
891};
892
893static struct omap_hwmod omap44xx_counter_32k_hwmod = {
894 .name = "counter_32k",
895 .class = &omap44xx_counter_hwmod_class,
a5322c6f 896 .clkdm_name = "l4_wkup_clkdm",
407a6888
BC		 897 .flags = HWMOD_SWSUP_SIDLE,
898 .main_clk = "sys_32k_ck",
00fe610b 899 .prcm = {
407a6888 900 .omap4 = {
d0f0631d 901 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
407a6888
BC		 902 },
903 },
904 .slaves = omap44xx_counter_32k_slaves,
905 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
906 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
907};
908
d7cf5f33
BC		 909/*
910 * 'dma' class
911 * dma controller for data exchange between memory to memory (i.e. internal or
912 * external memory) and gp peripherals to memory or memory to gp peripherals
913 */
914
915static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
916 .rev_offs = 0x0000,
917 .sysc_offs = 0x002c,
918 .syss_offs = 0x0028,
919 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
920 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
921 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
922 SYSS_HAS_RESET_STATUS),
923 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
924 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
925 .sysc_fields = &omap_hwmod_sysc_type1,
926};
927
928static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
929 .name = "dma",
930 .sysc = &omap44xx_dma_sysc,
931};
932
933/* dma dev_attr */
934static struct omap_dma_dev_attr dma_dev_attr = {
935 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
936 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
937 .lch_count = 32,
938};
939
940/* dma_system */
941static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
942 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
943 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
944 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
945 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
212738a4 946 { .irq = -1 }
d7cf5f33
BC		 947};
948
949/* dma_system master ports */
950static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
951 &omap44xx_dma_system__l3_main_2,
952};
953
954static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
955 {
956 .pa_start = 0x4a056000,
1286eeb2 957 .pa_end = 0x4a056fff,
d7cf5f33
BC		 958 .flags = ADDR_TYPE_RT
959 },
78183f3f 960 { }
d7cf5f33
BC		 961};
962
963/* l4_cfg -> dma_system */
964static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
965 .master = &omap44xx_l4_cfg_hwmod,
966 .slave = &omap44xx_dma_system_hwmod,
967 .clk = "l4_div_ck",
968 .addr = omap44xx_dma_system_addrs,
d7cf5f33
BC		 969 .user = OCP_USER_MPU | OCP_USER_SDMA,
970};
971
972/* dma_system slave ports */
973static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
974 &omap44xx_l4_cfg__dma_system,
975};
976
977static struct omap_hwmod omap44xx_dma_system_hwmod = {
978 .name = "dma_system",
979 .class = &omap44xx_dma_hwmod_class,
a5322c6f 980 .clkdm_name = "l3_dma_clkdm",
d7cf5f33 981 .mpu_irqs = omap44xx_dma_system_irqs,
d7cf5f33
BC		 982 .main_clk = "l3_div_ck",
983 .prcm = {
984 .omap4 = {
d0f0631d 985 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
d7cf5f33
BC		 986 },
987 },
988 .dev_attr = &dma_dev_attr,
989 .slaves = omap44xx_dma_system_slaves,
990 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
991 .masters = omap44xx_dma_system_masters,
992 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
993 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
994};
995
8ca476da
BC		 996/*
997 * 'dmic' class
998 * digital microphone controller
999 */
1000
1001static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1002 .rev_offs = 0x0000,
1003 .sysc_offs = 0x0010,
1004 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1005 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1006 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1007 SIDLE_SMART_WKUP),
1008 .sysc_fields = &omap_hwmod_sysc_type2,
1009};
1010
1011static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1012 .name = "dmic",
1013 .sysc = &omap44xx_dmic_sysc,
1014};
1015
1016/* dmic */
1017static struct omap_hwmod omap44xx_dmic_hwmod;
1018static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1019 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
212738a4 1020 { .irq = -1 }
8ca476da
BC		 1021};
1022
1023static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1024 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
bc614958 1025 { .dma_req = -1 }
8ca476da
BC		 1026};
1027
1028static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1029 {
1030 .pa_start = 0x4012e000,
1031 .pa_end = 0x4012e07f,
1032 .flags = ADDR_TYPE_RT
1033 },
78183f3f 1034 { }
8ca476da
BC		 1035};
1036
1037/* l4_abe -> dmic */
1038static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1039 .master = &omap44xx_l4_abe_hwmod,
1040 .slave = &omap44xx_dmic_hwmod,
1041 .clk = "ocp_abe_iclk",
1042 .addr = omap44xx_dmic_addrs,
8ca476da
BC		 1043 .user = OCP_USER_MPU,
1044};
1045
1046static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1047 {
1048 .pa_start = 0x4902e000,
1049 .pa_end = 0x4902e07f,
1050 .flags = ADDR_TYPE_RT
1051 },
78183f3f 1052 { }
8ca476da
BC		 1053};
1054
1055/* l4_abe -> dmic (dma) */
1056static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1057 .master = &omap44xx_l4_abe_hwmod,
1058 .slave = &omap44xx_dmic_hwmod,
1059 .clk = "ocp_abe_iclk",
1060 .addr = omap44xx_dmic_dma_addrs,
8ca476da
BC		 1061 .user = OCP_USER_SDMA,
1062};
1063
1064/* dmic slave ports */
1065static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1066 &omap44xx_l4_abe__dmic,
1067 &omap44xx_l4_abe__dmic_dma,
1068};
1069
1070static struct omap_hwmod omap44xx_dmic_hwmod = {
1071 .name = "dmic",
1072 .class = &omap44xx_dmic_hwmod_class,
a5322c6f 1073 .clkdm_name = "abe_clkdm",
8ca476da 1074 .mpu_irqs = omap44xx_dmic_irqs,
8ca476da 1075 .sdma_reqs = omap44xx_dmic_sdma_reqs,
8ca476da 1076 .main_clk = "dmic_fck",
00fe610b 1077 .prcm = {
8ca476da 1078 .omap4 = {
d0f0631d 1079 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
8ca476da
BC		 1080 },
1081 },
1082 .slaves = omap44xx_dmic_slaves,
1083 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1084 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1085};
1086
8f25bdc5
BC		 1087/*
1088 * 'dsp' class
1089 * dsp sub-system
1090 */
1091
1092static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 1093 .name = "dsp",
8f25bdc5
BC		 1094};
1095
1096/* dsp */
1097static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1098 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
212738a4 1099 { .irq = -1 }
8f25bdc5
BC		 1100};
1101
1102static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1103 { .name = "mmu_cache", .rst_shift = 1 },
1104};
1105
1106static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1107 { .name = "dsp", .rst_shift = 0 },
1108};
1109
1110/* dsp -> iva */
1111static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1112 .master = &omap44xx_dsp_hwmod,
1113 .slave = &omap44xx_iva_hwmod,
1114 .clk = "dpll_iva_m5x2_ck",
1115};
1116
1117/* dsp master ports */
1118static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1119 &omap44xx_dsp__l3_main_1,
1120 &omap44xx_dsp__l4_abe,
1121 &omap44xx_dsp__iva,
1122};
1123
1124/* l4_cfg -> dsp */
1125static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1126 .master = &omap44xx_l4_cfg_hwmod,
1127 .slave = &omap44xx_dsp_hwmod,
1128 .clk = "l4_div_ck",
1129 .user = OCP_USER_MPU | OCP_USER_SDMA,
1130};
1131
1132/* dsp slave ports */
1133static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1134 &omap44xx_l4_cfg__dsp,
1135};
1136
1137/* Pseudo hwmod for reset control purpose only */
1138static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1139 .name = "dsp_c0",
1140 .class = &omap44xx_dsp_hwmod_class,
a5322c6f 1141 .clkdm_name = "tesla_clkdm",
8f25bdc5
BC		 1142 .flags = HWMOD_INIT_NO_RESET,
1143 .rst_lines = omap44xx_dsp_c0_resets,
1144 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1145 .prcm = {
1146 .omap4 = {
eaac329d 1147 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
8f25bdc5
BC		 1148 },
1149 },
1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1151};
1152
1153static struct omap_hwmod omap44xx_dsp_hwmod = {
1154 .name = "dsp",
1155 .class = &omap44xx_dsp_hwmod_class,
a5322c6f 1156 .clkdm_name = "tesla_clkdm",
8f25bdc5 1157 .mpu_irqs = omap44xx_dsp_irqs,
8f25bdc5
BC		 1158 .rst_lines = omap44xx_dsp_resets,
1159 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1160 .main_clk = "dsp_fck",
1161 .prcm = {
1162 .omap4 = {
d0f0631d 1163 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
eaac329d 1164 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
8f25bdc5
BC		 1165 },
1166 },
1167 .slaves = omap44xx_dsp_slaves,
1168 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1169 .masters = omap44xx_dsp_masters,
1170 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1171 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1172};
1173
d63bd74f
BC		 1174/*
1175 * 'dss' class
1176 * display sub-system
1177 */
1178
1179static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1180 .rev_offs = 0x0000,
1181 .syss_offs = 0x0014,
1182 .sysc_flags = SYSS_HAS_RESET_STATUS,
1183};
1184
1185static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1186 .name = "dss",
1187 .sysc = &omap44xx_dss_sysc,
1188};
1189
1190/* dss */
1191/* dss master ports */
1192static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1193 &omap44xx_dss__l3_main_1,
1194};
1195
1196static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1197 {
1198 .pa_start = 0x58000000,
1199 .pa_end = 0x5800007f,
1200 .flags = ADDR_TYPE_RT
1201 },
78183f3f 1202 { }
d63bd74f
BC		 1203};
1204
1205/* l3_main_2 -> dss */
1206static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1207 .master = &omap44xx_l3_main_2_hwmod,
1208 .slave = &omap44xx_dss_hwmod,
da7cdfac 1209 .clk = "dss_fck",
d63bd74f 1210 .addr = omap44xx_dss_dma_addrs,
d63bd74f
BC		 1211 .user = OCP_USER_SDMA,
1212};
1213
1214static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1215 {
1216 .pa_start = 0x48040000,
1217 .pa_end = 0x4804007f,
1218 .flags = ADDR_TYPE_RT
1219 },
78183f3f 1220 { }
d63bd74f
BC		 1221};
1222
1223/* l4_per -> dss */
1224static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1225 .master = &omap44xx_l4_per_hwmod,
1226 .slave = &omap44xx_dss_hwmod,
1227 .clk = "l4_div_ck",
1228 .addr = omap44xx_dss_addrs,
d63bd74f
BC		 1229 .user = OCP_USER_MPU,
1230};
1231
1232/* dss slave ports */
1233static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1234 &omap44xx_l3_main_2__dss,
1235 &omap44xx_l4_per__dss,
1236};
1237
1238static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1239 { .role = "sys_clk", .clk = "dss_sys_clk" },
1240 { .role = "tv_clk", .clk = "dss_tv_clk" },
1241 { .role = "dss_clk", .clk = "dss_dss_clk" },
1242 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1243};
1244
1245static struct omap_hwmod omap44xx_dss_hwmod = {
1246 .name = "dss_core",
1247 .class = &omap44xx_dss_hwmod_class,
a5322c6f 1248 .clkdm_name = "l3_dss_clkdm",
da7cdfac 1249 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1250 .prcm = {
1251 .omap4 = {
d0f0631d 1252 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
d63bd74f
BC		 1253 },
1254 },
1255 .opt_clks = dss_opt_clks,
1256 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1257 .slaves = omap44xx_dss_slaves,
1258 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1259 .masters = omap44xx_dss_masters,
1260 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1261 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1262};
1263
1264/*
1265 * 'dispc' class
1266 * display controller
1267 */
1268
1269static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1270 .rev_offs = 0x0000,
1271 .sysc_offs = 0x0010,
1272 .syss_offs = 0x0014,
1273 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1274 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1275 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1276 SYSS_HAS_RESET_STATUS),
1277 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1278 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1279 .sysc_fields = &omap_hwmod_sysc_type1,
1280};
1281
1282static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1283 .name = "dispc",
1284 .sysc = &omap44xx_dispc_sysc,
1285};
1286
1287/* dss_dispc */
1288static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1289static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1290 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
212738a4 1291 { .irq = -1 }
d63bd74f
BC		 1292};
1293
1294static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1295 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
bc614958 1296 { .dma_req = -1 }
d63bd74f
BC		 1297};
1298
1299static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1300 {
1301 .pa_start = 0x58001000,
1302 .pa_end = 0x58001fff,
1303 .flags = ADDR_TYPE_RT
1304 },
78183f3f 1305 { }
d63bd74f
BC		 1306};
1307
1308/* l3_main_2 -> dss_dispc */
1309static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1310 .master = &omap44xx_l3_main_2_hwmod,
1311 .slave = &omap44xx_dss_dispc_hwmod,
da7cdfac 1312 .clk = "dss_fck",
d63bd74f 1313 .addr = omap44xx_dss_dispc_dma_addrs,
d63bd74f
BC		 1314 .user = OCP_USER_SDMA,
1315};
1316
1317static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1318 {
1319 .pa_start = 0x48041000,
1320 .pa_end = 0x48041fff,
1321 .flags = ADDR_TYPE_RT
1322 },
78183f3f 1323 { }
d63bd74f
BC		 1324};
1325
1326/* l4_per -> dss_dispc */
1327static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1328 .master = &omap44xx_l4_per_hwmod,
1329 .slave = &omap44xx_dss_dispc_hwmod,
1330 .clk = "l4_div_ck",
1331 .addr = omap44xx_dss_dispc_addrs,
d63bd74f
BC		 1332 .user = OCP_USER_MPU,
1333};
1334
1335/* dss_dispc slave ports */
1336static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1337 &omap44xx_l3_main_2__dss_dispc,
1338 &omap44xx_l4_per__dss_dispc,
1339};
1340
3a23aafc
TV		 1341static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1342 { .role = "sys_clk", .clk = "dss_sys_clk" },
1343 { .role = "tv_clk", .clk = "dss_tv_clk" },
1344 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1345};
1346
d63bd74f
BC		 1347static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1348 .name = "dss_dispc",
1349 .class = &omap44xx_dispc_hwmod_class,
a5322c6f 1350 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1351 .mpu_irqs = omap44xx_dss_dispc_irqs,
d63bd74f 1352 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
da7cdfac 1353 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1354 .prcm = {
1355 .omap4 = {
d0f0631d 1356 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
d63bd74f
BC		 1357 },
1358 },
3a23aafc
TV		 1359 .opt_clks = dss_dispc_opt_clks,
1360 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
d63bd74f
BC		 1361 .slaves = omap44xx_dss_dispc_slaves,
1362 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1363 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1364};
1365
1366/*
1367 * 'dsi' class
1368 * display serial interface controller
1369 */
1370
1371static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1372 .rev_offs = 0x0000,
1373 .sysc_offs = 0x0010,
1374 .syss_offs = 0x0014,
1375 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1376 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1377 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1378 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1379 .sysc_fields = &omap_hwmod_sysc_type1,
1380};
1381
1382static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1383 .name = "dsi",
1384 .sysc = &omap44xx_dsi_sysc,
1385};
1386
1387/* dss_dsi1 */
1388static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1389static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1390 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
212738a4 1391 { .irq = -1 }
d63bd74f
BC		 1392};
1393
1394static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1395 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
bc614958 1396 { .dma_req = -1 }
d63bd74f
BC		 1397};
1398
1399static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1400 {
1401 .pa_start = 0x58004000,
1402 .pa_end = 0x580041ff,
1403 .flags = ADDR_TYPE_RT
1404 },
78183f3f 1405 { }
d63bd74f
BC		 1406};
1407
1408/* l3_main_2 -> dss_dsi1 */
1409static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1410 .master = &omap44xx_l3_main_2_hwmod,
1411 .slave = &omap44xx_dss_dsi1_hwmod,
da7cdfac 1412 .clk = "dss_fck",
d63bd74f 1413 .addr = omap44xx_dss_dsi1_dma_addrs,
d63bd74f
BC		 1414 .user = OCP_USER_SDMA,
1415};
1416
1417static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1418 {
1419 .pa_start = 0x48044000,
1420 .pa_end = 0x480441ff,
1421 .flags = ADDR_TYPE_RT
1422 },
78183f3f 1423 { }
d63bd74f
BC		 1424};
1425
1426/* l4_per -> dss_dsi1 */
1427static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1428 .master = &omap44xx_l4_per_hwmod,
1429 .slave = &omap44xx_dss_dsi1_hwmod,
1430 .clk = "l4_div_ck",
1431 .addr = omap44xx_dss_dsi1_addrs,
d63bd74f
BC		 1432 .user = OCP_USER_MPU,
1433};
1434
1435/* dss_dsi1 slave ports */
1436static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1437 &omap44xx_l3_main_2__dss_dsi1,
1438 &omap44xx_l4_per__dss_dsi1,
1439};
1440
3a23aafc
TV		 1441static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1442 { .role = "sys_clk", .clk = "dss_sys_clk" },
1443};
1444
d63bd74f
BC		 1445static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1446 .name = "dss_dsi1",
1447 .class = &omap44xx_dsi_hwmod_class,
a5322c6f 1448 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1449 .mpu_irqs = omap44xx_dss_dsi1_irqs,
d63bd74f 1450 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
da7cdfac 1451 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1452 .prcm = {
1453 .omap4 = {
d0f0631d 1454 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
d63bd74f
BC		 1455 },
1456 },
3a23aafc
TV		 1457 .opt_clks = dss_dsi1_opt_clks,
1458 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
d63bd74f
BC		 1459 .slaves = omap44xx_dss_dsi1_slaves,
1460 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1461 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1462};
1463
1464/* dss_dsi2 */
1465static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1466static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1467 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
212738a4 1468 { .irq = -1 }
d63bd74f
BC		 1469};
1470
1471static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1472 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
bc614958 1473 { .dma_req = -1 }
d63bd74f
BC		 1474};
1475
1476static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1477 {
1478 .pa_start = 0x58005000,
1479 .pa_end = 0x580051ff,
1480 .flags = ADDR_TYPE_RT
1481 },
78183f3f 1482 { }
d63bd74f
BC		 1483};
1484
1485/* l3_main_2 -> dss_dsi2 */
1486static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1487 .master = &omap44xx_l3_main_2_hwmod,
1488 .slave = &omap44xx_dss_dsi2_hwmod,
da7cdfac 1489 .clk = "dss_fck",
d63bd74f 1490 .addr = omap44xx_dss_dsi2_dma_addrs,
d63bd74f
BC		 1491 .user = OCP_USER_SDMA,
1492};
1493
1494static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1495 {
1496 .pa_start = 0x48045000,
1497 .pa_end = 0x480451ff,
1498 .flags = ADDR_TYPE_RT
1499 },
78183f3f 1500 { }
d63bd74f
BC		 1501};
1502
1503/* l4_per -> dss_dsi2 */
1504static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1505 .master = &omap44xx_l4_per_hwmod,
1506 .slave = &omap44xx_dss_dsi2_hwmod,
1507 .clk = "l4_div_ck",
1508 .addr = omap44xx_dss_dsi2_addrs,
d63bd74f
BC		 1509 .user = OCP_USER_MPU,
1510};
1511
1512/* dss_dsi2 slave ports */
1513static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1514 &omap44xx_l3_main_2__dss_dsi2,
1515 &omap44xx_l4_per__dss_dsi2,
1516};
1517
3a23aafc
TV		 1518static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1519 { .role = "sys_clk", .clk = "dss_sys_clk" },
1520};
1521
d63bd74f
BC		 1522static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1523 .name = "dss_dsi2",
1524 .class = &omap44xx_dsi_hwmod_class,
a5322c6f 1525 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1526 .mpu_irqs = omap44xx_dss_dsi2_irqs,
d63bd74f 1527 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
da7cdfac 1528 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1529 .prcm = {
1530 .omap4 = {
d0f0631d 1531 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
d63bd74f
BC		 1532 },
1533 },
3a23aafc
TV		 1534 .opt_clks = dss_dsi2_opt_clks,
1535 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
d63bd74f
BC		 1536 .slaves = omap44xx_dss_dsi2_slaves,
1537 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1538 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1539};
1540
1541/*
1542 * 'hdmi' class
1543 * hdmi controller
1544 */
1545
1546static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1547 .rev_offs = 0x0000,
1548 .sysc_offs = 0x0010,
1549 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1550 SYSC_HAS_SOFTRESET),
1551 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1552 SIDLE_SMART_WKUP),
1553 .sysc_fields = &omap_hwmod_sysc_type2,
1554};
1555
1556static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1557 .name = "hdmi",
1558 .sysc = &omap44xx_hdmi_sysc,
1559};
1560
1561/* dss_hdmi */
1562static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1563static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1564 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
212738a4 1565 { .irq = -1 }
d63bd74f
BC		 1566};
1567
1568static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1569 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
bc614958 1570 { .dma_req = -1 }
d63bd74f
BC		 1571};
1572
1573static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1574 {
1575 .pa_start = 0x58006000,
1576 .pa_end = 0x58006fff,
1577 .flags = ADDR_TYPE_RT
1578 },
78183f3f 1579 { }
d63bd74f
BC		 1580};
1581
1582/* l3_main_2 -> dss_hdmi */
1583static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1584 .master = &omap44xx_l3_main_2_hwmod,
1585 .slave = &omap44xx_dss_hdmi_hwmod,
da7cdfac 1586 .clk = "dss_fck",
d63bd74f 1587 .addr = omap44xx_dss_hdmi_dma_addrs,
d63bd74f
BC		 1588 .user = OCP_USER_SDMA,
1589};
1590
1591static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1592 {
1593 .pa_start = 0x48046000,
1594 .pa_end = 0x48046fff,
1595 .flags = ADDR_TYPE_RT
1596 },
78183f3f 1597 { }
d63bd74f
BC		 1598};
1599
1600/* l4_per -> dss_hdmi */
1601static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1602 .master = &omap44xx_l4_per_hwmod,
1603 .slave = &omap44xx_dss_hdmi_hwmod,
1604 .clk = "l4_div_ck",
1605 .addr = omap44xx_dss_hdmi_addrs,
d63bd74f
BC		 1606 .user = OCP_USER_MPU,
1607};
1608
1609/* dss_hdmi slave ports */
1610static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1611 &omap44xx_l3_main_2__dss_hdmi,
1612 &omap44xx_l4_per__dss_hdmi,
1613};
1614
3a23aafc
TV		 1615static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1616 { .role = "sys_clk", .clk = "dss_sys_clk" },
1617};
1618
d63bd74f
BC		 1619static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1620 .name = "dss_hdmi",
1621 .class = &omap44xx_hdmi_hwmod_class,
a5322c6f 1622 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1623 .mpu_irqs = omap44xx_dss_hdmi_irqs,
d63bd74f 1624 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
da7cdfac 1625 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1626 .prcm = {
1627 .omap4 = {
d0f0631d 1628 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
d63bd74f
BC		 1629 },
1630 },
3a23aafc
TV		 1631 .opt_clks = dss_hdmi_opt_clks,
1632 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
d63bd74f
BC		 1633 .slaves = omap44xx_dss_hdmi_slaves,
1634 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1635 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1636};
1637
1638/*
1639 * 'rfbi' class
1640 * remote frame buffer interface
1641 */
1642
1643static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1644 .rev_offs = 0x0000,
1645 .sysc_offs = 0x0010,
1646 .syss_offs = 0x0014,
1647 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1648 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1649 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1650 .sysc_fields = &omap_hwmod_sysc_type1,
1651};
1652
1653static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1654 .name = "rfbi",
1655 .sysc = &omap44xx_rfbi_sysc,
1656};
1657
1658/* dss_rfbi */
1659static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1660static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1661 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
bc614958 1662 { .dma_req = -1 }
d63bd74f
BC		 1663};
1664
1665static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1666 {
1667 .pa_start = 0x58002000,
1668 .pa_end = 0x580020ff,
1669 .flags = ADDR_TYPE_RT
1670 },
78183f3f 1671 { }
d63bd74f
BC		 1672};
1673
1674/* l3_main_2 -> dss_rfbi */
1675static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1676 .master = &omap44xx_l3_main_2_hwmod,
1677 .slave = &omap44xx_dss_rfbi_hwmod,
da7cdfac 1678 .clk = "dss_fck",
d63bd74f 1679 .addr = omap44xx_dss_rfbi_dma_addrs,
d63bd74f
BC		 1680 .user = OCP_USER_SDMA,
1681};
1682
1683static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1684 {
1685 .pa_start = 0x48042000,
1686 .pa_end = 0x480420ff,
1687 .flags = ADDR_TYPE_RT
1688 },
78183f3f 1689 { }
d63bd74f
BC		 1690};
1691
1692/* l4_per -> dss_rfbi */
1693static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1694 .master = &omap44xx_l4_per_hwmod,
1695 .slave = &omap44xx_dss_rfbi_hwmod,
1696 .clk = "l4_div_ck",
1697 .addr = omap44xx_dss_rfbi_addrs,
d63bd74f
BC		 1698 .user = OCP_USER_MPU,
1699};
1700
1701/* dss_rfbi slave ports */
1702static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1703 &omap44xx_l3_main_2__dss_rfbi,
1704 &omap44xx_l4_per__dss_rfbi,
1705};
1706
3a23aafc
TV		 1707static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1708 { .role = "ick", .clk = "dss_fck" },
1709};
1710
d63bd74f
BC		 1711static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1712 .name = "dss_rfbi",
1713 .class = &omap44xx_rfbi_hwmod_class,
a5322c6f 1714 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1715 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
da7cdfac 1716 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1717 .prcm = {
1718 .omap4 = {
d0f0631d 1719 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
d63bd74f
BC		 1720 },
1721 },
3a23aafc
TV		 1722 .opt_clks = dss_rfbi_opt_clks,
1723 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
d63bd74f
BC		 1724 .slaves = omap44xx_dss_rfbi_slaves,
1725 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1726 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1727};
1728
1729/*
1730 * 'venc' class
1731 * video encoder
1732 */
1733
1734static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1735 .name = "venc",
1736};
1737
1738/* dss_venc */
1739static struct omap_hwmod omap44xx_dss_venc_hwmod;
1740static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1741 {
1742 .pa_start = 0x58003000,
1743 .pa_end = 0x580030ff,
1744 .flags = ADDR_TYPE_RT
1745 },
78183f3f 1746 { }
d63bd74f
BC		 1747};
1748
1749/* l3_main_2 -> dss_venc */
1750static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1751 .master = &omap44xx_l3_main_2_hwmod,
1752 .slave = &omap44xx_dss_venc_hwmod,
da7cdfac 1753 .clk = "dss_fck",
d63bd74f 1754 .addr = omap44xx_dss_venc_dma_addrs,
d63bd74f
BC		 1755 .user = OCP_USER_SDMA,
1756};
1757
1758static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1759 {
1760 .pa_start = 0x48043000,
1761 .pa_end = 0x480430ff,
1762 .flags = ADDR_TYPE_RT
1763 },
78183f3f 1764 { }
d63bd74f
BC		 1765};
1766
1767/* l4_per -> dss_venc */
1768static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1769 .master = &omap44xx_l4_per_hwmod,
1770 .slave = &omap44xx_dss_venc_hwmod,
1771 .clk = "l4_div_ck",
1772 .addr = omap44xx_dss_venc_addrs,
d63bd74f
BC		 1773 .user = OCP_USER_MPU,
1774};
1775
1776/* dss_venc slave ports */
1777static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1778 &omap44xx_l3_main_2__dss_venc,
1779 &omap44xx_l4_per__dss_venc,
1780};
1781
1782static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1783 .name = "dss_venc",
1784 .class = &omap44xx_venc_hwmod_class,
a5322c6f 1785 .clkdm_name = "l3_dss_clkdm",
da7cdfac 1786 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1787 .prcm = {
1788 .omap4 = {
d0f0631d 1789 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
d63bd74f
BC		 1790 },
1791 },
1792 .slaves = omap44xx_dss_venc_slaves,
1793 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1794 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1795};
1796
3b54baad
BC		 1797/*
1798 * 'gpio' class
1799 * general purpose io module
1800 */
1801
1802static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1803 .rev_offs = 0x0000,
f776471f 1804 .sysc_offs = 0x0010,
3b54baad 1805 .syss_offs = 0x0114,
0cfe8751
BC		 1806 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1807 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1808 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1809 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1810 SIDLE_SMART_WKUP),
f776471f
BC		 1811 .sysc_fields = &omap_hwmod_sysc_type1,
1812};
1813
3b54baad 1814static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 1815 .name = "gpio",
1816 .sysc = &omap44xx_gpio_sysc,
1817 .rev = 2,
f776471f
BC		 1818};
1819
3b54baad
BC		 1820/* gpio dev_attr */
1821static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 1822 .bank_width = 32,
1823 .dbck_flag = true,
f776471f
BC		 1824};
1825
3b54baad
BC		 1826/* gpio1 */
1827static struct omap_hwmod omap44xx_gpio1_hwmod;
1828static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1829 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
212738a4 1830 { .irq = -1 }
f776471f
BC		 1831};
1832
3b54baad 1833static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 1834 {
3b54baad
BC		 1835 .pa_start = 0x4a310000,
1836 .pa_end = 0x4a3101ff,
f776471f
BC		 1837 .flags = ADDR_TYPE_RT
1838 },
78183f3f 1839 { }
f776471f
BC		 1840};
1841
3b54baad
BC		 1842/* l4_wkup -> gpio1 */
1843static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1844 .master = &omap44xx_l4_wkup_hwmod,
1845 .slave = &omap44xx_gpio1_hwmod,
b399bca8 1846 .clk = "l4_wkup_clk_mux_ck",
3b54baad 1847 .addr = omap44xx_gpio1_addrs,
f776471f
BC		 1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849};
1850
3b54baad
BC		 1851/* gpio1 slave ports */
1852static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1853 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 1854};
1855
3b54baad 1856static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 1857 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 1858};
1859
1860static struct omap_hwmod omap44xx_gpio1_hwmod = {
1861 .name = "gpio1",
1862 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 1863 .clkdm_name = "l4_wkup_clkdm",
3b54baad 1864 .mpu_irqs = omap44xx_gpio1_irqs,
3b54baad 1865 .main_clk = "gpio1_ick",
f776471f
BC		 1866 .prcm = {
1867 .omap4 = {
d0f0631d 1868 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
f776471f
BC		 1869 },
1870 },
3b54baad
BC		 1871 .opt_clks = gpio1_opt_clks,
1872 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1873 .dev_attr = &gpio_dev_attr,
1874 .slaves = omap44xx_gpio1_slaves,
1875 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 1876 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1877};
1878
3b54baad
BC		 1879/* gpio2 */
1880static struct omap_hwmod omap44xx_gpio2_hwmod;
1881static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1882 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
212738a4 1883 { .irq = -1 }
f776471f
BC		 1884};
1885
3b54baad 1886static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 1887 {
3b54baad
BC		 1888 .pa_start = 0x48055000,
1889 .pa_end = 0x480551ff,
f776471f
BC		 1890 .flags = ADDR_TYPE_RT
1891 },
78183f3f 1892 { }
f776471f
BC		 1893};
1894
3b54baad
BC		 1895/* l4_per -> gpio2 */
1896static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 1897 .master = &omap44xx_l4_per_hwmod,
3b54baad 1898 .slave = &omap44xx_gpio2_hwmod,
b399bca8 1899 .clk = "l4_div_ck",
3b54baad 1900 .addr = omap44xx_gpio2_addrs,
f776471f
BC		 1901 .user = OCP_USER_MPU | OCP_USER_SDMA,
1902};
1903
3b54baad
BC		 1904/* gpio2 slave ports */
1905static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1906 &omap44xx_l4_per__gpio2,
f776471f
BC		 1907};
1908
3b54baad 1909static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 1910 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 1911};
1912
1913static struct omap_hwmod omap44xx_gpio2_hwmod = {
1914 .name = "gpio2",
1915 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 1916 .clkdm_name = "l4_per_clkdm",
b399bca8 1917 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1918 .mpu_irqs = omap44xx_gpio2_irqs,
3b54baad 1919 .main_clk = "gpio2_ick",
f776471f
BC		 1920 .prcm = {
1921 .omap4 = {
d0f0631d 1922 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
f776471f
BC		 1923 },
1924 },
3b54baad
BC		 1925 .opt_clks = gpio2_opt_clks,
1926 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1927 .dev_attr = &gpio_dev_attr,
1928 .slaves = omap44xx_gpio2_slaves,
1929 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 1930 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1931};
1932
3b54baad
BC		 1933/* gpio3 */
1934static struct omap_hwmod omap44xx_gpio3_hwmod;
1935static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1936 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
212738a4 1937 { .irq = -1 }
f776471f
BC		 1938};
1939
3b54baad 1940static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 1941 {
3b54baad
BC		 1942 .pa_start = 0x48057000,
1943 .pa_end = 0x480571ff,
f776471f
BC		 1944 .flags = ADDR_TYPE_RT
1945 },
78183f3f 1946 { }
f776471f
BC		 1947};
1948
3b54baad
BC		 1949/* l4_per -> gpio3 */
1950static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 1951 .master = &omap44xx_l4_per_hwmod,
3b54baad 1952 .slave = &omap44xx_gpio3_hwmod,
b399bca8 1953 .clk = "l4_div_ck",
3b54baad 1954 .addr = omap44xx_gpio3_addrs,
f776471f
BC		 1955 .user = OCP_USER_MPU | OCP_USER_SDMA,
1956};
1957
3b54baad
BC		 1958/* gpio3 slave ports */
1959static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1960 &omap44xx_l4_per__gpio3,
f776471f
BC		 1961};
1962
3b54baad 1963static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 1964 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 1965};
1966
1967static struct omap_hwmod omap44xx_gpio3_hwmod = {
1968 .name = "gpio3",
1969 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 1970 .clkdm_name = "l4_per_clkdm",
b399bca8 1971 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1972 .mpu_irqs = omap44xx_gpio3_irqs,
3b54baad 1973 .main_clk = "gpio3_ick",
f776471f
BC		 1974 .prcm = {
1975 .omap4 = {
d0f0631d 1976 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
f776471f
BC		 1977 },
1978 },
3b54baad
BC		 1979 .opt_clks = gpio3_opt_clks,
1980 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1981 .dev_attr = &gpio_dev_attr,
1982 .slaves = omap44xx_gpio3_slaves,
1983 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 1984 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1985};
1986
3b54baad
BC		 1987/* gpio4 */
1988static struct omap_hwmod omap44xx_gpio4_hwmod;
1989static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1990 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
212738a4 1991 { .irq = -1 }
f776471f
BC		 1992};
1993
3b54baad 1994static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 1995 {
3b54baad
BC		 1996 .pa_start = 0x48059000,
1997 .pa_end = 0x480591ff,
f776471f
BC		 1998 .flags = ADDR_TYPE_RT
1999 },
78183f3f 2000 { }
f776471f
BC		 2001};
2002
3b54baad
BC		 2003/* l4_per -> gpio4 */
2004static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 2005 .master = &omap44xx_l4_per_hwmod,
3b54baad 2006 .slave = &omap44xx_gpio4_hwmod,
b399bca8 2007 .clk = "l4_div_ck",
3b54baad 2008 .addr = omap44xx_gpio4_addrs,
f776471f
BC		 2009 .user = OCP_USER_MPU | OCP_USER_SDMA,
2010};
2011
3b54baad
BC		 2012/* gpio4 slave ports */
2013static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2014 &omap44xx_l4_per__gpio4,
f776471f
BC		 2015};
2016
3b54baad 2017static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 2018 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 2019};
2020
2021static struct omap_hwmod omap44xx_gpio4_hwmod = {
2022 .name = "gpio4",
2023 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 2024 .clkdm_name = "l4_per_clkdm",
b399bca8 2025 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 2026 .mpu_irqs = omap44xx_gpio4_irqs,
3b54baad 2027 .main_clk = "gpio4_ick",
f776471f
BC		 2028 .prcm = {
2029 .omap4 = {
d0f0631d 2030 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
f776471f
BC		 2031 },
2032 },
3b54baad
BC		 2033 .opt_clks = gpio4_opt_clks,
2034 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2035 .dev_attr = &gpio_dev_attr,
2036 .slaves = omap44xx_gpio4_slaves,
2037 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 2038 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2039};
2040
3b54baad
BC		 2041/* gpio5 */
2042static struct omap_hwmod omap44xx_gpio5_hwmod;
2043static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2044 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
212738a4 2045 { .irq = -1 }
55d2cb08
BC		 2046};
2047
3b54baad
BC		 2048static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2049 {
2050 .pa_start = 0x4805b000,
2051 .pa_end = 0x4805b1ff,
2052 .flags = ADDR_TYPE_RT
2053 },
78183f3f 2054 { }
55d2cb08
BC		 2055};
2056
3b54baad
BC		 2057/* l4_per -> gpio5 */
2058static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2059 .master = &omap44xx_l4_per_hwmod,
2060 .slave = &omap44xx_gpio5_hwmod,
b399bca8 2061 .clk = "l4_div_ck",
3b54baad 2062 .addr = omap44xx_gpio5_addrs,
3b54baad 2063 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 2064};
2065
3b54baad
BC		 2066/* gpio5 slave ports */
2067static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2068 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 2069};
2070
3b54baad 2071static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 2072 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 2073};
2074
3b54baad
BC		 2075static struct omap_hwmod omap44xx_gpio5_hwmod = {
2076 .name = "gpio5",
2077 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 2078 .clkdm_name = "l4_per_clkdm",
b399bca8 2079 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 2080 .mpu_irqs = omap44xx_gpio5_irqs,
3b54baad 2081 .main_clk = "gpio5_ick",
55d2cb08
BC		 2082 .prcm = {
2083 .omap4 = {
d0f0631d 2084 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
55d2cb08
BC		 2085 },
2086 },
3b54baad
BC		 2087 .opt_clks = gpio5_opt_clks,
2088 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2089 .dev_attr = &gpio_dev_attr,
2090 .slaves = omap44xx_gpio5_slaves,
2091 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 2092 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2093};
2094
3b54baad
BC		 2095/* gpio6 */
2096static struct omap_hwmod omap44xx_gpio6_hwmod;
2097static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2098 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
212738a4 2099 { .irq = -1 }
92b18d1c
BC		 2100};
2101
3b54baad 2102static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 2103 {
3b54baad
BC		 2104 .pa_start = 0x4805d000,
2105 .pa_end = 0x4805d1ff,
92b18d1c
BC		 2106 .flags = ADDR_TYPE_RT
2107 },
78183f3f 2108 { }
92b18d1c
BC		 2109};
2110
3b54baad
BC		 2111/* l4_per -> gpio6 */
2112static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2113 .master = &omap44xx_l4_per_hwmod,
2114 .slave = &omap44xx_gpio6_hwmod,
b399bca8 2115 .clk = "l4_div_ck",
3b54baad 2116 .addr = omap44xx_gpio6_addrs,
3b54baad 2117 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 2118};
2119
3b54baad
BC		 2120/* gpio6 slave ports */
2121static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2122 &omap44xx_l4_per__gpio6,
db12ba53
BC		 2123};
2124
3b54baad 2125static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 2126 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 2127};
2128
3b54baad
BC		 2129static struct omap_hwmod omap44xx_gpio6_hwmod = {
2130 .name = "gpio6",
2131 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 2132 .clkdm_name = "l4_per_clkdm",
b399bca8 2133 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 2134 .mpu_irqs = omap44xx_gpio6_irqs,
3b54baad
BC		 2135 .main_clk = "gpio6_ick",
2136 .prcm = {
2137 .omap4 = {
d0f0631d 2138 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
3b54baad 2139 },
db12ba53 2140 },
3b54baad
BC		 2141 .opt_clks = gpio6_opt_clks,
2142 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2143 .dev_attr = &gpio_dev_attr,
2144 .slaves = omap44xx_gpio6_slaves,
2145 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 2147};
2148
407a6888
BC		 2149/*
2150 * 'hsi' class
2151 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2152 * serial if)
2153 */
2154
2155static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2156 .rev_offs = 0x0000,
2157 .sysc_offs = 0x0010,
2158 .syss_offs = 0x0014,
2159 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2160 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2161 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2162 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2163 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2164 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2165 .sysc_fields = &omap_hwmod_sysc_type1,
2166};
2167
2168static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2169 .name = "hsi",
2170 .sysc = &omap44xx_hsi_sysc,
2171};
2172
2173/* hsi */
2174static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2175 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2176 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2177 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
212738a4 2178 { .irq = -1 }
407a6888
BC		 2179};
2180
2181/* hsi master ports */
2182static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2183 &omap44xx_hsi__l3_main_2,
2184};
2185
2186static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2187 {
2188 .pa_start = 0x4a058000,
2189 .pa_end = 0x4a05bfff,
2190 .flags = ADDR_TYPE_RT
2191 },
78183f3f 2192 { }
407a6888
BC		 2193};
2194
2195/* l4_cfg -> hsi */
2196static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2197 .master = &omap44xx_l4_cfg_hwmod,
2198 .slave = &omap44xx_hsi_hwmod,
2199 .clk = "l4_div_ck",
2200 .addr = omap44xx_hsi_addrs,
407a6888
BC		 2201 .user = OCP_USER_MPU | OCP_USER_SDMA,
2202};
2203
2204/* hsi slave ports */
2205static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2206 &omap44xx_l4_cfg__hsi,
2207};
2208
2209static struct omap_hwmod omap44xx_hsi_hwmod = {
2210 .name = "hsi",
2211 .class = &omap44xx_hsi_hwmod_class,
a5322c6f 2212 .clkdm_name = "l3_init_clkdm",
407a6888 2213 .mpu_irqs = omap44xx_hsi_irqs,
407a6888 2214 .main_clk = "hsi_fck",
00fe610b 2215 .prcm = {
407a6888 2216 .omap4 = {
d0f0631d 2217 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
407a6888
BC		 2218 },
2219 },
2220 .slaves = omap44xx_hsi_slaves,
2221 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2222 .masters = omap44xx_hsi_masters,
2223 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2224 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2225};
2226
3b54baad
BC		 2227/*
2228 * 'i2c' class
2229 * multimaster high-speed i2c controller
2230 */
db12ba53 2231
3b54baad
BC		 2232static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2233 .sysc_offs = 0x0010,
2234 .syss_offs = 0x0090,
2235 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2236 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 2237 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2238 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2239 SIDLE_SMART_WKUP),
3b54baad 2240 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 2241};
2242
3b54baad 2243static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 2244 .name = "i2c",
2245 .sysc = &omap44xx_i2c_sysc,
db791a75 2246 .rev = OMAP_I2C_IP_VERSION_2,
6d3c55fd 2247 .reset = &omap_i2c_reset,
db12ba53
BC		 2248};
2249
4d4441a6
AG		 2250static struct omap_i2c_dev_attr i2c_dev_attr = {
2251 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2252};
2253
3b54baad
BC		 2254/* i2c1 */
2255static struct omap_hwmod omap44xx_i2c1_hwmod;
2256static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2257 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
212738a4 2258 { .irq = -1 }
db12ba53
BC		 2259};
2260
3b54baad
BC		 2261static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2262 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2263 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
bc614958 2264 { .dma_req = -1 }
db12ba53
BC		 2265};
2266
3b54baad 2267static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 2268 {
3b54baad
BC		 2269 .pa_start = 0x48070000,
2270 .pa_end = 0x480700ff,
db12ba53
BC		 2271 .flags = ADDR_TYPE_RT
2272 },
78183f3f 2273 { }
db12ba53
BC		 2274};
2275
3b54baad
BC		 2276/* l4_per -> i2c1 */
2277static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2278 .master = &omap44xx_l4_per_hwmod,
2279 .slave = &omap44xx_i2c1_hwmod,
2280 .clk = "l4_div_ck",
2281 .addr = omap44xx_i2c1_addrs,
92b18d1c
BC		 2282 .user = OCP_USER_MPU | OCP_USER_SDMA,
2283};
2284
3b54baad
BC		 2285/* i2c1 slave ports */
2286static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2287 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 2288};
2289
3b54baad
BC		 2290static struct omap_hwmod omap44xx_i2c1_hwmod = {
2291 .name = "i2c1",
2292 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2293 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2294 .flags = HWMOD_16BIT_REG,
3b54baad 2295 .mpu_irqs = omap44xx_i2c1_irqs,
3b54baad 2296 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
3b54baad 2297 .main_clk = "i2c1_fck",
92b18d1c
BC		 2298 .prcm = {
2299 .omap4 = {
d0f0631d 2300 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
92b18d1c
BC		 2301 },
2302 },
3b54baad
BC		 2303 .slaves = omap44xx_i2c1_slaves,
2304 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
4d4441a6 2305 .dev_attr = &i2c_dev_attr,
92b18d1c
BC		 2306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2307};
2308
3b54baad
BC		 2309/* i2c2 */
2310static struct omap_hwmod omap44xx_i2c2_hwmod;
2311static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2312 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
212738a4 2313 { .irq = -1 }
92b18d1c
BC		 2314};
2315
3b54baad
BC		 2316static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2317 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2318 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
bc614958 2319 { .dma_req = -1 }
3b54baad
BC		 2320};
2321
2322static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 2323 {
3b54baad
BC		 2324 .pa_start = 0x48072000,
2325 .pa_end = 0x480720ff,
92b18d1c
BC		 2326 .flags = ADDR_TYPE_RT
2327 },
78183f3f 2328 { }
92b18d1c
BC		 2329};
2330
3b54baad
BC		 2331/* l4_per -> i2c2 */
2332static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 2333 .master = &omap44xx_l4_per_hwmod,
3b54baad 2334 .slave = &omap44xx_i2c2_hwmod,
db12ba53 2335 .clk = "l4_div_ck",
3b54baad 2336 .addr = omap44xx_i2c2_addrs,
db12ba53
BC		 2337 .user = OCP_USER_MPU | OCP_USER_SDMA,
2338};
2339
3b54baad
BC		 2340/* i2c2 slave ports */
2341static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2342 &omap44xx_l4_per__i2c2,
db12ba53
BC		 2343};
2344
3b54baad
BC		 2345static struct omap_hwmod omap44xx_i2c2_hwmod = {
2346 .name = "i2c2",
2347 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2348 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2349 .flags = HWMOD_16BIT_REG,
3b54baad 2350 .mpu_irqs = omap44xx_i2c2_irqs,
3b54baad 2351 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
3b54baad 2352 .main_clk = "i2c2_fck",
db12ba53
BC		 2353 .prcm = {
2354 .omap4 = {
d0f0631d 2355 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
db12ba53
BC		 2356 },
2357 },
3b54baad
BC		 2358 .slaves = omap44xx_i2c2_slaves,
2359 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
4d4441a6 2360 .dev_attr = &i2c_dev_attr,
db12ba53
BC		 2361 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2362};
2363
3b54baad
BC		 2364/* i2c3 */
2365static struct omap_hwmod omap44xx_i2c3_hwmod;
2366static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2367 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
212738a4 2368 { .irq = -1 }
db12ba53
BC		 2369};
2370
3b54baad
BC		 2371static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2372 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2373 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
bc614958 2374 { .dma_req = -1 }
92b18d1c
BC		 2375};
2376
3b54baad 2377static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 2378 {
3b54baad
BC		 2379 .pa_start = 0x48060000,
2380 .pa_end = 0x480600ff,
92b18d1c
BC		 2381 .flags = ADDR_TYPE_RT
2382 },
78183f3f 2383 { }
92b18d1c
BC		 2384};
2385
3b54baad
BC		 2386/* l4_per -> i2c3 */
2387static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 2388 .master = &omap44xx_l4_per_hwmod,
3b54baad 2389 .slave = &omap44xx_i2c3_hwmod,
db12ba53 2390 .clk = "l4_div_ck",
3b54baad 2391 .addr = omap44xx_i2c3_addrs,
db12ba53
BC		 2392 .user = OCP_USER_MPU | OCP_USER_SDMA,
2393};
2394
3b54baad
BC		 2395/* i2c3 slave ports */
2396static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2397 &omap44xx_l4_per__i2c3,
db12ba53
BC		 2398};
2399
3b54baad
BC		 2400static struct omap_hwmod omap44xx_i2c3_hwmod = {
2401 .name = "i2c3",
2402 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2403 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2404 .flags = HWMOD_16BIT_REG,
3b54baad 2405 .mpu_irqs = omap44xx_i2c3_irqs,
3b54baad 2406 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
3b54baad 2407 .main_clk = "i2c3_fck",
db12ba53
BC		 2408 .prcm = {
2409 .omap4 = {
d0f0631d 2410 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
db12ba53
BC		 2411 },
2412 },
3b54baad
BC		 2413 .slaves = omap44xx_i2c3_slaves,
2414 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
4d4441a6 2415 .dev_attr = &i2c_dev_attr,
db12ba53
BC		 2416 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2417};
2418
3b54baad
BC		 2419/* i2c4 */
2420static struct omap_hwmod omap44xx_i2c4_hwmod;
2421static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2422 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
212738a4 2423 { .irq = -1 }
db12ba53
BC		 2424};
2425
3b54baad
BC		 2426static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2427 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2428 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
bc614958 2429 { .dma_req = -1 }
db12ba53
BC		 2430};
2431
3b54baad 2432static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 2433 {
3b54baad
BC		 2434 .pa_start = 0x48350000,
2435 .pa_end = 0x483500ff,
db12ba53
BC		 2436 .flags = ADDR_TYPE_RT
2437 },
78183f3f 2438 { }
db12ba53
BC		 2439};
2440
3b54baad
BC		 2441/* l4_per -> i2c4 */
2442static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2443 .master = &omap44xx_l4_per_hwmod,
2444 .slave = &omap44xx_i2c4_hwmod,
2445 .clk = "l4_div_ck",
2446 .addr = omap44xx_i2c4_addrs,
3b54baad 2447 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 2448};
2449
3b54baad
BC		 2450/* i2c4 slave ports */
2451static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2452 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 2453};
2454
3b54baad
BC		 2455static struct omap_hwmod omap44xx_i2c4_hwmod = {
2456 .name = "i2c4",
2457 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2458 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2459 .flags = HWMOD_16BIT_REG,
3b54baad 2460 .mpu_irqs = omap44xx_i2c4_irqs,
3b54baad 2461 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
3b54baad 2462 .main_clk = "i2c4_fck",
92b18d1c
BC		 2463 .prcm = {
2464 .omap4 = {
d0f0631d 2465 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
92b18d1c
BC		 2466 },
2467 },
3b54baad
BC		 2468 .slaves = omap44xx_i2c4_slaves,
2469 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
4d4441a6 2470 .dev_attr = &i2c_dev_attr,
92b18d1c
BC		 2471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2472};
2473
407a6888
BC		 2474/*
2475 * 'ipu' class
2476 * imaging processor unit
2477 */
2478
2479static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2480 .name = "ipu",
2481};
2482
2483/* ipu */
2484static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2485 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
212738a4 2486 { .irq = -1 }
407a6888
BC		 2487};
2488
2489static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2490 { .name = "cpu0", .rst_shift = 0 },
2491};
2492
2493static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2494 { .name = "cpu1", .rst_shift = 1 },
2495};
2496
2497static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2498 { .name = "mmu_cache", .rst_shift = 2 },
2499};
2500
2501/* ipu master ports */
2502static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2503 &omap44xx_ipu__l3_main_2,
2504};
2505
2506/* l3_main_2 -> ipu */
2507static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2508 .master = &omap44xx_l3_main_2_hwmod,
2509 .slave = &omap44xx_ipu_hwmod,
2510 .clk = "l3_div_ck",
2511 .user = OCP_USER_MPU | OCP_USER_SDMA,
2512};
2513
2514/* ipu slave ports */
2515static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2516 &omap44xx_l3_main_2__ipu,
2517};
2518
2519/* Pseudo hwmod for reset control purpose only */
2520static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2521 .name = "ipu_c0",
2522 .class = &omap44xx_ipu_hwmod_class,
a5322c6f 2523 .clkdm_name = "ducati_clkdm",
407a6888
BC		 2524 .flags = HWMOD_INIT_NO_RESET,
2525 .rst_lines = omap44xx_ipu_c0_resets,
2526 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
00fe610b 2527 .prcm = {
407a6888 2528 .omap4 = {
eaac329d 2529 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
407a6888
BC		 2530 },
2531 },
2532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2533};
2534
2535/* Pseudo hwmod for reset control purpose only */
2536static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2537 .name = "ipu_c1",
2538 .class = &omap44xx_ipu_hwmod_class,
a5322c6f 2539 .clkdm_name = "ducati_clkdm",
407a6888
BC		 2540 .flags = HWMOD_INIT_NO_RESET,
2541 .rst_lines = omap44xx_ipu_c1_resets,
2542 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
00fe610b 2543 .prcm = {
407a6888 2544 .omap4 = {
eaac329d 2545 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
407a6888
BC		 2546 },
2547 },
2548 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2549};
2550
2551static struct omap_hwmod omap44xx_ipu_hwmod = {
2552 .name = "ipu",
2553 .class = &omap44xx_ipu_hwmod_class,
a5322c6f 2554 .clkdm_name = "ducati_clkdm",
407a6888 2555 .mpu_irqs = omap44xx_ipu_irqs,
407a6888
BC		 2556 .rst_lines = omap44xx_ipu_resets,
2557 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2558 .main_clk = "ipu_fck",
00fe610b 2559 .prcm = {
407a6888 2560 .omap4 = {
d0f0631d 2561 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
eaac329d 2562 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
407a6888
BC		 2563 },
2564 },
2565 .slaves = omap44xx_ipu_slaves,
2566 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2567 .masters = omap44xx_ipu_masters,
2568 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2569 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2570};
2571
2572/*
2573 * 'iss' class
2574 * external images sensor pixel data processor
2575 */
2576
2577static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2578 .rev_offs = 0x0000,
2579 .sysc_offs = 0x0010,
2580 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2581 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2583 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2584 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2585 .sysc_fields = &omap_hwmod_sysc_type2,
2586};
2587
2588static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2589 .name = "iss",
2590 .sysc = &omap44xx_iss_sysc,
2591};
2592
2593/* iss */
2594static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2595 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
212738a4 2596 { .irq = -1 }
407a6888
BC		 2597};
2598
2599static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2600 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2601 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2602 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2603 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
bc614958 2604 { .dma_req = -1 }
407a6888
BC		 2605};
2606
2607/* iss master ports */
2608static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2609 &omap44xx_iss__l3_main_2,
2610};
2611
2612static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2613 {
2614 .pa_start = 0x52000000,
2615 .pa_end = 0x520000ff,
2616 .flags = ADDR_TYPE_RT
2617 },
78183f3f 2618 { }
407a6888
BC		 2619};
2620
2621/* l3_main_2 -> iss */
2622static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2623 .master = &omap44xx_l3_main_2_hwmod,
2624 .slave = &omap44xx_iss_hwmod,
2625 .clk = "l3_div_ck",
2626 .addr = omap44xx_iss_addrs,
407a6888
BC		 2627 .user = OCP_USER_MPU | OCP_USER_SDMA,
2628};
2629
2630/* iss slave ports */
2631static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2632 &omap44xx_l3_main_2__iss,
2633};
2634
2635static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2636 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2637};
2638
2639static struct omap_hwmod omap44xx_iss_hwmod = {
2640 .name = "iss",
2641 .class = &omap44xx_iss_hwmod_class,
a5322c6f 2642 .clkdm_name = "iss_clkdm",
407a6888 2643 .mpu_irqs = omap44xx_iss_irqs,
407a6888 2644 .sdma_reqs = omap44xx_iss_sdma_reqs,
407a6888 2645 .main_clk = "iss_fck",
00fe610b 2646 .prcm = {
407a6888 2647 .omap4 = {
d0f0631d 2648 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
407a6888
BC		 2649 },
2650 },
2651 .opt_clks = iss_opt_clks,
2652 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2653 .slaves = omap44xx_iss_slaves,
2654 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2655 .masters = omap44xx_iss_masters,
2656 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2657 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2658};
2659
8f25bdc5
BC		 2660/*
2661 * 'iva' class
2662 * multi-standard video encoder/decoder hardware accelerator
2663 */
2664
2665static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 2666 .name = "iva",
8f25bdc5
BC		 2667};
2668
2669/* iva */
2670static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2671 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2672 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2673 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
212738a4 2674 { .irq = -1 }
8f25bdc5
BC		 2675};
2676
2677static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2678 { .name = "logic", .rst_shift = 2 },
2679};
2680
2681static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2682 { .name = "seq0", .rst_shift = 0 },
2683};
2684
2685static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2686 { .name = "seq1", .rst_shift = 1 },
2687};
2688
2689/* iva master ports */
2690static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2691 &omap44xx_iva__l3_main_2,
2692 &omap44xx_iva__l3_instr,
2693};
2694
2695static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2696 {
2697 .pa_start = 0x5a000000,
2698 .pa_end = 0x5a07ffff,
2699 .flags = ADDR_TYPE_RT
2700 },
78183f3f 2701 { }
8f25bdc5
BC		 2702};
2703
2704/* l3_main_2 -> iva */
2705static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2706 .master = &omap44xx_l3_main_2_hwmod,
2707 .slave = &omap44xx_iva_hwmod,
2708 .clk = "l3_div_ck",
2709 .addr = omap44xx_iva_addrs,
8f25bdc5
BC		 2710 .user = OCP_USER_MPU,
2711};
2712
2713/* iva slave ports */
2714static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2715 &omap44xx_dsp__iva,
2716 &omap44xx_l3_main_2__iva,
2717};
2718
2719/* Pseudo hwmod for reset control purpose only */
2720static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2721 .name = "iva_seq0",
2722 .class = &omap44xx_iva_hwmod_class,
a5322c6f 2723 .clkdm_name = "ivahd_clkdm",
8f25bdc5
BC		 2724 .flags = HWMOD_INIT_NO_RESET,
2725 .rst_lines = omap44xx_iva_seq0_resets,
2726 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2727 .prcm = {
2728 .omap4 = {
eaac329d 2729 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
8f25bdc5
BC		 2730 },
2731 },
2732 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2733};
2734
2735/* Pseudo hwmod for reset control purpose only */
2736static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2737 .name = "iva_seq1",
2738 .class = &omap44xx_iva_hwmod_class,
a5322c6f 2739 .clkdm_name = "ivahd_clkdm",
8f25bdc5
BC		 2740 .flags = HWMOD_INIT_NO_RESET,
2741 .rst_lines = omap44xx_iva_seq1_resets,
2742 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2743 .prcm = {
2744 .omap4 = {
eaac329d 2745 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
8f25bdc5
BC		 2746 },
2747 },
2748 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2749};
2750
2751static struct omap_hwmod omap44xx_iva_hwmod = {
2752 .name = "iva",
2753 .class = &omap44xx_iva_hwmod_class,
a5322c6f 2754 .clkdm_name = "ivahd_clkdm",
8f25bdc5 2755 .mpu_irqs = omap44xx_iva_irqs,
8f25bdc5
BC		 2756 .rst_lines = omap44xx_iva_resets,
2757 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2758 .main_clk = "iva_fck",
2759 .prcm = {
2760 .omap4 = {
d0f0631d 2761 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
eaac329d 2762 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
8f25bdc5
BC		 2763 },
2764 },
2765 .slaves = omap44xx_iva_slaves,
2766 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2767 .masters = omap44xx_iva_masters,
2768 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2770};
2771
407a6888
BC		 2772/*
2773 * 'kbd' class
2774 * keyboard controller
2775 */
2776
2777static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2778 .rev_offs = 0x0000,
2779 .sysc_offs = 0x0010,
2780 .syss_offs = 0x0014,
2781 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2782 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2783 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2784 SYSS_HAS_RESET_STATUS),
2785 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2786 .sysc_fields = &omap_hwmod_sysc_type1,
2787};
2788
2789static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2790 .name = "kbd",
2791 .sysc = &omap44xx_kbd_sysc,
2792};
2793
2794/* kbd */
2795static struct omap_hwmod omap44xx_kbd_hwmod;
2796static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2797 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
212738a4 2798 { .irq = -1 }
407a6888
BC		 2799};
2800
2801static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2802 {
2803 .pa_start = 0x4a31c000,
2804 .pa_end = 0x4a31c07f,
2805 .flags = ADDR_TYPE_RT
2806 },
78183f3f 2807 { }
407a6888
BC		 2808};
2809
2810/* l4_wkup -> kbd */
2811static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2812 .master = &omap44xx_l4_wkup_hwmod,
2813 .slave = &omap44xx_kbd_hwmod,
2814 .clk = "l4_wkup_clk_mux_ck",
2815 .addr = omap44xx_kbd_addrs,
407a6888
BC		 2816 .user = OCP_USER_MPU | OCP_USER_SDMA,
2817};
2818
2819/* kbd slave ports */
2820static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2821 &omap44xx_l4_wkup__kbd,
2822};
2823
2824static struct omap_hwmod omap44xx_kbd_hwmod = {
2825 .name = "kbd",
2826 .class = &omap44xx_kbd_hwmod_class,
a5322c6f 2827 .clkdm_name = "l4_wkup_clkdm",
407a6888 2828 .mpu_irqs = omap44xx_kbd_irqs,
407a6888 2829 .main_clk = "kbd_fck",
00fe610b 2830 .prcm = {
407a6888 2831 .omap4 = {
d0f0631d 2832 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
407a6888
BC		 2833 },
2834 },
2835 .slaves = omap44xx_kbd_slaves,
2836 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2837 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2838};
2839
ec5df927
BC		 2840/*
2841 * 'mailbox' class
2842 * mailbox module allowing communication between the on-chip processors using a
2843 * queued mailbox-interrupt mechanism.
2844 */
2845
2846static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2847 .rev_offs = 0x0000,
2848 .sysc_offs = 0x0010,
2849 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2850 SYSC_HAS_SOFTRESET),
2851 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2852 .sysc_fields = &omap_hwmod_sysc_type2,
2853};
2854
2855static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2856 .name = "mailbox",
2857 .sysc = &omap44xx_mailbox_sysc,
2858};
2859
2860/* mailbox */
2861static struct omap_hwmod omap44xx_mailbox_hwmod;
2862static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2863 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
212738a4 2864 { .irq = -1 }
ec5df927
BC		 2865};
2866
2867static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2868 {
2869 .pa_start = 0x4a0f4000,
2870 .pa_end = 0x4a0f41ff,
2871 .flags = ADDR_TYPE_RT
2872 },
78183f3f 2873 { }
ec5df927
BC		 2874};
2875
2876/* l4_cfg -> mailbox */
2877static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2878 .master = &omap44xx_l4_cfg_hwmod,
2879 .slave = &omap44xx_mailbox_hwmod,
2880 .clk = "l4_div_ck",
2881 .addr = omap44xx_mailbox_addrs,
ec5df927
BC		 2882 .user = OCP_USER_MPU | OCP_USER_SDMA,
2883};
2884
2885/* mailbox slave ports */
2886static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2887 &omap44xx_l4_cfg__mailbox,
2888};
2889
2890static struct omap_hwmod omap44xx_mailbox_hwmod = {
2891 .name = "mailbox",
2892 .class = &omap44xx_mailbox_hwmod_class,
a5322c6f 2893 .clkdm_name = "l4_cfg_clkdm",
ec5df927 2894 .mpu_irqs = omap44xx_mailbox_irqs,
00fe610b 2895 .prcm = {
ec5df927 2896 .omap4 = {
d0f0631d 2897 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
ec5df927
BC		 2898 },
2899 },
2900 .slaves = omap44xx_mailbox_slaves,
2901 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2902 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2903};
2904
4ddff493
BC		 2905/*
2906 * 'mcbsp' class
2907 * multi channel buffered serial port controller
2908 */
2909
2910static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2911 .sysc_offs = 0x008c,
2912 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2913 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2914 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2915 .sysc_fields = &omap_hwmod_sysc_type1,
2916};
2917
2918static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2919 .name = "mcbsp",
2920 .sysc = &omap44xx_mcbsp_sysc,
cb7e9ded 2921 .rev = MCBSP_CONFIG_TYPE4,
4ddff493
BC		 2922};
2923
2924/* mcbsp1 */
2925static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2926static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2927 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
212738a4 2928 { .irq = -1 }
4ddff493
BC		 2929};
2930
2931static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2932 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2933 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
bc614958 2934 { .dma_req = -1 }
4ddff493
BC		 2935};
2936
2937static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2938 {
cb7e9ded 2939 .name = "mpu",
4ddff493
BC		 2940 .pa_start = 0x40122000,
2941 .pa_end = 0x401220ff,
2942 .flags = ADDR_TYPE_RT
2943 },
78183f3f 2944 { }
4ddff493
BC		 2945};
2946
2947/* l4_abe -> mcbsp1 */
2948static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2949 .master = &omap44xx_l4_abe_hwmod,
2950 .slave = &omap44xx_mcbsp1_hwmod,
2951 .clk = "ocp_abe_iclk",
2952 .addr = omap44xx_mcbsp1_addrs,
4ddff493
BC		 2953 .user = OCP_USER_MPU,
2954};
2955
2956static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2957 {
cb7e9ded 2958 .name = "dma",
4ddff493
BC		 2959 .pa_start = 0x49022000,
2960 .pa_end = 0x490220ff,
2961 .flags = ADDR_TYPE_RT
2962 },
78183f3f 2963 { }
4ddff493
BC		 2964};
2965
2966/* l4_abe -> mcbsp1 (dma) */
2967static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2968 .master = &omap44xx_l4_abe_hwmod,
2969 .slave = &omap44xx_mcbsp1_hwmod,
2970 .clk = "ocp_abe_iclk",
2971 .addr = omap44xx_mcbsp1_dma_addrs,
4ddff493
BC		 2972 .user = OCP_USER_SDMA,
2973};
2974
2975/* mcbsp1 slave ports */
2976static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2977 &omap44xx_l4_abe__mcbsp1,
2978 &omap44xx_l4_abe__mcbsp1_dma,
2979};
2980
2981static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2982 .name = "mcbsp1",
2983 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 2984 .clkdm_name = "abe_clkdm",
4ddff493 2985 .mpu_irqs = omap44xx_mcbsp1_irqs,
4ddff493 2986 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
4ddff493
BC		 2987 .main_clk = "mcbsp1_fck",
2988 .prcm = {
2989 .omap4 = {
d0f0631d 2990 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
4ddff493
BC		 2991 },
2992 },
2993 .slaves = omap44xx_mcbsp1_slaves,
2994 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2995 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2996};
2997
2998/* mcbsp2 */
2999static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3000static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3001 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
212738a4 3002 { .irq = -1 }
4ddff493
BC		 3003};
3004
3005static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3006 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3007 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
bc614958 3008 { .dma_req = -1 }
4ddff493
BC		 3009};
3010
3011static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3012 {
cb7e9ded 3013 .name = "mpu",
4ddff493
BC		 3014 .pa_start = 0x40124000,
3015 .pa_end = 0x401240ff,
3016 .flags = ADDR_TYPE_RT
3017 },
78183f3f 3018 { }
4ddff493
BC		 3019};
3020
3021/* l4_abe -> mcbsp2 */
3022static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3023 .master = &omap44xx_l4_abe_hwmod,
3024 .slave = &omap44xx_mcbsp2_hwmod,
3025 .clk = "ocp_abe_iclk",
3026 .addr = omap44xx_mcbsp2_addrs,
4ddff493
BC		 3027 .user = OCP_USER_MPU,
3028};
3029
3030static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3031 {
cb7e9ded 3032 .name = "dma",
4ddff493
BC		 3033 .pa_start = 0x49024000,
3034 .pa_end = 0x490240ff,
3035 .flags = ADDR_TYPE_RT
3036 },
78183f3f 3037 { }
4ddff493
BC		 3038};
3039
3040/* l4_abe -> mcbsp2 (dma) */
3041static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3042 .master = &omap44xx_l4_abe_hwmod,
3043 .slave = &omap44xx_mcbsp2_hwmod,
3044 .clk = "ocp_abe_iclk",
3045 .addr = omap44xx_mcbsp2_dma_addrs,
4ddff493
BC		 3046 .user = OCP_USER_SDMA,
3047};
3048
3049/* mcbsp2 slave ports */
3050static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3051 &omap44xx_l4_abe__mcbsp2,
3052 &omap44xx_l4_abe__mcbsp2_dma,
3053};
3054
3055static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3056 .name = "mcbsp2",
3057 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 3058 .clkdm_name = "abe_clkdm",
4ddff493 3059 .mpu_irqs = omap44xx_mcbsp2_irqs,
4ddff493 3060 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
4ddff493
BC		 3061 .main_clk = "mcbsp2_fck",
3062 .prcm = {
3063 .omap4 = {
d0f0631d 3064 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
4ddff493
BC		 3065 },
3066 },
3067 .slaves = omap44xx_mcbsp2_slaves,
3068 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3069 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3070};
3071
3072/* mcbsp3 */
3073static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3074static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3075 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
212738a4 3076 { .irq = -1 }
4ddff493
BC		 3077};
3078
3079static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3080 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3081 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
bc614958 3082 { .dma_req = -1 }
4ddff493
BC		 3083};
3084
3085static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3086 {
cb7e9ded 3087 .name = "mpu",
4ddff493
BC		 3088 .pa_start = 0x40126000,
3089 .pa_end = 0x401260ff,
3090 .flags = ADDR_TYPE_RT
3091 },
78183f3f 3092 { }
4ddff493
BC		 3093};
3094
3095/* l4_abe -> mcbsp3 */
3096static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3097 .master = &omap44xx_l4_abe_hwmod,
3098 .slave = &omap44xx_mcbsp3_hwmod,
3099 .clk = "ocp_abe_iclk",
3100 .addr = omap44xx_mcbsp3_addrs,
4ddff493
BC		 3101 .user = OCP_USER_MPU,
3102};
3103
3104static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3105 {
cb7e9ded 3106 .name = "dma",
4ddff493
BC		 3107 .pa_start = 0x49026000,
3108 .pa_end = 0x490260ff,
3109 .flags = ADDR_TYPE_RT
3110 },
78183f3f 3111 { }
4ddff493
BC		 3112};
3113
3114/* l4_abe -> mcbsp3 (dma) */
3115static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3116 .master = &omap44xx_l4_abe_hwmod,
3117 .slave = &omap44xx_mcbsp3_hwmod,
3118 .clk = "ocp_abe_iclk",
3119 .addr = omap44xx_mcbsp3_dma_addrs,
4ddff493
BC		 3120 .user = OCP_USER_SDMA,
3121};
3122
3123/* mcbsp3 slave ports */
3124static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3125 &omap44xx_l4_abe__mcbsp3,
3126 &omap44xx_l4_abe__mcbsp3_dma,
3127};
3128
3129static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3130 .name = "mcbsp3",
3131 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 3132 .clkdm_name = "abe_clkdm",
4ddff493 3133 .mpu_irqs = omap44xx_mcbsp3_irqs,
4ddff493 3134 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
4ddff493
BC		 3135 .main_clk = "mcbsp3_fck",
3136 .prcm = {
3137 .omap4 = {
d0f0631d 3138 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
4ddff493
BC		 3139 },
3140 },
3141 .slaves = omap44xx_mcbsp3_slaves,
3142 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3143 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3144};
3145
3146/* mcbsp4 */
3147static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3148static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3149 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
212738a4 3150 { .irq = -1 }
4ddff493
BC		 3151};
3152
3153static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3154 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3155 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
bc614958 3156 { .dma_req = -1 }
4ddff493
BC		 3157};
3158
3159static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3160 {
3161 .pa_start = 0x48096000,
3162 .pa_end = 0x480960ff,
3163 .flags = ADDR_TYPE_RT
3164 },
78183f3f 3165 { }
4ddff493
BC		 3166};
3167
3168/* l4_per -> mcbsp4 */
3169static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3170 .master = &omap44xx_l4_per_hwmod,
3171 .slave = &omap44xx_mcbsp4_hwmod,
3172 .clk = "l4_div_ck",
3173 .addr = omap44xx_mcbsp4_addrs,
4ddff493
BC		 3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175};
3176
3177/* mcbsp4 slave ports */
3178static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3179 &omap44xx_l4_per__mcbsp4,
3180};
3181
3182static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3183 .name = "mcbsp4",
3184 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 3185 .clkdm_name = "l4_per_clkdm",
4ddff493 3186 .mpu_irqs = omap44xx_mcbsp4_irqs,
4ddff493 3187 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
4ddff493
BC		 3188 .main_clk = "mcbsp4_fck",
3189 .prcm = {
3190 .omap4 = {
d0f0631d 3191 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
4ddff493
BC		 3192 },
3193 },
3194 .slaves = omap44xx_mcbsp4_slaves,
3195 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3196 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3197};
3198
407a6888
BC		 3199/*
3200 * 'mcpdm' class
3201 * multi channel pdm controller (proprietary interface with phoenix power
3202 * ic)
3203 */
3204
3205static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3206 .rev_offs = 0x0000,
3207 .sysc_offs = 0x0010,
3208 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3209 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3210 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3211 SIDLE_SMART_WKUP),
3212 .sysc_fields = &omap_hwmod_sysc_type2,
3213};
3214
3215static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3216 .name = "mcpdm",
3217 .sysc = &omap44xx_mcpdm_sysc,
3218};
3219
3220/* mcpdm */
3221static struct omap_hwmod omap44xx_mcpdm_hwmod;
3222static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3223 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
212738a4 3224 { .irq = -1 }
407a6888
BC		 3225};
3226
3227static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3228 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3229 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
bc614958 3230 { .dma_req = -1 }
407a6888
BC		 3231};
3232
3233static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3234 {
3235 .pa_start = 0x40132000,
3236 .pa_end = 0x4013207f,
3237 .flags = ADDR_TYPE_RT
3238 },
78183f3f 3239 { }
407a6888
BC		 3240};
3241
3242/* l4_abe -> mcpdm */
3243static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3244 .master = &omap44xx_l4_abe_hwmod,
3245 .slave = &omap44xx_mcpdm_hwmod,
3246 .clk = "ocp_abe_iclk",
3247 .addr = omap44xx_mcpdm_addrs,
407a6888
BC		 3248 .user = OCP_USER_MPU,
3249};
3250
3251static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3252 {
3253 .pa_start = 0x49032000,
3254 .pa_end = 0x4903207f,
3255 .flags = ADDR_TYPE_RT
3256 },
78183f3f 3257 { }
407a6888
BC		 3258};
3259
3260/* l4_abe -> mcpdm (dma) */
3261static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3262 .master = &omap44xx_l4_abe_hwmod,
3263 .slave = &omap44xx_mcpdm_hwmod,
3264 .clk = "ocp_abe_iclk",
3265 .addr = omap44xx_mcpdm_dma_addrs,
407a6888
BC		 3266 .user = OCP_USER_SDMA,
3267};
3268
3269/* mcpdm slave ports */
3270static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3271 &omap44xx_l4_abe__mcpdm,
3272 &omap44xx_l4_abe__mcpdm_dma,
3273};
3274
3275static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3276 .name = "mcpdm",
3277 .class = &omap44xx_mcpdm_hwmod_class,
a5322c6f 3278 .clkdm_name = "abe_clkdm",
407a6888 3279 .mpu_irqs = omap44xx_mcpdm_irqs,
407a6888 3280 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
407a6888 3281 .main_clk = "mcpdm_fck",
00fe610b 3282 .prcm = {
407a6888 3283 .omap4 = {
d0f0631d 3284 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
407a6888
BC		 3285 },
3286 },
3287 .slaves = omap44xx_mcpdm_slaves,
3288 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3290};
3291
9bcbd7f0
BC		 3292/*
3293 * 'mcspi' class
3294 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3295 * bus
3296 */
3297
3298static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3299 .rev_offs = 0x0000,
3300 .sysc_offs = 0x0010,
3301 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3302 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3304 SIDLE_SMART_WKUP),
3305 .sysc_fields = &omap_hwmod_sysc_type2,
3306};
3307
3308static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3309 .name = "mcspi",
3310 .sysc = &omap44xx_mcspi_sysc,
905a74d9 3311 .rev = OMAP4_MCSPI_REV,
9bcbd7f0
BC		 3312};
3313
3314/* mcspi1 */
3315static struct omap_hwmod omap44xx_mcspi1_hwmod;
3316static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3317 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
212738a4 3318 { .irq = -1 }
9bcbd7f0
BC		 3319};
3320
3321static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3322 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3323 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3324 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3325 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3326 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3327 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3328 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3329 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
bc614958 3330 { .dma_req = -1 }
9bcbd7f0
BC		 3331};
3332
3333static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3334 {
3335 .pa_start = 0x48098000,
3336 .pa_end = 0x480981ff,
3337 .flags = ADDR_TYPE_RT
3338 },
78183f3f 3339 { }
9bcbd7f0
BC		 3340};
3341
3342/* l4_per -> mcspi1 */
3343static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3344 .master = &omap44xx_l4_per_hwmod,
3345 .slave = &omap44xx_mcspi1_hwmod,
3346 .clk = "l4_div_ck",
3347 .addr = omap44xx_mcspi1_addrs,
9bcbd7f0
BC		 3348 .user = OCP_USER_MPU | OCP_USER_SDMA,
3349};
3350
3351/* mcspi1 slave ports */
3352static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3353 &omap44xx_l4_per__mcspi1,
3354};
3355
905a74d9
BC		 3356/* mcspi1 dev_attr */
3357static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3358 .num_chipselect = 4,
3359};
3360
9bcbd7f0
BC		 3361static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3362 .name = "mcspi1",
3363 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3364 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3365 .mpu_irqs = omap44xx_mcspi1_irqs,
9bcbd7f0 3366 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
9bcbd7f0
BC		 3367 .main_clk = "mcspi1_fck",
3368 .prcm = {
3369 .omap4 = {
d0f0631d 3370 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
9bcbd7f0
BC		 3371 },
3372 },
905a74d9 3373 .dev_attr = &mcspi1_dev_attr,
9bcbd7f0
BC		 3374 .slaves = omap44xx_mcspi1_slaves,
3375 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3376 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3377};
3378
3379/* mcspi2 */
3380static struct omap_hwmod omap44xx_mcspi2_hwmod;
3381static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3382 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
212738a4 3383 { .irq = -1 }
9bcbd7f0
BC		 3384};
3385
3386static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3387 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3388 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3389 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3390 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
bc614958 3391 { .dma_req = -1 }
9bcbd7f0
BC		 3392};
3393
3394static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3395 {
3396 .pa_start = 0x4809a000,
3397 .pa_end = 0x4809a1ff,
3398 .flags = ADDR_TYPE_RT
3399 },
78183f3f 3400 { }
9bcbd7f0
BC		 3401};
3402
3403/* l4_per -> mcspi2 */
3404static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3405 .master = &omap44xx_l4_per_hwmod,
3406 .slave = &omap44xx_mcspi2_hwmod,
3407 .clk = "l4_div_ck",
3408 .addr = omap44xx_mcspi2_addrs,
9bcbd7f0
BC		 3409 .user = OCP_USER_MPU | OCP_USER_SDMA,
3410};
3411
3412/* mcspi2 slave ports */
3413static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3414 &omap44xx_l4_per__mcspi2,
3415};
3416
905a74d9
BC		 3417/* mcspi2 dev_attr */
3418static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3419 .num_chipselect = 2,
3420};
3421
9bcbd7f0
BC		 3422static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3423 .name = "mcspi2",
3424 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3425 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3426 .mpu_irqs = omap44xx_mcspi2_irqs,
9bcbd7f0 3427 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
9bcbd7f0
BC		 3428 .main_clk = "mcspi2_fck",
3429 .prcm = {
3430 .omap4 = {
d0f0631d 3431 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
9bcbd7f0
BC		 3432 },
3433 },
905a74d9 3434 .dev_attr = &mcspi2_dev_attr,
9bcbd7f0
BC		 3435 .slaves = omap44xx_mcspi2_slaves,
3436 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3437 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3438};
3439
3440/* mcspi3 */
3441static struct omap_hwmod omap44xx_mcspi3_hwmod;
3442static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3443 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
212738a4 3444 { .irq = -1 }
9bcbd7f0
BC		 3445};
3446
3447static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3448 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3449 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3450 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3451 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
bc614958 3452 { .dma_req = -1 }
9bcbd7f0
BC		 3453};
3454
3455static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3456 {
3457 .pa_start = 0x480b8000,
3458 .pa_end = 0x480b81ff,
3459 .flags = ADDR_TYPE_RT
3460 },
78183f3f 3461 { }
9bcbd7f0
BC		 3462};
3463
3464/* l4_per -> mcspi3 */
3465static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3466 .master = &omap44xx_l4_per_hwmod,
3467 .slave = &omap44xx_mcspi3_hwmod,
3468 .clk = "l4_div_ck",
3469 .addr = omap44xx_mcspi3_addrs,
9bcbd7f0
BC		 3470 .user = OCP_USER_MPU | OCP_USER_SDMA,
3471};
3472
3473/* mcspi3 slave ports */
3474static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3475 &omap44xx_l4_per__mcspi3,
3476};
3477
905a74d9
BC		 3478/* mcspi3 dev_attr */
3479static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3480 .num_chipselect = 2,
3481};
3482
9bcbd7f0
BC		 3483static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3484 .name = "mcspi3",
3485 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3486 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3487 .mpu_irqs = omap44xx_mcspi3_irqs,
9bcbd7f0 3488 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
9bcbd7f0
BC		 3489 .main_clk = "mcspi3_fck",
3490 .prcm = {
3491 .omap4 = {
d0f0631d 3492 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
9bcbd7f0
BC		 3493 },
3494 },
905a74d9 3495 .dev_attr = &mcspi3_dev_attr,
9bcbd7f0
BC		 3496 .slaves = omap44xx_mcspi3_slaves,
3497 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3499};
3500
3501/* mcspi4 */
3502static struct omap_hwmod omap44xx_mcspi4_hwmod;
3503static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3504 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
212738a4 3505 { .irq = -1 }
9bcbd7f0
BC		 3506};
3507
3508static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3509 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3510 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
bc614958 3511 { .dma_req = -1 }
9bcbd7f0
BC		 3512};
3513
3514static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3515 {
3516 .pa_start = 0x480ba000,
3517 .pa_end = 0x480ba1ff,
3518 .flags = ADDR_TYPE_RT
3519 },
78183f3f 3520 { }
9bcbd7f0
BC		 3521};
3522
3523/* l4_per -> mcspi4 */
3524static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3525 .master = &omap44xx_l4_per_hwmod,
3526 .slave = &omap44xx_mcspi4_hwmod,
3527 .clk = "l4_div_ck",
3528 .addr = omap44xx_mcspi4_addrs,
9bcbd7f0
BC		 3529 .user = OCP_USER_MPU | OCP_USER_SDMA,
3530};
3531
3532/* mcspi4 slave ports */
3533static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3534 &omap44xx_l4_per__mcspi4,
3535};
3536
905a74d9
BC		 3537/* mcspi4 dev_attr */
3538static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3539 .num_chipselect = 1,
3540};
3541
9bcbd7f0
BC		 3542static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3543 .name = "mcspi4",
3544 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3545 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3546 .mpu_irqs = omap44xx_mcspi4_irqs,
9bcbd7f0 3547 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
9bcbd7f0
BC		 3548 .main_clk = "mcspi4_fck",
3549 .prcm = {
3550 .omap4 = {
d0f0631d 3551 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
9bcbd7f0
BC		 3552 },
3553 },
905a74d9 3554 .dev_attr = &mcspi4_dev_attr,
9bcbd7f0
BC		 3555 .slaves = omap44xx_mcspi4_slaves,
3556 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3557 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3558};
3559
407a6888
BC		 3560/*
3561 * 'mmc' class
3562 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3563 */
3564
3565static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3566 .rev_offs = 0x0000,
3567 .sysc_offs = 0x0010,
3568 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3569 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3570 SYSC_HAS_SOFTRESET),
3571 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3572 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 3573 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 3574 .sysc_fields = &omap_hwmod_sysc_type2,
3575};
3576
3577static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3578 .name = "mmc",
3579 .sysc = &omap44xx_mmc_sysc,
3580};
3581
3582/* mmc1 */
3583static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3584 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
212738a4 3585 { .irq = -1 }
407a6888
BC		 3586};
3587
3588static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3589 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3590 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
bc614958 3591 { .dma_req = -1 }
407a6888
BC		 3592};
3593
3594/* mmc1 master ports */
3595static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3596 &omap44xx_mmc1__l3_main_1,
3597};
3598
3599static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3600 {
3601 .pa_start = 0x4809c000,
3602 .pa_end = 0x4809c3ff,
3603 .flags = ADDR_TYPE_RT
3604 },
78183f3f 3605 { }
407a6888
BC		 3606};
3607
3608/* l4_per -> mmc1 */
3609static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3610 .master = &omap44xx_l4_per_hwmod,
3611 .slave = &omap44xx_mmc1_hwmod,
3612 .clk = "l4_div_ck",
3613 .addr = omap44xx_mmc1_addrs,
407a6888
BC		 3614 .user = OCP_USER_MPU | OCP_USER_SDMA,
3615};
3616
3617/* mmc1 slave ports */
3618static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3619 &omap44xx_l4_per__mmc1,
3620};
3621
6ab8946f
KK		 3622/* mmc1 dev_attr */
3623static struct omap_mmc_dev_attr mmc1_dev_attr = {
3624 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3625};
3626
407a6888
BC		 3627static struct omap_hwmod omap44xx_mmc1_hwmod = {
3628 .name = "mmc1",
3629 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3630 .clkdm_name = "l3_init_clkdm",
407a6888 3631 .mpu_irqs = omap44xx_mmc1_irqs,
407a6888 3632 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
407a6888 3633 .main_clk = "mmc1_fck",
00fe610b 3634 .prcm = {
407a6888 3635 .omap4 = {
d0f0631d 3636 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
407a6888
BC		 3637 },
3638 },
6ab8946f 3639 .dev_attr = &mmc1_dev_attr,
407a6888
BC		 3640 .slaves = omap44xx_mmc1_slaves,
3641 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3642 .masters = omap44xx_mmc1_masters,
3643 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3644 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3645};
3646
3647/* mmc2 */
3648static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3649 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
212738a4 3650 { .irq = -1 }
407a6888
BC		 3651};
3652
3653static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3654 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3655 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
bc614958 3656 { .dma_req = -1 }
407a6888
BC		 3657};
3658
3659/* mmc2 master ports */
3660static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3661 &omap44xx_mmc2__l3_main_1,
3662};
3663
3664static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3665 {
3666 .pa_start = 0x480b4000,
3667 .pa_end = 0x480b43ff,
3668 .flags = ADDR_TYPE_RT
3669 },
78183f3f 3670 { }
407a6888
BC		 3671};
3672
3673/* l4_per -> mmc2 */
3674static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3675 .master = &omap44xx_l4_per_hwmod,
3676 .slave = &omap44xx_mmc2_hwmod,
3677 .clk = "l4_div_ck",
3678 .addr = omap44xx_mmc2_addrs,
407a6888
BC		 3679 .user = OCP_USER_MPU | OCP_USER_SDMA,
3680};
3681
3682/* mmc2 slave ports */
3683static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3684 &omap44xx_l4_per__mmc2,
3685};
3686
3687static struct omap_hwmod omap44xx_mmc2_hwmod = {
3688 .name = "mmc2",
3689 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3690 .clkdm_name = "l3_init_clkdm",
407a6888 3691 .mpu_irqs = omap44xx_mmc2_irqs,
407a6888 3692 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
407a6888 3693 .main_clk = "mmc2_fck",
00fe610b 3694 .prcm = {
407a6888 3695 .omap4 = {
d0f0631d 3696 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
407a6888
BC		 3697 },
3698 },
3699 .slaves = omap44xx_mmc2_slaves,
3700 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3701 .masters = omap44xx_mmc2_masters,
3702 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3703 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3704};
3705
3706/* mmc3 */
3707static struct omap_hwmod omap44xx_mmc3_hwmod;
3708static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3709 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
212738a4 3710 { .irq = -1 }
407a6888
BC		 3711};
3712
3713static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3714 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3715 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
bc614958 3716 { .dma_req = -1 }
407a6888
BC		 3717};
3718
3719static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3720 {
3721 .pa_start = 0x480ad000,
3722 .pa_end = 0x480ad3ff,
3723 .flags = ADDR_TYPE_RT
3724 },
78183f3f 3725 { }
407a6888
BC		 3726};
3727
3728/* l4_per -> mmc3 */
3729static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3730 .master = &omap44xx_l4_per_hwmod,
3731 .slave = &omap44xx_mmc3_hwmod,
3732 .clk = "l4_div_ck",
3733 .addr = omap44xx_mmc3_addrs,
407a6888
BC		 3734 .user = OCP_USER_MPU | OCP_USER_SDMA,
3735};
3736
3737/* mmc3 slave ports */
3738static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3739 &omap44xx_l4_per__mmc3,
3740};
3741
3742static struct omap_hwmod omap44xx_mmc3_hwmod = {
3743 .name = "mmc3",
3744 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3745 .clkdm_name = "l4_per_clkdm",
407a6888 3746 .mpu_irqs = omap44xx_mmc3_irqs,
407a6888 3747 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
407a6888 3748 .main_clk = "mmc3_fck",
00fe610b 3749 .prcm = {
407a6888 3750 .omap4 = {
d0f0631d 3751 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
407a6888
BC		 3752 },
3753 },
3754 .slaves = omap44xx_mmc3_slaves,
3755 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3756 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3757};
3758
3759/* mmc4 */
3760static struct omap_hwmod omap44xx_mmc4_hwmod;
3761static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3762 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
212738a4 3763 { .irq = -1 }
407a6888
BC		 3764};
3765
3766static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3767 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3768 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
bc614958 3769 { .dma_req = -1 }
407a6888
BC		 3770};
3771
3772static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3773 {
3774 .pa_start = 0x480d1000,
3775 .pa_end = 0x480d13ff,
3776 .flags = ADDR_TYPE_RT
3777 },
78183f3f 3778 { }
407a6888
BC		 3779};
3780
3781/* l4_per -> mmc4 */
3782static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3783 .master = &omap44xx_l4_per_hwmod,
3784 .slave = &omap44xx_mmc4_hwmod,
3785 .clk = "l4_div_ck",
3786 .addr = omap44xx_mmc4_addrs,
407a6888
BC		 3787 .user = OCP_USER_MPU | OCP_USER_SDMA,
3788};
3789
3790/* mmc4 slave ports */
3791static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3792 &omap44xx_l4_per__mmc4,
3793};
3794
3795static struct omap_hwmod omap44xx_mmc4_hwmod = {
3796 .name = "mmc4",
3797 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3798 .clkdm_name = "l4_per_clkdm",
407a6888 3799 .mpu_irqs = omap44xx_mmc4_irqs,
212738a4 3800
407a6888 3801 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
407a6888 3802 .main_clk = "mmc4_fck",
00fe610b 3803 .prcm = {
407a6888 3804 .omap4 = {
d0f0631d 3805 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
407a6888
BC		 3806 },
3807 },
3808 .slaves = omap44xx_mmc4_slaves,
3809 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3810 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3811};
3812
3813/* mmc5 */
3814static struct omap_hwmod omap44xx_mmc5_hwmod;
3815static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3816 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
212738a4 3817 { .irq = -1 }
407a6888
BC		 3818};
3819
3820static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3821 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3822 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
bc614958 3823 { .dma_req = -1 }
407a6888
BC		 3824};
3825
3826static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3827 {
3828 .pa_start = 0x480d5000,
3829 .pa_end = 0x480d53ff,
3830 .flags = ADDR_TYPE_RT
3831 },
78183f3f 3832 { }
407a6888
BC		 3833};
3834
3835/* l4_per -> mmc5 */
3836static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3837 .master = &omap44xx_l4_per_hwmod,
3838 .slave = &omap44xx_mmc5_hwmod,
3839 .clk = "l4_div_ck",
3840 .addr = omap44xx_mmc5_addrs,
407a6888
BC		 3841 .user = OCP_USER_MPU | OCP_USER_SDMA,
3842};
3843
3844/* mmc5 slave ports */
3845static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3846 &omap44xx_l4_per__mmc5,
3847};
3848
3849static struct omap_hwmod omap44xx_mmc5_hwmod = {
3850 .name = "mmc5",
3851 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3852 .clkdm_name = "l4_per_clkdm",
407a6888 3853 .mpu_irqs = omap44xx_mmc5_irqs,
407a6888 3854 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
407a6888 3855 .main_clk = "mmc5_fck",
00fe610b 3856 .prcm = {
407a6888 3857 .omap4 = {
d0f0631d 3858 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
407a6888
BC		 3859 },
3860 },
3861 .slaves = omap44xx_mmc5_slaves,
3862 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3863 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3864};
3865
3b54baad
BC		 3866/*
3867 * 'mpu' class
3868 * mpu sub-system
3869 */
3870
3871static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 3872 .name = "mpu",
db12ba53
BC		 3873};
3874
3b54baad
BC		 3875/* mpu */
3876static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3877 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3878 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3879 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
212738a4 3880 { .irq = -1 }
db12ba53
BC		 3881};
3882
3b54baad
BC		 3883/* mpu master ports */
3884static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3885 &omap44xx_mpu__l3_main_1,
3886 &omap44xx_mpu__l4_abe,
3887 &omap44xx_mpu__dmm,
3888};
3889
3890static struct omap_hwmod omap44xx_mpu_hwmod = {
3891 .name = "mpu",
3892 .class = &omap44xx_mpu_hwmod_class,
a5322c6f 3893 .clkdm_name = "mpuss_clkdm",
7ecc5373 3894 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 3895 .mpu_irqs = omap44xx_mpu_irqs,
3b54baad 3896 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 3897 .prcm = {
3898 .omap4 = {
d0f0631d 3899 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
db12ba53
BC		 3900 },
3901 },
3b54baad
BC		 3902 .masters = omap44xx_mpu_masters,
3903 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 3904 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3905};
3906
1f6a717f
BC		 3907/*
3908 * 'smartreflex' class
3909 * smartreflex module (monitor silicon performance and outputs a measure of
3910 * performance error)
3911 */
3912
3913/* The IP is not compliant to type1 / type2 scheme */
3914static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3915 .sidle_shift = 24,
3916 .enwkup_shift = 26,
3917};
3918
3919static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3920 .sysc_offs = 0x0038,
3921 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3922 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3923 SIDLE_SMART_WKUP),
3924 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3925};
3926
3927static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 3928 .name = "smartreflex",
3929 .sysc = &omap44xx_smartreflex_sysc,
3930 .rev = 2,
1f6a717f
BC		 3931};
3932
3933/* smartreflex_core */
3934static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3935static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3936 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
212738a4 3937 { .irq = -1 }
1f6a717f
BC		 3938};
3939
3940static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3941 {
3942 .pa_start = 0x4a0dd000,
3943 .pa_end = 0x4a0dd03f,
3944 .flags = ADDR_TYPE_RT
3945 },
78183f3f 3946 { }
1f6a717f
BC		 3947};
3948
3949/* l4_cfg -> smartreflex_core */
3950static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3951 .master = &omap44xx_l4_cfg_hwmod,
3952 .slave = &omap44xx_smartreflex_core_hwmod,
3953 .clk = "l4_div_ck",
3954 .addr = omap44xx_smartreflex_core_addrs,
1f6a717f
BC		 3955 .user = OCP_USER_MPU | OCP_USER_SDMA,
3956};
3957
3958/* smartreflex_core slave ports */
3959static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3960 &omap44xx_l4_cfg__smartreflex_core,
3961};
3962
3963static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3964 .name = "smartreflex_core",
3965 .class = &omap44xx_smartreflex_hwmod_class,
a5322c6f 3966 .clkdm_name = "l4_ao_clkdm",
1f6a717f 3967 .mpu_irqs = omap44xx_smartreflex_core_irqs,
212738a4 3968
1f6a717f
BC		 3969 .main_clk = "smartreflex_core_fck",
3970 .vdd_name = "core",
3971 .prcm = {
3972 .omap4 = {
d0f0631d 3973 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
1f6a717f
BC		 3974 },
3975 },
3976 .slaves = omap44xx_smartreflex_core_slaves,
3977 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3978 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3979};
3980
3981/* smartreflex_iva */
3982static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3983static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3984 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
212738a4 3985 { .irq = -1 }
1f6a717f
BC		 3986};
3987
3988static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3989 {
3990 .pa_start = 0x4a0db000,
3991 .pa_end = 0x4a0db03f,
3992 .flags = ADDR_TYPE_RT
3993 },
78183f3f 3994 { }
1f6a717f
BC		 3995};
3996
3997/* l4_cfg -> smartreflex_iva */
3998static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3999 .master = &omap44xx_l4_cfg_hwmod,
4000 .slave = &omap44xx_smartreflex_iva_hwmod,
4001 .clk = "l4_div_ck",
4002 .addr = omap44xx_smartreflex_iva_addrs,
1f6a717f
BC		 4003 .user = OCP_USER_MPU | OCP_USER_SDMA,
4004};
4005
4006/* smartreflex_iva slave ports */
4007static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4008 &omap44xx_l4_cfg__smartreflex_iva,
4009};
4010
4011static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4012 .name = "smartreflex_iva",
4013 .class = &omap44xx_smartreflex_hwmod_class,
a5322c6f 4014 .clkdm_name = "l4_ao_clkdm",
1f6a717f 4015 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1f6a717f
BC		 4016 .main_clk = "smartreflex_iva_fck",
4017 .vdd_name = "iva",
4018 .prcm = {
4019 .omap4 = {
d0f0631d 4020 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
1f6a717f
BC		 4021 },
4022 },
4023 .slaves = omap44xx_smartreflex_iva_slaves,
4024 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4025 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4026};
4027
4028/* smartreflex_mpu */
4029static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4030static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4031 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
212738a4 4032 { .irq = -1 }
1f6a717f
BC		 4033};
4034
4035static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4036 {
4037 .pa_start = 0x4a0d9000,
4038 .pa_end = 0x4a0d903f,
4039 .flags = ADDR_TYPE_RT
4040 },
78183f3f 4041 { }
1f6a717f
BC		 4042};
4043
4044/* l4_cfg -> smartreflex_mpu */
4045static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4046 .master = &omap44xx_l4_cfg_hwmod,
4047 .slave = &omap44xx_smartreflex_mpu_hwmod,
4048 .clk = "l4_div_ck",
4049 .addr = omap44xx_smartreflex_mpu_addrs,
1f6a717f
BC		 4050 .user = OCP_USER_MPU | OCP_USER_SDMA,
4051};
4052
4053/* smartreflex_mpu slave ports */
4054static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4055 &omap44xx_l4_cfg__smartreflex_mpu,
4056};
4057
4058static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4059 .name = "smartreflex_mpu",
4060 .class = &omap44xx_smartreflex_hwmod_class,
a5322c6f 4061 .clkdm_name = "l4_ao_clkdm",
1f6a717f 4062 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1f6a717f
BC		 4063 .main_clk = "smartreflex_mpu_fck",
4064 .vdd_name = "mpu",
4065 .prcm = {
4066 .omap4 = {
d0f0631d 4067 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
1f6a717f
BC		 4068 },
4069 },
4070 .slaves = omap44xx_smartreflex_mpu_slaves,
4071 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4072 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4073};
4074
d11c217f
BC		 4075/*
4076 * 'spinlock' class
4077 * spinlock provides hardware assistance for synchronizing the processes
4078 * running on multiple processors
4079 */
4080
4081static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4082 .rev_offs = 0x0000,
4083 .sysc_offs = 0x0010,
4084 .syss_offs = 0x0014,
4085 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4086 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4087 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4089 SIDLE_SMART_WKUP),
4090 .sysc_fields = &omap_hwmod_sysc_type1,
4091};
4092
4093static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4094 .name = "spinlock",
4095 .sysc = &omap44xx_spinlock_sysc,
4096};
4097
4098/* spinlock */
4099static struct omap_hwmod omap44xx_spinlock_hwmod;
4100static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4101 {
4102 .pa_start = 0x4a0f6000,
4103 .pa_end = 0x4a0f6fff,
4104 .flags = ADDR_TYPE_RT
4105 },
78183f3f 4106 { }
d11c217f
BC		 4107};
4108
4109/* l4_cfg -> spinlock */
4110static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4111 .master = &omap44xx_l4_cfg_hwmod,
4112 .slave = &omap44xx_spinlock_hwmod,
4113 .clk = "l4_div_ck",
4114 .addr = omap44xx_spinlock_addrs,
d11c217f
BC		 4115 .user = OCP_USER_MPU | OCP_USER_SDMA,
4116};
4117
4118/* spinlock slave ports */
4119static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4120 &omap44xx_l4_cfg__spinlock,
4121};
4122
4123static struct omap_hwmod omap44xx_spinlock_hwmod = {
4124 .name = "spinlock",
4125 .class = &omap44xx_spinlock_hwmod_class,
a5322c6f 4126 .clkdm_name = "l4_cfg_clkdm",
d11c217f
BC		 4127 .prcm = {
4128 .omap4 = {
d0f0631d 4129 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
d11c217f
BC		 4130 },
4131 },
4132 .slaves = omap44xx_spinlock_slaves,
4133 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4134 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4135};
4136
35d1a66a
BC		 4137/*
4138 * 'timer' class
4139 * general purpose timer module with accurate 1ms tick
4140 * This class contains several variants: ['timer_1ms', 'timer']
4141 */
4142
4143static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4144 .rev_offs = 0x0000,
4145 .sysc_offs = 0x0010,
4146 .syss_offs = 0x0014,
4147 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4148 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4149 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4150 SYSS_HAS_RESET_STATUS),
4151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4152 .sysc_fields = &omap_hwmod_sysc_type1,
4153};
4154
4155static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4156 .name = "timer",
4157 .sysc = &omap44xx_timer_1ms_sysc,
4158};
4159
4160static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4161 .rev_offs = 0x0000,
4162 .sysc_offs = 0x0010,
4163 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4164 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4166 SIDLE_SMART_WKUP),
4167 .sysc_fields = &omap_hwmod_sysc_type2,
4168};
4169
4170static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4171 .name = "timer",
4172 .sysc = &omap44xx_timer_sysc,
4173};
4174
4175/* timer1 */
4176static struct omap_hwmod omap44xx_timer1_hwmod;
4177static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4178 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
212738a4 4179 { .irq = -1 }
35d1a66a
BC		 4180};
4181
4182static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4183 {
4184 .pa_start = 0x4a318000,
4185 .pa_end = 0x4a31807f,
4186 .flags = ADDR_TYPE_RT
4187 },
78183f3f 4188 { }
35d1a66a
BC		 4189};
4190
4191/* l4_wkup -> timer1 */
4192static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4193 .master = &omap44xx_l4_wkup_hwmod,
4194 .slave = &omap44xx_timer1_hwmod,
4195 .clk = "l4_wkup_clk_mux_ck",
4196 .addr = omap44xx_timer1_addrs,
35d1a66a
BC		 4197 .user = OCP_USER_MPU | OCP_USER_SDMA,
4198};
4199
4200/* timer1 slave ports */
4201static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4202 &omap44xx_l4_wkup__timer1,
4203};
4204
4205static struct omap_hwmod omap44xx_timer1_hwmod = {
4206 .name = "timer1",
4207 .class = &omap44xx_timer_1ms_hwmod_class,
a5322c6f 4208 .clkdm_name = "l4_wkup_clkdm",
35d1a66a 4209 .mpu_irqs = omap44xx_timer1_irqs,
35d1a66a
BC		 4210 .main_clk = "timer1_fck",
4211 .prcm = {
4212 .omap4 = {
d0f0631d 4213 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
35d1a66a
BC		 4214 },
4215 },
4216 .slaves = omap44xx_timer1_slaves,
4217 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4218 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4219};
4220
4221/* timer2 */
4222static struct omap_hwmod omap44xx_timer2_hwmod;
4223static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4224 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
212738a4 4225 { .irq = -1 }
35d1a66a
BC		 4226};
4227
4228static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4229 {
4230 .pa_start = 0x48032000,
4231 .pa_end = 0x4803207f,
4232 .flags = ADDR_TYPE_RT
4233 },
78183f3f 4234 { }
35d1a66a
BC		 4235};
4236
4237/* l4_per -> timer2 */
4238static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4239 .master = &omap44xx_l4_per_hwmod,
4240 .slave = &omap44xx_timer2_hwmod,
4241 .clk = "l4_div_ck",
4242 .addr = omap44xx_timer2_addrs,
35d1a66a
BC		 4243 .user = OCP_USER_MPU | OCP_USER_SDMA,
4244};
4245
4246/* timer2 slave ports */
4247static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4248 &omap44xx_l4_per__timer2,
4249};
4250
4251static struct omap_hwmod omap44xx_timer2_hwmod = {
4252 .name = "timer2",
4253 .class = &omap44xx_timer_1ms_hwmod_class,
a5322c6f 4254 .clkdm_name = "l4_per_clkdm",
35d1a66a 4255 .mpu_irqs = omap44xx_timer2_irqs,
35d1a66a
BC		 4256 .main_clk = "timer2_fck",
4257 .prcm = {
4258 .omap4 = {
d0f0631d 4259 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
35d1a66a
BC		 4260 },
4261 },
4262 .slaves = omap44xx_timer2_slaves,
4263 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4264 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4265};
4266
4267/* timer3 */
4268static struct omap_hwmod omap44xx_timer3_hwmod;
4269static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4270 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
212738a4 4271 { .irq = -1 }
35d1a66a
BC		 4272};
4273
4274static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4275 {
4276 .pa_start = 0x48034000,
4277 .pa_end = 0x4803407f,
4278 .flags = ADDR_TYPE_RT
4279 },
78183f3f 4280 { }
35d1a66a
BC		 4281};
4282
4283/* l4_per -> timer3 */
4284static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4285 .master = &omap44xx_l4_per_hwmod,
4286 .slave = &omap44xx_timer3_hwmod,
4287 .clk = "l4_div_ck",
4288 .addr = omap44xx_timer3_addrs,
35d1a66a
BC		 4289 .user = OCP_USER_MPU | OCP_USER_SDMA,
4290};
4291
4292/* timer3 slave ports */
4293static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4294 &omap44xx_l4_per__timer3,
4295};
4296
4297static struct omap_hwmod omap44xx_timer3_hwmod = {
4298 .name = "timer3",
4299 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4300 .clkdm_name = "l4_per_clkdm",
35d1a66a 4301 .mpu_irqs = omap44xx_timer3_irqs,
35d1a66a
BC		 4302 .main_clk = "timer3_fck",
4303 .prcm = {
4304 .omap4 = {
d0f0631d 4305 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
35d1a66a
BC		 4306 },
4307 },
4308 .slaves = omap44xx_timer3_slaves,
4309 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4311};
4312
4313/* timer4 */
4314static struct omap_hwmod omap44xx_timer4_hwmod;
4315static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4316 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
212738a4 4317 { .irq = -1 }
35d1a66a
BC		 4318};
4319
4320static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4321 {
4322 .pa_start = 0x48036000,
4323 .pa_end = 0x4803607f,
4324 .flags = ADDR_TYPE_RT
4325 },
78183f3f 4326 { }
35d1a66a
BC		 4327};
4328
4329/* l4_per -> timer4 */
4330static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4331 .master = &omap44xx_l4_per_hwmod,
4332 .slave = &omap44xx_timer4_hwmod,
4333 .clk = "l4_div_ck",
4334 .addr = omap44xx_timer4_addrs,
35d1a66a
BC		 4335 .user = OCP_USER_MPU | OCP_USER_SDMA,
4336};
4337
4338/* timer4 slave ports */
4339static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4340 &omap44xx_l4_per__timer4,
4341};
4342
4343static struct omap_hwmod omap44xx_timer4_hwmod = {
4344 .name = "timer4",
4345 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4346 .clkdm_name = "l4_per_clkdm",
35d1a66a 4347 .mpu_irqs = omap44xx_timer4_irqs,
35d1a66a
BC		 4348 .main_clk = "timer4_fck",
4349 .prcm = {
4350 .omap4 = {
d0f0631d 4351 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
35d1a66a
BC		 4352 },
4353 },
4354 .slaves = omap44xx_timer4_slaves,
4355 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4356 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4357};
4358
4359/* timer5 */
4360static struct omap_hwmod omap44xx_timer5_hwmod;
4361static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4362 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
212738a4 4363 { .irq = -1 }
35d1a66a
BC		 4364};
4365
4366static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4367 {
4368 .pa_start = 0x40138000,
4369 .pa_end = 0x4013807f,
4370 .flags = ADDR_TYPE_RT
4371 },
78183f3f 4372 { }
35d1a66a
BC		 4373};
4374
4375/* l4_abe -> timer5 */
4376static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4377 .master = &omap44xx_l4_abe_hwmod,
4378 .slave = &omap44xx_timer5_hwmod,
4379 .clk = "ocp_abe_iclk",
4380 .addr = omap44xx_timer5_addrs,
35d1a66a
BC		 4381 .user = OCP_USER_MPU,
4382};
4383
4384static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4385 {
4386 .pa_start = 0x49038000,
4387 .pa_end = 0x4903807f,
4388 .flags = ADDR_TYPE_RT
4389 },
78183f3f 4390 { }
35d1a66a
BC		 4391};
4392
4393/* l4_abe -> timer5 (dma) */
4394static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4395 .master = &omap44xx_l4_abe_hwmod,
4396 .slave = &omap44xx_timer5_hwmod,
4397 .clk = "ocp_abe_iclk",
4398 .addr = omap44xx_timer5_dma_addrs,
35d1a66a
BC		 4399 .user = OCP_USER_SDMA,
4400};
4401
4402/* timer5 slave ports */
4403static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4404 &omap44xx_l4_abe__timer5,
4405 &omap44xx_l4_abe__timer5_dma,
4406};
4407
4408static struct omap_hwmod omap44xx_timer5_hwmod = {
4409 .name = "timer5",
4410 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4411 .clkdm_name = "abe_clkdm",
35d1a66a 4412 .mpu_irqs = omap44xx_timer5_irqs,
35d1a66a
BC		 4413 .main_clk = "timer5_fck",
4414 .prcm = {
4415 .omap4 = {
d0f0631d 4416 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
35d1a66a
BC		 4417 },
4418 },
4419 .slaves = omap44xx_timer5_slaves,
4420 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4421 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4422};
4423
4424/* timer6 */
4425static struct omap_hwmod omap44xx_timer6_hwmod;
4426static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4427 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
212738a4 4428 { .irq = -1 }
35d1a66a
BC		 4429};
4430
4431static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4432 {
4433 .pa_start = 0x4013a000,
4434 .pa_end = 0x4013a07f,
4435 .flags = ADDR_TYPE_RT
4436 },
78183f3f 4437 { }
35d1a66a
BC		 4438};
4439
4440/* l4_abe -> timer6 */
4441static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4442 .master = &omap44xx_l4_abe_hwmod,
4443 .slave = &omap44xx_timer6_hwmod,
4444 .clk = "ocp_abe_iclk",
4445 .addr = omap44xx_timer6_addrs,
35d1a66a
BC		 4446 .user = OCP_USER_MPU,
4447};
4448
4449static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4450 {
4451 .pa_start = 0x4903a000,
4452 .pa_end = 0x4903a07f,
4453 .flags = ADDR_TYPE_RT
4454 },
78183f3f 4455 { }
35d1a66a
BC		 4456};
4457
4458/* l4_abe -> timer6 (dma) */
4459static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4460 .master = &omap44xx_l4_abe_hwmod,
4461 .slave = &omap44xx_timer6_hwmod,
4462 .clk = "ocp_abe_iclk",
4463 .addr = omap44xx_timer6_dma_addrs,
35d1a66a
BC		 4464 .user = OCP_USER_SDMA,
4465};
4466
4467/* timer6 slave ports */
4468static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4469 &omap44xx_l4_abe__timer6,
4470 &omap44xx_l4_abe__timer6_dma,
4471};
4472
4473static struct omap_hwmod omap44xx_timer6_hwmod = {
4474 .name = "timer6",
4475 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4476 .clkdm_name = "abe_clkdm",
35d1a66a 4477 .mpu_irqs = omap44xx_timer6_irqs,
212738a4 4478
35d1a66a
BC		 4479 .main_clk = "timer6_fck",
4480 .prcm = {
4481 .omap4 = {
d0f0631d 4482 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
35d1a66a
BC		 4483 },
4484 },
4485 .slaves = omap44xx_timer6_slaves,
4486 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4487 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4488};
4489
4490/* timer7 */
4491static struct omap_hwmod omap44xx_timer7_hwmod;
4492static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4493 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
212738a4 4494 { .irq = -1 }
35d1a66a
BC		 4495};
4496
4497static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4498 {
4499 .pa_start = 0x4013c000,
4500 .pa_end = 0x4013c07f,
4501 .flags = ADDR_TYPE_RT
4502 },
78183f3f 4503 { }
35d1a66a
BC		 4504};
4505
4506/* l4_abe -> timer7 */
4507static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4508 .master = &omap44xx_l4_abe_hwmod,
4509 .slave = &omap44xx_timer7_hwmod,
4510 .clk = "ocp_abe_iclk",
4511 .addr = omap44xx_timer7_addrs,
35d1a66a
BC		 4512 .user = OCP_USER_MPU,
4513};
4514
4515static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4516 {
4517 .pa_start = 0x4903c000,
4518 .pa_end = 0x4903c07f,
4519 .flags = ADDR_TYPE_RT
4520 },
78183f3f 4521 { }
35d1a66a
BC		 4522};
4523
4524/* l4_abe -> timer7 (dma) */
4525static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4526 .master = &omap44xx_l4_abe_hwmod,
4527 .slave = &omap44xx_timer7_hwmod,
4528 .clk = "ocp_abe_iclk",
4529 .addr = omap44xx_timer7_dma_addrs,
35d1a66a
BC		 4530 .user = OCP_USER_SDMA,
4531};
4532
4533/* timer7 slave ports */
4534static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4535 &omap44xx_l4_abe__timer7,
4536 &omap44xx_l4_abe__timer7_dma,
4537};
4538
4539static struct omap_hwmod omap44xx_timer7_hwmod = {
4540 .name = "timer7",
4541 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4542 .clkdm_name = "abe_clkdm",
35d1a66a 4543 .mpu_irqs = omap44xx_timer7_irqs,
35d1a66a
BC		 4544 .main_clk = "timer7_fck",
4545 .prcm = {
4546 .omap4 = {
d0f0631d 4547 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
35d1a66a
BC		 4548 },
4549 },
4550 .slaves = omap44xx_timer7_slaves,
4551 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4552 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4553};
4554
4555/* timer8 */
4556static struct omap_hwmod omap44xx_timer8_hwmod;
4557static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4558 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
212738a4 4559 { .irq = -1 }
35d1a66a
BC		 4560};
4561
4562static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4563 {
4564 .pa_start = 0x4013e000,
4565 .pa_end = 0x4013e07f,
4566 .flags = ADDR_TYPE_RT
4567 },
78183f3f 4568 { }
35d1a66a
BC		 4569};
4570
4571/* l4_abe -> timer8 */
4572static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4573 .master = &omap44xx_l4_abe_hwmod,
4574 .slave = &omap44xx_timer8_hwmod,
4575 .clk = "ocp_abe_iclk",
4576 .addr = omap44xx_timer8_addrs,
35d1a66a
BC		 4577 .user = OCP_USER_MPU,
4578};
4579
4580static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4581 {
4582 .pa_start = 0x4903e000,
4583 .pa_end = 0x4903e07f,
4584 .flags = ADDR_TYPE_RT
4585 },
78183f3f 4586 { }
35d1a66a
BC		 4587};
4588
4589/* l4_abe -> timer8 (dma) */
4590static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4591 .master = &omap44xx_l4_abe_hwmod,
4592 .slave = &omap44xx_timer8_hwmod,
4593 .clk = "ocp_abe_iclk",
4594 .addr = omap44xx_timer8_dma_addrs,
35d1a66a
BC		 4595 .user = OCP_USER_SDMA,
4596};
4597
4598/* timer8 slave ports */
4599static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4600 &omap44xx_l4_abe__timer8,
4601 &omap44xx_l4_abe__timer8_dma,
4602};
4603
4604static struct omap_hwmod omap44xx_timer8_hwmod = {
4605 .name = "timer8",
4606 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4607 .clkdm_name = "abe_clkdm",
35d1a66a 4608 .mpu_irqs = omap44xx_timer8_irqs,
35d1a66a
BC		 4609 .main_clk = "timer8_fck",
4610 .prcm = {
4611 .omap4 = {
d0f0631d 4612 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
35d1a66a
BC		 4613 },
4614 },
4615 .slaves = omap44xx_timer8_slaves,
4616 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4618};
4619
4620/* timer9 */
4621static struct omap_hwmod omap44xx_timer9_hwmod;
4622static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4623 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
212738a4 4624 { .irq = -1 }
35d1a66a
BC		 4625};
4626
4627static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4628 {
4629 .pa_start = 0x4803e000,
4630 .pa_end = 0x4803e07f,
4631 .flags = ADDR_TYPE_RT
4632 },
78183f3f 4633 { }
35d1a66a
BC		 4634};
4635
4636/* l4_per -> timer9 */
4637static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4638 .master = &omap44xx_l4_per_hwmod,
4639 .slave = &omap44xx_timer9_hwmod,
4640 .clk = "l4_div_ck",
4641 .addr = omap44xx_timer9_addrs,
35d1a66a
BC		 4642 .user = OCP_USER_MPU | OCP_USER_SDMA,
4643};
4644
4645/* timer9 slave ports */
4646static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4647 &omap44xx_l4_per__timer9,
4648};
4649
4650static struct omap_hwmod omap44xx_timer9_hwmod = {
4651 .name = "timer9",
4652 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4653 .clkdm_name = "l4_per_clkdm",
35d1a66a 4654 .mpu_irqs = omap44xx_timer9_irqs,
35d1a66a
BC		 4655 .main_clk = "timer9_fck",
4656 .prcm = {
4657 .omap4 = {
d0f0631d 4658 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
35d1a66a
BC		 4659 },
4660 },
4661 .slaves = omap44xx_timer9_slaves,
4662 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4663 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4664};
4665
4666/* timer10 */
4667static struct omap_hwmod omap44xx_timer10_hwmod;
4668static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4669 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
212738a4 4670 { .irq = -1 }
35d1a66a
BC		 4671};
4672
4673static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4674 {
4675 .pa_start = 0x48086000,
4676 .pa_end = 0x4808607f,
4677 .flags = ADDR_TYPE_RT
4678 },
78183f3f 4679 { }
35d1a66a
BC		 4680};
4681
4682/* l4_per -> timer10 */
4683static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4684 .master = &omap44xx_l4_per_hwmod,
4685 .slave = &omap44xx_timer10_hwmod,
4686 .clk = "l4_div_ck",
4687 .addr = omap44xx_timer10_addrs,
35d1a66a
BC		 4688 .user = OCP_USER_MPU | OCP_USER_SDMA,
4689};
4690
4691/* timer10 slave ports */
4692static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4693 &omap44xx_l4_per__timer10,
4694};
4695
4696static struct omap_hwmod omap44xx_timer10_hwmod = {
4697 .name = "timer10",
4698 .class = &omap44xx_timer_1ms_hwmod_class,
a5322c6f 4699 .clkdm_name = "l4_per_clkdm",
35d1a66a 4700 .mpu_irqs = omap44xx_timer10_irqs,
35d1a66a
BC		 4701 .main_clk = "timer10_fck",
4702 .prcm = {
4703 .omap4 = {
d0f0631d 4704 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
35d1a66a
BC		 4705 },
4706 },
4707 .slaves = omap44xx_timer10_slaves,
4708 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4710};
4711
4712/* timer11 */
4713static struct omap_hwmod omap44xx_timer11_hwmod;
4714static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4715 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
212738a4 4716 { .irq = -1 }
35d1a66a
BC		 4717};
4718
4719static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4720 {
4721 .pa_start = 0x48088000,
4722 .pa_end = 0x4808807f,
4723 .flags = ADDR_TYPE_RT
4724 },
78183f3f 4725 { }
35d1a66a
BC		 4726};
4727
4728/* l4_per -> timer11 */
4729static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4730 .master = &omap44xx_l4_per_hwmod,
4731 .slave = &omap44xx_timer11_hwmod,
4732 .clk = "l4_div_ck",
4733 .addr = omap44xx_timer11_addrs,
35d1a66a
BC		 4734 .user = OCP_USER_MPU | OCP_USER_SDMA,
4735};
4736
4737/* timer11 slave ports */
4738static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4739 &omap44xx_l4_per__timer11,
4740};
4741
4742static struct omap_hwmod omap44xx_timer11_hwmod = {
4743 .name = "timer11",
4744 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4745 .clkdm_name = "l4_per_clkdm",
35d1a66a 4746 .mpu_irqs = omap44xx_timer11_irqs,
35d1a66a
BC		 4747 .main_clk = "timer11_fck",
4748 .prcm = {
4749 .omap4 = {
d0f0631d 4750 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
35d1a66a
BC		 4751 },
4752 },
4753 .slaves = omap44xx_timer11_slaves,
4754 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4755 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4756};
4757
9780a9cf 4758/*
3b54baad
BC		 4759 * 'uart' class
4760 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 4761 */
4762
3b54baad
BC		 4763static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4764 .rev_offs = 0x0050,
4765 .sysc_offs = 0x0054,
4766 .syss_offs = 0x0058,
4767 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 4768 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4769 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4771 SIDLE_SMART_WKUP),
9780a9cf
BC		 4772 .sysc_fields = &omap_hwmod_sysc_type1,
4773};
4774
3b54baad 4775static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 4776 .name = "uart",
4777 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 4778};
4779
3b54baad
BC		 4780/* uart1 */
4781static struct omap_hwmod omap44xx_uart1_hwmod;
4782static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4783 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
212738a4 4784 { .irq = -1 }
9780a9cf
BC		 4785};
4786
3b54baad
BC		 4787static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4788 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4789 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
bc614958 4790 { .dma_req = -1 }
9780a9cf
BC		 4791};
4792
3b54baad 4793static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 4794 {
3b54baad
BC		 4795 .pa_start = 0x4806a000,
4796 .pa_end = 0x4806a0ff,
9780a9cf
BC		 4797 .flags = ADDR_TYPE_RT
4798 },
78183f3f 4799 { }
9780a9cf
BC		 4800};
4801
3b54baad
BC		 4802/* l4_per -> uart1 */
4803static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4804 .master = &omap44xx_l4_per_hwmod,
4805 .slave = &omap44xx_uart1_hwmod,
4806 .clk = "l4_div_ck",
4807 .addr = omap44xx_uart1_addrs,
9780a9cf
BC		 4808 .user = OCP_USER_MPU | OCP_USER_SDMA,
4809};
4810
3b54baad
BC		 4811/* uart1 slave ports */
4812static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4813 &omap44xx_l4_per__uart1,
9780a9cf
BC		 4814};
4815
3b54baad
BC		 4816static struct omap_hwmod omap44xx_uart1_hwmod = {
4817 .name = "uart1",
4818 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4819 .clkdm_name = "l4_per_clkdm",
3b54baad 4820 .mpu_irqs = omap44xx_uart1_irqs,
3b54baad 4821 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3b54baad 4822 .main_clk = "uart1_fck",
9780a9cf
BC		 4823 .prcm = {
4824 .omap4 = {
d0f0631d 4825 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
9780a9cf
BC		 4826 },
4827 },
3b54baad
BC		 4828 .slaves = omap44xx_uart1_slaves,
4829 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 4830 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4831};
4832
3b54baad
BC		 4833/* uart2 */
4834static struct omap_hwmod omap44xx_uart2_hwmod;
4835static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4836 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
212738a4 4837 { .irq = -1 }
9780a9cf
BC		 4838};
4839
3b54baad
BC		 4840static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4841 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4842 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
bc614958 4843 { .dma_req = -1 }
3b54baad
BC		 4844};
4845
4846static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 4847 {
3b54baad
BC		 4848 .pa_start = 0x4806c000,
4849 .pa_end = 0x4806c0ff,
9780a9cf
BC		 4850 .flags = ADDR_TYPE_RT
4851 },
78183f3f 4852 { }
9780a9cf
BC		 4853};
4854
3b54baad
BC		 4855/* l4_per -> uart2 */
4856static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 4857 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4858 .slave = &omap44xx_uart2_hwmod,
4859 .clk = "l4_div_ck",
4860 .addr = omap44xx_uart2_addrs,
9780a9cf
BC		 4861 .user = OCP_USER_MPU | OCP_USER_SDMA,
4862};
4863
3b54baad
BC		 4864/* uart2 slave ports */
4865static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4866 &omap44xx_l4_per__uart2,
9780a9cf
BC		 4867};
4868
3b54baad
BC		 4869static struct omap_hwmod omap44xx_uart2_hwmod = {
4870 .name = "uart2",
4871 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4872 .clkdm_name = "l4_per_clkdm",
3b54baad 4873 .mpu_irqs = omap44xx_uart2_irqs,
3b54baad 4874 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3b54baad 4875 .main_clk = "uart2_fck",
9780a9cf
BC		 4876 .prcm = {
4877 .omap4 = {
d0f0631d 4878 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
9780a9cf
BC		 4879 },
4880 },
3b54baad
BC		 4881 .slaves = omap44xx_uart2_slaves,
4882 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 4883 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4884};
4885
3b54baad
BC		 4886/* uart3 */
4887static struct omap_hwmod omap44xx_uart3_hwmod;
4888static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4889 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
212738a4 4890 { .irq = -1 }
9780a9cf
BC		 4891};
4892
3b54baad
BC		 4893static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4894 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4895 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
bc614958 4896 { .dma_req = -1 }
3b54baad
BC		 4897};
4898
4899static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 4900 {
3b54baad
BC		 4901 .pa_start = 0x48020000,
4902 .pa_end = 0x480200ff,
9780a9cf
BC		 4903 .flags = ADDR_TYPE_RT
4904 },
78183f3f 4905 { }
9780a9cf
BC		 4906};
4907
3b54baad
BC		 4908/* l4_per -> uart3 */
4909static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 4910 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4911 .slave = &omap44xx_uart3_hwmod,
4912 .clk = "l4_div_ck",
4913 .addr = omap44xx_uart3_addrs,
9780a9cf
BC		 4914 .user = OCP_USER_MPU | OCP_USER_SDMA,
4915};
4916
3b54baad
BC		 4917/* uart3 slave ports */
4918static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4919 &omap44xx_l4_per__uart3,
4920};
4921
4922static struct omap_hwmod omap44xx_uart3_hwmod = {
4923 .name = "uart3",
4924 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4925 .clkdm_name = "l4_per_clkdm",
7ecc5373 4926 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 4927 .mpu_irqs = omap44xx_uart3_irqs,
3b54baad 4928 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3b54baad 4929 .main_clk = "uart3_fck",
9780a9cf
BC		 4930 .prcm = {
4931 .omap4 = {
d0f0631d 4932 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
9780a9cf
BC		 4933 },
4934 },
3b54baad
BC		 4935 .slaves = omap44xx_uart3_slaves,
4936 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 4937 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4938};
4939
3b54baad
BC		 4940/* uart4 */
4941static struct omap_hwmod omap44xx_uart4_hwmod;
4942static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4943 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
212738a4 4944 { .irq = -1 }
9780a9cf
BC		 4945};
4946
3b54baad
BC		 4947static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4948 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4949 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
bc614958 4950 { .dma_req = -1 }
3b54baad
BC		 4951};
4952
4953static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 4954 {
3b54baad
BC		 4955 .pa_start = 0x4806e000,
4956 .pa_end = 0x4806e0ff,
9780a9cf
BC		 4957 .flags = ADDR_TYPE_RT
4958 },
78183f3f 4959 { }
9780a9cf
BC		 4960};
4961
3b54baad
BC		 4962/* l4_per -> uart4 */
4963static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 4964 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4965 .slave = &omap44xx_uart4_hwmod,
4966 .clk = "l4_div_ck",
4967 .addr = omap44xx_uart4_addrs,
9780a9cf
BC		 4968 .user = OCP_USER_MPU | OCP_USER_SDMA,
4969};
4970
3b54baad
BC		 4971/* uart4 slave ports */
4972static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4973 &omap44xx_l4_per__uart4,
9780a9cf
BC		 4974};
4975
3b54baad
BC		 4976static struct omap_hwmod omap44xx_uart4_hwmod = {
4977 .name = "uart4",
4978 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4979 .clkdm_name = "l4_per_clkdm",
3b54baad 4980 .mpu_irqs = omap44xx_uart4_irqs,
3b54baad 4981 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3b54baad 4982 .main_clk = "uart4_fck",
9780a9cf
BC		 4983 .prcm = {
4984 .omap4 = {
d0f0631d 4985 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
9780a9cf
BC		 4986 },
4987 },
3b54baad
BC		 4988 .slaves = omap44xx_uart4_slaves,
4989 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 4990 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4991};
4992
5844c4ea
BC		 4993/*
4994 * 'usb_otg_hs' class
4995 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4996 */
4997
4998static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4999 .rev_offs = 0x0400,
5000 .sysc_offs = 0x0404,
5001 .syss_offs = 0x0408,
5002 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5003 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5004 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5005 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5006 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5007 MSTANDBY_SMART),
5008 .sysc_fields = &omap_hwmod_sysc_type1,
5009};
5010
5011static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
00fe610b
BC		 5012 .name = "usb_otg_hs",
5013 .sysc = &omap44xx_usb_otg_hs_sysc,
5844c4ea
BC		 5014};
5015
5016/* usb_otg_hs */
5017static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5018 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5019 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
212738a4 5020 { .irq = -1 }
5844c4ea
BC		 5021};
5022
5023/* usb_otg_hs master ports */
5024static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5025 &omap44xx_usb_otg_hs__l3_main_2,
5026};
5027
5028static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5029 {
5030 .pa_start = 0x4a0ab000,
5031 .pa_end = 0x4a0ab003,
5032 .flags = ADDR_TYPE_RT
5033 },
78183f3f 5034 { }
5844c4ea
BC		 5035};
5036
5037/* l4_cfg -> usb_otg_hs */
5038static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5039 .master = &omap44xx_l4_cfg_hwmod,
5040 .slave = &omap44xx_usb_otg_hs_hwmod,
5041 .clk = "l4_div_ck",
5042 .addr = omap44xx_usb_otg_hs_addrs,
5844c4ea
BC		 5043 .user = OCP_USER_MPU | OCP_USER_SDMA,
5044};
5045
5046/* usb_otg_hs slave ports */
5047static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5048 &omap44xx_l4_cfg__usb_otg_hs,
5049};
5050
5051static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5052 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5053};
5054
5055static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5056 .name = "usb_otg_hs",
5057 .class = &omap44xx_usb_otg_hs_hwmod_class,
a5322c6f 5058 .clkdm_name = "l3_init_clkdm",
5844c4ea
BC		 5059 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5060 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5844c4ea
BC		 5061 .main_clk = "usb_otg_hs_ick",
5062 .prcm = {
5063 .omap4 = {
d0f0631d 5064 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5844c4ea
BC		 5065 },
5066 },
5067 .opt_clks = usb_otg_hs_opt_clks,
00fe610b 5068 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5844c4ea
BC		 5069 .slaves = omap44xx_usb_otg_hs_slaves,
5070 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5071 .masters = omap44xx_usb_otg_hs_masters,
5072 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5073 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5074};
5075
3b54baad
BC		 5076/*
5077 * 'wd_timer' class
5078 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5079 * overflow condition
5080 */
5081
5082static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5083 .rev_offs = 0x0000,
5084 .sysc_offs = 0x0010,
5085 .syss_offs = 0x0014,
5086 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 5087 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 5088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5089 SIDLE_SMART_WKUP),
3b54baad 5090 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 5091};
5092
3b54baad
BC		 5093static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5094 .name = "wd_timer",
5095 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 5096 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 5097};
5098
5099/* wd_timer2 */
5100static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5101static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5102 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
212738a4 5103 { .irq = -1 }
3b54baad
BC		 5104};
5105
5106static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 5107 {
3b54baad
BC		 5108 .pa_start = 0x4a314000,
5109 .pa_end = 0x4a31407f,
9780a9cf
BC		 5110 .flags = ADDR_TYPE_RT
5111 },
78183f3f 5112 { }
9780a9cf
BC		 5113};
5114
3b54baad
BC		 5115/* l4_wkup -> wd_timer2 */
5116static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5117 .master = &omap44xx_l4_wkup_hwmod,
5118 .slave = &omap44xx_wd_timer2_hwmod,
5119 .clk = "l4_wkup_clk_mux_ck",
5120 .addr = omap44xx_wd_timer2_addrs,
9780a9cf
BC		 5121 .user = OCP_USER_MPU | OCP_USER_SDMA,
5122};
5123
3b54baad
BC		 5124/* wd_timer2 slave ports */
5125static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5126 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 5127};
5128
3b54baad
BC		 5129static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5130 .name = "wd_timer2",
5131 .class = &omap44xx_wd_timer_hwmod_class,
a5322c6f 5132 .clkdm_name = "l4_wkup_clkdm",
3b54baad 5133 .mpu_irqs = omap44xx_wd_timer2_irqs,
3b54baad 5134 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 5135 .prcm = {
5136 .omap4 = {
d0f0631d 5137 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
9780a9cf
BC		 5138 },
5139 },
3b54baad
BC		 5140 .slaves = omap44xx_wd_timer2_slaves,
5141 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 5142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5143};
5144
3b54baad
BC		 5145/* wd_timer3 */
5146static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5147static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5148 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
212738a4 5149 { .irq = -1 }
9780a9cf
BC		 5150};
5151
3b54baad 5152static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 5153 {
3b54baad
BC		 5154 .pa_start = 0x40130000,
5155 .pa_end = 0x4013007f,
9780a9cf
BC		 5156 .flags = ADDR_TYPE_RT
5157 },
78183f3f 5158 { }
9780a9cf
BC		 5159};
5160
3b54baad
BC		 5161/* l4_abe -> wd_timer3 */
5162static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5163 .master = &omap44xx_l4_abe_hwmod,
5164 .slave = &omap44xx_wd_timer3_hwmod,
5165 .clk = "ocp_abe_iclk",
5166 .addr = omap44xx_wd_timer3_addrs,
3b54baad 5167 .user = OCP_USER_MPU,
9780a9cf
BC		 5168};
5169
3b54baad
BC		 5170static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5171 {
5172 .pa_start = 0x49030000,
5173 .pa_end = 0x4903007f,
5174 .flags = ADDR_TYPE_RT
5175 },
78183f3f 5176 { }
9780a9cf
BC		 5177};
5178
3b54baad
BC		 5179/* l4_abe -> wd_timer3 (dma) */
5180static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5181 .master = &omap44xx_l4_abe_hwmod,
5182 .slave = &omap44xx_wd_timer3_hwmod,
5183 .clk = "ocp_abe_iclk",
5184 .addr = omap44xx_wd_timer3_dma_addrs,
3b54baad 5185 .user = OCP_USER_SDMA,
9780a9cf
BC		 5186};
5187
3b54baad
BC		 5188/* wd_timer3 slave ports */
5189static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5190 &omap44xx_l4_abe__wd_timer3,
5191 &omap44xx_l4_abe__wd_timer3_dma,
5192};
5193
5194static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5195 .name = "wd_timer3",
5196 .class = &omap44xx_wd_timer_hwmod_class,
a5322c6f 5197 .clkdm_name = "abe_clkdm",
3b54baad 5198 .mpu_irqs = omap44xx_wd_timer3_irqs,
3b54baad 5199 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 5200 .prcm = {
5201 .omap4 = {
d0f0631d 5202 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
9780a9cf
BC		 5203 },
5204 },
3b54baad
BC		 5205 .slaves = omap44xx_wd_timer3_slaves,
5206 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 5207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5208};
531ce0d5 5209
55d2cb08 5210static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 5211
55d2cb08
BC		 5212 /* dmm class */
5213 &omap44xx_dmm_hwmod,
3b54baad 5214
55d2cb08
BC		 5215 /* emif_fw class */
5216 &omap44xx_emif_fw_hwmod,
3b54baad 5217
55d2cb08
BC		 5218 /* l3 class */
5219 &omap44xx_l3_instr_hwmod,
5220 &omap44xx_l3_main_1_hwmod,
5221 &omap44xx_l3_main_2_hwmod,
5222 &omap44xx_l3_main_3_hwmod,
3b54baad 5223
55d2cb08
BC		 5224 /* l4 class */
5225 &omap44xx_l4_abe_hwmod,
5226 &omap44xx_l4_cfg_hwmod,
5227 &omap44xx_l4_per_hwmod,
5228 &omap44xx_l4_wkup_hwmod,
531ce0d5 5229
55d2cb08
BC		 5230 /* mpu_bus class */
5231 &omap44xx_mpu_private_hwmod,
5232
407a6888
BC		 5233 /* aess class */
5234/* &omap44xx_aess_hwmod, */
5235
5236 /* bandgap class */
5237 &omap44xx_bandgap_hwmod,
5238
5239 /* counter class */
5240/* &omap44xx_counter_32k_hwmod, */
5241
d7cf5f33
BC		 5242 /* dma class */
5243 &omap44xx_dma_system_hwmod,
5244
8ca476da
BC		 5245 /* dmic class */
5246 &omap44xx_dmic_hwmod,
5247
8f25bdc5
BC		 5248 /* dsp class */
5249 &omap44xx_dsp_hwmod,
5250 &omap44xx_dsp_c0_hwmod,
5251
d63bd74f
BC		 5252 /* dss class */
5253 &omap44xx_dss_hwmod,
5254 &omap44xx_dss_dispc_hwmod,
5255 &omap44xx_dss_dsi1_hwmod,
5256 &omap44xx_dss_dsi2_hwmod,
5257 &omap44xx_dss_hdmi_hwmod,
5258 &omap44xx_dss_rfbi_hwmod,
5259 &omap44xx_dss_venc_hwmod,
5260
9780a9cf
BC		 5261 /* gpio class */
5262 &omap44xx_gpio1_hwmod,
5263 &omap44xx_gpio2_hwmod,
5264 &omap44xx_gpio3_hwmod,
5265 &omap44xx_gpio4_hwmod,
5266 &omap44xx_gpio5_hwmod,
5267 &omap44xx_gpio6_hwmod,
5268
407a6888
BC		 5269 /* hsi class */
5270/* &omap44xx_hsi_hwmod, */
5271
3b54baad
BC		 5272 /* i2c class */
5273 &omap44xx_i2c1_hwmod,
5274 &omap44xx_i2c2_hwmod,
5275 &omap44xx_i2c3_hwmod,
5276 &omap44xx_i2c4_hwmod,
5277
407a6888
BC		 5278 /* ipu class */
5279 &omap44xx_ipu_hwmod,
5280 &omap44xx_ipu_c0_hwmod,
5281 &omap44xx_ipu_c1_hwmod,
5282
5283 /* iss class */
5284/* &omap44xx_iss_hwmod, */
5285
8f25bdc5
BC		 5286 /* iva class */
5287 &omap44xx_iva_hwmod,
5288 &omap44xx_iva_seq0_hwmod,
5289 &omap44xx_iva_seq1_hwmod,
5290
407a6888 5291 /* kbd class */
4998b245 5292 &omap44xx_kbd_hwmod,
407a6888 5293
ec5df927
BC		 5294 /* mailbox class */
5295 &omap44xx_mailbox_hwmod,
5296
4ddff493
BC		 5297 /* mcbsp class */
5298 &omap44xx_mcbsp1_hwmod,
5299 &omap44xx_mcbsp2_hwmod,
5300 &omap44xx_mcbsp3_hwmod,
5301 &omap44xx_mcbsp4_hwmod,
5302
407a6888
BC		 5303 /* mcpdm class */
5304/* &omap44xx_mcpdm_hwmod, */
5305
9bcbd7f0
BC		 5306 /* mcspi class */
5307 &omap44xx_mcspi1_hwmod,
5308 &omap44xx_mcspi2_hwmod,
5309 &omap44xx_mcspi3_hwmod,
5310 &omap44xx_mcspi4_hwmod,
5311
407a6888 5312 /* mmc class */
17203bda
AG		 5313 &omap44xx_mmc1_hwmod,
5314 &omap44xx_mmc2_hwmod,
5315 &omap44xx_mmc3_hwmod,
5316 &omap44xx_mmc4_hwmod,
5317 &omap44xx_mmc5_hwmod,
407a6888 5318
55d2cb08
BC		 5319 /* mpu class */
5320 &omap44xx_mpu_hwmod,
db12ba53 5321
1f6a717f
BC		 5322 /* smartreflex class */
5323 &omap44xx_smartreflex_core_hwmod,
5324 &omap44xx_smartreflex_iva_hwmod,
5325 &omap44xx_smartreflex_mpu_hwmod,
5326
d11c217f
BC		 5327 /* spinlock class */
5328 &omap44xx_spinlock_hwmod,
5329
35d1a66a
BC		 5330 /* timer class */
5331 &omap44xx_timer1_hwmod,
5332 &omap44xx_timer2_hwmod,
5333 &omap44xx_timer3_hwmod,
5334 &omap44xx_timer4_hwmod,
5335 &omap44xx_timer5_hwmod,
5336 &omap44xx_timer6_hwmod,
5337 &omap44xx_timer7_hwmod,
5338 &omap44xx_timer8_hwmod,
5339 &omap44xx_timer9_hwmod,
5340 &omap44xx_timer10_hwmod,
5341 &omap44xx_timer11_hwmod,
5342
db12ba53
BC		 5343 /* uart class */
5344 &omap44xx_uart1_hwmod,
5345 &omap44xx_uart2_hwmod,
5346 &omap44xx_uart3_hwmod,
5347 &omap44xx_uart4_hwmod,
3b54baad 5348
5844c4ea
BC		 5349 /* usb_otg_hs class */
5350 &omap44xx_usb_otg_hs_hwmod,
5351
3b54baad
BC		 5352 /* wd_timer class */
5353 &omap44xx_wd_timer2_hwmod,
5354 &omap44xx_wd_timer3_hwmod,
5355
55d2cb08
BC		 5356 NULL,
5357};
5358
5359int __init omap44xx_hwmod_init(void)
5360{
550c8092 5361 return omap_hwmod_register(omap44xx_hwmods);
55d2cb08
BC		 5362}
5363
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