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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
d63bd74f | 4 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
6d3c55fd | 25 | #include <plat/i2c.h> |
9780a9cf | 26 | #include <plat/gpio.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
4d4441a6 | 31 | #include <plat/i2c.h> |
c345c8b0 | 32 | #include <plat/dmtimer.h> |
13662dc5 | 33 | #include <plat/common.h> |
55d2cb08 BC |
34 | |
35 | #include "omap_hwmod_common_data.h" | |
36 | ||
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
ff2516fb | 41 | #include "wd_timer.h" |
55d2cb08 BC |
42 | |
43 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
44 | #define OMAP44XX_IRQ_GIC_START 32 | |
45 | ||
46 | /* Base offset for all OMAP4 dma requests */ | |
47 | #define OMAP44XX_DMA_REQ_START 1 | |
48 | ||
49 | /* Backward references (IPs with Bus Master capability) */ | |
407a6888 | 50 | static struct omap_hwmod omap44xx_aess_hwmod; |
531ce0d5 | 51 | static struct omap_hwmod omap44xx_dma_system_hwmod; |
55d2cb08 | 52 | static struct omap_hwmod omap44xx_dmm_hwmod; |
8f25bdc5 | 53 | static struct omap_hwmod omap44xx_dsp_hwmod; |
d63bd74f | 54 | static struct omap_hwmod omap44xx_dss_hwmod; |
55d2cb08 | 55 | static struct omap_hwmod omap44xx_emif_fw_hwmod; |
407a6888 BC |
56 | static struct omap_hwmod omap44xx_hsi_hwmod; |
57 | static struct omap_hwmod omap44xx_ipu_hwmod; | |
58 | static struct omap_hwmod omap44xx_iss_hwmod; | |
8f25bdc5 | 59 | static struct omap_hwmod omap44xx_iva_hwmod; |
55d2cb08 BC |
60 | static struct omap_hwmod omap44xx_l3_instr_hwmod; |
61 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; | |
62 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; | |
63 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; | |
64 | static struct omap_hwmod omap44xx_l4_abe_hwmod; | |
65 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; | |
66 | static struct omap_hwmod omap44xx_l4_per_hwmod; | |
67 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; | |
407a6888 BC |
68 | static struct omap_hwmod omap44xx_mmc1_hwmod; |
69 | static struct omap_hwmod omap44xx_mmc2_hwmod; | |
55d2cb08 BC |
70 | static struct omap_hwmod omap44xx_mpu_hwmod; |
71 | static struct omap_hwmod omap44xx_mpu_private_hwmod; | |
5844c4ea | 72 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; |
af88fa9a BC |
73 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod; |
74 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; | |
55d2cb08 BC |
75 | |
76 | /* | |
77 | * Interconnects omap_hwmod structures | |
78 | * hwmods that compose the global OMAP interconnect | |
79 | */ | |
80 | ||
81 | /* | |
82 | * 'dmm' class | |
83 | * instance(s): dmm | |
84 | */ | |
85 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 86 | .name = "dmm", |
55d2cb08 BC |
87 | }; |
88 | ||
7e69ed97 BC |
89 | /* dmm */ |
90 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
91 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
92 | { .irq = -1 } | |
93 | }; | |
94 | ||
55d2cb08 BC |
95 | /* l3_main_1 -> dmm */ |
96 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
97 | .master = &omap44xx_l3_main_1_hwmod, | |
98 | .slave = &omap44xx_dmm_hwmod, | |
99 | .clk = "l3_div_ck", | |
659fa822 BC |
100 | .user = OCP_USER_SDMA, |
101 | }; | |
102 | ||
103 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { | |
104 | { | |
105 | .pa_start = 0x4e000000, | |
106 | .pa_end = 0x4e0007ff, | |
107 | .flags = ADDR_TYPE_RT | |
108 | }, | |
78183f3f | 109 | { } |
55d2cb08 BC |
110 | }; |
111 | ||
112 | /* mpu -> dmm */ | |
113 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
114 | .master = &omap44xx_mpu_hwmod, | |
115 | .slave = &omap44xx_dmm_hwmod, | |
116 | .clk = "l3_div_ck", | |
659fa822 | 117 | .addr = omap44xx_dmm_addrs, |
659fa822 | 118 | .user = OCP_USER_MPU, |
55d2cb08 BC |
119 | }; |
120 | ||
121 | /* dmm slave ports */ | |
122 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { | |
123 | &omap44xx_l3_main_1__dmm, | |
124 | &omap44xx_mpu__dmm, | |
125 | }; | |
126 | ||
55d2cb08 BC |
127 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
128 | .name = "dmm", | |
129 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 130 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
131 | .prcm = { |
132 | .omap4 = { | |
133 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 134 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
135 | }, |
136 | }, | |
55d2cb08 BC |
137 | .slaves = omap44xx_dmm_slaves, |
138 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | |
a5322c6f | 139 | .mpu_irqs = omap44xx_dmm_irqs, |
55d2cb08 BC |
140 | }; |
141 | ||
142 | /* | |
143 | * 'emif_fw' class | |
144 | * instance(s): emif_fw | |
145 | */ | |
146 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 147 | .name = "emif_fw", |
55d2cb08 BC |
148 | }; |
149 | ||
7e69ed97 | 150 | /* emif_fw */ |
55d2cb08 BC |
151 | /* dmm -> emif_fw */ |
152 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
153 | .master = &omap44xx_dmm_hwmod, | |
154 | .slave = &omap44xx_emif_fw_hwmod, | |
155 | .clk = "l3_div_ck", | |
156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
157 | }; | |
158 | ||
659fa822 BC |
159 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { |
160 | { | |
161 | .pa_start = 0x4a20c000, | |
162 | .pa_end = 0x4a20c0ff, | |
163 | .flags = ADDR_TYPE_RT | |
164 | }, | |
78183f3f | 165 | { } |
659fa822 BC |
166 | }; |
167 | ||
55d2cb08 BC |
168 | /* l4_cfg -> emif_fw */ |
169 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
170 | .master = &omap44xx_l4_cfg_hwmod, | |
171 | .slave = &omap44xx_emif_fw_hwmod, | |
172 | .clk = "l4_div_ck", | |
659fa822 | 173 | .addr = omap44xx_emif_fw_addrs, |
659fa822 | 174 | .user = OCP_USER_MPU, |
55d2cb08 BC |
175 | }; |
176 | ||
177 | /* emif_fw slave ports */ | |
178 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { | |
179 | &omap44xx_dmm__emif_fw, | |
180 | &omap44xx_l4_cfg__emif_fw, | |
181 | }; | |
182 | ||
183 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |
184 | .name = "emif_fw", | |
185 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 186 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
187 | .prcm = { |
188 | .omap4 = { | |
189 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 190 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
191 | }, |
192 | }, | |
55d2cb08 BC |
193 | .slaves = omap44xx_emif_fw_slaves, |
194 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), | |
55d2cb08 BC |
195 | }; |
196 | ||
197 | /* | |
198 | * 'l3' class | |
199 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
200 | */ | |
201 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 202 | .name = "l3", |
55d2cb08 BC |
203 | }; |
204 | ||
7e69ed97 | 205 | /* l3_instr */ |
8f25bdc5 BC |
206 | /* iva -> l3_instr */ |
207 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
208 | .master = &omap44xx_iva_hwmod, | |
209 | .slave = &omap44xx_l3_instr_hwmod, | |
210 | .clk = "l3_div_ck", | |
211 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
212 | }; | |
213 | ||
55d2cb08 BC |
214 | /* l3_main_3 -> l3_instr */ |
215 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
216 | .master = &omap44xx_l3_main_3_hwmod, | |
217 | .slave = &omap44xx_l3_instr_hwmod, | |
218 | .clk = "l3_div_ck", | |
219 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
220 | }; | |
221 | ||
222 | /* l3_instr slave ports */ | |
223 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { | |
8f25bdc5 | 224 | &omap44xx_iva__l3_instr, |
55d2cb08 BC |
225 | &omap44xx_l3_main_3__l3_instr, |
226 | }; | |
227 | ||
228 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |
229 | .name = "l3_instr", | |
230 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 231 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
232 | .prcm = { |
233 | .omap4 = { | |
234 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 235 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 236 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
237 | }, |
238 | }, | |
55d2cb08 BC |
239 | .slaves = omap44xx_l3_instr_slaves, |
240 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), | |
55d2cb08 BC |
241 | }; |
242 | ||
7e69ed97 | 243 | /* l3_main_1 */ |
9b4021be BC |
244 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
245 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
246 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
247 | { .irq = -1 } | |
248 | }; | |
249 | ||
8f25bdc5 BC |
250 | /* dsp -> l3_main_1 */ |
251 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
252 | .master = &omap44xx_dsp_hwmod, | |
253 | .slave = &omap44xx_l3_main_1_hwmod, | |
254 | .clk = "l3_div_ck", | |
255 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
256 | }; | |
257 | ||
d63bd74f BC |
258 | /* dss -> l3_main_1 */ |
259 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
260 | .master = &omap44xx_dss_hwmod, | |
261 | .slave = &omap44xx_l3_main_1_hwmod, | |
262 | .clk = "l3_div_ck", | |
263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
264 | }; | |
265 | ||
55d2cb08 BC |
266 | /* l3_main_2 -> l3_main_1 */ |
267 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
268 | .master = &omap44xx_l3_main_2_hwmod, | |
269 | .slave = &omap44xx_l3_main_1_hwmod, | |
270 | .clk = "l3_div_ck", | |
271 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
272 | }; | |
273 | ||
274 | /* l4_cfg -> l3_main_1 */ | |
275 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
276 | .master = &omap44xx_l4_cfg_hwmod, | |
277 | .slave = &omap44xx_l3_main_1_hwmod, | |
278 | .clk = "l4_div_ck", | |
279 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
280 | }; | |
281 | ||
407a6888 BC |
282 | /* mmc1 -> l3_main_1 */ |
283 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
284 | .master = &omap44xx_mmc1_hwmod, | |
285 | .slave = &omap44xx_l3_main_1_hwmod, | |
286 | .clk = "l3_div_ck", | |
287 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
288 | }; | |
289 | ||
290 | /* mmc2 -> l3_main_1 */ | |
291 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
292 | .master = &omap44xx_mmc2_hwmod, | |
293 | .slave = &omap44xx_l3_main_1_hwmod, | |
294 | .clk = "l3_div_ck", | |
295 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
296 | }; | |
297 | ||
c4645234 | 298 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { |
299 | { | |
300 | .pa_start = 0x44000000, | |
301 | .pa_end = 0x44000fff, | |
9b4021be | 302 | .flags = ADDR_TYPE_RT |
c4645234 | 303 | }, |
78183f3f | 304 | { } |
c4645234 | 305 | }; |
306 | ||
55d2cb08 BC |
307 | /* mpu -> l3_main_1 */ |
308 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
309 | .master = &omap44xx_mpu_hwmod, | |
310 | .slave = &omap44xx_l3_main_1_hwmod, | |
311 | .clk = "l3_div_ck", | |
c4645234 | 312 | .addr = omap44xx_l3_main_1_addrs, |
9b4021be | 313 | .user = OCP_USER_MPU, |
55d2cb08 BC |
314 | }; |
315 | ||
316 | /* l3_main_1 slave ports */ | |
317 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { | |
8f25bdc5 | 318 | &omap44xx_dsp__l3_main_1, |
d63bd74f | 319 | &omap44xx_dss__l3_main_1, |
55d2cb08 BC |
320 | &omap44xx_l3_main_2__l3_main_1, |
321 | &omap44xx_l4_cfg__l3_main_1, | |
407a6888 BC |
322 | &omap44xx_mmc1__l3_main_1, |
323 | &omap44xx_mmc2__l3_main_1, | |
55d2cb08 BC |
324 | &omap44xx_mpu__l3_main_1, |
325 | }; | |
326 | ||
327 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |
328 | .name = "l3_main_1", | |
329 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 330 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 331 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
332 | .prcm = { |
333 | .omap4 = { | |
334 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 335 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
336 | }, |
337 | }, | |
55d2cb08 BC |
338 | .slaves = omap44xx_l3_main_1_slaves, |
339 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | |
55d2cb08 BC |
340 | }; |
341 | ||
7e69ed97 | 342 | /* l3_main_2 */ |
d7cf5f33 BC |
343 | /* dma_system -> l3_main_2 */ |
344 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
345 | .master = &omap44xx_dma_system_hwmod, | |
346 | .slave = &omap44xx_l3_main_2_hwmod, | |
347 | .clk = "l3_div_ck", | |
348 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
349 | }; | |
350 | ||
407a6888 BC |
351 | /* hsi -> l3_main_2 */ |
352 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
353 | .master = &omap44xx_hsi_hwmod, | |
354 | .slave = &omap44xx_l3_main_2_hwmod, | |
355 | .clk = "l3_div_ck", | |
356 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
357 | }; | |
358 | ||
359 | /* ipu -> l3_main_2 */ | |
360 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
361 | .master = &omap44xx_ipu_hwmod, | |
362 | .slave = &omap44xx_l3_main_2_hwmod, | |
363 | .clk = "l3_div_ck", | |
364 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
365 | }; | |
366 | ||
367 | /* iss -> l3_main_2 */ | |
368 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
369 | .master = &omap44xx_iss_hwmod, | |
370 | .slave = &omap44xx_l3_main_2_hwmod, | |
371 | .clk = "l3_div_ck", | |
372 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
373 | }; | |
374 | ||
8f25bdc5 BC |
375 | /* iva -> l3_main_2 */ |
376 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
377 | .master = &omap44xx_iva_hwmod, | |
378 | .slave = &omap44xx_l3_main_2_hwmod, | |
379 | .clk = "l3_div_ck", | |
380 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
381 | }; | |
382 | ||
c4645234 | 383 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { |
384 | { | |
385 | .pa_start = 0x44800000, | |
386 | .pa_end = 0x44801fff, | |
9b4021be | 387 | .flags = ADDR_TYPE_RT |
c4645234 | 388 | }, |
78183f3f | 389 | { } |
c4645234 | 390 | }; |
391 | ||
55d2cb08 BC |
392 | /* l3_main_1 -> l3_main_2 */ |
393 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
394 | .master = &omap44xx_l3_main_1_hwmod, | |
395 | .slave = &omap44xx_l3_main_2_hwmod, | |
396 | .clk = "l3_div_ck", | |
c4645234 | 397 | .addr = omap44xx_l3_main_2_addrs, |
9b4021be | 398 | .user = OCP_USER_MPU, |
55d2cb08 BC |
399 | }; |
400 | ||
401 | /* l4_cfg -> l3_main_2 */ | |
402 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
403 | .master = &omap44xx_l4_cfg_hwmod, | |
404 | .slave = &omap44xx_l3_main_2_hwmod, | |
405 | .clk = "l4_div_ck", | |
406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
407 | }; | |
408 | ||
5844c4ea BC |
409 | /* usb_otg_hs -> l3_main_2 */ |
410 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
411 | .master = &omap44xx_usb_otg_hs_hwmod, | |
412 | .slave = &omap44xx_l3_main_2_hwmod, | |
413 | .clk = "l3_div_ck", | |
414 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
415 | }; | |
416 | ||
55d2cb08 BC |
417 | /* l3_main_2 slave ports */ |
418 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { | |
531ce0d5 | 419 | &omap44xx_dma_system__l3_main_2, |
407a6888 BC |
420 | &omap44xx_hsi__l3_main_2, |
421 | &omap44xx_ipu__l3_main_2, | |
422 | &omap44xx_iss__l3_main_2, | |
8f25bdc5 | 423 | &omap44xx_iva__l3_main_2, |
55d2cb08 BC |
424 | &omap44xx_l3_main_1__l3_main_2, |
425 | &omap44xx_l4_cfg__l3_main_2, | |
5844c4ea | 426 | &omap44xx_usb_otg_hs__l3_main_2, |
55d2cb08 BC |
427 | }; |
428 | ||
429 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { | |
430 | .name = "l3_main_2", | |
431 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 432 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
433 | .prcm = { |
434 | .omap4 = { | |
435 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 436 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
437 | }, |
438 | }, | |
55d2cb08 BC |
439 | .slaves = omap44xx_l3_main_2_slaves, |
440 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), | |
55d2cb08 BC |
441 | }; |
442 | ||
7e69ed97 | 443 | /* l3_main_3 */ |
c4645234 | 444 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { |
445 | { | |
446 | .pa_start = 0x45000000, | |
447 | .pa_end = 0x45000fff, | |
9b4021be | 448 | .flags = ADDR_TYPE_RT |
c4645234 | 449 | }, |
78183f3f | 450 | { } |
c4645234 | 451 | }; |
452 | ||
55d2cb08 BC |
453 | /* l3_main_1 -> l3_main_3 */ |
454 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
455 | .master = &omap44xx_l3_main_1_hwmod, | |
456 | .slave = &omap44xx_l3_main_3_hwmod, | |
457 | .clk = "l3_div_ck", | |
c4645234 | 458 | .addr = omap44xx_l3_main_3_addrs, |
9b4021be | 459 | .user = OCP_USER_MPU, |
55d2cb08 BC |
460 | }; |
461 | ||
462 | /* l3_main_2 -> l3_main_3 */ | |
463 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
464 | .master = &omap44xx_l3_main_2_hwmod, | |
465 | .slave = &omap44xx_l3_main_3_hwmod, | |
466 | .clk = "l3_div_ck", | |
467 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
468 | }; | |
469 | ||
470 | /* l4_cfg -> l3_main_3 */ | |
471 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
472 | .master = &omap44xx_l4_cfg_hwmod, | |
473 | .slave = &omap44xx_l3_main_3_hwmod, | |
474 | .clk = "l4_div_ck", | |
475 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
476 | }; | |
477 | ||
478 | /* l3_main_3 slave ports */ | |
479 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { | |
480 | &omap44xx_l3_main_1__l3_main_3, | |
481 | &omap44xx_l3_main_2__l3_main_3, | |
482 | &omap44xx_l4_cfg__l3_main_3, | |
483 | }; | |
484 | ||
485 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |
486 | .name = "l3_main_3", | |
487 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 488 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
489 | .prcm = { |
490 | .omap4 = { | |
491 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 492 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 493 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
494 | }, |
495 | }, | |
55d2cb08 BC |
496 | .slaves = omap44xx_l3_main_3_slaves, |
497 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), | |
55d2cb08 BC |
498 | }; |
499 | ||
500 | /* | |
501 | * 'l4' class | |
502 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
503 | */ | |
504 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 505 | .name = "l4", |
55d2cb08 BC |
506 | }; |
507 | ||
7e69ed97 | 508 | /* l4_abe */ |
407a6888 BC |
509 | /* aess -> l4_abe */ |
510 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { | |
511 | .master = &omap44xx_aess_hwmod, | |
512 | .slave = &omap44xx_l4_abe_hwmod, | |
513 | .clk = "ocp_abe_iclk", | |
514 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
515 | }; | |
516 | ||
8f25bdc5 BC |
517 | /* dsp -> l4_abe */ |
518 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
519 | .master = &omap44xx_dsp_hwmod, | |
520 | .slave = &omap44xx_l4_abe_hwmod, | |
521 | .clk = "ocp_abe_iclk", | |
522 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
523 | }; | |
524 | ||
55d2cb08 BC |
525 | /* l3_main_1 -> l4_abe */ |
526 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
527 | .master = &omap44xx_l3_main_1_hwmod, | |
528 | .slave = &omap44xx_l4_abe_hwmod, | |
529 | .clk = "l3_div_ck", | |
530 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
531 | }; | |
532 | ||
533 | /* mpu -> l4_abe */ | |
534 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
535 | .master = &omap44xx_mpu_hwmod, | |
536 | .slave = &omap44xx_l4_abe_hwmod, | |
537 | .clk = "ocp_abe_iclk", | |
538 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
539 | }; | |
540 | ||
541 | /* l4_abe slave ports */ | |
542 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { | |
407a6888 | 543 | &omap44xx_aess__l4_abe, |
8f25bdc5 | 544 | &omap44xx_dsp__l4_abe, |
55d2cb08 BC |
545 | &omap44xx_l3_main_1__l4_abe, |
546 | &omap44xx_mpu__l4_abe, | |
547 | }; | |
548 | ||
549 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { | |
550 | .name = "l4_abe", | |
551 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 552 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
553 | .prcm = { |
554 | .omap4 = { | |
555 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
556 | }, | |
557 | }, | |
55d2cb08 BC |
558 | .slaves = omap44xx_l4_abe_slaves, |
559 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), | |
55d2cb08 BC |
560 | }; |
561 | ||
7e69ed97 | 562 | /* l4_cfg */ |
55d2cb08 BC |
563 | /* l3_main_1 -> l4_cfg */ |
564 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
565 | .master = &omap44xx_l3_main_1_hwmod, | |
566 | .slave = &omap44xx_l4_cfg_hwmod, | |
567 | .clk = "l3_div_ck", | |
568 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
569 | }; | |
570 | ||
571 | /* l4_cfg slave ports */ | |
572 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { | |
573 | &omap44xx_l3_main_1__l4_cfg, | |
574 | }; | |
575 | ||
576 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { | |
577 | .name = "l4_cfg", | |
578 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 579 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
580 | .prcm = { |
581 | .omap4 = { | |
582 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 583 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
584 | }, |
585 | }, | |
55d2cb08 BC |
586 | .slaves = omap44xx_l4_cfg_slaves, |
587 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), | |
55d2cb08 BC |
588 | }; |
589 | ||
7e69ed97 | 590 | /* l4_per */ |
55d2cb08 BC |
591 | /* l3_main_2 -> l4_per */ |
592 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
593 | .master = &omap44xx_l3_main_2_hwmod, | |
594 | .slave = &omap44xx_l4_per_hwmod, | |
595 | .clk = "l3_div_ck", | |
596 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
597 | }; | |
598 | ||
599 | /* l4_per slave ports */ | |
600 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { | |
601 | &omap44xx_l3_main_2__l4_per, | |
602 | }; | |
603 | ||
604 | static struct omap_hwmod omap44xx_l4_per_hwmod = { | |
605 | .name = "l4_per", | |
606 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 607 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
608 | .prcm = { |
609 | .omap4 = { | |
610 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 611 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
612 | }, |
613 | }, | |
55d2cb08 BC |
614 | .slaves = omap44xx_l4_per_slaves, |
615 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), | |
55d2cb08 BC |
616 | }; |
617 | ||
7e69ed97 | 618 | /* l4_wkup */ |
55d2cb08 BC |
619 | /* l4_cfg -> l4_wkup */ |
620 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
621 | .master = &omap44xx_l4_cfg_hwmod, | |
622 | .slave = &omap44xx_l4_wkup_hwmod, | |
623 | .clk = "l4_div_ck", | |
624 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
625 | }; | |
626 | ||
627 | /* l4_wkup slave ports */ | |
628 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { | |
629 | &omap44xx_l4_cfg__l4_wkup, | |
630 | }; | |
631 | ||
632 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |
633 | .name = "l4_wkup", | |
634 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 635 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
636 | .prcm = { |
637 | .omap4 = { | |
638 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 639 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
640 | }, |
641 | }, | |
55d2cb08 BC |
642 | .slaves = omap44xx_l4_wkup_slaves, |
643 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), | |
55d2cb08 BC |
644 | }; |
645 | ||
f776471f | 646 | /* |
3b54baad BC |
647 | * 'mpu_bus' class |
648 | * instance(s): mpu_private | |
f776471f | 649 | */ |
3b54baad | 650 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 651 | .name = "mpu_bus", |
3b54baad | 652 | }; |
f776471f | 653 | |
7e69ed97 | 654 | /* mpu_private */ |
3b54baad BC |
655 | /* mpu -> mpu_private */ |
656 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
657 | .master = &omap44xx_mpu_hwmod, | |
658 | .slave = &omap44xx_mpu_private_hwmod, | |
659 | .clk = "l3_div_ck", | |
660 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
661 | }; | |
662 | ||
663 | /* mpu_private slave ports */ | |
664 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { | |
665 | &omap44xx_mpu__mpu_private, | |
666 | }; | |
667 | ||
668 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |
669 | .name = "mpu_private", | |
670 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 671 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
672 | .slaves = omap44xx_mpu_private_slaves, |
673 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), | |
3b54baad BC |
674 | }; |
675 | ||
676 | /* | |
677 | * Modules omap_hwmod structures | |
678 | * | |
679 | * The following IPs are excluded for the moment because: | |
680 | * - They do not need an explicit SW control using omap_hwmod API. | |
681 | * - They still need to be validated with the driver | |
682 | * properly adapted to omap_hwmod / omap_device | |
683 | * | |
3b54baad BC |
684 | * c2c |
685 | * c2c_target_fw | |
686 | * cm_core | |
687 | * cm_core_aon | |
3b54baad BC |
688 | * ctrl_module_core |
689 | * ctrl_module_pad_core | |
690 | * ctrl_module_pad_wkup | |
691 | * ctrl_module_wkup | |
692 | * debugss | |
3b54baad BC |
693 | * efuse_ctrl_cust |
694 | * efuse_ctrl_std | |
695 | * elm | |
696 | * emif1 | |
697 | * emif2 | |
698 | * fdif | |
699 | * gpmc | |
700 | * gpu | |
701 | * hdq1w | |
00fe610b BC |
702 | * mcasp |
703 | * mpu_c0 | |
704 | * mpu_c1 | |
3b54baad BC |
705 | * ocmc_ram |
706 | * ocp2scp_usb_phy | |
707 | * ocp_wp_noc | |
3b54baad BC |
708 | * prcm_mpu |
709 | * prm | |
710 | * scrm | |
711 | * sl2if | |
712 | * slimbus1 | |
713 | * slimbus2 | |
3b54baad BC |
714 | * usb_host_fs |
715 | * usb_host_hs | |
3b54baad BC |
716 | * usb_phy_cm |
717 | * usb_tll_hs | |
718 | * usim | |
719 | */ | |
720 | ||
407a6888 BC |
721 | /* |
722 | * 'aess' class | |
723 | * audio engine sub system | |
724 | */ | |
725 | ||
726 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
727 | .rev_offs = 0x0000, | |
728 | .sysc_offs = 0x0010, | |
729 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
730 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
731 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
732 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
733 | .sysc_fields = &omap_hwmod_sysc_type2, |
734 | }; | |
735 | ||
736 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
737 | .name = "aess", | |
738 | .sysc = &omap44xx_aess_sysc, | |
739 | }; | |
740 | ||
741 | /* aess */ | |
742 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
743 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 744 | { .irq = -1 } |
407a6888 BC |
745 | }; |
746 | ||
747 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
748 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
749 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
750 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
751 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
752 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
753 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
754 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
755 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 756 | { .dma_req = -1 } |
407a6888 BC |
757 | }; |
758 | ||
759 | /* aess master ports */ | |
760 | static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { | |
761 | &omap44xx_aess__l4_abe, | |
762 | }; | |
763 | ||
764 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { | |
765 | { | |
766 | .pa_start = 0x401f1000, | |
767 | .pa_end = 0x401f13ff, | |
768 | .flags = ADDR_TYPE_RT | |
769 | }, | |
78183f3f | 770 | { } |
407a6888 BC |
771 | }; |
772 | ||
773 | /* l4_abe -> aess */ | |
774 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { | |
775 | .master = &omap44xx_l4_abe_hwmod, | |
776 | .slave = &omap44xx_aess_hwmod, | |
777 | .clk = "ocp_abe_iclk", | |
778 | .addr = omap44xx_aess_addrs, | |
407a6888 BC |
779 | .user = OCP_USER_MPU, |
780 | }; | |
781 | ||
782 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
783 | { | |
784 | .pa_start = 0x490f1000, | |
785 | .pa_end = 0x490f13ff, | |
786 | .flags = ADDR_TYPE_RT | |
787 | }, | |
78183f3f | 788 | { } |
407a6888 BC |
789 | }; |
790 | ||
791 | /* l4_abe -> aess (dma) */ | |
792 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { | |
793 | .master = &omap44xx_l4_abe_hwmod, | |
794 | .slave = &omap44xx_aess_hwmod, | |
795 | .clk = "ocp_abe_iclk", | |
796 | .addr = omap44xx_aess_dma_addrs, | |
407a6888 BC |
797 | .user = OCP_USER_SDMA, |
798 | }; | |
799 | ||
800 | /* aess slave ports */ | |
801 | static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { | |
802 | &omap44xx_l4_abe__aess, | |
803 | &omap44xx_l4_abe__aess_dma, | |
804 | }; | |
805 | ||
806 | static struct omap_hwmod omap44xx_aess_hwmod = { | |
807 | .name = "aess", | |
808 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 809 | .clkdm_name = "abe_clkdm", |
407a6888 | 810 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 811 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 812 | .main_clk = "aess_fck", |
00fe610b | 813 | .prcm = { |
407a6888 | 814 | .omap4 = { |
d0f0631d | 815 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 816 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 817 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
818 | }, |
819 | }, | |
820 | .slaves = omap44xx_aess_slaves, | |
821 | .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), | |
822 | .masters = omap44xx_aess_masters, | |
823 | .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), | |
407a6888 BC |
824 | }; |
825 | ||
826 | /* | |
827 | * 'bandgap' class | |
828 | * bangap reference for ldo regulators | |
829 | */ | |
830 | ||
831 | static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { | |
832 | .name = "bandgap", | |
833 | }; | |
834 | ||
835 | /* bandgap */ | |
836 | static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { | |
837 | { .role = "fclk", .clk = "bandgap_fclk" }, | |
838 | }; | |
839 | ||
840 | static struct omap_hwmod omap44xx_bandgap_hwmod = { | |
841 | .name = "bandgap", | |
842 | .class = &omap44xx_bandgap_hwmod_class, | |
a5322c6f | 843 | .clkdm_name = "l4_wkup_clkdm", |
00fe610b | 844 | .prcm = { |
407a6888 | 845 | .omap4 = { |
d0f0631d | 846 | .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, |
407a6888 BC |
847 | }, |
848 | }, | |
849 | .opt_clks = bandgap_opt_clks, | |
850 | .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), | |
407a6888 BC |
851 | }; |
852 | ||
853 | /* | |
854 | * 'counter' class | |
855 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
856 | */ | |
857 | ||
858 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
859 | .rev_offs = 0x0000, | |
860 | .sysc_offs = 0x0004, | |
861 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
862 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
863 | SIDLE_SMART_WKUP), | |
864 | .sysc_fields = &omap_hwmod_sysc_type1, | |
865 | }; | |
866 | ||
867 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
868 | .name = "counter", | |
869 | .sysc = &omap44xx_counter_sysc, | |
870 | }; | |
871 | ||
872 | /* counter_32k */ | |
873 | static struct omap_hwmod omap44xx_counter_32k_hwmod; | |
874 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { | |
875 | { | |
876 | .pa_start = 0x4a304000, | |
877 | .pa_end = 0x4a30401f, | |
878 | .flags = ADDR_TYPE_RT | |
879 | }, | |
78183f3f | 880 | { } |
407a6888 BC |
881 | }; |
882 | ||
883 | /* l4_wkup -> counter_32k */ | |
884 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
885 | .master = &omap44xx_l4_wkup_hwmod, | |
886 | .slave = &omap44xx_counter_32k_hwmod, | |
887 | .clk = "l4_wkup_clk_mux_ck", | |
888 | .addr = omap44xx_counter_32k_addrs, | |
407a6888 BC |
889 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
890 | }; | |
891 | ||
892 | /* counter_32k slave ports */ | |
893 | static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { | |
894 | &omap44xx_l4_wkup__counter_32k, | |
895 | }; | |
896 | ||
897 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { | |
898 | .name = "counter_32k", | |
899 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 900 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
901 | .flags = HWMOD_SWSUP_SIDLE, |
902 | .main_clk = "sys_32k_ck", | |
00fe610b | 903 | .prcm = { |
407a6888 | 904 | .omap4 = { |
d0f0631d | 905 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 906 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
907 | }, |
908 | }, | |
909 | .slaves = omap44xx_counter_32k_slaves, | |
910 | .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), | |
407a6888 BC |
911 | }; |
912 | ||
d7cf5f33 BC |
913 | /* |
914 | * 'dma' class | |
915 | * dma controller for data exchange between memory to memory (i.e. internal or | |
916 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
917 | */ | |
918 | ||
919 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
920 | .rev_offs = 0x0000, | |
921 | .sysc_offs = 0x002c, | |
922 | .syss_offs = 0x0028, | |
923 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
924 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
925 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
926 | SYSS_HAS_RESET_STATUS), | |
927 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
928 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
929 | .sysc_fields = &omap_hwmod_sysc_type1, | |
930 | }; | |
931 | ||
932 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
933 | .name = "dma", | |
934 | .sysc = &omap44xx_dma_sysc, | |
935 | }; | |
936 | ||
937 | /* dma dev_attr */ | |
938 | static struct omap_dma_dev_attr dma_dev_attr = { | |
939 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
940 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
941 | .lch_count = 32, | |
942 | }; | |
943 | ||
944 | /* dma_system */ | |
945 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
946 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
947 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
948 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
949 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 950 | { .irq = -1 } |
d7cf5f33 BC |
951 | }; |
952 | ||
953 | /* dma_system master ports */ | |
954 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { | |
955 | &omap44xx_dma_system__l3_main_2, | |
956 | }; | |
957 | ||
958 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
959 | { | |
960 | .pa_start = 0x4a056000, | |
1286eeb2 | 961 | .pa_end = 0x4a056fff, |
d7cf5f33 BC |
962 | .flags = ADDR_TYPE_RT |
963 | }, | |
78183f3f | 964 | { } |
d7cf5f33 BC |
965 | }; |
966 | ||
967 | /* l4_cfg -> dma_system */ | |
968 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
969 | .master = &omap44xx_l4_cfg_hwmod, | |
970 | .slave = &omap44xx_dma_system_hwmod, | |
971 | .clk = "l4_div_ck", | |
972 | .addr = omap44xx_dma_system_addrs, | |
d7cf5f33 BC |
973 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
974 | }; | |
975 | ||
976 | /* dma_system slave ports */ | |
977 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { | |
978 | &omap44xx_l4_cfg__dma_system, | |
979 | }; | |
980 | ||
981 | static struct omap_hwmod omap44xx_dma_system_hwmod = { | |
982 | .name = "dma_system", | |
983 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 984 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 985 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
986 | .main_clk = "l3_div_ck", |
987 | .prcm = { | |
988 | .omap4 = { | |
d0f0631d | 989 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 990 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
991 | }, |
992 | }, | |
993 | .dev_attr = &dma_dev_attr, | |
994 | .slaves = omap44xx_dma_system_slaves, | |
995 | .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), | |
996 | .masters = omap44xx_dma_system_masters, | |
997 | .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), | |
d7cf5f33 BC |
998 | }; |
999 | ||
8ca476da BC |
1000 | /* |
1001 | * 'dmic' class | |
1002 | * digital microphone controller | |
1003 | */ | |
1004 | ||
1005 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
1006 | .rev_offs = 0x0000, | |
1007 | .sysc_offs = 0x0010, | |
1008 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1009 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1010 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1011 | SIDLE_SMART_WKUP), | |
1012 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1013 | }; | |
1014 | ||
1015 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
1016 | .name = "dmic", | |
1017 | .sysc = &omap44xx_dmic_sysc, | |
1018 | }; | |
1019 | ||
1020 | /* dmic */ | |
1021 | static struct omap_hwmod omap44xx_dmic_hwmod; | |
1022 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { | |
1023 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1024 | { .irq = -1 } |
8ca476da BC |
1025 | }; |
1026 | ||
1027 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
1028 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1029 | { .dma_req = -1 } |
8ca476da BC |
1030 | }; |
1031 | ||
1032 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
1033 | { | |
1034 | .pa_start = 0x4012e000, | |
1035 | .pa_end = 0x4012e07f, | |
1036 | .flags = ADDR_TYPE_RT | |
1037 | }, | |
78183f3f | 1038 | { } |
8ca476da BC |
1039 | }; |
1040 | ||
1041 | /* l4_abe -> dmic */ | |
1042 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
1043 | .master = &omap44xx_l4_abe_hwmod, | |
1044 | .slave = &omap44xx_dmic_hwmod, | |
1045 | .clk = "ocp_abe_iclk", | |
1046 | .addr = omap44xx_dmic_addrs, | |
8ca476da BC |
1047 | .user = OCP_USER_MPU, |
1048 | }; | |
1049 | ||
1050 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
1051 | { | |
1052 | .pa_start = 0x4902e000, | |
1053 | .pa_end = 0x4902e07f, | |
1054 | .flags = ADDR_TYPE_RT | |
1055 | }, | |
78183f3f | 1056 | { } |
8ca476da BC |
1057 | }; |
1058 | ||
1059 | /* l4_abe -> dmic (dma) */ | |
1060 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
1061 | .master = &omap44xx_l4_abe_hwmod, | |
1062 | .slave = &omap44xx_dmic_hwmod, | |
1063 | .clk = "ocp_abe_iclk", | |
1064 | .addr = omap44xx_dmic_dma_addrs, | |
8ca476da BC |
1065 | .user = OCP_USER_SDMA, |
1066 | }; | |
1067 | ||
1068 | /* dmic slave ports */ | |
1069 | static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { | |
1070 | &omap44xx_l4_abe__dmic, | |
1071 | &omap44xx_l4_abe__dmic_dma, | |
1072 | }; | |
1073 | ||
1074 | static struct omap_hwmod omap44xx_dmic_hwmod = { | |
1075 | .name = "dmic", | |
1076 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 1077 | .clkdm_name = "abe_clkdm", |
8ca476da | 1078 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 1079 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 1080 | .main_clk = "dmic_fck", |
00fe610b | 1081 | .prcm = { |
8ca476da | 1082 | .omap4 = { |
d0f0631d | 1083 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 1084 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 1085 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
1086 | }, |
1087 | }, | |
1088 | .slaves = omap44xx_dmic_slaves, | |
1089 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), | |
8ca476da BC |
1090 | }; |
1091 | ||
8f25bdc5 BC |
1092 | /* |
1093 | * 'dsp' class | |
1094 | * dsp sub-system | |
1095 | */ | |
1096 | ||
1097 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 1098 | .name = "dsp", |
8f25bdc5 BC |
1099 | }; |
1100 | ||
1101 | /* dsp */ | |
1102 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
1103 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1104 | { .irq = -1 } |
8f25bdc5 BC |
1105 | }; |
1106 | ||
1107 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
1108 | { .name = "mmu_cache", .rst_shift = 1 }, | |
1109 | }; | |
1110 | ||
1111 | static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { | |
1112 | { .name = "dsp", .rst_shift = 0 }, | |
1113 | }; | |
1114 | ||
1115 | /* dsp -> iva */ | |
1116 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
1117 | .master = &omap44xx_dsp_hwmod, | |
1118 | .slave = &omap44xx_iva_hwmod, | |
1119 | .clk = "dpll_iva_m5x2_ck", | |
1120 | }; | |
1121 | ||
1122 | /* dsp master ports */ | |
1123 | static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { | |
1124 | &omap44xx_dsp__l3_main_1, | |
1125 | &omap44xx_dsp__l4_abe, | |
1126 | &omap44xx_dsp__iva, | |
1127 | }; | |
1128 | ||
1129 | /* l4_cfg -> dsp */ | |
1130 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
1131 | .master = &omap44xx_l4_cfg_hwmod, | |
1132 | .slave = &omap44xx_dsp_hwmod, | |
1133 | .clk = "l4_div_ck", | |
1134 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1135 | }; | |
1136 | ||
1137 | /* dsp slave ports */ | |
1138 | static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { | |
1139 | &omap44xx_l4_cfg__dsp, | |
1140 | }; | |
1141 | ||
1142 | /* Pseudo hwmod for reset control purpose only */ | |
1143 | static struct omap_hwmod omap44xx_dsp_c0_hwmod = { | |
1144 | .name = "dsp_c0", | |
1145 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 1146 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 BC |
1147 | .flags = HWMOD_INIT_NO_RESET, |
1148 | .rst_lines = omap44xx_dsp_c0_resets, | |
1149 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), | |
1150 | .prcm = { | |
1151 | .omap4 = { | |
eaac329d | 1152 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
8f25bdc5 BC |
1153 | }, |
1154 | }, | |
8f25bdc5 BC |
1155 | }; |
1156 | ||
1157 | static struct omap_hwmod omap44xx_dsp_hwmod = { | |
1158 | .name = "dsp", | |
1159 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 1160 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 1161 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
1162 | .rst_lines = omap44xx_dsp_resets, |
1163 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
1164 | .main_clk = "dsp_fck", | |
1165 | .prcm = { | |
1166 | .omap4 = { | |
d0f0631d | 1167 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 1168 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 1169 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 1170 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1171 | }, |
1172 | }, | |
1173 | .slaves = omap44xx_dsp_slaves, | |
1174 | .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), | |
1175 | .masters = omap44xx_dsp_masters, | |
1176 | .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), | |
8f25bdc5 BC |
1177 | }; |
1178 | ||
d63bd74f BC |
1179 | /* |
1180 | * 'dss' class | |
1181 | * display sub-system | |
1182 | */ | |
1183 | ||
1184 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
1185 | .rev_offs = 0x0000, | |
1186 | .syss_offs = 0x0014, | |
1187 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
1188 | }; | |
1189 | ||
1190 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
1191 | .name = "dss", | |
1192 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 1193 | .reset = omap_dss_reset, |
d63bd74f BC |
1194 | }; |
1195 | ||
1196 | /* dss */ | |
1197 | /* dss master ports */ | |
1198 | static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { | |
1199 | &omap44xx_dss__l3_main_1, | |
1200 | }; | |
1201 | ||
1202 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
1203 | { | |
1204 | .pa_start = 0x58000000, | |
1205 | .pa_end = 0x5800007f, | |
1206 | .flags = ADDR_TYPE_RT | |
1207 | }, | |
78183f3f | 1208 | { } |
d63bd74f BC |
1209 | }; |
1210 | ||
1211 | /* l3_main_2 -> dss */ | |
1212 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
1213 | .master = &omap44xx_l3_main_2_hwmod, | |
1214 | .slave = &omap44xx_dss_hwmod, | |
da7cdfac | 1215 | .clk = "dss_fck", |
d63bd74f | 1216 | .addr = omap44xx_dss_dma_addrs, |
d63bd74f BC |
1217 | .user = OCP_USER_SDMA, |
1218 | }; | |
1219 | ||
1220 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
1221 | { | |
1222 | .pa_start = 0x48040000, | |
1223 | .pa_end = 0x4804007f, | |
1224 | .flags = ADDR_TYPE_RT | |
1225 | }, | |
78183f3f | 1226 | { } |
d63bd74f BC |
1227 | }; |
1228 | ||
1229 | /* l4_per -> dss */ | |
1230 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
1231 | .master = &omap44xx_l4_per_hwmod, | |
1232 | .slave = &omap44xx_dss_hwmod, | |
1233 | .clk = "l4_div_ck", | |
1234 | .addr = omap44xx_dss_addrs, | |
d63bd74f BC |
1235 | .user = OCP_USER_MPU, |
1236 | }; | |
1237 | ||
1238 | /* dss slave ports */ | |
1239 | static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { | |
1240 | &omap44xx_l3_main_2__dss, | |
1241 | &omap44xx_l4_per__dss, | |
1242 | }; | |
1243 | ||
1244 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
1245 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1246 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 1247 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
1248 | }; |
1249 | ||
1250 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
1251 | .name = "dss_core", | |
37ad0855 | 1252 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 1253 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 1254 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 1255 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1256 | .prcm = { |
1257 | .omap4 = { | |
d0f0631d | 1258 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1259 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1260 | }, |
1261 | }, | |
1262 | .opt_clks = dss_opt_clks, | |
1263 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1264 | .slaves = omap44xx_dss_slaves, | |
1265 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), | |
1266 | .masters = omap44xx_dss_masters, | |
1267 | .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), | |
d63bd74f BC |
1268 | }; |
1269 | ||
1270 | /* | |
1271 | * 'dispc' class | |
1272 | * display controller | |
1273 | */ | |
1274 | ||
1275 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
1276 | .rev_offs = 0x0000, | |
1277 | .sysc_offs = 0x0010, | |
1278 | .syss_offs = 0x0014, | |
1279 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1280 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
1281 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1282 | SYSS_HAS_RESET_STATUS), | |
1283 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1284 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1285 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1286 | }; | |
1287 | ||
1288 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
1289 | .name = "dispc", | |
1290 | .sysc = &omap44xx_dispc_sysc, | |
1291 | }; | |
1292 | ||
1293 | /* dss_dispc */ | |
1294 | static struct omap_hwmod omap44xx_dss_dispc_hwmod; | |
1295 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { | |
1296 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1297 | { .irq = -1 } |
d63bd74f BC |
1298 | }; |
1299 | ||
1300 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
1301 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1302 | { .dma_req = -1 } |
d63bd74f BC |
1303 | }; |
1304 | ||
1305 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
1306 | { | |
1307 | .pa_start = 0x58001000, | |
1308 | .pa_end = 0x58001fff, | |
1309 | .flags = ADDR_TYPE_RT | |
1310 | }, | |
78183f3f | 1311 | { } |
d63bd74f BC |
1312 | }; |
1313 | ||
1314 | /* l3_main_2 -> dss_dispc */ | |
1315 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
1316 | .master = &omap44xx_l3_main_2_hwmod, | |
1317 | .slave = &omap44xx_dss_dispc_hwmod, | |
da7cdfac | 1318 | .clk = "dss_fck", |
d63bd74f | 1319 | .addr = omap44xx_dss_dispc_dma_addrs, |
d63bd74f BC |
1320 | .user = OCP_USER_SDMA, |
1321 | }; | |
1322 | ||
1323 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
1324 | { | |
1325 | .pa_start = 0x48041000, | |
1326 | .pa_end = 0x48041fff, | |
1327 | .flags = ADDR_TYPE_RT | |
1328 | }, | |
78183f3f | 1329 | { } |
d63bd74f BC |
1330 | }; |
1331 | ||
b923d40d AT |
1332 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
1333 | .manager_count = 3, | |
1334 | .has_framedonetv_irq = 1 | |
1335 | }; | |
1336 | ||
d63bd74f BC |
1337 | /* l4_per -> dss_dispc */ |
1338 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
1339 | .master = &omap44xx_l4_per_hwmod, | |
1340 | .slave = &omap44xx_dss_dispc_hwmod, | |
1341 | .clk = "l4_div_ck", | |
1342 | .addr = omap44xx_dss_dispc_addrs, | |
d63bd74f BC |
1343 | .user = OCP_USER_MPU, |
1344 | }; | |
1345 | ||
1346 | /* dss_dispc slave ports */ | |
1347 | static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { | |
1348 | &omap44xx_l3_main_2__dss_dispc, | |
1349 | &omap44xx_l4_per__dss_dispc, | |
1350 | }; | |
1351 | ||
1352 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { | |
1353 | .name = "dss_dispc", | |
1354 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 1355 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1356 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 1357 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 1358 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1359 | .prcm = { |
1360 | .omap4 = { | |
d0f0631d | 1361 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1362 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1363 | }, |
1364 | }, | |
1365 | .slaves = omap44xx_dss_dispc_slaves, | |
1366 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), | |
b923d40d | 1367 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
1368 | }; |
1369 | ||
1370 | /* | |
1371 | * 'dsi' class | |
1372 | * display serial interface controller | |
1373 | */ | |
1374 | ||
1375 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
1376 | .rev_offs = 0x0000, | |
1377 | .sysc_offs = 0x0010, | |
1378 | .syss_offs = 0x0014, | |
1379 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1380 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1381 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1382 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1383 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1384 | }; | |
1385 | ||
1386 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
1387 | .name = "dsi", | |
1388 | .sysc = &omap44xx_dsi_sysc, | |
1389 | }; | |
1390 | ||
1391 | /* dss_dsi1 */ | |
1392 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod; | |
1393 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { | |
1394 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1395 | { .irq = -1 } |
d63bd74f BC |
1396 | }; |
1397 | ||
1398 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
1399 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1400 | { .dma_req = -1 } |
d63bd74f BC |
1401 | }; |
1402 | ||
1403 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
1404 | { | |
1405 | .pa_start = 0x58004000, | |
1406 | .pa_end = 0x580041ff, | |
1407 | .flags = ADDR_TYPE_RT | |
1408 | }, | |
78183f3f | 1409 | { } |
d63bd74f BC |
1410 | }; |
1411 | ||
1412 | /* l3_main_2 -> dss_dsi1 */ | |
1413 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
1414 | .master = &omap44xx_l3_main_2_hwmod, | |
1415 | .slave = &omap44xx_dss_dsi1_hwmod, | |
da7cdfac | 1416 | .clk = "dss_fck", |
d63bd74f | 1417 | .addr = omap44xx_dss_dsi1_dma_addrs, |
d63bd74f BC |
1418 | .user = OCP_USER_SDMA, |
1419 | }; | |
1420 | ||
1421 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
1422 | { | |
1423 | .pa_start = 0x48044000, | |
1424 | .pa_end = 0x480441ff, | |
1425 | .flags = ADDR_TYPE_RT | |
1426 | }, | |
78183f3f | 1427 | { } |
d63bd74f BC |
1428 | }; |
1429 | ||
1430 | /* l4_per -> dss_dsi1 */ | |
1431 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
1432 | .master = &omap44xx_l4_per_hwmod, | |
1433 | .slave = &omap44xx_dss_dsi1_hwmod, | |
1434 | .clk = "l4_div_ck", | |
1435 | .addr = omap44xx_dss_dsi1_addrs, | |
d63bd74f BC |
1436 | .user = OCP_USER_MPU, |
1437 | }; | |
1438 | ||
1439 | /* dss_dsi1 slave ports */ | |
1440 | static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { | |
1441 | &omap44xx_l3_main_2__dss_dsi1, | |
1442 | &omap44xx_l4_per__dss_dsi1, | |
1443 | }; | |
1444 | ||
3a23aafc TV |
1445 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
1446 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1447 | }; | |
1448 | ||
d63bd74f BC |
1449 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
1450 | .name = "dss_dsi1", | |
1451 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 1452 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1453 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 1454 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 1455 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1456 | .prcm = { |
1457 | .omap4 = { | |
d0f0631d | 1458 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1459 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1460 | }, |
1461 | }, | |
3a23aafc TV |
1462 | .opt_clks = dss_dsi1_opt_clks, |
1463 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
1464 | .slaves = omap44xx_dss_dsi1_slaves, |
1465 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), | |
d63bd74f BC |
1466 | }; |
1467 | ||
1468 | /* dss_dsi2 */ | |
1469 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod; | |
1470 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { | |
1471 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1472 | { .irq = -1 } |
d63bd74f BC |
1473 | }; |
1474 | ||
1475 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
1476 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1477 | { .dma_req = -1 } |
d63bd74f BC |
1478 | }; |
1479 | ||
1480 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
1481 | { | |
1482 | .pa_start = 0x58005000, | |
1483 | .pa_end = 0x580051ff, | |
1484 | .flags = ADDR_TYPE_RT | |
1485 | }, | |
78183f3f | 1486 | { } |
d63bd74f BC |
1487 | }; |
1488 | ||
1489 | /* l3_main_2 -> dss_dsi2 */ | |
1490 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
1491 | .master = &omap44xx_l3_main_2_hwmod, | |
1492 | .slave = &omap44xx_dss_dsi2_hwmod, | |
da7cdfac | 1493 | .clk = "dss_fck", |
d63bd74f | 1494 | .addr = omap44xx_dss_dsi2_dma_addrs, |
d63bd74f BC |
1495 | .user = OCP_USER_SDMA, |
1496 | }; | |
1497 | ||
1498 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
1499 | { | |
1500 | .pa_start = 0x48045000, | |
1501 | .pa_end = 0x480451ff, | |
1502 | .flags = ADDR_TYPE_RT | |
1503 | }, | |
78183f3f | 1504 | { } |
d63bd74f BC |
1505 | }; |
1506 | ||
1507 | /* l4_per -> dss_dsi2 */ | |
1508 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
1509 | .master = &omap44xx_l4_per_hwmod, | |
1510 | .slave = &omap44xx_dss_dsi2_hwmod, | |
1511 | .clk = "l4_div_ck", | |
1512 | .addr = omap44xx_dss_dsi2_addrs, | |
d63bd74f BC |
1513 | .user = OCP_USER_MPU, |
1514 | }; | |
1515 | ||
1516 | /* dss_dsi2 slave ports */ | |
1517 | static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { | |
1518 | &omap44xx_l3_main_2__dss_dsi2, | |
1519 | &omap44xx_l4_per__dss_dsi2, | |
1520 | }; | |
1521 | ||
3a23aafc TV |
1522 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
1523 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1524 | }; | |
1525 | ||
d63bd74f BC |
1526 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
1527 | .name = "dss_dsi2", | |
1528 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 1529 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1530 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 1531 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 1532 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1533 | .prcm = { |
1534 | .omap4 = { | |
d0f0631d | 1535 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1536 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1537 | }, |
1538 | }, | |
3a23aafc TV |
1539 | .opt_clks = dss_dsi2_opt_clks, |
1540 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
1541 | .slaves = omap44xx_dss_dsi2_slaves, |
1542 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), | |
d63bd74f BC |
1543 | }; |
1544 | ||
1545 | /* | |
1546 | * 'hdmi' class | |
1547 | * hdmi controller | |
1548 | */ | |
1549 | ||
1550 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
1551 | .rev_offs = 0x0000, | |
1552 | .sysc_offs = 0x0010, | |
1553 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1554 | SYSC_HAS_SOFTRESET), | |
1555 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1556 | SIDLE_SMART_WKUP), | |
1557 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1558 | }; | |
1559 | ||
1560 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
1561 | .name = "hdmi", | |
1562 | .sysc = &omap44xx_hdmi_sysc, | |
1563 | }; | |
1564 | ||
1565 | /* dss_hdmi */ | |
1566 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod; | |
1567 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { | |
1568 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1569 | { .irq = -1 } |
d63bd74f BC |
1570 | }; |
1571 | ||
1572 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
1573 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1574 | { .dma_req = -1 } |
d63bd74f BC |
1575 | }; |
1576 | ||
1577 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
1578 | { | |
1579 | .pa_start = 0x58006000, | |
1580 | .pa_end = 0x58006fff, | |
1581 | .flags = ADDR_TYPE_RT | |
1582 | }, | |
78183f3f | 1583 | { } |
d63bd74f BC |
1584 | }; |
1585 | ||
1586 | /* l3_main_2 -> dss_hdmi */ | |
1587 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
1588 | .master = &omap44xx_l3_main_2_hwmod, | |
1589 | .slave = &omap44xx_dss_hdmi_hwmod, | |
da7cdfac | 1590 | .clk = "dss_fck", |
d63bd74f | 1591 | .addr = omap44xx_dss_hdmi_dma_addrs, |
d63bd74f BC |
1592 | .user = OCP_USER_SDMA, |
1593 | }; | |
1594 | ||
1595 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
1596 | { | |
1597 | .pa_start = 0x48046000, | |
1598 | .pa_end = 0x48046fff, | |
1599 | .flags = ADDR_TYPE_RT | |
1600 | }, | |
78183f3f | 1601 | { } |
d63bd74f BC |
1602 | }; |
1603 | ||
1604 | /* l4_per -> dss_hdmi */ | |
1605 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
1606 | .master = &omap44xx_l4_per_hwmod, | |
1607 | .slave = &omap44xx_dss_hdmi_hwmod, | |
1608 | .clk = "l4_div_ck", | |
1609 | .addr = omap44xx_dss_hdmi_addrs, | |
d63bd74f BC |
1610 | .user = OCP_USER_MPU, |
1611 | }; | |
1612 | ||
1613 | /* dss_hdmi slave ports */ | |
1614 | static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { | |
1615 | &omap44xx_l3_main_2__dss_hdmi, | |
1616 | &omap44xx_l4_per__dss_hdmi, | |
1617 | }; | |
1618 | ||
3a23aafc TV |
1619 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
1620 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1621 | }; | |
1622 | ||
d63bd74f BC |
1623 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
1624 | .name = "dss_hdmi", | |
1625 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 1626 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1627 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 1628 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 1629 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
1630 | .prcm = { |
1631 | .omap4 = { | |
d0f0631d | 1632 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1633 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1634 | }, |
1635 | }, | |
3a23aafc TV |
1636 | .opt_clks = dss_hdmi_opt_clks, |
1637 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
1638 | .slaves = omap44xx_dss_hdmi_slaves, |
1639 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), | |
d63bd74f BC |
1640 | }; |
1641 | ||
1642 | /* | |
1643 | * 'rfbi' class | |
1644 | * remote frame buffer interface | |
1645 | */ | |
1646 | ||
1647 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
1648 | .rev_offs = 0x0000, | |
1649 | .sysc_offs = 0x0010, | |
1650 | .syss_offs = 0x0014, | |
1651 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1652 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1653 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1654 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1655 | }; | |
1656 | ||
1657 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
1658 | .name = "rfbi", | |
1659 | .sysc = &omap44xx_rfbi_sysc, | |
1660 | }; | |
1661 | ||
1662 | /* dss_rfbi */ | |
1663 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod; | |
1664 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { | |
1665 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1666 | { .dma_req = -1 } |
d63bd74f BC |
1667 | }; |
1668 | ||
1669 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
1670 | { | |
1671 | .pa_start = 0x58002000, | |
1672 | .pa_end = 0x580020ff, | |
1673 | .flags = ADDR_TYPE_RT | |
1674 | }, | |
78183f3f | 1675 | { } |
d63bd74f BC |
1676 | }; |
1677 | ||
1678 | /* l3_main_2 -> dss_rfbi */ | |
1679 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
1680 | .master = &omap44xx_l3_main_2_hwmod, | |
1681 | .slave = &omap44xx_dss_rfbi_hwmod, | |
da7cdfac | 1682 | .clk = "dss_fck", |
d63bd74f | 1683 | .addr = omap44xx_dss_rfbi_dma_addrs, |
d63bd74f BC |
1684 | .user = OCP_USER_SDMA, |
1685 | }; | |
1686 | ||
1687 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
1688 | { | |
1689 | .pa_start = 0x48042000, | |
1690 | .pa_end = 0x480420ff, | |
1691 | .flags = ADDR_TYPE_RT | |
1692 | }, | |
78183f3f | 1693 | { } |
d63bd74f BC |
1694 | }; |
1695 | ||
1696 | /* l4_per -> dss_rfbi */ | |
1697 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
1698 | .master = &omap44xx_l4_per_hwmod, | |
1699 | .slave = &omap44xx_dss_rfbi_hwmod, | |
1700 | .clk = "l4_div_ck", | |
1701 | .addr = omap44xx_dss_rfbi_addrs, | |
d63bd74f BC |
1702 | .user = OCP_USER_MPU, |
1703 | }; | |
1704 | ||
1705 | /* dss_rfbi slave ports */ | |
1706 | static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { | |
1707 | &omap44xx_l3_main_2__dss_rfbi, | |
1708 | &omap44xx_l4_per__dss_rfbi, | |
1709 | }; | |
1710 | ||
3a23aafc TV |
1711 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
1712 | { .role = "ick", .clk = "dss_fck" }, | |
1713 | }; | |
1714 | ||
d63bd74f BC |
1715 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
1716 | .name = "dss_rfbi", | |
1717 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 1718 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1719 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 1720 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1721 | .prcm = { |
1722 | .omap4 = { | |
d0f0631d | 1723 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1724 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1725 | }, |
1726 | }, | |
3a23aafc TV |
1727 | .opt_clks = dss_rfbi_opt_clks, |
1728 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
1729 | .slaves = omap44xx_dss_rfbi_slaves, |
1730 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), | |
d63bd74f BC |
1731 | }; |
1732 | ||
1733 | /* | |
1734 | * 'venc' class | |
1735 | * video encoder | |
1736 | */ | |
1737 | ||
1738 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
1739 | .name = "venc", | |
1740 | }; | |
1741 | ||
1742 | /* dss_venc */ | |
1743 | static struct omap_hwmod omap44xx_dss_venc_hwmod; | |
1744 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
1745 | { | |
1746 | .pa_start = 0x58003000, | |
1747 | .pa_end = 0x580030ff, | |
1748 | .flags = ADDR_TYPE_RT | |
1749 | }, | |
78183f3f | 1750 | { } |
d63bd74f BC |
1751 | }; |
1752 | ||
1753 | /* l3_main_2 -> dss_venc */ | |
1754 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
1755 | .master = &omap44xx_l3_main_2_hwmod, | |
1756 | .slave = &omap44xx_dss_venc_hwmod, | |
da7cdfac | 1757 | .clk = "dss_fck", |
d63bd74f | 1758 | .addr = omap44xx_dss_venc_dma_addrs, |
d63bd74f BC |
1759 | .user = OCP_USER_SDMA, |
1760 | }; | |
1761 | ||
1762 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
1763 | { | |
1764 | .pa_start = 0x48043000, | |
1765 | .pa_end = 0x480430ff, | |
1766 | .flags = ADDR_TYPE_RT | |
1767 | }, | |
78183f3f | 1768 | { } |
d63bd74f BC |
1769 | }; |
1770 | ||
1771 | /* l4_per -> dss_venc */ | |
1772 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
1773 | .master = &omap44xx_l4_per_hwmod, | |
1774 | .slave = &omap44xx_dss_venc_hwmod, | |
1775 | .clk = "l4_div_ck", | |
1776 | .addr = omap44xx_dss_venc_addrs, | |
d63bd74f BC |
1777 | .user = OCP_USER_MPU, |
1778 | }; | |
1779 | ||
1780 | /* dss_venc slave ports */ | |
1781 | static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { | |
1782 | &omap44xx_l3_main_2__dss_venc, | |
1783 | &omap44xx_l4_per__dss_venc, | |
1784 | }; | |
1785 | ||
1786 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { | |
1787 | .name = "dss_venc", | |
1788 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 1789 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 1790 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
1791 | .prcm = { |
1792 | .omap4 = { | |
d0f0631d | 1793 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1794 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1795 | }, |
1796 | }, | |
1797 | .slaves = omap44xx_dss_venc_slaves, | |
1798 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), | |
d63bd74f BC |
1799 | }; |
1800 | ||
3b54baad BC |
1801 | /* |
1802 | * 'gpio' class | |
1803 | * general purpose io module | |
1804 | */ | |
1805 | ||
1806 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1807 | .rev_offs = 0x0000, | |
f776471f | 1808 | .sysc_offs = 0x0010, |
3b54baad | 1809 | .syss_offs = 0x0114, |
0cfe8751 BC |
1810 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1811 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1812 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1813 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1814 | SIDLE_SMART_WKUP), | |
f776471f BC |
1815 | .sysc_fields = &omap_hwmod_sysc_type1, |
1816 | }; | |
1817 | ||
3b54baad | 1818 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1819 | .name = "gpio", |
1820 | .sysc = &omap44xx_gpio_sysc, | |
1821 | .rev = 2, | |
f776471f BC |
1822 | }; |
1823 | ||
3b54baad BC |
1824 | /* gpio dev_attr */ |
1825 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1826 | .bank_width = 32, |
1827 | .dbck_flag = true, | |
f776471f BC |
1828 | }; |
1829 | ||
3b54baad BC |
1830 | /* gpio1 */ |
1831 | static struct omap_hwmod omap44xx_gpio1_hwmod; | |
1832 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | |
1833 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1834 | { .irq = -1 } |
f776471f BC |
1835 | }; |
1836 | ||
3b54baad | 1837 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
f776471f | 1838 | { |
3b54baad BC |
1839 | .pa_start = 0x4a310000, |
1840 | .pa_end = 0x4a3101ff, | |
f776471f BC |
1841 | .flags = ADDR_TYPE_RT |
1842 | }, | |
78183f3f | 1843 | { } |
f776471f BC |
1844 | }; |
1845 | ||
3b54baad BC |
1846 | /* l4_wkup -> gpio1 */ |
1847 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
1848 | .master = &omap44xx_l4_wkup_hwmod, | |
1849 | .slave = &omap44xx_gpio1_hwmod, | |
b399bca8 | 1850 | .clk = "l4_wkup_clk_mux_ck", |
3b54baad | 1851 | .addr = omap44xx_gpio1_addrs, |
f776471f BC |
1852 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1853 | }; | |
1854 | ||
3b54baad BC |
1855 | /* gpio1 slave ports */ |
1856 | static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { | |
1857 | &omap44xx_l4_wkup__gpio1, | |
f776471f BC |
1858 | }; |
1859 | ||
3b54baad | 1860 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1861 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1862 | }; |
1863 | ||
1864 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1865 | .name = "gpio1", | |
1866 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1867 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1868 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1869 | .main_clk = "gpio1_ick", |
f776471f BC |
1870 | .prcm = { |
1871 | .omap4 = { | |
d0f0631d | 1872 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1873 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1874 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1875 | }, |
1876 | }, | |
3b54baad BC |
1877 | .opt_clks = gpio1_opt_clks, |
1878 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1879 | .dev_attr = &gpio_dev_attr, | |
1880 | .slaves = omap44xx_gpio1_slaves, | |
1881 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), | |
f776471f BC |
1882 | }; |
1883 | ||
3b54baad BC |
1884 | /* gpio2 */ |
1885 | static struct omap_hwmod omap44xx_gpio2_hwmod; | |
1886 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | |
1887 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1888 | { .irq = -1 } |
f776471f BC |
1889 | }; |
1890 | ||
3b54baad | 1891 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
f776471f | 1892 | { |
3b54baad BC |
1893 | .pa_start = 0x48055000, |
1894 | .pa_end = 0x480551ff, | |
f776471f BC |
1895 | .flags = ADDR_TYPE_RT |
1896 | }, | |
78183f3f | 1897 | { } |
f776471f BC |
1898 | }; |
1899 | ||
3b54baad BC |
1900 | /* l4_per -> gpio2 */ |
1901 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
f776471f | 1902 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1903 | .slave = &omap44xx_gpio2_hwmod, |
b399bca8 | 1904 | .clk = "l4_div_ck", |
3b54baad | 1905 | .addr = omap44xx_gpio2_addrs, |
f776471f BC |
1906 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1907 | }; | |
1908 | ||
3b54baad BC |
1909 | /* gpio2 slave ports */ |
1910 | static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { | |
1911 | &omap44xx_l4_per__gpio2, | |
f776471f BC |
1912 | }; |
1913 | ||
3b54baad | 1914 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1915 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1916 | }; |
1917 | ||
1918 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1919 | .name = "gpio2", | |
1920 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1921 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1922 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1923 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1924 | .main_clk = "gpio2_ick", |
f776471f BC |
1925 | .prcm = { |
1926 | .omap4 = { | |
d0f0631d | 1927 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1928 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1929 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1930 | }, |
1931 | }, | |
3b54baad BC |
1932 | .opt_clks = gpio2_opt_clks, |
1933 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1934 | .dev_attr = &gpio_dev_attr, | |
1935 | .slaves = omap44xx_gpio2_slaves, | |
1936 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), | |
f776471f BC |
1937 | }; |
1938 | ||
3b54baad BC |
1939 | /* gpio3 */ |
1940 | static struct omap_hwmod omap44xx_gpio3_hwmod; | |
1941 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | |
1942 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1943 | { .irq = -1 } |
f776471f BC |
1944 | }; |
1945 | ||
3b54baad | 1946 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
f776471f | 1947 | { |
3b54baad BC |
1948 | .pa_start = 0x48057000, |
1949 | .pa_end = 0x480571ff, | |
f776471f BC |
1950 | .flags = ADDR_TYPE_RT |
1951 | }, | |
78183f3f | 1952 | { } |
f776471f BC |
1953 | }; |
1954 | ||
3b54baad BC |
1955 | /* l4_per -> gpio3 */ |
1956 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
f776471f | 1957 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1958 | .slave = &omap44xx_gpio3_hwmod, |
b399bca8 | 1959 | .clk = "l4_div_ck", |
3b54baad | 1960 | .addr = omap44xx_gpio3_addrs, |
f776471f BC |
1961 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1962 | }; | |
1963 | ||
3b54baad BC |
1964 | /* gpio3 slave ports */ |
1965 | static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { | |
1966 | &omap44xx_l4_per__gpio3, | |
f776471f BC |
1967 | }; |
1968 | ||
3b54baad | 1969 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1970 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1971 | }; |
1972 | ||
1973 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1974 | .name = "gpio3", | |
1975 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1976 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1977 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1978 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1979 | .main_clk = "gpio3_ick", |
f776471f BC |
1980 | .prcm = { |
1981 | .omap4 = { | |
d0f0631d | 1982 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1983 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1984 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1985 | }, |
1986 | }, | |
3b54baad BC |
1987 | .opt_clks = gpio3_opt_clks, |
1988 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1989 | .dev_attr = &gpio_dev_attr, | |
1990 | .slaves = omap44xx_gpio3_slaves, | |
1991 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), | |
f776471f BC |
1992 | }; |
1993 | ||
3b54baad BC |
1994 | /* gpio4 */ |
1995 | static struct omap_hwmod omap44xx_gpio4_hwmod; | |
1996 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | |
1997 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1998 | { .irq = -1 } |
f776471f BC |
1999 | }; |
2000 | ||
3b54baad | 2001 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
f776471f | 2002 | { |
3b54baad BC |
2003 | .pa_start = 0x48059000, |
2004 | .pa_end = 0x480591ff, | |
f776471f BC |
2005 | .flags = ADDR_TYPE_RT |
2006 | }, | |
78183f3f | 2007 | { } |
f776471f BC |
2008 | }; |
2009 | ||
3b54baad BC |
2010 | /* l4_per -> gpio4 */ |
2011 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
f776471f | 2012 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2013 | .slave = &omap44xx_gpio4_hwmod, |
b399bca8 | 2014 | .clk = "l4_div_ck", |
3b54baad | 2015 | .addr = omap44xx_gpio4_addrs, |
f776471f BC |
2016 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2017 | }; | |
2018 | ||
3b54baad BC |
2019 | /* gpio4 slave ports */ |
2020 | static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { | |
2021 | &omap44xx_l4_per__gpio4, | |
f776471f BC |
2022 | }; |
2023 | ||
3b54baad | 2024 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 2025 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
2026 | }; |
2027 | ||
2028 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
2029 | .name = "gpio4", | |
2030 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2031 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2032 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2033 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 2034 | .main_clk = "gpio4_ick", |
f776471f BC |
2035 | .prcm = { |
2036 | .omap4 = { | |
d0f0631d | 2037 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 2038 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 2039 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
2040 | }, |
2041 | }, | |
3b54baad BC |
2042 | .opt_clks = gpio4_opt_clks, |
2043 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
2044 | .dev_attr = &gpio_dev_attr, | |
2045 | .slaves = omap44xx_gpio4_slaves, | |
2046 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), | |
f776471f BC |
2047 | }; |
2048 | ||
3b54baad BC |
2049 | /* gpio5 */ |
2050 | static struct omap_hwmod omap44xx_gpio5_hwmod; | |
2051 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | |
2052 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2053 | { .irq = -1 } |
55d2cb08 BC |
2054 | }; |
2055 | ||
3b54baad BC |
2056 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
2057 | { | |
2058 | .pa_start = 0x4805b000, | |
2059 | .pa_end = 0x4805b1ff, | |
2060 | .flags = ADDR_TYPE_RT | |
2061 | }, | |
78183f3f | 2062 | { } |
55d2cb08 BC |
2063 | }; |
2064 | ||
3b54baad BC |
2065 | /* l4_per -> gpio5 */ |
2066 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
2067 | .master = &omap44xx_l4_per_hwmod, | |
2068 | .slave = &omap44xx_gpio5_hwmod, | |
b399bca8 | 2069 | .clk = "l4_div_ck", |
3b54baad | 2070 | .addr = omap44xx_gpio5_addrs, |
3b54baad | 2071 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
55d2cb08 BC |
2072 | }; |
2073 | ||
3b54baad BC |
2074 | /* gpio5 slave ports */ |
2075 | static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { | |
2076 | &omap44xx_l4_per__gpio5, | |
55d2cb08 BC |
2077 | }; |
2078 | ||
3b54baad | 2079 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
b399bca8 | 2080 | { .role = "dbclk", .clk = "gpio5_dbclk" }, |
55d2cb08 BC |
2081 | }; |
2082 | ||
3b54baad BC |
2083 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
2084 | .name = "gpio5", | |
2085 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2086 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2087 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2088 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 2089 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
2090 | .prcm = { |
2091 | .omap4 = { | |
d0f0631d | 2092 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 2093 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 2094 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
2095 | }, |
2096 | }, | |
3b54baad BC |
2097 | .opt_clks = gpio5_opt_clks, |
2098 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
2099 | .dev_attr = &gpio_dev_attr, | |
2100 | .slaves = omap44xx_gpio5_slaves, | |
2101 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), | |
55d2cb08 BC |
2102 | }; |
2103 | ||
3b54baad BC |
2104 | /* gpio6 */ |
2105 | static struct omap_hwmod omap44xx_gpio6_hwmod; | |
2106 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | |
2107 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2108 | { .irq = -1 } |
92b18d1c BC |
2109 | }; |
2110 | ||
3b54baad | 2111 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
92b18d1c | 2112 | { |
3b54baad BC |
2113 | .pa_start = 0x4805d000, |
2114 | .pa_end = 0x4805d1ff, | |
92b18d1c BC |
2115 | .flags = ADDR_TYPE_RT |
2116 | }, | |
78183f3f | 2117 | { } |
92b18d1c BC |
2118 | }; |
2119 | ||
3b54baad BC |
2120 | /* l4_per -> gpio6 */ |
2121 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
2122 | .master = &omap44xx_l4_per_hwmod, | |
2123 | .slave = &omap44xx_gpio6_hwmod, | |
b399bca8 | 2124 | .clk = "l4_div_ck", |
3b54baad | 2125 | .addr = omap44xx_gpio6_addrs, |
3b54baad | 2126 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
db12ba53 BC |
2127 | }; |
2128 | ||
3b54baad BC |
2129 | /* gpio6 slave ports */ |
2130 | static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { | |
2131 | &omap44xx_l4_per__gpio6, | |
db12ba53 BC |
2132 | }; |
2133 | ||
3b54baad | 2134 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 2135 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
2136 | }; |
2137 | ||
3b54baad BC |
2138 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
2139 | .name = "gpio6", | |
2140 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2141 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2142 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2143 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
2144 | .main_clk = "gpio6_ick", |
2145 | .prcm = { | |
2146 | .omap4 = { | |
d0f0631d | 2147 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 2148 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 2149 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 2150 | }, |
db12ba53 | 2151 | }, |
3b54baad BC |
2152 | .opt_clks = gpio6_opt_clks, |
2153 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
2154 | .dev_attr = &gpio_dev_attr, | |
2155 | .slaves = omap44xx_gpio6_slaves, | |
2156 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), | |
db12ba53 BC |
2157 | }; |
2158 | ||
407a6888 BC |
2159 | /* |
2160 | * 'hsi' class | |
2161 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
2162 | * serial if) | |
2163 | */ | |
2164 | ||
2165 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
2166 | .rev_offs = 0x0000, | |
2167 | .sysc_offs = 0x0010, | |
2168 | .syss_offs = 0x0014, | |
2169 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
2170 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2171 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2172 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2173 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2174 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2175 | .sysc_fields = &omap_hwmod_sysc_type1, |
2176 | }; | |
2177 | ||
2178 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
2179 | .name = "hsi", | |
2180 | .sysc = &omap44xx_hsi_sysc, | |
2181 | }; | |
2182 | ||
2183 | /* hsi */ | |
2184 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
2185 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
2186 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
2187 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2188 | { .irq = -1 } |
407a6888 BC |
2189 | }; |
2190 | ||
2191 | /* hsi master ports */ | |
2192 | static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { | |
2193 | &omap44xx_hsi__l3_main_2, | |
2194 | }; | |
2195 | ||
2196 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { | |
2197 | { | |
2198 | .pa_start = 0x4a058000, | |
2199 | .pa_end = 0x4a05bfff, | |
2200 | .flags = ADDR_TYPE_RT | |
2201 | }, | |
78183f3f | 2202 | { } |
407a6888 BC |
2203 | }; |
2204 | ||
2205 | /* l4_cfg -> hsi */ | |
2206 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
2207 | .master = &omap44xx_l4_cfg_hwmod, | |
2208 | .slave = &omap44xx_hsi_hwmod, | |
2209 | .clk = "l4_div_ck", | |
2210 | .addr = omap44xx_hsi_addrs, | |
407a6888 BC |
2211 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2212 | }; | |
2213 | ||
2214 | /* hsi slave ports */ | |
2215 | static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { | |
2216 | &omap44xx_l4_cfg__hsi, | |
2217 | }; | |
2218 | ||
2219 | static struct omap_hwmod omap44xx_hsi_hwmod = { | |
2220 | .name = "hsi", | |
2221 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 2222 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2223 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 2224 | .main_clk = "hsi_fck", |
00fe610b | 2225 | .prcm = { |
407a6888 | 2226 | .omap4 = { |
d0f0631d | 2227 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 2228 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 2229 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
2230 | }, |
2231 | }, | |
2232 | .slaves = omap44xx_hsi_slaves, | |
2233 | .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), | |
2234 | .masters = omap44xx_hsi_masters, | |
2235 | .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), | |
407a6888 BC |
2236 | }; |
2237 | ||
3b54baad BC |
2238 | /* |
2239 | * 'i2c' class | |
2240 | * multimaster high-speed i2c controller | |
2241 | */ | |
db12ba53 | 2242 | |
3b54baad BC |
2243 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
2244 | .sysc_offs = 0x0010, | |
2245 | .syss_offs = 0x0090, | |
2246 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2247 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 2248 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
2249 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2250 | SIDLE_SMART_WKUP), | |
3e47dc6a | 2251 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 2252 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
2253 | }; |
2254 | ||
3b54baad | 2255 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
2256 | .name = "i2c", |
2257 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 2258 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 2259 | .reset = &omap_i2c_reset, |
db12ba53 BC |
2260 | }; |
2261 | ||
4d4441a6 AG |
2262 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2263 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
2264 | }; | |
2265 | ||
3b54baad BC |
2266 | /* i2c1 */ |
2267 | static struct omap_hwmod omap44xx_i2c1_hwmod; | |
2268 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | |
2269 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2270 | { .irq = -1 } |
db12ba53 BC |
2271 | }; |
2272 | ||
3b54baad BC |
2273 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
2274 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
2275 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2276 | { .dma_req = -1 } |
db12ba53 BC |
2277 | }; |
2278 | ||
3b54baad | 2279 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
db12ba53 | 2280 | { |
3b54baad BC |
2281 | .pa_start = 0x48070000, |
2282 | .pa_end = 0x480700ff, | |
db12ba53 BC |
2283 | .flags = ADDR_TYPE_RT |
2284 | }, | |
78183f3f | 2285 | { } |
db12ba53 BC |
2286 | }; |
2287 | ||
3b54baad BC |
2288 | /* l4_per -> i2c1 */ |
2289 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
2290 | .master = &omap44xx_l4_per_hwmod, | |
2291 | .slave = &omap44xx_i2c1_hwmod, | |
2292 | .clk = "l4_div_ck", | |
2293 | .addr = omap44xx_i2c1_addrs, | |
92b18d1c BC |
2294 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2295 | }; | |
2296 | ||
3b54baad BC |
2297 | /* i2c1 slave ports */ |
2298 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | |
2299 | &omap44xx_l4_per__i2c1, | |
92b18d1c BC |
2300 | }; |
2301 | ||
3b54baad BC |
2302 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
2303 | .name = "i2c1", | |
2304 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2305 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2306 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2307 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 2308 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 2309 | .main_clk = "i2c1_fck", |
92b18d1c BC |
2310 | .prcm = { |
2311 | .omap4 = { | |
d0f0631d | 2312 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 2313 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 2314 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
2315 | }, |
2316 | }, | |
3b54baad BC |
2317 | .slaves = omap44xx_i2c1_slaves, |
2318 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | |
4d4441a6 | 2319 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
2320 | }; |
2321 | ||
3b54baad BC |
2322 | /* i2c2 */ |
2323 | static struct omap_hwmod omap44xx_i2c2_hwmod; | |
2324 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | |
2325 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2326 | { .irq = -1 } |
92b18d1c BC |
2327 | }; |
2328 | ||
3b54baad BC |
2329 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
2330 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
2331 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2332 | { .dma_req = -1 } |
3b54baad BC |
2333 | }; |
2334 | ||
2335 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
92b18d1c | 2336 | { |
3b54baad BC |
2337 | .pa_start = 0x48072000, |
2338 | .pa_end = 0x480720ff, | |
92b18d1c BC |
2339 | .flags = ADDR_TYPE_RT |
2340 | }, | |
78183f3f | 2341 | { } |
92b18d1c BC |
2342 | }; |
2343 | ||
3b54baad BC |
2344 | /* l4_per -> i2c2 */ |
2345 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
db12ba53 | 2346 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2347 | .slave = &omap44xx_i2c2_hwmod, |
db12ba53 | 2348 | .clk = "l4_div_ck", |
3b54baad | 2349 | .addr = omap44xx_i2c2_addrs, |
db12ba53 BC |
2350 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2351 | }; | |
2352 | ||
3b54baad BC |
2353 | /* i2c2 slave ports */ |
2354 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | |
2355 | &omap44xx_l4_per__i2c2, | |
db12ba53 BC |
2356 | }; |
2357 | ||
3b54baad BC |
2358 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
2359 | .name = "i2c2", | |
2360 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2361 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2362 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2363 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 2364 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 2365 | .main_clk = "i2c2_fck", |
db12ba53 BC |
2366 | .prcm = { |
2367 | .omap4 = { | |
d0f0631d | 2368 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 2369 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 2370 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
2371 | }, |
2372 | }, | |
3b54baad BC |
2373 | .slaves = omap44xx_i2c2_slaves, |
2374 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | |
4d4441a6 | 2375 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
2376 | }; |
2377 | ||
3b54baad BC |
2378 | /* i2c3 */ |
2379 | static struct omap_hwmod omap44xx_i2c3_hwmod; | |
2380 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | |
2381 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2382 | { .irq = -1 } |
db12ba53 BC |
2383 | }; |
2384 | ||
3b54baad BC |
2385 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
2386 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
2387 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2388 | { .dma_req = -1 } |
92b18d1c BC |
2389 | }; |
2390 | ||
3b54baad | 2391 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
92b18d1c | 2392 | { |
3b54baad BC |
2393 | .pa_start = 0x48060000, |
2394 | .pa_end = 0x480600ff, | |
92b18d1c BC |
2395 | .flags = ADDR_TYPE_RT |
2396 | }, | |
78183f3f | 2397 | { } |
92b18d1c BC |
2398 | }; |
2399 | ||
3b54baad BC |
2400 | /* l4_per -> i2c3 */ |
2401 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
db12ba53 | 2402 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2403 | .slave = &omap44xx_i2c3_hwmod, |
db12ba53 | 2404 | .clk = "l4_div_ck", |
3b54baad | 2405 | .addr = omap44xx_i2c3_addrs, |
db12ba53 BC |
2406 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2407 | }; | |
2408 | ||
3b54baad BC |
2409 | /* i2c3 slave ports */ |
2410 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | |
2411 | &omap44xx_l4_per__i2c3, | |
db12ba53 BC |
2412 | }; |
2413 | ||
3b54baad BC |
2414 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
2415 | .name = "i2c3", | |
2416 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2417 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2418 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2419 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 2420 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 2421 | .main_clk = "i2c3_fck", |
db12ba53 BC |
2422 | .prcm = { |
2423 | .omap4 = { | |
d0f0631d | 2424 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 2425 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 2426 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
2427 | }, |
2428 | }, | |
3b54baad BC |
2429 | .slaves = omap44xx_i2c3_slaves, |
2430 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | |
4d4441a6 | 2431 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
2432 | }; |
2433 | ||
3b54baad BC |
2434 | /* i2c4 */ |
2435 | static struct omap_hwmod omap44xx_i2c4_hwmod; | |
2436 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | |
2437 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2438 | { .irq = -1 } |
db12ba53 BC |
2439 | }; |
2440 | ||
3b54baad BC |
2441 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
2442 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
2443 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2444 | { .dma_req = -1 } |
db12ba53 BC |
2445 | }; |
2446 | ||
3b54baad | 2447 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
db12ba53 | 2448 | { |
3b54baad BC |
2449 | .pa_start = 0x48350000, |
2450 | .pa_end = 0x483500ff, | |
db12ba53 BC |
2451 | .flags = ADDR_TYPE_RT |
2452 | }, | |
78183f3f | 2453 | { } |
db12ba53 BC |
2454 | }; |
2455 | ||
3b54baad BC |
2456 | /* l4_per -> i2c4 */ |
2457 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
2458 | .master = &omap44xx_l4_per_hwmod, | |
2459 | .slave = &omap44xx_i2c4_hwmod, | |
2460 | .clk = "l4_div_ck", | |
2461 | .addr = omap44xx_i2c4_addrs, | |
3b54baad | 2462 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
92b18d1c BC |
2463 | }; |
2464 | ||
3b54baad BC |
2465 | /* i2c4 slave ports */ |
2466 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | |
2467 | &omap44xx_l4_per__i2c4, | |
92b18d1c BC |
2468 | }; |
2469 | ||
3b54baad BC |
2470 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
2471 | .name = "i2c4", | |
2472 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2473 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2474 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2475 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 2476 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 2477 | .main_clk = "i2c4_fck", |
92b18d1c BC |
2478 | .prcm = { |
2479 | .omap4 = { | |
d0f0631d | 2480 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 2481 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 2482 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
2483 | }, |
2484 | }, | |
3b54baad BC |
2485 | .slaves = omap44xx_i2c4_slaves, |
2486 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | |
4d4441a6 | 2487 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
2488 | }; |
2489 | ||
407a6888 BC |
2490 | /* |
2491 | * 'ipu' class | |
2492 | * imaging processor unit | |
2493 | */ | |
2494 | ||
2495 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
2496 | .name = "ipu", | |
2497 | }; | |
2498 | ||
2499 | /* ipu */ | |
2500 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
2501 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2502 | { .irq = -1 } |
407a6888 BC |
2503 | }; |
2504 | ||
2505 | static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { | |
2506 | { .name = "cpu0", .rst_shift = 0 }, | |
2507 | }; | |
2508 | ||
2509 | static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { | |
2510 | { .name = "cpu1", .rst_shift = 1 }, | |
2511 | }; | |
2512 | ||
2513 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { | |
2514 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2515 | }; | |
2516 | ||
2517 | /* ipu master ports */ | |
2518 | static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { | |
2519 | &omap44xx_ipu__l3_main_2, | |
2520 | }; | |
2521 | ||
2522 | /* l3_main_2 -> ipu */ | |
2523 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
2524 | .master = &omap44xx_l3_main_2_hwmod, | |
2525 | .slave = &omap44xx_ipu_hwmod, | |
2526 | .clk = "l3_div_ck", | |
2527 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2528 | }; | |
2529 | ||
2530 | /* ipu slave ports */ | |
2531 | static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { | |
2532 | &omap44xx_l3_main_2__ipu, | |
2533 | }; | |
2534 | ||
2535 | /* Pseudo hwmod for reset control purpose only */ | |
2536 | static struct omap_hwmod omap44xx_ipu_c0_hwmod = { | |
2537 | .name = "ipu_c0", | |
2538 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2539 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
2540 | .flags = HWMOD_INIT_NO_RESET, |
2541 | .rst_lines = omap44xx_ipu_c0_resets, | |
2542 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), | |
00fe610b | 2543 | .prcm = { |
407a6888 | 2544 | .omap4 = { |
eaac329d | 2545 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
407a6888 BC |
2546 | }, |
2547 | }, | |
407a6888 BC |
2548 | }; |
2549 | ||
2550 | /* Pseudo hwmod for reset control purpose only */ | |
2551 | static struct omap_hwmod omap44xx_ipu_c1_hwmod = { | |
2552 | .name = "ipu_c1", | |
2553 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2554 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
2555 | .flags = HWMOD_INIT_NO_RESET, |
2556 | .rst_lines = omap44xx_ipu_c1_resets, | |
2557 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), | |
00fe610b | 2558 | .prcm = { |
407a6888 | 2559 | .omap4 = { |
eaac329d | 2560 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
407a6888 BC |
2561 | }, |
2562 | }, | |
407a6888 BC |
2563 | }; |
2564 | ||
2565 | static struct omap_hwmod omap44xx_ipu_hwmod = { | |
2566 | .name = "ipu", | |
2567 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2568 | .clkdm_name = "ducati_clkdm", |
407a6888 | 2569 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
2570 | .rst_lines = omap44xx_ipu_resets, |
2571 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
2572 | .main_clk = "ipu_fck", | |
00fe610b | 2573 | .prcm = { |
407a6888 | 2574 | .omap4 = { |
d0f0631d | 2575 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 2576 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 2577 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 2578 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
2579 | }, |
2580 | }, | |
2581 | .slaves = omap44xx_ipu_slaves, | |
2582 | .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), | |
2583 | .masters = omap44xx_ipu_masters, | |
2584 | .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), | |
407a6888 BC |
2585 | }; |
2586 | ||
2587 | /* | |
2588 | * 'iss' class | |
2589 | * external images sensor pixel data processor | |
2590 | */ | |
2591 | ||
2592 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
2593 | .rev_offs = 0x0000, | |
2594 | .sysc_offs = 0x0010, | |
2595 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
2596 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2597 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2598 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2599 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2600 | .sysc_fields = &omap_hwmod_sysc_type2, |
2601 | }; | |
2602 | ||
2603 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
2604 | .name = "iss", | |
2605 | .sysc = &omap44xx_iss_sysc, | |
2606 | }; | |
2607 | ||
2608 | /* iss */ | |
2609 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
2610 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2611 | { .irq = -1 } |
407a6888 BC |
2612 | }; |
2613 | ||
2614 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
2615 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
2616 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
2617 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
2618 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2619 | { .dma_req = -1 } |
407a6888 BC |
2620 | }; |
2621 | ||
2622 | /* iss master ports */ | |
2623 | static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { | |
2624 | &omap44xx_iss__l3_main_2, | |
2625 | }; | |
2626 | ||
2627 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
2628 | { | |
2629 | .pa_start = 0x52000000, | |
2630 | .pa_end = 0x520000ff, | |
2631 | .flags = ADDR_TYPE_RT | |
2632 | }, | |
78183f3f | 2633 | { } |
407a6888 BC |
2634 | }; |
2635 | ||
2636 | /* l3_main_2 -> iss */ | |
2637 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
2638 | .master = &omap44xx_l3_main_2_hwmod, | |
2639 | .slave = &omap44xx_iss_hwmod, | |
2640 | .clk = "l3_div_ck", | |
2641 | .addr = omap44xx_iss_addrs, | |
407a6888 BC |
2642 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2643 | }; | |
2644 | ||
2645 | /* iss slave ports */ | |
2646 | static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { | |
2647 | &omap44xx_l3_main_2__iss, | |
2648 | }; | |
2649 | ||
2650 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { | |
2651 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
2652 | }; | |
2653 | ||
2654 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
2655 | .name = "iss", | |
2656 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 2657 | .clkdm_name = "iss_clkdm", |
407a6888 | 2658 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 2659 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 2660 | .main_clk = "iss_fck", |
00fe610b | 2661 | .prcm = { |
407a6888 | 2662 | .omap4 = { |
d0f0631d | 2663 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 2664 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 2665 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2666 | }, |
2667 | }, | |
2668 | .opt_clks = iss_opt_clks, | |
2669 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
2670 | .slaves = omap44xx_iss_slaves, | |
2671 | .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), | |
2672 | .masters = omap44xx_iss_masters, | |
2673 | .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), | |
407a6888 BC |
2674 | }; |
2675 | ||
8f25bdc5 BC |
2676 | /* |
2677 | * 'iva' class | |
2678 | * multi-standard video encoder/decoder hardware accelerator | |
2679 | */ | |
2680 | ||
2681 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 2682 | .name = "iva", |
8f25bdc5 BC |
2683 | }; |
2684 | ||
2685 | /* iva */ | |
2686 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
2687 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
2688 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
2689 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2690 | { .irq = -1 } |
8f25bdc5 BC |
2691 | }; |
2692 | ||
2693 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
2694 | { .name = "logic", .rst_shift = 2 }, | |
2695 | }; | |
2696 | ||
2697 | static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { | |
2698 | { .name = "seq0", .rst_shift = 0 }, | |
2699 | }; | |
2700 | ||
2701 | static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { | |
2702 | { .name = "seq1", .rst_shift = 1 }, | |
2703 | }; | |
2704 | ||
2705 | /* iva master ports */ | |
2706 | static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { | |
2707 | &omap44xx_iva__l3_main_2, | |
2708 | &omap44xx_iva__l3_instr, | |
2709 | }; | |
2710 | ||
2711 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { | |
2712 | { | |
2713 | .pa_start = 0x5a000000, | |
2714 | .pa_end = 0x5a07ffff, | |
2715 | .flags = ADDR_TYPE_RT | |
2716 | }, | |
78183f3f | 2717 | { } |
8f25bdc5 BC |
2718 | }; |
2719 | ||
2720 | /* l3_main_2 -> iva */ | |
2721 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
2722 | .master = &omap44xx_l3_main_2_hwmod, | |
2723 | .slave = &omap44xx_iva_hwmod, | |
2724 | .clk = "l3_div_ck", | |
2725 | .addr = omap44xx_iva_addrs, | |
8f25bdc5 BC |
2726 | .user = OCP_USER_MPU, |
2727 | }; | |
2728 | ||
2729 | /* iva slave ports */ | |
2730 | static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { | |
2731 | &omap44xx_dsp__iva, | |
2732 | &omap44xx_l3_main_2__iva, | |
2733 | }; | |
2734 | ||
2735 | /* Pseudo hwmod for reset control purpose only */ | |
2736 | static struct omap_hwmod omap44xx_iva_seq0_hwmod = { | |
2737 | .name = "iva_seq0", | |
2738 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2739 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
2740 | .flags = HWMOD_INIT_NO_RESET, |
2741 | .rst_lines = omap44xx_iva_seq0_resets, | |
2742 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), | |
2743 | .prcm = { | |
2744 | .omap4 = { | |
eaac329d | 2745 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
8f25bdc5 BC |
2746 | }, |
2747 | }, | |
8f25bdc5 BC |
2748 | }; |
2749 | ||
2750 | /* Pseudo hwmod for reset control purpose only */ | |
2751 | static struct omap_hwmod omap44xx_iva_seq1_hwmod = { | |
2752 | .name = "iva_seq1", | |
2753 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2754 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
2755 | .flags = HWMOD_INIT_NO_RESET, |
2756 | .rst_lines = omap44xx_iva_seq1_resets, | |
2757 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), | |
2758 | .prcm = { | |
2759 | .omap4 = { | |
eaac329d | 2760 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
8f25bdc5 BC |
2761 | }, |
2762 | }, | |
8f25bdc5 BC |
2763 | }; |
2764 | ||
2765 | static struct omap_hwmod omap44xx_iva_hwmod = { | |
2766 | .name = "iva", | |
2767 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2768 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 2769 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
2770 | .rst_lines = omap44xx_iva_resets, |
2771 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
2772 | .main_clk = "iva_fck", | |
2773 | .prcm = { | |
2774 | .omap4 = { | |
d0f0631d | 2775 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 2776 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 2777 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 2778 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
2779 | }, |
2780 | }, | |
2781 | .slaves = omap44xx_iva_slaves, | |
2782 | .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), | |
2783 | .masters = omap44xx_iva_masters, | |
2784 | .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), | |
8f25bdc5 BC |
2785 | }; |
2786 | ||
407a6888 BC |
2787 | /* |
2788 | * 'kbd' class | |
2789 | * keyboard controller | |
2790 | */ | |
2791 | ||
2792 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
2793 | .rev_offs = 0x0000, | |
2794 | .sysc_offs = 0x0010, | |
2795 | .syss_offs = 0x0014, | |
2796 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2797 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2798 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2799 | SYSS_HAS_RESET_STATUS), | |
2800 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2801 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2802 | }; | |
2803 | ||
2804 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
2805 | .name = "kbd", | |
2806 | .sysc = &omap44xx_kbd_sysc, | |
2807 | }; | |
2808 | ||
2809 | /* kbd */ | |
2810 | static struct omap_hwmod omap44xx_kbd_hwmod; | |
2811 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { | |
2812 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2813 | { .irq = -1 } |
407a6888 BC |
2814 | }; |
2815 | ||
2816 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
2817 | { | |
2818 | .pa_start = 0x4a31c000, | |
2819 | .pa_end = 0x4a31c07f, | |
2820 | .flags = ADDR_TYPE_RT | |
2821 | }, | |
78183f3f | 2822 | { } |
407a6888 BC |
2823 | }; |
2824 | ||
2825 | /* l4_wkup -> kbd */ | |
2826 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
2827 | .master = &omap44xx_l4_wkup_hwmod, | |
2828 | .slave = &omap44xx_kbd_hwmod, | |
2829 | .clk = "l4_wkup_clk_mux_ck", | |
2830 | .addr = omap44xx_kbd_addrs, | |
407a6888 BC |
2831 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2832 | }; | |
2833 | ||
2834 | /* kbd slave ports */ | |
2835 | static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { | |
2836 | &omap44xx_l4_wkup__kbd, | |
2837 | }; | |
2838 | ||
2839 | static struct omap_hwmod omap44xx_kbd_hwmod = { | |
2840 | .name = "kbd", | |
2841 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 2842 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 2843 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 2844 | .main_clk = "kbd_fck", |
00fe610b | 2845 | .prcm = { |
407a6888 | 2846 | .omap4 = { |
d0f0631d | 2847 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 2848 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 2849 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2850 | }, |
2851 | }, | |
2852 | .slaves = omap44xx_kbd_slaves, | |
2853 | .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), | |
407a6888 BC |
2854 | }; |
2855 | ||
ec5df927 BC |
2856 | /* |
2857 | * 'mailbox' class | |
2858 | * mailbox module allowing communication between the on-chip processors using a | |
2859 | * queued mailbox-interrupt mechanism. | |
2860 | */ | |
2861 | ||
2862 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
2863 | .rev_offs = 0x0000, | |
2864 | .sysc_offs = 0x0010, | |
2865 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2866 | SYSC_HAS_SOFTRESET), | |
2867 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2868 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2869 | }; | |
2870 | ||
2871 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
2872 | .name = "mailbox", | |
2873 | .sysc = &omap44xx_mailbox_sysc, | |
2874 | }; | |
2875 | ||
2876 | /* mailbox */ | |
2877 | static struct omap_hwmod omap44xx_mailbox_hwmod; | |
2878 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { | |
2879 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2880 | { .irq = -1 } |
ec5df927 BC |
2881 | }; |
2882 | ||
2883 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
2884 | { | |
2885 | .pa_start = 0x4a0f4000, | |
2886 | .pa_end = 0x4a0f41ff, | |
2887 | .flags = ADDR_TYPE_RT | |
2888 | }, | |
78183f3f | 2889 | { } |
ec5df927 BC |
2890 | }; |
2891 | ||
2892 | /* l4_cfg -> mailbox */ | |
2893 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
2894 | .master = &omap44xx_l4_cfg_hwmod, | |
2895 | .slave = &omap44xx_mailbox_hwmod, | |
2896 | .clk = "l4_div_ck", | |
2897 | .addr = omap44xx_mailbox_addrs, | |
ec5df927 BC |
2898 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2899 | }; | |
2900 | ||
2901 | /* mailbox slave ports */ | |
2902 | static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { | |
2903 | &omap44xx_l4_cfg__mailbox, | |
2904 | }; | |
2905 | ||
2906 | static struct omap_hwmod omap44xx_mailbox_hwmod = { | |
2907 | .name = "mailbox", | |
2908 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 2909 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 2910 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 2911 | .prcm = { |
ec5df927 | 2912 | .omap4 = { |
d0f0631d | 2913 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 2914 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
2915 | }, |
2916 | }, | |
2917 | .slaves = omap44xx_mailbox_slaves, | |
2918 | .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), | |
ec5df927 BC |
2919 | }; |
2920 | ||
4ddff493 BC |
2921 | /* |
2922 | * 'mcbsp' class | |
2923 | * multi channel buffered serial port controller | |
2924 | */ | |
2925 | ||
2926 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
2927 | .sysc_offs = 0x008c, | |
2928 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
2929 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2930 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2931 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2932 | }; | |
2933 | ||
2934 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
2935 | .name = "mcbsp", | |
2936 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 2937 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
2938 | }; |
2939 | ||
2940 | /* mcbsp1 */ | |
2941 | static struct omap_hwmod omap44xx_mcbsp1_hwmod; | |
2942 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { | |
2943 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2944 | { .irq = -1 } |
4ddff493 BC |
2945 | }; |
2946 | ||
2947 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
2948 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
2949 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2950 | { .dma_req = -1 } |
4ddff493 BC |
2951 | }; |
2952 | ||
2953 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { | |
2954 | { | |
cb7e9ded | 2955 | .name = "mpu", |
4ddff493 BC |
2956 | .pa_start = 0x40122000, |
2957 | .pa_end = 0x401220ff, | |
2958 | .flags = ADDR_TYPE_RT | |
2959 | }, | |
78183f3f | 2960 | { } |
4ddff493 BC |
2961 | }; |
2962 | ||
2963 | /* l4_abe -> mcbsp1 */ | |
2964 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
2965 | .master = &omap44xx_l4_abe_hwmod, | |
2966 | .slave = &omap44xx_mcbsp1_hwmod, | |
2967 | .clk = "ocp_abe_iclk", | |
2968 | .addr = omap44xx_mcbsp1_addrs, | |
4ddff493 BC |
2969 | .user = OCP_USER_MPU, |
2970 | }; | |
2971 | ||
2972 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
2973 | { | |
cb7e9ded | 2974 | .name = "dma", |
4ddff493 BC |
2975 | .pa_start = 0x49022000, |
2976 | .pa_end = 0x490220ff, | |
2977 | .flags = ADDR_TYPE_RT | |
2978 | }, | |
78183f3f | 2979 | { } |
4ddff493 BC |
2980 | }; |
2981 | ||
2982 | /* l4_abe -> mcbsp1 (dma) */ | |
2983 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
2984 | .master = &omap44xx_l4_abe_hwmod, | |
2985 | .slave = &omap44xx_mcbsp1_hwmod, | |
2986 | .clk = "ocp_abe_iclk", | |
2987 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4ddff493 BC |
2988 | .user = OCP_USER_SDMA, |
2989 | }; | |
2990 | ||
2991 | /* mcbsp1 slave ports */ | |
2992 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { | |
2993 | &omap44xx_l4_abe__mcbsp1, | |
2994 | &omap44xx_l4_abe__mcbsp1_dma, | |
2995 | }; | |
2996 | ||
2997 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |
2998 | .name = "mcbsp1", | |
2999 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3000 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3001 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 3002 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
3003 | .main_clk = "mcbsp1_fck", |
3004 | .prcm = { | |
3005 | .omap4 = { | |
d0f0631d | 3006 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 3007 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 3008 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3009 | }, |
3010 | }, | |
3011 | .slaves = omap44xx_mcbsp1_slaves, | |
3012 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), | |
4ddff493 BC |
3013 | }; |
3014 | ||
3015 | /* mcbsp2 */ | |
3016 | static struct omap_hwmod omap44xx_mcbsp2_hwmod; | |
3017 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { | |
3018 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3019 | { .irq = -1 } |
4ddff493 BC |
3020 | }; |
3021 | ||
3022 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
3023 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
3024 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3025 | { .dma_req = -1 } |
4ddff493 BC |
3026 | }; |
3027 | ||
3028 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
3029 | { | |
cb7e9ded | 3030 | .name = "mpu", |
4ddff493 BC |
3031 | .pa_start = 0x40124000, |
3032 | .pa_end = 0x401240ff, | |
3033 | .flags = ADDR_TYPE_RT | |
3034 | }, | |
78183f3f | 3035 | { } |
4ddff493 BC |
3036 | }; |
3037 | ||
3038 | /* l4_abe -> mcbsp2 */ | |
3039 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
3040 | .master = &omap44xx_l4_abe_hwmod, | |
3041 | .slave = &omap44xx_mcbsp2_hwmod, | |
3042 | .clk = "ocp_abe_iclk", | |
3043 | .addr = omap44xx_mcbsp2_addrs, | |
4ddff493 BC |
3044 | .user = OCP_USER_MPU, |
3045 | }; | |
3046 | ||
3047 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
3048 | { | |
cb7e9ded | 3049 | .name = "dma", |
4ddff493 BC |
3050 | .pa_start = 0x49024000, |
3051 | .pa_end = 0x490240ff, | |
3052 | .flags = ADDR_TYPE_RT | |
3053 | }, | |
78183f3f | 3054 | { } |
4ddff493 BC |
3055 | }; |
3056 | ||
3057 | /* l4_abe -> mcbsp2 (dma) */ | |
3058 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
3059 | .master = &omap44xx_l4_abe_hwmod, | |
3060 | .slave = &omap44xx_mcbsp2_hwmod, | |
3061 | .clk = "ocp_abe_iclk", | |
3062 | .addr = omap44xx_mcbsp2_dma_addrs, | |
4ddff493 BC |
3063 | .user = OCP_USER_SDMA, |
3064 | }; | |
3065 | ||
3066 | /* mcbsp2 slave ports */ | |
3067 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { | |
3068 | &omap44xx_l4_abe__mcbsp2, | |
3069 | &omap44xx_l4_abe__mcbsp2_dma, | |
3070 | }; | |
3071 | ||
3072 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |
3073 | .name = "mcbsp2", | |
3074 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3075 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3076 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 3077 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
3078 | .main_clk = "mcbsp2_fck", |
3079 | .prcm = { | |
3080 | .omap4 = { | |
d0f0631d | 3081 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 3082 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 3083 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3084 | }, |
3085 | }, | |
3086 | .slaves = omap44xx_mcbsp2_slaves, | |
3087 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), | |
4ddff493 BC |
3088 | }; |
3089 | ||
3090 | /* mcbsp3 */ | |
3091 | static struct omap_hwmod omap44xx_mcbsp3_hwmod; | |
3092 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { | |
3093 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3094 | { .irq = -1 } |
4ddff493 BC |
3095 | }; |
3096 | ||
3097 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
3098 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
3099 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3100 | { .dma_req = -1 } |
4ddff493 BC |
3101 | }; |
3102 | ||
3103 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
3104 | { | |
cb7e9ded | 3105 | .name = "mpu", |
4ddff493 BC |
3106 | .pa_start = 0x40126000, |
3107 | .pa_end = 0x401260ff, | |
3108 | .flags = ADDR_TYPE_RT | |
3109 | }, | |
78183f3f | 3110 | { } |
4ddff493 BC |
3111 | }; |
3112 | ||
3113 | /* l4_abe -> mcbsp3 */ | |
3114 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
3115 | .master = &omap44xx_l4_abe_hwmod, | |
3116 | .slave = &omap44xx_mcbsp3_hwmod, | |
3117 | .clk = "ocp_abe_iclk", | |
3118 | .addr = omap44xx_mcbsp3_addrs, | |
4ddff493 BC |
3119 | .user = OCP_USER_MPU, |
3120 | }; | |
3121 | ||
3122 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
3123 | { | |
cb7e9ded | 3124 | .name = "dma", |
4ddff493 BC |
3125 | .pa_start = 0x49026000, |
3126 | .pa_end = 0x490260ff, | |
3127 | .flags = ADDR_TYPE_RT | |
3128 | }, | |
78183f3f | 3129 | { } |
4ddff493 BC |
3130 | }; |
3131 | ||
3132 | /* l4_abe -> mcbsp3 (dma) */ | |
3133 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
3134 | .master = &omap44xx_l4_abe_hwmod, | |
3135 | .slave = &omap44xx_mcbsp3_hwmod, | |
3136 | .clk = "ocp_abe_iclk", | |
3137 | .addr = omap44xx_mcbsp3_dma_addrs, | |
4ddff493 BC |
3138 | .user = OCP_USER_SDMA, |
3139 | }; | |
3140 | ||
3141 | /* mcbsp3 slave ports */ | |
3142 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { | |
3143 | &omap44xx_l4_abe__mcbsp3, | |
3144 | &omap44xx_l4_abe__mcbsp3_dma, | |
3145 | }; | |
3146 | ||
3147 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |
3148 | .name = "mcbsp3", | |
3149 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3150 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3151 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 3152 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
3153 | .main_clk = "mcbsp3_fck", |
3154 | .prcm = { | |
3155 | .omap4 = { | |
d0f0631d | 3156 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 3157 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 3158 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3159 | }, |
3160 | }, | |
3161 | .slaves = omap44xx_mcbsp3_slaves, | |
3162 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), | |
4ddff493 BC |
3163 | }; |
3164 | ||
3165 | /* mcbsp4 */ | |
3166 | static struct omap_hwmod omap44xx_mcbsp4_hwmod; | |
3167 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { | |
3168 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3169 | { .irq = -1 } |
4ddff493 BC |
3170 | }; |
3171 | ||
3172 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
3173 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
3174 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3175 | { .dma_req = -1 } |
4ddff493 BC |
3176 | }; |
3177 | ||
3178 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
3179 | { | |
3180 | .pa_start = 0x48096000, | |
3181 | .pa_end = 0x480960ff, | |
3182 | .flags = ADDR_TYPE_RT | |
3183 | }, | |
78183f3f | 3184 | { } |
4ddff493 BC |
3185 | }; |
3186 | ||
3187 | /* l4_per -> mcbsp4 */ | |
3188 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
3189 | .master = &omap44xx_l4_per_hwmod, | |
3190 | .slave = &omap44xx_mcbsp4_hwmod, | |
3191 | .clk = "l4_div_ck", | |
3192 | .addr = omap44xx_mcbsp4_addrs, | |
4ddff493 BC |
3193 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3194 | }; | |
3195 | ||
3196 | /* mcbsp4 slave ports */ | |
3197 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { | |
3198 | &omap44xx_l4_per__mcbsp4, | |
3199 | }; | |
3200 | ||
3201 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { | |
3202 | .name = "mcbsp4", | |
3203 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3204 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 3205 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 3206 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
3207 | .main_clk = "mcbsp4_fck", |
3208 | .prcm = { | |
3209 | .omap4 = { | |
d0f0631d | 3210 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 3211 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 3212 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3213 | }, |
3214 | }, | |
3215 | .slaves = omap44xx_mcbsp4_slaves, | |
3216 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), | |
4ddff493 BC |
3217 | }; |
3218 | ||
407a6888 BC |
3219 | /* |
3220 | * 'mcpdm' class | |
3221 | * multi channel pdm controller (proprietary interface with phoenix power | |
3222 | * ic) | |
3223 | */ | |
3224 | ||
3225 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
3226 | .rev_offs = 0x0000, | |
3227 | .sysc_offs = 0x0010, | |
3228 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3229 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3230 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3231 | SIDLE_SMART_WKUP), | |
3232 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3233 | }; | |
3234 | ||
3235 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
3236 | .name = "mcpdm", | |
3237 | .sysc = &omap44xx_mcpdm_sysc, | |
3238 | }; | |
3239 | ||
3240 | /* mcpdm */ | |
3241 | static struct omap_hwmod omap44xx_mcpdm_hwmod; | |
3242 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { | |
3243 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3244 | { .irq = -1 } |
407a6888 BC |
3245 | }; |
3246 | ||
3247 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
3248 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
3249 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3250 | { .dma_req = -1 } |
407a6888 BC |
3251 | }; |
3252 | ||
3253 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
3254 | { | |
3255 | .pa_start = 0x40132000, | |
3256 | .pa_end = 0x4013207f, | |
3257 | .flags = ADDR_TYPE_RT | |
3258 | }, | |
78183f3f | 3259 | { } |
407a6888 BC |
3260 | }; |
3261 | ||
3262 | /* l4_abe -> mcpdm */ | |
3263 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
3264 | .master = &omap44xx_l4_abe_hwmod, | |
3265 | .slave = &omap44xx_mcpdm_hwmod, | |
3266 | .clk = "ocp_abe_iclk", | |
3267 | .addr = omap44xx_mcpdm_addrs, | |
407a6888 BC |
3268 | .user = OCP_USER_MPU, |
3269 | }; | |
3270 | ||
3271 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
3272 | { | |
3273 | .pa_start = 0x49032000, | |
3274 | .pa_end = 0x4903207f, | |
3275 | .flags = ADDR_TYPE_RT | |
3276 | }, | |
78183f3f | 3277 | { } |
407a6888 BC |
3278 | }; |
3279 | ||
3280 | /* l4_abe -> mcpdm (dma) */ | |
3281 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
3282 | .master = &omap44xx_l4_abe_hwmod, | |
3283 | .slave = &omap44xx_mcpdm_hwmod, | |
3284 | .clk = "ocp_abe_iclk", | |
3285 | .addr = omap44xx_mcpdm_dma_addrs, | |
407a6888 BC |
3286 | .user = OCP_USER_SDMA, |
3287 | }; | |
3288 | ||
3289 | /* mcpdm slave ports */ | |
3290 | static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { | |
3291 | &omap44xx_l4_abe__mcpdm, | |
3292 | &omap44xx_l4_abe__mcpdm_dma, | |
3293 | }; | |
3294 | ||
3295 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |
3296 | .name = "mcpdm", | |
3297 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 3298 | .clkdm_name = "abe_clkdm", |
407a6888 | 3299 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 3300 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 3301 | .main_clk = "mcpdm_fck", |
00fe610b | 3302 | .prcm = { |
407a6888 | 3303 | .omap4 = { |
d0f0631d | 3304 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 3305 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 3306 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3307 | }, |
3308 | }, | |
3309 | .slaves = omap44xx_mcpdm_slaves, | |
3310 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), | |
407a6888 BC |
3311 | }; |
3312 | ||
9bcbd7f0 BC |
3313 | /* |
3314 | * 'mcspi' class | |
3315 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
3316 | * bus | |
3317 | */ | |
3318 | ||
3319 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
3320 | .rev_offs = 0x0000, | |
3321 | .sysc_offs = 0x0010, | |
3322 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3323 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3324 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3325 | SIDLE_SMART_WKUP), | |
3326 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3327 | }; | |
3328 | ||
3329 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
3330 | .name = "mcspi", | |
3331 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 3332 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
3333 | }; |
3334 | ||
3335 | /* mcspi1 */ | |
3336 | static struct omap_hwmod omap44xx_mcspi1_hwmod; | |
3337 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { | |
3338 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3339 | { .irq = -1 } |
9bcbd7f0 BC |
3340 | }; |
3341 | ||
3342 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
3343 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
3344 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
3345 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
3346 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
3347 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
3348 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
3349 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
3350 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3351 | { .dma_req = -1 } |
9bcbd7f0 BC |
3352 | }; |
3353 | ||
3354 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
3355 | { | |
3356 | .pa_start = 0x48098000, | |
3357 | .pa_end = 0x480981ff, | |
3358 | .flags = ADDR_TYPE_RT | |
3359 | }, | |
78183f3f | 3360 | { } |
9bcbd7f0 BC |
3361 | }; |
3362 | ||
3363 | /* l4_per -> mcspi1 */ | |
3364 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
3365 | .master = &omap44xx_l4_per_hwmod, | |
3366 | .slave = &omap44xx_mcspi1_hwmod, | |
3367 | .clk = "l4_div_ck", | |
3368 | .addr = omap44xx_mcspi1_addrs, | |
9bcbd7f0 BC |
3369 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3370 | }; | |
3371 | ||
3372 | /* mcspi1 slave ports */ | |
3373 | static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { | |
3374 | &omap44xx_l4_per__mcspi1, | |
3375 | }; | |
3376 | ||
905a74d9 BC |
3377 | /* mcspi1 dev_attr */ |
3378 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
3379 | .num_chipselect = 4, | |
3380 | }; | |
3381 | ||
9bcbd7f0 BC |
3382 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
3383 | .name = "mcspi1", | |
3384 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3385 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3386 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 3387 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
3388 | .main_clk = "mcspi1_fck", |
3389 | .prcm = { | |
3390 | .omap4 = { | |
d0f0631d | 3391 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 3392 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 3393 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3394 | }, |
3395 | }, | |
905a74d9 | 3396 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
3397 | .slaves = omap44xx_mcspi1_slaves, |
3398 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), | |
9bcbd7f0 BC |
3399 | }; |
3400 | ||
3401 | /* mcspi2 */ | |
3402 | static struct omap_hwmod omap44xx_mcspi2_hwmod; | |
3403 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { | |
3404 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3405 | { .irq = -1 } |
9bcbd7f0 BC |
3406 | }; |
3407 | ||
3408 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
3409 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
3410 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
3411 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
3412 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3413 | { .dma_req = -1 } |
9bcbd7f0 BC |
3414 | }; |
3415 | ||
3416 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
3417 | { | |
3418 | .pa_start = 0x4809a000, | |
3419 | .pa_end = 0x4809a1ff, | |
3420 | .flags = ADDR_TYPE_RT | |
3421 | }, | |
78183f3f | 3422 | { } |
9bcbd7f0 BC |
3423 | }; |
3424 | ||
3425 | /* l4_per -> mcspi2 */ | |
3426 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
3427 | .master = &omap44xx_l4_per_hwmod, | |
3428 | .slave = &omap44xx_mcspi2_hwmod, | |
3429 | .clk = "l4_div_ck", | |
3430 | .addr = omap44xx_mcspi2_addrs, | |
9bcbd7f0 BC |
3431 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3432 | }; | |
3433 | ||
3434 | /* mcspi2 slave ports */ | |
3435 | static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { | |
3436 | &omap44xx_l4_per__mcspi2, | |
3437 | }; | |
3438 | ||
905a74d9 BC |
3439 | /* mcspi2 dev_attr */ |
3440 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
3441 | .num_chipselect = 2, | |
3442 | }; | |
3443 | ||
9bcbd7f0 BC |
3444 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
3445 | .name = "mcspi2", | |
3446 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3447 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3448 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 3449 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
3450 | .main_clk = "mcspi2_fck", |
3451 | .prcm = { | |
3452 | .omap4 = { | |
d0f0631d | 3453 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 3454 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 3455 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3456 | }, |
3457 | }, | |
905a74d9 | 3458 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
3459 | .slaves = omap44xx_mcspi2_slaves, |
3460 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), | |
9bcbd7f0 BC |
3461 | }; |
3462 | ||
3463 | /* mcspi3 */ | |
3464 | static struct omap_hwmod omap44xx_mcspi3_hwmod; | |
3465 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { | |
3466 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3467 | { .irq = -1 } |
9bcbd7f0 BC |
3468 | }; |
3469 | ||
3470 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
3471 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
3472 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
3473 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
3474 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3475 | { .dma_req = -1 } |
9bcbd7f0 BC |
3476 | }; |
3477 | ||
3478 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
3479 | { | |
3480 | .pa_start = 0x480b8000, | |
3481 | .pa_end = 0x480b81ff, | |
3482 | .flags = ADDR_TYPE_RT | |
3483 | }, | |
78183f3f | 3484 | { } |
9bcbd7f0 BC |
3485 | }; |
3486 | ||
3487 | /* l4_per -> mcspi3 */ | |
3488 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
3489 | .master = &omap44xx_l4_per_hwmod, | |
3490 | .slave = &omap44xx_mcspi3_hwmod, | |
3491 | .clk = "l4_div_ck", | |
3492 | .addr = omap44xx_mcspi3_addrs, | |
9bcbd7f0 BC |
3493 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3494 | }; | |
3495 | ||
3496 | /* mcspi3 slave ports */ | |
3497 | static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { | |
3498 | &omap44xx_l4_per__mcspi3, | |
3499 | }; | |
3500 | ||
905a74d9 BC |
3501 | /* mcspi3 dev_attr */ |
3502 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
3503 | .num_chipselect = 2, | |
3504 | }; | |
3505 | ||
9bcbd7f0 BC |
3506 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
3507 | .name = "mcspi3", | |
3508 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3509 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3510 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 3511 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
3512 | .main_clk = "mcspi3_fck", |
3513 | .prcm = { | |
3514 | .omap4 = { | |
d0f0631d | 3515 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 3516 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 3517 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3518 | }, |
3519 | }, | |
905a74d9 | 3520 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
3521 | .slaves = omap44xx_mcspi3_slaves, |
3522 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), | |
9bcbd7f0 BC |
3523 | }; |
3524 | ||
3525 | /* mcspi4 */ | |
3526 | static struct omap_hwmod omap44xx_mcspi4_hwmod; | |
3527 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { | |
3528 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3529 | { .irq = -1 } |
9bcbd7f0 BC |
3530 | }; |
3531 | ||
3532 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
3533 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
3534 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3535 | { .dma_req = -1 } |
9bcbd7f0 BC |
3536 | }; |
3537 | ||
3538 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
3539 | { | |
3540 | .pa_start = 0x480ba000, | |
3541 | .pa_end = 0x480ba1ff, | |
3542 | .flags = ADDR_TYPE_RT | |
3543 | }, | |
78183f3f | 3544 | { } |
9bcbd7f0 BC |
3545 | }; |
3546 | ||
3547 | /* l4_per -> mcspi4 */ | |
3548 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
3549 | .master = &omap44xx_l4_per_hwmod, | |
3550 | .slave = &omap44xx_mcspi4_hwmod, | |
3551 | .clk = "l4_div_ck", | |
3552 | .addr = omap44xx_mcspi4_addrs, | |
9bcbd7f0 BC |
3553 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3554 | }; | |
3555 | ||
3556 | /* mcspi4 slave ports */ | |
3557 | static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { | |
3558 | &omap44xx_l4_per__mcspi4, | |
3559 | }; | |
3560 | ||
905a74d9 BC |
3561 | /* mcspi4 dev_attr */ |
3562 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
3563 | .num_chipselect = 1, | |
3564 | }; | |
3565 | ||
9bcbd7f0 BC |
3566 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
3567 | .name = "mcspi4", | |
3568 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3569 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3570 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 3571 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
3572 | .main_clk = "mcspi4_fck", |
3573 | .prcm = { | |
3574 | .omap4 = { | |
d0f0631d | 3575 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 3576 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 3577 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3578 | }, |
3579 | }, | |
905a74d9 | 3580 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
3581 | .slaves = omap44xx_mcspi4_slaves, |
3582 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), | |
9bcbd7f0 BC |
3583 | }; |
3584 | ||
407a6888 BC |
3585 | /* |
3586 | * 'mmc' class | |
3587 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
3588 | */ | |
3589 | ||
3590 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
3591 | .rev_offs = 0x0000, | |
3592 | .sysc_offs = 0x0010, | |
3593 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
3594 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
3595 | SYSC_HAS_SOFTRESET), | |
3596 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3597 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 3598 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
3599 | .sysc_fields = &omap_hwmod_sysc_type2, |
3600 | }; | |
3601 | ||
3602 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
3603 | .name = "mmc", | |
3604 | .sysc = &omap44xx_mmc_sysc, | |
3605 | }; | |
3606 | ||
3607 | /* mmc1 */ | |
3608 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
3609 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3610 | { .irq = -1 } |
407a6888 BC |
3611 | }; |
3612 | ||
3613 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
3614 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
3615 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3616 | { .dma_req = -1 } |
407a6888 BC |
3617 | }; |
3618 | ||
3619 | /* mmc1 master ports */ | |
3620 | static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { | |
3621 | &omap44xx_mmc1__l3_main_1, | |
3622 | }; | |
3623 | ||
3624 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
3625 | { | |
3626 | .pa_start = 0x4809c000, | |
3627 | .pa_end = 0x4809c3ff, | |
3628 | .flags = ADDR_TYPE_RT | |
3629 | }, | |
78183f3f | 3630 | { } |
407a6888 BC |
3631 | }; |
3632 | ||
3633 | /* l4_per -> mmc1 */ | |
3634 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
3635 | .master = &omap44xx_l4_per_hwmod, | |
3636 | .slave = &omap44xx_mmc1_hwmod, | |
3637 | .clk = "l4_div_ck", | |
3638 | .addr = omap44xx_mmc1_addrs, | |
407a6888 BC |
3639 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3640 | }; | |
3641 | ||
3642 | /* mmc1 slave ports */ | |
3643 | static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { | |
3644 | &omap44xx_l4_per__mmc1, | |
3645 | }; | |
3646 | ||
6ab8946f KK |
3647 | /* mmc1 dev_attr */ |
3648 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
3649 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
3650 | }; | |
3651 | ||
407a6888 BC |
3652 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
3653 | .name = "mmc1", | |
3654 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3655 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 3656 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 3657 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 3658 | .main_clk = "mmc1_fck", |
00fe610b | 3659 | .prcm = { |
407a6888 | 3660 | .omap4 = { |
d0f0631d | 3661 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 3662 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 3663 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3664 | }, |
3665 | }, | |
6ab8946f | 3666 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
3667 | .slaves = omap44xx_mmc1_slaves, |
3668 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), | |
3669 | .masters = omap44xx_mmc1_masters, | |
3670 | .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), | |
407a6888 BC |
3671 | }; |
3672 | ||
3673 | /* mmc2 */ | |
3674 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
3675 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3676 | { .irq = -1 } |
407a6888 BC |
3677 | }; |
3678 | ||
3679 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
3680 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
3681 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3682 | { .dma_req = -1 } |
407a6888 BC |
3683 | }; |
3684 | ||
3685 | /* mmc2 master ports */ | |
3686 | static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { | |
3687 | &omap44xx_mmc2__l3_main_1, | |
3688 | }; | |
3689 | ||
3690 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
3691 | { | |
3692 | .pa_start = 0x480b4000, | |
3693 | .pa_end = 0x480b43ff, | |
3694 | .flags = ADDR_TYPE_RT | |
3695 | }, | |
78183f3f | 3696 | { } |
407a6888 BC |
3697 | }; |
3698 | ||
3699 | /* l4_per -> mmc2 */ | |
3700 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
3701 | .master = &omap44xx_l4_per_hwmod, | |
3702 | .slave = &omap44xx_mmc2_hwmod, | |
3703 | .clk = "l4_div_ck", | |
3704 | .addr = omap44xx_mmc2_addrs, | |
407a6888 BC |
3705 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3706 | }; | |
3707 | ||
3708 | /* mmc2 slave ports */ | |
3709 | static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { | |
3710 | &omap44xx_l4_per__mmc2, | |
3711 | }; | |
3712 | ||
3713 | static struct omap_hwmod omap44xx_mmc2_hwmod = { | |
3714 | .name = "mmc2", | |
3715 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3716 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 3717 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 3718 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 3719 | .main_clk = "mmc2_fck", |
00fe610b | 3720 | .prcm = { |
407a6888 | 3721 | .omap4 = { |
d0f0631d | 3722 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 3723 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 3724 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3725 | }, |
3726 | }, | |
3727 | .slaves = omap44xx_mmc2_slaves, | |
3728 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), | |
3729 | .masters = omap44xx_mmc2_masters, | |
3730 | .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), | |
407a6888 BC |
3731 | }; |
3732 | ||
3733 | /* mmc3 */ | |
3734 | static struct omap_hwmod omap44xx_mmc3_hwmod; | |
3735 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { | |
3736 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3737 | { .irq = -1 } |
407a6888 BC |
3738 | }; |
3739 | ||
3740 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
3741 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
3742 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3743 | { .dma_req = -1 } |
407a6888 BC |
3744 | }; |
3745 | ||
3746 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
3747 | { | |
3748 | .pa_start = 0x480ad000, | |
3749 | .pa_end = 0x480ad3ff, | |
3750 | .flags = ADDR_TYPE_RT | |
3751 | }, | |
78183f3f | 3752 | { } |
407a6888 BC |
3753 | }; |
3754 | ||
3755 | /* l4_per -> mmc3 */ | |
3756 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
3757 | .master = &omap44xx_l4_per_hwmod, | |
3758 | .slave = &omap44xx_mmc3_hwmod, | |
3759 | .clk = "l4_div_ck", | |
3760 | .addr = omap44xx_mmc3_addrs, | |
407a6888 BC |
3761 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3762 | }; | |
3763 | ||
3764 | /* mmc3 slave ports */ | |
3765 | static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { | |
3766 | &omap44xx_l4_per__mmc3, | |
3767 | }; | |
3768 | ||
3769 | static struct omap_hwmod omap44xx_mmc3_hwmod = { | |
3770 | .name = "mmc3", | |
3771 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3772 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3773 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 3774 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 3775 | .main_clk = "mmc3_fck", |
00fe610b | 3776 | .prcm = { |
407a6888 | 3777 | .omap4 = { |
d0f0631d | 3778 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 3779 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 3780 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3781 | }, |
3782 | }, | |
3783 | .slaves = omap44xx_mmc3_slaves, | |
3784 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), | |
407a6888 BC |
3785 | }; |
3786 | ||
3787 | /* mmc4 */ | |
3788 | static struct omap_hwmod omap44xx_mmc4_hwmod; | |
3789 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { | |
3790 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3791 | { .irq = -1 } |
407a6888 BC |
3792 | }; |
3793 | ||
3794 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
3795 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
3796 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3797 | { .dma_req = -1 } |
407a6888 BC |
3798 | }; |
3799 | ||
3800 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
3801 | { | |
3802 | .pa_start = 0x480d1000, | |
3803 | .pa_end = 0x480d13ff, | |
3804 | .flags = ADDR_TYPE_RT | |
3805 | }, | |
78183f3f | 3806 | { } |
407a6888 BC |
3807 | }; |
3808 | ||
3809 | /* l4_per -> mmc4 */ | |
3810 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
3811 | .master = &omap44xx_l4_per_hwmod, | |
3812 | .slave = &omap44xx_mmc4_hwmod, | |
3813 | .clk = "l4_div_ck", | |
3814 | .addr = omap44xx_mmc4_addrs, | |
407a6888 BC |
3815 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3816 | }; | |
3817 | ||
3818 | /* mmc4 slave ports */ | |
3819 | static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { | |
3820 | &omap44xx_l4_per__mmc4, | |
3821 | }; | |
3822 | ||
3823 | static struct omap_hwmod omap44xx_mmc4_hwmod = { | |
3824 | .name = "mmc4", | |
3825 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3826 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3827 | .mpu_irqs = omap44xx_mmc4_irqs, |
212738a4 | 3828 | |
407a6888 | 3829 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 3830 | .main_clk = "mmc4_fck", |
00fe610b | 3831 | .prcm = { |
407a6888 | 3832 | .omap4 = { |
d0f0631d | 3833 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 3834 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 3835 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3836 | }, |
3837 | }, | |
3838 | .slaves = omap44xx_mmc4_slaves, | |
3839 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), | |
407a6888 BC |
3840 | }; |
3841 | ||
3842 | /* mmc5 */ | |
3843 | static struct omap_hwmod omap44xx_mmc5_hwmod; | |
3844 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { | |
3845 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3846 | { .irq = -1 } |
407a6888 BC |
3847 | }; |
3848 | ||
3849 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
3850 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
3851 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3852 | { .dma_req = -1 } |
407a6888 BC |
3853 | }; |
3854 | ||
3855 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
3856 | { | |
3857 | .pa_start = 0x480d5000, | |
3858 | .pa_end = 0x480d53ff, | |
3859 | .flags = ADDR_TYPE_RT | |
3860 | }, | |
78183f3f | 3861 | { } |
407a6888 BC |
3862 | }; |
3863 | ||
3864 | /* l4_per -> mmc5 */ | |
3865 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
3866 | .master = &omap44xx_l4_per_hwmod, | |
3867 | .slave = &omap44xx_mmc5_hwmod, | |
3868 | .clk = "l4_div_ck", | |
3869 | .addr = omap44xx_mmc5_addrs, | |
407a6888 BC |
3870 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3871 | }; | |
3872 | ||
3873 | /* mmc5 slave ports */ | |
3874 | static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { | |
3875 | &omap44xx_l4_per__mmc5, | |
3876 | }; | |
3877 | ||
3878 | static struct omap_hwmod omap44xx_mmc5_hwmod = { | |
3879 | .name = "mmc5", | |
3880 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3881 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3882 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 3883 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 3884 | .main_clk = "mmc5_fck", |
00fe610b | 3885 | .prcm = { |
407a6888 | 3886 | .omap4 = { |
d0f0631d | 3887 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 3888 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 3889 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3890 | }, |
3891 | }, | |
3892 | .slaves = omap44xx_mmc5_slaves, | |
3893 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), | |
407a6888 BC |
3894 | }; |
3895 | ||
3b54baad BC |
3896 | /* |
3897 | * 'mpu' class | |
3898 | * mpu sub-system | |
3899 | */ | |
3900 | ||
3901 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 3902 | .name = "mpu", |
db12ba53 BC |
3903 | }; |
3904 | ||
3b54baad BC |
3905 | /* mpu */ |
3906 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
3907 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
3908 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
3909 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3910 | { .irq = -1 } |
db12ba53 BC |
3911 | }; |
3912 | ||
3b54baad BC |
3913 | /* mpu master ports */ |
3914 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { | |
3915 | &omap44xx_mpu__l3_main_1, | |
3916 | &omap44xx_mpu__l4_abe, | |
3917 | &omap44xx_mpu__dmm, | |
3918 | }; | |
3919 | ||
3920 | static struct omap_hwmod omap44xx_mpu_hwmod = { | |
3921 | .name = "mpu", | |
3922 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 3923 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 3924 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3925 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 3926 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
3927 | .prcm = { |
3928 | .omap4 = { | |
d0f0631d | 3929 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 3930 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
3931 | }, |
3932 | }, | |
3b54baad BC |
3933 | .masters = omap44xx_mpu_masters, |
3934 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), | |
db12ba53 BC |
3935 | }; |
3936 | ||
1f6a717f BC |
3937 | /* |
3938 | * 'smartreflex' class | |
3939 | * smartreflex module (monitor silicon performance and outputs a measure of | |
3940 | * performance error) | |
3941 | */ | |
3942 | ||
3943 | /* The IP is not compliant to type1 / type2 scheme */ | |
3944 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
3945 | .sidle_shift = 24, | |
3946 | .enwkup_shift = 26, | |
3947 | }; | |
3948 | ||
3949 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
3950 | .sysc_offs = 0x0038, | |
3951 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
3952 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3953 | SIDLE_SMART_WKUP), | |
3954 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
3955 | }; | |
3956 | ||
3957 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
3958 | .name = "smartreflex", |
3959 | .sysc = &omap44xx_smartreflex_sysc, | |
3960 | .rev = 2, | |
1f6a717f BC |
3961 | }; |
3962 | ||
3963 | /* smartreflex_core */ | |
3964 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod; | |
3965 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { | |
3966 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3967 | { .irq = -1 } |
1f6a717f BC |
3968 | }; |
3969 | ||
3970 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { | |
3971 | { | |
3972 | .pa_start = 0x4a0dd000, | |
3973 | .pa_end = 0x4a0dd03f, | |
3974 | .flags = ADDR_TYPE_RT | |
3975 | }, | |
78183f3f | 3976 | { } |
1f6a717f BC |
3977 | }; |
3978 | ||
3979 | /* l4_cfg -> smartreflex_core */ | |
3980 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
3981 | .master = &omap44xx_l4_cfg_hwmod, | |
3982 | .slave = &omap44xx_smartreflex_core_hwmod, | |
3983 | .clk = "l4_div_ck", | |
3984 | .addr = omap44xx_smartreflex_core_addrs, | |
1f6a717f BC |
3985 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3986 | }; | |
3987 | ||
3988 | /* smartreflex_core slave ports */ | |
3989 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { | |
3990 | &omap44xx_l4_cfg__smartreflex_core, | |
3991 | }; | |
3992 | ||
3993 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | |
3994 | .name = "smartreflex_core", | |
3995 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 3996 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 3997 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 3998 | |
1f6a717f BC |
3999 | .main_clk = "smartreflex_core_fck", |
4000 | .vdd_name = "core", | |
4001 | .prcm = { | |
4002 | .omap4 = { | |
d0f0631d | 4003 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 4004 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 4005 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4006 | }, |
4007 | }, | |
4008 | .slaves = omap44xx_smartreflex_core_slaves, | |
4009 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), | |
1f6a717f BC |
4010 | }; |
4011 | ||
4012 | /* smartreflex_iva */ | |
4013 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; | |
4014 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { | |
4015 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4016 | { .irq = -1 } |
1f6a717f BC |
4017 | }; |
4018 | ||
4019 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
4020 | { | |
4021 | .pa_start = 0x4a0db000, | |
4022 | .pa_end = 0x4a0db03f, | |
4023 | .flags = ADDR_TYPE_RT | |
4024 | }, | |
78183f3f | 4025 | { } |
1f6a717f BC |
4026 | }; |
4027 | ||
4028 | /* l4_cfg -> smartreflex_iva */ | |
4029 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
4030 | .master = &omap44xx_l4_cfg_hwmod, | |
4031 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
4032 | .clk = "l4_div_ck", | |
4033 | .addr = omap44xx_smartreflex_iva_addrs, | |
1f6a717f BC |
4034 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4035 | }; | |
4036 | ||
4037 | /* smartreflex_iva slave ports */ | |
4038 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { | |
4039 | &omap44xx_l4_cfg__smartreflex_iva, | |
4040 | }; | |
4041 | ||
4042 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | |
4043 | .name = "smartreflex_iva", | |
4044 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4045 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4046 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f BC |
4047 | .main_clk = "smartreflex_iva_fck", |
4048 | .vdd_name = "iva", | |
4049 | .prcm = { | |
4050 | .omap4 = { | |
d0f0631d | 4051 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 4052 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 4053 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4054 | }, |
4055 | }, | |
4056 | .slaves = omap44xx_smartreflex_iva_slaves, | |
4057 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), | |
1f6a717f BC |
4058 | }; |
4059 | ||
4060 | /* smartreflex_mpu */ | |
4061 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; | |
4062 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { | |
4063 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4064 | { .irq = -1 } |
1f6a717f BC |
4065 | }; |
4066 | ||
4067 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
4068 | { | |
4069 | .pa_start = 0x4a0d9000, | |
4070 | .pa_end = 0x4a0d903f, | |
4071 | .flags = ADDR_TYPE_RT | |
4072 | }, | |
78183f3f | 4073 | { } |
1f6a717f BC |
4074 | }; |
4075 | ||
4076 | /* l4_cfg -> smartreflex_mpu */ | |
4077 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
4078 | .master = &omap44xx_l4_cfg_hwmod, | |
4079 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
4080 | .clk = "l4_div_ck", | |
4081 | .addr = omap44xx_smartreflex_mpu_addrs, | |
1f6a717f BC |
4082 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4083 | }; | |
4084 | ||
4085 | /* smartreflex_mpu slave ports */ | |
4086 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { | |
4087 | &omap44xx_l4_cfg__smartreflex_mpu, | |
4088 | }; | |
4089 | ||
4090 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | |
4091 | .name = "smartreflex_mpu", | |
4092 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4093 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4094 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f BC |
4095 | .main_clk = "smartreflex_mpu_fck", |
4096 | .vdd_name = "mpu", | |
4097 | .prcm = { | |
4098 | .omap4 = { | |
d0f0631d | 4099 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 4100 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 4101 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4102 | }, |
4103 | }, | |
4104 | .slaves = omap44xx_smartreflex_mpu_slaves, | |
4105 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), | |
1f6a717f BC |
4106 | }; |
4107 | ||
d11c217f BC |
4108 | /* |
4109 | * 'spinlock' class | |
4110 | * spinlock provides hardware assistance for synchronizing the processes | |
4111 | * running on multiple processors | |
4112 | */ | |
4113 | ||
4114 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
4115 | .rev_offs = 0x0000, | |
4116 | .sysc_offs = 0x0010, | |
4117 | .syss_offs = 0x0014, | |
4118 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
4119 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
4120 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
4121 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
4122 | SIDLE_SMART_WKUP), | |
4123 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4124 | }; | |
4125 | ||
4126 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
4127 | .name = "spinlock", | |
4128 | .sysc = &omap44xx_spinlock_sysc, | |
4129 | }; | |
4130 | ||
4131 | /* spinlock */ | |
4132 | static struct omap_hwmod omap44xx_spinlock_hwmod; | |
4133 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
4134 | { | |
4135 | .pa_start = 0x4a0f6000, | |
4136 | .pa_end = 0x4a0f6fff, | |
4137 | .flags = ADDR_TYPE_RT | |
4138 | }, | |
78183f3f | 4139 | { } |
d11c217f BC |
4140 | }; |
4141 | ||
4142 | /* l4_cfg -> spinlock */ | |
4143 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
4144 | .master = &omap44xx_l4_cfg_hwmod, | |
4145 | .slave = &omap44xx_spinlock_hwmod, | |
4146 | .clk = "l4_div_ck", | |
4147 | .addr = omap44xx_spinlock_addrs, | |
d11c217f BC |
4148 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4149 | }; | |
4150 | ||
4151 | /* spinlock slave ports */ | |
4152 | static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { | |
4153 | &omap44xx_l4_cfg__spinlock, | |
4154 | }; | |
4155 | ||
4156 | static struct omap_hwmod omap44xx_spinlock_hwmod = { | |
4157 | .name = "spinlock", | |
4158 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 4159 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
4160 | .prcm = { |
4161 | .omap4 = { | |
d0f0631d | 4162 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 4163 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
4164 | }, |
4165 | }, | |
4166 | .slaves = omap44xx_spinlock_slaves, | |
4167 | .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), | |
d11c217f BC |
4168 | }; |
4169 | ||
35d1a66a BC |
4170 | /* |
4171 | * 'timer' class | |
4172 | * general purpose timer module with accurate 1ms tick | |
4173 | * This class contains several variants: ['timer_1ms', 'timer'] | |
4174 | */ | |
4175 | ||
4176 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
4177 | .rev_offs = 0x0000, | |
4178 | .sysc_offs = 0x0010, | |
4179 | .syss_offs = 0x0014, | |
4180 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
4181 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
4182 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
4183 | SYSS_HAS_RESET_STATUS), | |
4184 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
4185 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4186 | }; | |
4187 | ||
4188 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
4189 | .name = "timer", | |
4190 | .sysc = &omap44xx_timer_1ms_sysc, | |
4191 | }; | |
4192 | ||
4193 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
4194 | .rev_offs = 0x0000, | |
4195 | .sysc_offs = 0x0010, | |
4196 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
4197 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
4198 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
4199 | SIDLE_SMART_WKUP), | |
4200 | .sysc_fields = &omap_hwmod_sysc_type2, | |
4201 | }; | |
4202 | ||
4203 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
4204 | .name = "timer", | |
4205 | .sysc = &omap44xx_timer_sysc, | |
4206 | }; | |
4207 | ||
c345c8b0 TKD |
4208 | /* always-on timers dev attribute */ |
4209 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
4210 | .timer_capability = OMAP_TIMER_ALWON, | |
4211 | }; | |
4212 | ||
4213 | /* pwm timers dev attribute */ | |
4214 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
4215 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
4216 | }; | |
4217 | ||
35d1a66a BC |
4218 | /* timer1 */ |
4219 | static struct omap_hwmod omap44xx_timer1_hwmod; | |
4220 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { | |
4221 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4222 | { .irq = -1 } |
35d1a66a BC |
4223 | }; |
4224 | ||
4225 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
4226 | { | |
4227 | .pa_start = 0x4a318000, | |
4228 | .pa_end = 0x4a31807f, | |
4229 | .flags = ADDR_TYPE_RT | |
4230 | }, | |
78183f3f | 4231 | { } |
35d1a66a BC |
4232 | }; |
4233 | ||
4234 | /* l4_wkup -> timer1 */ | |
4235 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
4236 | .master = &omap44xx_l4_wkup_hwmod, | |
4237 | .slave = &omap44xx_timer1_hwmod, | |
4238 | .clk = "l4_wkup_clk_mux_ck", | |
4239 | .addr = omap44xx_timer1_addrs, | |
35d1a66a BC |
4240 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4241 | }; | |
4242 | ||
4243 | /* timer1 slave ports */ | |
4244 | static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { | |
4245 | &omap44xx_l4_wkup__timer1, | |
4246 | }; | |
4247 | ||
4248 | static struct omap_hwmod omap44xx_timer1_hwmod = { | |
4249 | .name = "timer1", | |
4250 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4251 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 4252 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
4253 | .main_clk = "timer1_fck", |
4254 | .prcm = { | |
4255 | .omap4 = { | |
d0f0631d | 4256 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 4257 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 4258 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4259 | }, |
4260 | }, | |
c345c8b0 | 4261 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4262 | .slaves = omap44xx_timer1_slaves, |
4263 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), | |
35d1a66a BC |
4264 | }; |
4265 | ||
4266 | /* timer2 */ | |
4267 | static struct omap_hwmod omap44xx_timer2_hwmod; | |
4268 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { | |
4269 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4270 | { .irq = -1 } |
35d1a66a BC |
4271 | }; |
4272 | ||
4273 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
4274 | { | |
4275 | .pa_start = 0x48032000, | |
4276 | .pa_end = 0x4803207f, | |
4277 | .flags = ADDR_TYPE_RT | |
4278 | }, | |
78183f3f | 4279 | { } |
35d1a66a BC |
4280 | }; |
4281 | ||
4282 | /* l4_per -> timer2 */ | |
4283 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
4284 | .master = &omap44xx_l4_per_hwmod, | |
4285 | .slave = &omap44xx_timer2_hwmod, | |
4286 | .clk = "l4_div_ck", | |
4287 | .addr = omap44xx_timer2_addrs, | |
35d1a66a BC |
4288 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4289 | }; | |
4290 | ||
4291 | /* timer2 slave ports */ | |
4292 | static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { | |
4293 | &omap44xx_l4_per__timer2, | |
4294 | }; | |
4295 | ||
4296 | static struct omap_hwmod omap44xx_timer2_hwmod = { | |
4297 | .name = "timer2", | |
4298 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4299 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4300 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
4301 | .main_clk = "timer2_fck", |
4302 | .prcm = { | |
4303 | .omap4 = { | |
d0f0631d | 4304 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 4305 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 4306 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4307 | }, |
4308 | }, | |
c345c8b0 | 4309 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4310 | .slaves = omap44xx_timer2_slaves, |
4311 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), | |
35d1a66a BC |
4312 | }; |
4313 | ||
4314 | /* timer3 */ | |
4315 | static struct omap_hwmod omap44xx_timer3_hwmod; | |
4316 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { | |
4317 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4318 | { .irq = -1 } |
35d1a66a BC |
4319 | }; |
4320 | ||
4321 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
4322 | { | |
4323 | .pa_start = 0x48034000, | |
4324 | .pa_end = 0x4803407f, | |
4325 | .flags = ADDR_TYPE_RT | |
4326 | }, | |
78183f3f | 4327 | { } |
35d1a66a BC |
4328 | }; |
4329 | ||
4330 | /* l4_per -> timer3 */ | |
4331 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
4332 | .master = &omap44xx_l4_per_hwmod, | |
4333 | .slave = &omap44xx_timer3_hwmod, | |
4334 | .clk = "l4_div_ck", | |
4335 | .addr = omap44xx_timer3_addrs, | |
35d1a66a BC |
4336 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4337 | }; | |
4338 | ||
4339 | /* timer3 slave ports */ | |
4340 | static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { | |
4341 | &omap44xx_l4_per__timer3, | |
4342 | }; | |
4343 | ||
4344 | static struct omap_hwmod omap44xx_timer3_hwmod = { | |
4345 | .name = "timer3", | |
4346 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4347 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4348 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
4349 | .main_clk = "timer3_fck", |
4350 | .prcm = { | |
4351 | .omap4 = { | |
d0f0631d | 4352 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 4353 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 4354 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4355 | }, |
4356 | }, | |
c345c8b0 | 4357 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4358 | .slaves = omap44xx_timer3_slaves, |
4359 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), | |
35d1a66a BC |
4360 | }; |
4361 | ||
4362 | /* timer4 */ | |
4363 | static struct omap_hwmod omap44xx_timer4_hwmod; | |
4364 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { | |
4365 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4366 | { .irq = -1 } |
35d1a66a BC |
4367 | }; |
4368 | ||
4369 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
4370 | { | |
4371 | .pa_start = 0x48036000, | |
4372 | .pa_end = 0x4803607f, | |
4373 | .flags = ADDR_TYPE_RT | |
4374 | }, | |
78183f3f | 4375 | { } |
35d1a66a BC |
4376 | }; |
4377 | ||
4378 | /* l4_per -> timer4 */ | |
4379 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
4380 | .master = &omap44xx_l4_per_hwmod, | |
4381 | .slave = &omap44xx_timer4_hwmod, | |
4382 | .clk = "l4_div_ck", | |
4383 | .addr = omap44xx_timer4_addrs, | |
35d1a66a BC |
4384 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4385 | }; | |
4386 | ||
4387 | /* timer4 slave ports */ | |
4388 | static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { | |
4389 | &omap44xx_l4_per__timer4, | |
4390 | }; | |
4391 | ||
4392 | static struct omap_hwmod omap44xx_timer4_hwmod = { | |
4393 | .name = "timer4", | |
4394 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4395 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4396 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
4397 | .main_clk = "timer4_fck", |
4398 | .prcm = { | |
4399 | .omap4 = { | |
d0f0631d | 4400 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 4401 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 4402 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4403 | }, |
4404 | }, | |
c345c8b0 | 4405 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4406 | .slaves = omap44xx_timer4_slaves, |
4407 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), | |
35d1a66a BC |
4408 | }; |
4409 | ||
4410 | /* timer5 */ | |
4411 | static struct omap_hwmod omap44xx_timer5_hwmod; | |
4412 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { | |
4413 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4414 | { .irq = -1 } |
35d1a66a BC |
4415 | }; |
4416 | ||
4417 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
4418 | { | |
4419 | .pa_start = 0x40138000, | |
4420 | .pa_end = 0x4013807f, | |
4421 | .flags = ADDR_TYPE_RT | |
4422 | }, | |
78183f3f | 4423 | { } |
35d1a66a BC |
4424 | }; |
4425 | ||
4426 | /* l4_abe -> timer5 */ | |
4427 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
4428 | .master = &omap44xx_l4_abe_hwmod, | |
4429 | .slave = &omap44xx_timer5_hwmod, | |
4430 | .clk = "ocp_abe_iclk", | |
4431 | .addr = omap44xx_timer5_addrs, | |
35d1a66a BC |
4432 | .user = OCP_USER_MPU, |
4433 | }; | |
4434 | ||
4435 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
4436 | { | |
4437 | .pa_start = 0x49038000, | |
4438 | .pa_end = 0x4903807f, | |
4439 | .flags = ADDR_TYPE_RT | |
4440 | }, | |
78183f3f | 4441 | { } |
35d1a66a BC |
4442 | }; |
4443 | ||
4444 | /* l4_abe -> timer5 (dma) */ | |
4445 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
4446 | .master = &omap44xx_l4_abe_hwmod, | |
4447 | .slave = &omap44xx_timer5_hwmod, | |
4448 | .clk = "ocp_abe_iclk", | |
4449 | .addr = omap44xx_timer5_dma_addrs, | |
35d1a66a BC |
4450 | .user = OCP_USER_SDMA, |
4451 | }; | |
4452 | ||
4453 | /* timer5 slave ports */ | |
4454 | static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { | |
4455 | &omap44xx_l4_abe__timer5, | |
4456 | &omap44xx_l4_abe__timer5_dma, | |
4457 | }; | |
4458 | ||
4459 | static struct omap_hwmod omap44xx_timer5_hwmod = { | |
4460 | .name = "timer5", | |
4461 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4462 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4463 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
4464 | .main_clk = "timer5_fck", |
4465 | .prcm = { | |
4466 | .omap4 = { | |
d0f0631d | 4467 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 4468 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 4469 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4470 | }, |
4471 | }, | |
c345c8b0 | 4472 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4473 | .slaves = omap44xx_timer5_slaves, |
4474 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), | |
35d1a66a BC |
4475 | }; |
4476 | ||
4477 | /* timer6 */ | |
4478 | static struct omap_hwmod omap44xx_timer6_hwmod; | |
4479 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { | |
4480 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4481 | { .irq = -1 } |
35d1a66a BC |
4482 | }; |
4483 | ||
4484 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
4485 | { | |
4486 | .pa_start = 0x4013a000, | |
4487 | .pa_end = 0x4013a07f, | |
4488 | .flags = ADDR_TYPE_RT | |
4489 | }, | |
78183f3f | 4490 | { } |
35d1a66a BC |
4491 | }; |
4492 | ||
4493 | /* l4_abe -> timer6 */ | |
4494 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
4495 | .master = &omap44xx_l4_abe_hwmod, | |
4496 | .slave = &omap44xx_timer6_hwmod, | |
4497 | .clk = "ocp_abe_iclk", | |
4498 | .addr = omap44xx_timer6_addrs, | |
35d1a66a BC |
4499 | .user = OCP_USER_MPU, |
4500 | }; | |
4501 | ||
4502 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
4503 | { | |
4504 | .pa_start = 0x4903a000, | |
4505 | .pa_end = 0x4903a07f, | |
4506 | .flags = ADDR_TYPE_RT | |
4507 | }, | |
78183f3f | 4508 | { } |
35d1a66a BC |
4509 | }; |
4510 | ||
4511 | /* l4_abe -> timer6 (dma) */ | |
4512 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
4513 | .master = &omap44xx_l4_abe_hwmod, | |
4514 | .slave = &omap44xx_timer6_hwmod, | |
4515 | .clk = "ocp_abe_iclk", | |
4516 | .addr = omap44xx_timer6_dma_addrs, | |
35d1a66a BC |
4517 | .user = OCP_USER_SDMA, |
4518 | }; | |
4519 | ||
4520 | /* timer6 slave ports */ | |
4521 | static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { | |
4522 | &omap44xx_l4_abe__timer6, | |
4523 | &omap44xx_l4_abe__timer6_dma, | |
4524 | }; | |
4525 | ||
4526 | static struct omap_hwmod omap44xx_timer6_hwmod = { | |
4527 | .name = "timer6", | |
4528 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4529 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4530 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 4531 | |
35d1a66a BC |
4532 | .main_clk = "timer6_fck", |
4533 | .prcm = { | |
4534 | .omap4 = { | |
d0f0631d | 4535 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 4536 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 4537 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4538 | }, |
4539 | }, | |
c345c8b0 | 4540 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4541 | .slaves = omap44xx_timer6_slaves, |
4542 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), | |
35d1a66a BC |
4543 | }; |
4544 | ||
4545 | /* timer7 */ | |
4546 | static struct omap_hwmod omap44xx_timer7_hwmod; | |
4547 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { | |
4548 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4549 | { .irq = -1 } |
35d1a66a BC |
4550 | }; |
4551 | ||
4552 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
4553 | { | |
4554 | .pa_start = 0x4013c000, | |
4555 | .pa_end = 0x4013c07f, | |
4556 | .flags = ADDR_TYPE_RT | |
4557 | }, | |
78183f3f | 4558 | { } |
35d1a66a BC |
4559 | }; |
4560 | ||
4561 | /* l4_abe -> timer7 */ | |
4562 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
4563 | .master = &omap44xx_l4_abe_hwmod, | |
4564 | .slave = &omap44xx_timer7_hwmod, | |
4565 | .clk = "ocp_abe_iclk", | |
4566 | .addr = omap44xx_timer7_addrs, | |
35d1a66a BC |
4567 | .user = OCP_USER_MPU, |
4568 | }; | |
4569 | ||
4570 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
4571 | { | |
4572 | .pa_start = 0x4903c000, | |
4573 | .pa_end = 0x4903c07f, | |
4574 | .flags = ADDR_TYPE_RT | |
4575 | }, | |
78183f3f | 4576 | { } |
35d1a66a BC |
4577 | }; |
4578 | ||
4579 | /* l4_abe -> timer7 (dma) */ | |
4580 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
4581 | .master = &omap44xx_l4_abe_hwmod, | |
4582 | .slave = &omap44xx_timer7_hwmod, | |
4583 | .clk = "ocp_abe_iclk", | |
4584 | .addr = omap44xx_timer7_dma_addrs, | |
35d1a66a BC |
4585 | .user = OCP_USER_SDMA, |
4586 | }; | |
4587 | ||
4588 | /* timer7 slave ports */ | |
4589 | static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { | |
4590 | &omap44xx_l4_abe__timer7, | |
4591 | &omap44xx_l4_abe__timer7_dma, | |
4592 | }; | |
4593 | ||
4594 | static struct omap_hwmod omap44xx_timer7_hwmod = { | |
4595 | .name = "timer7", | |
4596 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4597 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4598 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
4599 | .main_clk = "timer7_fck", |
4600 | .prcm = { | |
4601 | .omap4 = { | |
d0f0631d | 4602 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 4603 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 4604 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4605 | }, |
4606 | }, | |
c345c8b0 | 4607 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4608 | .slaves = omap44xx_timer7_slaves, |
4609 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), | |
35d1a66a BC |
4610 | }; |
4611 | ||
4612 | /* timer8 */ | |
4613 | static struct omap_hwmod omap44xx_timer8_hwmod; | |
4614 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { | |
4615 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4616 | { .irq = -1 } |
35d1a66a BC |
4617 | }; |
4618 | ||
4619 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
4620 | { | |
4621 | .pa_start = 0x4013e000, | |
4622 | .pa_end = 0x4013e07f, | |
4623 | .flags = ADDR_TYPE_RT | |
4624 | }, | |
78183f3f | 4625 | { } |
35d1a66a BC |
4626 | }; |
4627 | ||
4628 | /* l4_abe -> timer8 */ | |
4629 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
4630 | .master = &omap44xx_l4_abe_hwmod, | |
4631 | .slave = &omap44xx_timer8_hwmod, | |
4632 | .clk = "ocp_abe_iclk", | |
4633 | .addr = omap44xx_timer8_addrs, | |
35d1a66a BC |
4634 | .user = OCP_USER_MPU, |
4635 | }; | |
4636 | ||
4637 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
4638 | { | |
4639 | .pa_start = 0x4903e000, | |
4640 | .pa_end = 0x4903e07f, | |
4641 | .flags = ADDR_TYPE_RT | |
4642 | }, | |
78183f3f | 4643 | { } |
35d1a66a BC |
4644 | }; |
4645 | ||
4646 | /* l4_abe -> timer8 (dma) */ | |
4647 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
4648 | .master = &omap44xx_l4_abe_hwmod, | |
4649 | .slave = &omap44xx_timer8_hwmod, | |
4650 | .clk = "ocp_abe_iclk", | |
4651 | .addr = omap44xx_timer8_dma_addrs, | |
35d1a66a BC |
4652 | .user = OCP_USER_SDMA, |
4653 | }; | |
4654 | ||
4655 | /* timer8 slave ports */ | |
4656 | static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { | |
4657 | &omap44xx_l4_abe__timer8, | |
4658 | &omap44xx_l4_abe__timer8_dma, | |
4659 | }; | |
4660 | ||
4661 | static struct omap_hwmod omap44xx_timer8_hwmod = { | |
4662 | .name = "timer8", | |
4663 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4664 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4665 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
4666 | .main_clk = "timer8_fck", |
4667 | .prcm = { | |
4668 | .omap4 = { | |
d0f0631d | 4669 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 4670 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 4671 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4672 | }, |
4673 | }, | |
c345c8b0 | 4674 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4675 | .slaves = omap44xx_timer8_slaves, |
4676 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), | |
35d1a66a BC |
4677 | }; |
4678 | ||
4679 | /* timer9 */ | |
4680 | static struct omap_hwmod omap44xx_timer9_hwmod; | |
4681 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { | |
4682 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4683 | { .irq = -1 } |
35d1a66a BC |
4684 | }; |
4685 | ||
4686 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
4687 | { | |
4688 | .pa_start = 0x4803e000, | |
4689 | .pa_end = 0x4803e07f, | |
4690 | .flags = ADDR_TYPE_RT | |
4691 | }, | |
78183f3f | 4692 | { } |
35d1a66a BC |
4693 | }; |
4694 | ||
4695 | /* l4_per -> timer9 */ | |
4696 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
4697 | .master = &omap44xx_l4_per_hwmod, | |
4698 | .slave = &omap44xx_timer9_hwmod, | |
4699 | .clk = "l4_div_ck", | |
4700 | .addr = omap44xx_timer9_addrs, | |
35d1a66a BC |
4701 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4702 | }; | |
4703 | ||
4704 | /* timer9 slave ports */ | |
4705 | static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { | |
4706 | &omap44xx_l4_per__timer9, | |
4707 | }; | |
4708 | ||
4709 | static struct omap_hwmod omap44xx_timer9_hwmod = { | |
4710 | .name = "timer9", | |
4711 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4712 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4713 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
4714 | .main_clk = "timer9_fck", |
4715 | .prcm = { | |
4716 | .omap4 = { | |
d0f0631d | 4717 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 4718 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 4719 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4720 | }, |
4721 | }, | |
c345c8b0 | 4722 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4723 | .slaves = omap44xx_timer9_slaves, |
4724 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), | |
35d1a66a BC |
4725 | }; |
4726 | ||
4727 | /* timer10 */ | |
4728 | static struct omap_hwmod omap44xx_timer10_hwmod; | |
4729 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { | |
4730 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4731 | { .irq = -1 } |
35d1a66a BC |
4732 | }; |
4733 | ||
4734 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
4735 | { | |
4736 | .pa_start = 0x48086000, | |
4737 | .pa_end = 0x4808607f, | |
4738 | .flags = ADDR_TYPE_RT | |
4739 | }, | |
78183f3f | 4740 | { } |
35d1a66a BC |
4741 | }; |
4742 | ||
4743 | /* l4_per -> timer10 */ | |
4744 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
4745 | .master = &omap44xx_l4_per_hwmod, | |
4746 | .slave = &omap44xx_timer10_hwmod, | |
4747 | .clk = "l4_div_ck", | |
4748 | .addr = omap44xx_timer10_addrs, | |
35d1a66a BC |
4749 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4750 | }; | |
4751 | ||
4752 | /* timer10 slave ports */ | |
4753 | static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { | |
4754 | &omap44xx_l4_per__timer10, | |
4755 | }; | |
4756 | ||
4757 | static struct omap_hwmod omap44xx_timer10_hwmod = { | |
4758 | .name = "timer10", | |
4759 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4760 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4761 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
4762 | .main_clk = "timer10_fck", |
4763 | .prcm = { | |
4764 | .omap4 = { | |
d0f0631d | 4765 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 4766 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 4767 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4768 | }, |
4769 | }, | |
c345c8b0 | 4770 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4771 | .slaves = omap44xx_timer10_slaves, |
4772 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), | |
35d1a66a BC |
4773 | }; |
4774 | ||
4775 | /* timer11 */ | |
4776 | static struct omap_hwmod omap44xx_timer11_hwmod; | |
4777 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { | |
4778 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4779 | { .irq = -1 } |
35d1a66a BC |
4780 | }; |
4781 | ||
4782 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
4783 | { | |
4784 | .pa_start = 0x48088000, | |
4785 | .pa_end = 0x4808807f, | |
4786 | .flags = ADDR_TYPE_RT | |
4787 | }, | |
78183f3f | 4788 | { } |
35d1a66a BC |
4789 | }; |
4790 | ||
4791 | /* l4_per -> timer11 */ | |
4792 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
4793 | .master = &omap44xx_l4_per_hwmod, | |
4794 | .slave = &omap44xx_timer11_hwmod, | |
4795 | .clk = "l4_div_ck", | |
4796 | .addr = omap44xx_timer11_addrs, | |
35d1a66a BC |
4797 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4798 | }; | |
4799 | ||
4800 | /* timer11 slave ports */ | |
4801 | static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { | |
4802 | &omap44xx_l4_per__timer11, | |
4803 | }; | |
4804 | ||
4805 | static struct omap_hwmod omap44xx_timer11_hwmod = { | |
4806 | .name = "timer11", | |
4807 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4808 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4809 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
4810 | .main_clk = "timer11_fck", |
4811 | .prcm = { | |
4812 | .omap4 = { | |
d0f0631d | 4813 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 4814 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 4815 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4816 | }, |
4817 | }, | |
c345c8b0 | 4818 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4819 | .slaves = omap44xx_timer11_slaves, |
4820 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), | |
35d1a66a BC |
4821 | }; |
4822 | ||
9780a9cf | 4823 | /* |
3b54baad BC |
4824 | * 'uart' class |
4825 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
4826 | */ |
4827 | ||
3b54baad BC |
4828 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
4829 | .rev_offs = 0x0050, | |
4830 | .sysc_offs = 0x0054, | |
4831 | .syss_offs = 0x0058, | |
4832 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
4833 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
4834 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
4835 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
4836 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
4837 | .sysc_fields = &omap_hwmod_sysc_type1, |
4838 | }; | |
4839 | ||
3b54baad | 4840 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
4841 | .name = "uart", |
4842 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
4843 | }; |
4844 | ||
3b54baad BC |
4845 | /* uart1 */ |
4846 | static struct omap_hwmod omap44xx_uart1_hwmod; | |
4847 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | |
4848 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4849 | { .irq = -1 } |
9780a9cf BC |
4850 | }; |
4851 | ||
3b54baad BC |
4852 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
4853 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
4854 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4855 | { .dma_req = -1 } |
9780a9cf BC |
4856 | }; |
4857 | ||
3b54baad | 4858 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
9780a9cf | 4859 | { |
3b54baad BC |
4860 | .pa_start = 0x4806a000, |
4861 | .pa_end = 0x4806a0ff, | |
9780a9cf BC |
4862 | .flags = ADDR_TYPE_RT |
4863 | }, | |
78183f3f | 4864 | { } |
9780a9cf BC |
4865 | }; |
4866 | ||
3b54baad BC |
4867 | /* l4_per -> uart1 */ |
4868 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
4869 | .master = &omap44xx_l4_per_hwmod, | |
4870 | .slave = &omap44xx_uart1_hwmod, | |
4871 | .clk = "l4_div_ck", | |
4872 | .addr = omap44xx_uart1_addrs, | |
9780a9cf BC |
4873 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4874 | }; | |
4875 | ||
3b54baad BC |
4876 | /* uart1 slave ports */ |
4877 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { | |
4878 | &omap44xx_l4_per__uart1, | |
9780a9cf BC |
4879 | }; |
4880 | ||
3b54baad BC |
4881 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
4882 | .name = "uart1", | |
4883 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 4884 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 4885 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 4886 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 4887 | .main_clk = "uart1_fck", |
9780a9cf BC |
4888 | .prcm = { |
4889 | .omap4 = { | |
d0f0631d | 4890 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 4891 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 4892 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
4893 | }, |
4894 | }, | |
3b54baad BC |
4895 | .slaves = omap44xx_uart1_slaves, |
4896 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), | |
9780a9cf BC |
4897 | }; |
4898 | ||
3b54baad BC |
4899 | /* uart2 */ |
4900 | static struct omap_hwmod omap44xx_uart2_hwmod; | |
4901 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | |
4902 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4903 | { .irq = -1 } |
9780a9cf BC |
4904 | }; |
4905 | ||
3b54baad BC |
4906 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
4907 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
4908 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4909 | { .dma_req = -1 } |
3b54baad BC |
4910 | }; |
4911 | ||
4912 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | |
9780a9cf | 4913 | { |
3b54baad BC |
4914 | .pa_start = 0x4806c000, |
4915 | .pa_end = 0x4806c0ff, | |
9780a9cf BC |
4916 | .flags = ADDR_TYPE_RT |
4917 | }, | |
78183f3f | 4918 | { } |
9780a9cf BC |
4919 | }; |
4920 | ||
3b54baad BC |
4921 | /* l4_per -> uart2 */ |
4922 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
9780a9cf | 4923 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
4924 | .slave = &omap44xx_uart2_hwmod, |
4925 | .clk = "l4_div_ck", | |
4926 | .addr = omap44xx_uart2_addrs, | |
9780a9cf BC |
4927 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4928 | }; | |
4929 | ||
3b54baad BC |
4930 | /* uart2 slave ports */ |
4931 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { | |
4932 | &omap44xx_l4_per__uart2, | |
9780a9cf BC |
4933 | }; |
4934 | ||
3b54baad BC |
4935 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
4936 | .name = "uart2", | |
4937 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 4938 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 4939 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 4940 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 4941 | .main_clk = "uart2_fck", |
9780a9cf BC |
4942 | .prcm = { |
4943 | .omap4 = { | |
d0f0631d | 4944 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 4945 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 4946 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
4947 | }, |
4948 | }, | |
3b54baad BC |
4949 | .slaves = omap44xx_uart2_slaves, |
4950 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), | |
9780a9cf BC |
4951 | }; |
4952 | ||
3b54baad BC |
4953 | /* uart3 */ |
4954 | static struct omap_hwmod omap44xx_uart3_hwmod; | |
4955 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | |
4956 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4957 | { .irq = -1 } |
9780a9cf BC |
4958 | }; |
4959 | ||
3b54baad BC |
4960 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
4961 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
4962 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4963 | { .dma_req = -1 } |
3b54baad BC |
4964 | }; |
4965 | ||
4966 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | |
9780a9cf | 4967 | { |
3b54baad BC |
4968 | .pa_start = 0x48020000, |
4969 | .pa_end = 0x480200ff, | |
9780a9cf BC |
4970 | .flags = ADDR_TYPE_RT |
4971 | }, | |
78183f3f | 4972 | { } |
9780a9cf BC |
4973 | }; |
4974 | ||
3b54baad BC |
4975 | /* l4_per -> uart3 */ |
4976 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
9780a9cf | 4977 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
4978 | .slave = &omap44xx_uart3_hwmod, |
4979 | .clk = "l4_div_ck", | |
4980 | .addr = omap44xx_uart3_addrs, | |
9780a9cf BC |
4981 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4982 | }; | |
4983 | ||
3b54baad BC |
4984 | /* uart3 slave ports */ |
4985 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { | |
4986 | &omap44xx_l4_per__uart3, | |
4987 | }; | |
4988 | ||
4989 | static struct omap_hwmod omap44xx_uart3_hwmod = { | |
4990 | .name = "uart3", | |
4991 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 4992 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 4993 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 4994 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 4995 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 4996 | .main_clk = "uart3_fck", |
9780a9cf BC |
4997 | .prcm = { |
4998 | .omap4 = { | |
d0f0631d | 4999 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 5000 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 5001 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5002 | }, |
5003 | }, | |
3b54baad BC |
5004 | .slaves = omap44xx_uart3_slaves, |
5005 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), | |
9780a9cf BC |
5006 | }; |
5007 | ||
3b54baad BC |
5008 | /* uart4 */ |
5009 | static struct omap_hwmod omap44xx_uart4_hwmod; | |
5010 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | |
5011 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5012 | { .irq = -1 } |
9780a9cf BC |
5013 | }; |
5014 | ||
3b54baad BC |
5015 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
5016 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
5017 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 5018 | { .dma_req = -1 } |
3b54baad BC |
5019 | }; |
5020 | ||
5021 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | |
9780a9cf | 5022 | { |
3b54baad BC |
5023 | .pa_start = 0x4806e000, |
5024 | .pa_end = 0x4806e0ff, | |
9780a9cf BC |
5025 | .flags = ADDR_TYPE_RT |
5026 | }, | |
78183f3f | 5027 | { } |
9780a9cf BC |
5028 | }; |
5029 | ||
3b54baad BC |
5030 | /* l4_per -> uart4 */ |
5031 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
9780a9cf | 5032 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
5033 | .slave = &omap44xx_uart4_hwmod, |
5034 | .clk = "l4_div_ck", | |
5035 | .addr = omap44xx_uart4_addrs, | |
9780a9cf BC |
5036 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5037 | }; | |
5038 | ||
3b54baad BC |
5039 | /* uart4 slave ports */ |
5040 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { | |
5041 | &omap44xx_l4_per__uart4, | |
9780a9cf BC |
5042 | }; |
5043 | ||
3b54baad BC |
5044 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
5045 | .name = "uart4", | |
5046 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 5047 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 5048 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 5049 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 5050 | .main_clk = "uart4_fck", |
9780a9cf BC |
5051 | .prcm = { |
5052 | .omap4 = { | |
d0f0631d | 5053 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 5054 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 5055 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5056 | }, |
5057 | }, | |
3b54baad BC |
5058 | .slaves = omap44xx_uart4_slaves, |
5059 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), | |
9780a9cf BC |
5060 | }; |
5061 | ||
5844c4ea BC |
5062 | /* |
5063 | * 'usb_otg_hs' class | |
5064 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
5065 | */ | |
5066 | ||
5067 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
5068 | .rev_offs = 0x0400, | |
5069 | .sysc_offs = 0x0404, | |
5070 | .syss_offs = 0x0408, | |
5071 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
5072 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
5073 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
5074 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
5075 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
5076 | MSTANDBY_SMART), | |
5077 | .sysc_fields = &omap_hwmod_sysc_type1, | |
5078 | }; | |
5079 | ||
5080 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
00fe610b BC |
5081 | .name = "usb_otg_hs", |
5082 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
5844c4ea BC |
5083 | }; |
5084 | ||
5085 | /* usb_otg_hs */ | |
5086 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
5087 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
5088 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5089 | { .irq = -1 } |
5844c4ea BC |
5090 | }; |
5091 | ||
5092 | /* usb_otg_hs master ports */ | |
5093 | static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { | |
5094 | &omap44xx_usb_otg_hs__l3_main_2, | |
5095 | }; | |
5096 | ||
5097 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
5098 | { | |
5099 | .pa_start = 0x4a0ab000, | |
5100 | .pa_end = 0x4a0ab003, | |
5101 | .flags = ADDR_TYPE_RT | |
5102 | }, | |
78183f3f | 5103 | { } |
5844c4ea BC |
5104 | }; |
5105 | ||
5106 | /* l4_cfg -> usb_otg_hs */ | |
5107 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
5108 | .master = &omap44xx_l4_cfg_hwmod, | |
5109 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
5110 | .clk = "l4_div_ck", | |
5111 | .addr = omap44xx_usb_otg_hs_addrs, | |
5844c4ea BC |
5112 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5113 | }; | |
5114 | ||
5115 | /* usb_otg_hs slave ports */ | |
5116 | static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { | |
5117 | &omap44xx_l4_cfg__usb_otg_hs, | |
5118 | }; | |
5119 | ||
5120 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
5121 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
5122 | }; | |
5123 | ||
5124 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
5125 | .name = "usb_otg_hs", | |
5126 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
a5322c6f | 5127 | .clkdm_name = "l3_init_clkdm", |
5844c4ea BC |
5128 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
5129 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
5844c4ea BC |
5130 | .main_clk = "usb_otg_hs_ick", |
5131 | .prcm = { | |
5132 | .omap4 = { | |
d0f0631d | 5133 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, |
27bb00b5 | 5134 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, |
03fdefe5 | 5135 | .modulemode = MODULEMODE_HWCTRL, |
5844c4ea BC |
5136 | }, |
5137 | }, | |
5138 | .opt_clks = usb_otg_hs_opt_clks, | |
00fe610b | 5139 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), |
5844c4ea BC |
5140 | .slaves = omap44xx_usb_otg_hs_slaves, |
5141 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), | |
5142 | .masters = omap44xx_usb_otg_hs_masters, | |
5143 | .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), | |
5844c4ea BC |
5144 | }; |
5145 | ||
3b54baad BC |
5146 | /* |
5147 | * 'wd_timer' class | |
5148 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
5149 | * overflow condition | |
5150 | */ | |
5151 | ||
5152 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
5153 | .rev_offs = 0x0000, | |
5154 | .sysc_offs = 0x0010, | |
5155 | .syss_offs = 0x0014, | |
5156 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 5157 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
5158 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
5159 | SIDLE_SMART_WKUP), | |
3b54baad | 5160 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
5161 | }; |
5162 | ||
3b54baad BC |
5163 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
5164 | .name = "wd_timer", | |
5165 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 5166 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
5167 | }; |
5168 | ||
5169 | /* wd_timer2 */ | |
5170 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | |
5171 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | |
5172 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5173 | { .irq = -1 } |
3b54baad BC |
5174 | }; |
5175 | ||
5176 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | |
9780a9cf | 5177 | { |
3b54baad BC |
5178 | .pa_start = 0x4a314000, |
5179 | .pa_end = 0x4a31407f, | |
9780a9cf BC |
5180 | .flags = ADDR_TYPE_RT |
5181 | }, | |
78183f3f | 5182 | { } |
9780a9cf BC |
5183 | }; |
5184 | ||
3b54baad BC |
5185 | /* l4_wkup -> wd_timer2 */ |
5186 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
5187 | .master = &omap44xx_l4_wkup_hwmod, | |
5188 | .slave = &omap44xx_wd_timer2_hwmod, | |
5189 | .clk = "l4_wkup_clk_mux_ck", | |
5190 | .addr = omap44xx_wd_timer2_addrs, | |
9780a9cf BC |
5191 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5192 | }; | |
5193 | ||
3b54baad BC |
5194 | /* wd_timer2 slave ports */ |
5195 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | |
5196 | &omap44xx_l4_wkup__wd_timer2, | |
9780a9cf BC |
5197 | }; |
5198 | ||
3b54baad BC |
5199 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
5200 | .name = "wd_timer2", | |
5201 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 5202 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 5203 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 5204 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
5205 | .prcm = { |
5206 | .omap4 = { | |
d0f0631d | 5207 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 5208 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 5209 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5210 | }, |
5211 | }, | |
3b54baad BC |
5212 | .slaves = omap44xx_wd_timer2_slaves, |
5213 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | |
9780a9cf BC |
5214 | }; |
5215 | ||
3b54baad BC |
5216 | /* wd_timer3 */ |
5217 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | |
5218 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | |
5219 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5220 | { .irq = -1 } |
9780a9cf BC |
5221 | }; |
5222 | ||
3b54baad | 5223 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
9780a9cf | 5224 | { |
3b54baad BC |
5225 | .pa_start = 0x40130000, |
5226 | .pa_end = 0x4013007f, | |
9780a9cf BC |
5227 | .flags = ADDR_TYPE_RT |
5228 | }, | |
78183f3f | 5229 | { } |
9780a9cf BC |
5230 | }; |
5231 | ||
3b54baad BC |
5232 | /* l4_abe -> wd_timer3 */ |
5233 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
5234 | .master = &omap44xx_l4_abe_hwmod, | |
5235 | .slave = &omap44xx_wd_timer3_hwmod, | |
5236 | .clk = "ocp_abe_iclk", | |
5237 | .addr = omap44xx_wd_timer3_addrs, | |
3b54baad | 5238 | .user = OCP_USER_MPU, |
9780a9cf BC |
5239 | }; |
5240 | ||
3b54baad BC |
5241 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
5242 | { | |
5243 | .pa_start = 0x49030000, | |
5244 | .pa_end = 0x4903007f, | |
5245 | .flags = ADDR_TYPE_RT | |
5246 | }, | |
78183f3f | 5247 | { } |
9780a9cf BC |
5248 | }; |
5249 | ||
3b54baad BC |
5250 | /* l4_abe -> wd_timer3 (dma) */ |
5251 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
5252 | .master = &omap44xx_l4_abe_hwmod, | |
5253 | .slave = &omap44xx_wd_timer3_hwmod, | |
5254 | .clk = "ocp_abe_iclk", | |
5255 | .addr = omap44xx_wd_timer3_dma_addrs, | |
3b54baad | 5256 | .user = OCP_USER_SDMA, |
9780a9cf BC |
5257 | }; |
5258 | ||
3b54baad BC |
5259 | /* wd_timer3 slave ports */ |
5260 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | |
5261 | &omap44xx_l4_abe__wd_timer3, | |
5262 | &omap44xx_l4_abe__wd_timer3_dma, | |
5263 | }; | |
5264 | ||
5265 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |
5266 | .name = "wd_timer3", | |
5267 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 5268 | .clkdm_name = "abe_clkdm", |
3b54baad | 5269 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 5270 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
5271 | .prcm = { |
5272 | .omap4 = { | |
d0f0631d | 5273 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 5274 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 5275 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5276 | }, |
5277 | }, | |
3b54baad BC |
5278 | .slaves = omap44xx_wd_timer3_slaves, |
5279 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | |
9780a9cf | 5280 | }; |
531ce0d5 | 5281 | |
af88fa9a BC |
5282 | /* |
5283 | * 'usb_host_hs' class | |
5284 | * high-speed multi-port usb host controller | |
5285 | */ | |
5286 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
5287 | .master = &omap44xx_usb_host_hs_hwmod, | |
5288 | .slave = &omap44xx_l3_main_2_hwmod, | |
5289 | .clk = "l3_div_ck", | |
5290 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5291 | }; | |
5292 | ||
5293 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { | |
5294 | .rev_offs = 0x0000, | |
5295 | .sysc_offs = 0x0010, | |
5296 | .syss_offs = 0x0014, | |
5297 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
5298 | SYSC_HAS_SOFTRESET), | |
5299 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
5300 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
5301 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
5302 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5303 | }; | |
5304 | ||
5305 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { | |
5306 | .name = "usb_host_hs", | |
5307 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5308 | }; | |
5309 | ||
5310 | static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { | |
5311 | &omap44xx_usb_host_hs__l3_main_2, | |
5312 | }; | |
5313 | ||
5314 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { | |
5315 | { | |
5316 | .name = "uhh", | |
5317 | .pa_start = 0x4a064000, | |
5318 | .pa_end = 0x4a0647ff, | |
5319 | .flags = ADDR_TYPE_RT | |
5320 | }, | |
5321 | { | |
5322 | .name = "ohci", | |
5323 | .pa_start = 0x4a064800, | |
5324 | .pa_end = 0x4a064bff, | |
5325 | }, | |
5326 | { | |
5327 | .name = "ehci", | |
5328 | .pa_start = 0x4a064c00, | |
5329 | .pa_end = 0x4a064fff, | |
5330 | }, | |
5331 | {} | |
5332 | }; | |
5333 | ||
5334 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
5335 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
5336 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
5337 | { .irq = -1 } | |
5338 | }; | |
5339 | ||
5340 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
5341 | .master = &omap44xx_l4_cfg_hwmod, | |
5342 | .slave = &omap44xx_usb_host_hs_hwmod, | |
5343 | .clk = "l4_div_ck", | |
5344 | .addr = omap44xx_usb_host_hs_addrs, | |
5345 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5346 | }; | |
5347 | ||
5348 | static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { | |
5349 | &omap44xx_l4_cfg__usb_host_hs, | |
5350 | }; | |
5351 | ||
5352 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { | |
5353 | .name = "usb_host_hs", | |
5354 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
5355 | .clkdm_name = "l3_init_clkdm", | |
5356 | .main_clk = "usb_host_hs_fck", | |
5357 | .prcm = { | |
5358 | .omap4 = { | |
5359 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, | |
5360 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
5361 | .modulemode = MODULEMODE_SWCTRL, | |
5362 | }, | |
5363 | }, | |
5364 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
5365 | .slaves = omap44xx_usb_host_hs_slaves, | |
5366 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), | |
5367 | .masters = omap44xx_usb_host_hs_masters, | |
5368 | .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), | |
5369 | ||
5370 | /* | |
5371 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
5372 | * id: i660 | |
5373 | * | |
5374 | * Description: | |
5375 | * In the following configuration : | |
5376 | * - USBHOST module is set to smart-idle mode | |
5377 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
5378 | * happens when the system is going to a low power mode : all ports | |
5379 | * have been suspended, the master part of the USBHOST module has | |
5380 | * entered the standby state, and SW has cut the functional clocks) | |
5381 | * - an USBHOST interrupt occurs before the module is able to answer | |
5382 | * idle_ack, typically a remote wakeup IRQ. | |
5383 | * Then the USB HOST module will enter a deadlock situation where it | |
5384 | * is no more accessible nor functional. | |
5385 | * | |
5386 | * Workaround: | |
5387 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
5388 | */ | |
5389 | ||
5390 | /* | |
5391 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
5392 | * Id: i571 | |
5393 | * | |
5394 | * Description: | |
5395 | * When the USBHOST module is set to smart-standby mode, and when it is | |
5396 | * ready to enter the standby state (i.e. all ports are suspended and | |
5397 | * all attached devices are in suspend mode), then it can wrongly assert | |
5398 | * the Mstandby signal too early while there are still some residual OCP | |
5399 | * transactions ongoing. If this condition occurs, the internal state | |
5400 | * machine may go to an undefined state and the USB link may be stuck | |
5401 | * upon the next resume. | |
5402 | * | |
5403 | * Workaround: | |
5404 | * Don't use smart standby; use only force standby, | |
5405 | * hence HWMOD_SWSUP_MSTANDBY | |
5406 | */ | |
5407 | ||
5408 | /* | |
5409 | * During system boot; If the hwmod framework resets the module | |
5410 | * the module will have smart idle settings; which can lead to deadlock | |
5411 | * (above Errata Id:i660); so, dont reset the module during boot; | |
5412 | * Use HWMOD_INIT_NO_RESET. | |
5413 | */ | |
5414 | ||
5415 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
5416 | HWMOD_INIT_NO_RESET, | |
5417 | }; | |
5418 | ||
5419 | /* | |
5420 | * 'usb_tll_hs' class | |
5421 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
5422 | */ | |
5423 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
5424 | .rev_offs = 0x0000, | |
5425 | .sysc_offs = 0x0010, | |
5426 | .syss_offs = 0x0014, | |
5427 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
5428 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
5429 | SYSC_HAS_AUTOIDLE), | |
5430 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
5431 | .sysc_fields = &omap_hwmod_sysc_type1, | |
5432 | }; | |
5433 | ||
5434 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
5435 | .name = "usb_tll_hs", | |
5436 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
5437 | }; | |
5438 | ||
5439 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
5440 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
5441 | { .irq = -1 } | |
5442 | }; | |
5443 | ||
5444 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
5445 | { | |
5446 | .name = "tll", | |
5447 | .pa_start = 0x4a062000, | |
5448 | .pa_end = 0x4a063fff, | |
5449 | .flags = ADDR_TYPE_RT | |
5450 | }, | |
5451 | {} | |
5452 | }; | |
5453 | ||
5454 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { | |
5455 | .master = &omap44xx_l4_cfg_hwmod, | |
5456 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
5457 | .clk = "l4_div_ck", | |
5458 | .addr = omap44xx_usb_tll_hs_addrs, | |
5459 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5460 | }; | |
5461 | ||
5462 | static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { | |
5463 | &omap44xx_l4_cfg__usb_tll_hs, | |
5464 | }; | |
5465 | ||
5466 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
5467 | .name = "usb_tll_hs", | |
5468 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
5469 | .clkdm_name = "l3_init_clkdm", | |
5470 | .main_clk = "usb_tll_hs_ick", | |
5471 | .prcm = { | |
5472 | .omap4 = { | |
5473 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
5474 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
5475 | .modulemode = MODULEMODE_HWCTRL, | |
5476 | }, | |
5477 | }, | |
5478 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
5479 | .slaves = omap44xx_usb_tll_hs_slaves, | |
5480 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), | |
5481 | }; | |
5482 | ||
55d2cb08 | 5483 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
fe13471c | 5484 | |
55d2cb08 BC |
5485 | /* dmm class */ |
5486 | &omap44xx_dmm_hwmod, | |
3b54baad | 5487 | |
55d2cb08 BC |
5488 | /* emif_fw class */ |
5489 | &omap44xx_emif_fw_hwmod, | |
3b54baad | 5490 | |
55d2cb08 BC |
5491 | /* l3 class */ |
5492 | &omap44xx_l3_instr_hwmod, | |
5493 | &omap44xx_l3_main_1_hwmod, | |
5494 | &omap44xx_l3_main_2_hwmod, | |
5495 | &omap44xx_l3_main_3_hwmod, | |
3b54baad | 5496 | |
55d2cb08 BC |
5497 | /* l4 class */ |
5498 | &omap44xx_l4_abe_hwmod, | |
5499 | &omap44xx_l4_cfg_hwmod, | |
5500 | &omap44xx_l4_per_hwmod, | |
5501 | &omap44xx_l4_wkup_hwmod, | |
531ce0d5 | 5502 | |
55d2cb08 BC |
5503 | /* mpu_bus class */ |
5504 | &omap44xx_mpu_private_hwmod, | |
5505 | ||
407a6888 BC |
5506 | /* aess class */ |
5507 | /* &omap44xx_aess_hwmod, */ | |
5508 | ||
5509 | /* bandgap class */ | |
5510 | &omap44xx_bandgap_hwmod, | |
5511 | ||
5512 | /* counter class */ | |
5513 | /* &omap44xx_counter_32k_hwmod, */ | |
5514 | ||
d7cf5f33 BC |
5515 | /* dma class */ |
5516 | &omap44xx_dma_system_hwmod, | |
5517 | ||
8ca476da BC |
5518 | /* dmic class */ |
5519 | &omap44xx_dmic_hwmod, | |
5520 | ||
8f25bdc5 BC |
5521 | /* dsp class */ |
5522 | &omap44xx_dsp_hwmod, | |
5523 | &omap44xx_dsp_c0_hwmod, | |
5524 | ||
d63bd74f BC |
5525 | /* dss class */ |
5526 | &omap44xx_dss_hwmod, | |
5527 | &omap44xx_dss_dispc_hwmod, | |
5528 | &omap44xx_dss_dsi1_hwmod, | |
5529 | &omap44xx_dss_dsi2_hwmod, | |
5530 | &omap44xx_dss_hdmi_hwmod, | |
5531 | &omap44xx_dss_rfbi_hwmod, | |
5532 | &omap44xx_dss_venc_hwmod, | |
5533 | ||
9780a9cf BC |
5534 | /* gpio class */ |
5535 | &omap44xx_gpio1_hwmod, | |
5536 | &omap44xx_gpio2_hwmod, | |
5537 | &omap44xx_gpio3_hwmod, | |
5538 | &omap44xx_gpio4_hwmod, | |
5539 | &omap44xx_gpio5_hwmod, | |
5540 | &omap44xx_gpio6_hwmod, | |
5541 | ||
407a6888 BC |
5542 | /* hsi class */ |
5543 | /* &omap44xx_hsi_hwmod, */ | |
5544 | ||
3b54baad BC |
5545 | /* i2c class */ |
5546 | &omap44xx_i2c1_hwmod, | |
5547 | &omap44xx_i2c2_hwmod, | |
5548 | &omap44xx_i2c3_hwmod, | |
5549 | &omap44xx_i2c4_hwmod, | |
5550 | ||
407a6888 BC |
5551 | /* ipu class */ |
5552 | &omap44xx_ipu_hwmod, | |
5553 | &omap44xx_ipu_c0_hwmod, | |
5554 | &omap44xx_ipu_c1_hwmod, | |
5555 | ||
5556 | /* iss class */ | |
5557 | /* &omap44xx_iss_hwmod, */ | |
5558 | ||
8f25bdc5 BC |
5559 | /* iva class */ |
5560 | &omap44xx_iva_hwmod, | |
5561 | &omap44xx_iva_seq0_hwmod, | |
5562 | &omap44xx_iva_seq1_hwmod, | |
5563 | ||
407a6888 | 5564 | /* kbd class */ |
4998b245 | 5565 | &omap44xx_kbd_hwmod, |
407a6888 | 5566 | |
ec5df927 BC |
5567 | /* mailbox class */ |
5568 | &omap44xx_mailbox_hwmod, | |
5569 | ||
4ddff493 BC |
5570 | /* mcbsp class */ |
5571 | &omap44xx_mcbsp1_hwmod, | |
5572 | &omap44xx_mcbsp2_hwmod, | |
5573 | &omap44xx_mcbsp3_hwmod, | |
5574 | &omap44xx_mcbsp4_hwmod, | |
5575 | ||
407a6888 | 5576 | /* mcpdm class */ |
d05e2ea8 | 5577 | &omap44xx_mcpdm_hwmod, |
407a6888 | 5578 | |
9bcbd7f0 BC |
5579 | /* mcspi class */ |
5580 | &omap44xx_mcspi1_hwmod, | |
5581 | &omap44xx_mcspi2_hwmod, | |
5582 | &omap44xx_mcspi3_hwmod, | |
5583 | &omap44xx_mcspi4_hwmod, | |
5584 | ||
407a6888 | 5585 | /* mmc class */ |
17203bda AG |
5586 | &omap44xx_mmc1_hwmod, |
5587 | &omap44xx_mmc2_hwmod, | |
5588 | &omap44xx_mmc3_hwmod, | |
5589 | &omap44xx_mmc4_hwmod, | |
5590 | &omap44xx_mmc5_hwmod, | |
407a6888 | 5591 | |
55d2cb08 BC |
5592 | /* mpu class */ |
5593 | &omap44xx_mpu_hwmod, | |
db12ba53 | 5594 | |
1f6a717f BC |
5595 | /* smartreflex class */ |
5596 | &omap44xx_smartreflex_core_hwmod, | |
5597 | &omap44xx_smartreflex_iva_hwmod, | |
5598 | &omap44xx_smartreflex_mpu_hwmod, | |
5599 | ||
d11c217f BC |
5600 | /* spinlock class */ |
5601 | &omap44xx_spinlock_hwmod, | |
5602 | ||
35d1a66a BC |
5603 | /* timer class */ |
5604 | &omap44xx_timer1_hwmod, | |
5605 | &omap44xx_timer2_hwmod, | |
5606 | &omap44xx_timer3_hwmod, | |
5607 | &omap44xx_timer4_hwmod, | |
5608 | &omap44xx_timer5_hwmod, | |
5609 | &omap44xx_timer6_hwmod, | |
5610 | &omap44xx_timer7_hwmod, | |
5611 | &omap44xx_timer8_hwmod, | |
5612 | &omap44xx_timer9_hwmod, | |
5613 | &omap44xx_timer10_hwmod, | |
5614 | &omap44xx_timer11_hwmod, | |
5615 | ||
db12ba53 BC |
5616 | /* uart class */ |
5617 | &omap44xx_uart1_hwmod, | |
5618 | &omap44xx_uart2_hwmod, | |
5619 | &omap44xx_uart3_hwmod, | |
5620 | &omap44xx_uart4_hwmod, | |
3b54baad | 5621 | |
af88fa9a BC |
5622 | /* usb host class */ |
5623 | &omap44xx_usb_host_hs_hwmod, | |
5624 | &omap44xx_usb_tll_hs_hwmod, | |
5625 | ||
5844c4ea BC |
5626 | /* usb_otg_hs class */ |
5627 | &omap44xx_usb_otg_hs_hwmod, | |
5628 | ||
3b54baad BC |
5629 | /* wd_timer class */ |
5630 | &omap44xx_wd_timer2_hwmod, | |
5631 | &omap44xx_wd_timer3_hwmod, | |
55d2cb08 BC |
5632 | NULL, |
5633 | }; | |
5634 | ||
5635 | int __init omap44xx_hwmod_init(void) | |
5636 | { | |
550c8092 | 5637 | return omap_hwmod_register(omap44xx_hwmods); |
55d2cb08 BC |
5638 | } |
5639 |