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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
d63bd74f | 4 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
6d3c55fd | 25 | #include <plat/i2c.h> |
9780a9cf | 26 | #include <plat/gpio.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
c345c8b0 | 31 | #include <plat/dmtimer.h> |
13662dc5 | 32 | #include <plat/common.h> |
55d2cb08 BC |
33 | |
34 | #include "omap_hwmod_common_data.h" | |
35 | ||
cea6b942 | 36 | #include "smartreflex.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
ff2516fb | 41 | #include "wd_timer.h" |
55d2cb08 BC |
42 | |
43 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
44 | #define OMAP44XX_IRQ_GIC_START 32 | |
45 | ||
46 | /* Base offset for all OMAP4 dma requests */ | |
47 | #define OMAP44XX_DMA_REQ_START 1 | |
48 | ||
49 | /* Backward references (IPs with Bus Master capability) */ | |
407a6888 | 50 | static struct omap_hwmod omap44xx_aess_hwmod; |
531ce0d5 | 51 | static struct omap_hwmod omap44xx_dma_system_hwmod; |
55d2cb08 | 52 | static struct omap_hwmod omap44xx_dmm_hwmod; |
8f25bdc5 | 53 | static struct omap_hwmod omap44xx_dsp_hwmod; |
d63bd74f | 54 | static struct omap_hwmod omap44xx_dss_hwmod; |
55d2cb08 | 55 | static struct omap_hwmod omap44xx_emif_fw_hwmod; |
407a6888 BC |
56 | static struct omap_hwmod omap44xx_hsi_hwmod; |
57 | static struct omap_hwmod omap44xx_ipu_hwmod; | |
58 | static struct omap_hwmod omap44xx_iss_hwmod; | |
8f25bdc5 | 59 | static struct omap_hwmod omap44xx_iva_hwmod; |
55d2cb08 BC |
60 | static struct omap_hwmod omap44xx_l3_instr_hwmod; |
61 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; | |
62 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; | |
63 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; | |
64 | static struct omap_hwmod omap44xx_l4_abe_hwmod; | |
65 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; | |
66 | static struct omap_hwmod omap44xx_l4_per_hwmod; | |
67 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; | |
407a6888 BC |
68 | static struct omap_hwmod omap44xx_mmc1_hwmod; |
69 | static struct omap_hwmod omap44xx_mmc2_hwmod; | |
55d2cb08 BC |
70 | static struct omap_hwmod omap44xx_mpu_hwmod; |
71 | static struct omap_hwmod omap44xx_mpu_private_hwmod; | |
5844c4ea | 72 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; |
af88fa9a BC |
73 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod; |
74 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; | |
55d2cb08 BC |
75 | |
76 | /* | |
77 | * Interconnects omap_hwmod structures | |
78 | * hwmods that compose the global OMAP interconnect | |
79 | */ | |
80 | ||
81 | /* | |
82 | * 'dmm' class | |
83 | * instance(s): dmm | |
84 | */ | |
85 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 86 | .name = "dmm", |
55d2cb08 BC |
87 | }; |
88 | ||
7e69ed97 BC |
89 | /* dmm */ |
90 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
91 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
92 | { .irq = -1 } | |
93 | }; | |
94 | ||
55d2cb08 BC |
95 | /* l3_main_1 -> dmm */ |
96 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
97 | .master = &omap44xx_l3_main_1_hwmod, | |
98 | .slave = &omap44xx_dmm_hwmod, | |
99 | .clk = "l3_div_ck", | |
659fa822 BC |
100 | .user = OCP_USER_SDMA, |
101 | }; | |
102 | ||
103 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { | |
104 | { | |
105 | .pa_start = 0x4e000000, | |
106 | .pa_end = 0x4e0007ff, | |
107 | .flags = ADDR_TYPE_RT | |
108 | }, | |
78183f3f | 109 | { } |
55d2cb08 BC |
110 | }; |
111 | ||
112 | /* mpu -> dmm */ | |
113 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
114 | .master = &omap44xx_mpu_hwmod, | |
115 | .slave = &omap44xx_dmm_hwmod, | |
116 | .clk = "l3_div_ck", | |
659fa822 | 117 | .addr = omap44xx_dmm_addrs, |
659fa822 | 118 | .user = OCP_USER_MPU, |
55d2cb08 BC |
119 | }; |
120 | ||
121 | /* dmm slave ports */ | |
122 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { | |
123 | &omap44xx_l3_main_1__dmm, | |
124 | &omap44xx_mpu__dmm, | |
125 | }; | |
126 | ||
55d2cb08 BC |
127 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
128 | .name = "dmm", | |
129 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 130 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
131 | .prcm = { |
132 | .omap4 = { | |
133 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 134 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
135 | }, |
136 | }, | |
55d2cb08 BC |
137 | .slaves = omap44xx_dmm_slaves, |
138 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | |
a5322c6f | 139 | .mpu_irqs = omap44xx_dmm_irqs, |
55d2cb08 BC |
140 | }; |
141 | ||
142 | /* | |
143 | * 'emif_fw' class | |
144 | * instance(s): emif_fw | |
145 | */ | |
146 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 147 | .name = "emif_fw", |
55d2cb08 BC |
148 | }; |
149 | ||
7e69ed97 | 150 | /* emif_fw */ |
55d2cb08 BC |
151 | /* dmm -> emif_fw */ |
152 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
153 | .master = &omap44xx_dmm_hwmod, | |
154 | .slave = &omap44xx_emif_fw_hwmod, | |
155 | .clk = "l3_div_ck", | |
156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
157 | }; | |
158 | ||
659fa822 BC |
159 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { |
160 | { | |
161 | .pa_start = 0x4a20c000, | |
162 | .pa_end = 0x4a20c0ff, | |
163 | .flags = ADDR_TYPE_RT | |
164 | }, | |
78183f3f | 165 | { } |
659fa822 BC |
166 | }; |
167 | ||
55d2cb08 BC |
168 | /* l4_cfg -> emif_fw */ |
169 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
170 | .master = &omap44xx_l4_cfg_hwmod, | |
171 | .slave = &omap44xx_emif_fw_hwmod, | |
172 | .clk = "l4_div_ck", | |
659fa822 | 173 | .addr = omap44xx_emif_fw_addrs, |
659fa822 | 174 | .user = OCP_USER_MPU, |
55d2cb08 BC |
175 | }; |
176 | ||
177 | /* emif_fw slave ports */ | |
178 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { | |
179 | &omap44xx_dmm__emif_fw, | |
180 | &omap44xx_l4_cfg__emif_fw, | |
181 | }; | |
182 | ||
183 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |
184 | .name = "emif_fw", | |
185 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 186 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
187 | .prcm = { |
188 | .omap4 = { | |
189 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 190 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
191 | }, |
192 | }, | |
55d2cb08 BC |
193 | .slaves = omap44xx_emif_fw_slaves, |
194 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), | |
55d2cb08 BC |
195 | }; |
196 | ||
197 | /* | |
198 | * 'l3' class | |
199 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
200 | */ | |
201 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 202 | .name = "l3", |
55d2cb08 BC |
203 | }; |
204 | ||
7e69ed97 | 205 | /* l3_instr */ |
8f25bdc5 BC |
206 | /* iva -> l3_instr */ |
207 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
208 | .master = &omap44xx_iva_hwmod, | |
209 | .slave = &omap44xx_l3_instr_hwmod, | |
210 | .clk = "l3_div_ck", | |
211 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
212 | }; | |
213 | ||
55d2cb08 BC |
214 | /* l3_main_3 -> l3_instr */ |
215 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
216 | .master = &omap44xx_l3_main_3_hwmod, | |
217 | .slave = &omap44xx_l3_instr_hwmod, | |
218 | .clk = "l3_div_ck", | |
219 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
220 | }; | |
221 | ||
222 | /* l3_instr slave ports */ | |
223 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { | |
8f25bdc5 | 224 | &omap44xx_iva__l3_instr, |
55d2cb08 BC |
225 | &omap44xx_l3_main_3__l3_instr, |
226 | }; | |
227 | ||
228 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |
229 | .name = "l3_instr", | |
230 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 231 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
232 | .prcm = { |
233 | .omap4 = { | |
234 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 235 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 236 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
237 | }, |
238 | }, | |
55d2cb08 BC |
239 | .slaves = omap44xx_l3_instr_slaves, |
240 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), | |
55d2cb08 BC |
241 | }; |
242 | ||
7e69ed97 | 243 | /* l3_main_1 */ |
9b4021be BC |
244 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
245 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
246 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
247 | { .irq = -1 } | |
248 | }; | |
249 | ||
8f25bdc5 BC |
250 | /* dsp -> l3_main_1 */ |
251 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
252 | .master = &omap44xx_dsp_hwmod, | |
253 | .slave = &omap44xx_l3_main_1_hwmod, | |
254 | .clk = "l3_div_ck", | |
255 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
256 | }; | |
257 | ||
d63bd74f BC |
258 | /* dss -> l3_main_1 */ |
259 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
260 | .master = &omap44xx_dss_hwmod, | |
261 | .slave = &omap44xx_l3_main_1_hwmod, | |
262 | .clk = "l3_div_ck", | |
263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
264 | }; | |
265 | ||
55d2cb08 BC |
266 | /* l3_main_2 -> l3_main_1 */ |
267 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
268 | .master = &omap44xx_l3_main_2_hwmod, | |
269 | .slave = &omap44xx_l3_main_1_hwmod, | |
270 | .clk = "l3_div_ck", | |
271 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
272 | }; | |
273 | ||
274 | /* l4_cfg -> l3_main_1 */ | |
275 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
276 | .master = &omap44xx_l4_cfg_hwmod, | |
277 | .slave = &omap44xx_l3_main_1_hwmod, | |
278 | .clk = "l4_div_ck", | |
279 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
280 | }; | |
281 | ||
407a6888 BC |
282 | /* mmc1 -> l3_main_1 */ |
283 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
284 | .master = &omap44xx_mmc1_hwmod, | |
285 | .slave = &omap44xx_l3_main_1_hwmod, | |
286 | .clk = "l3_div_ck", | |
287 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
288 | }; | |
289 | ||
290 | /* mmc2 -> l3_main_1 */ | |
291 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
292 | .master = &omap44xx_mmc2_hwmod, | |
293 | .slave = &omap44xx_l3_main_1_hwmod, | |
294 | .clk = "l3_div_ck", | |
295 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
296 | }; | |
297 | ||
c4645234 | 298 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { |
299 | { | |
300 | .pa_start = 0x44000000, | |
301 | .pa_end = 0x44000fff, | |
9b4021be | 302 | .flags = ADDR_TYPE_RT |
c4645234 | 303 | }, |
78183f3f | 304 | { } |
c4645234 | 305 | }; |
306 | ||
55d2cb08 BC |
307 | /* mpu -> l3_main_1 */ |
308 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
309 | .master = &omap44xx_mpu_hwmod, | |
310 | .slave = &omap44xx_l3_main_1_hwmod, | |
311 | .clk = "l3_div_ck", | |
c4645234 | 312 | .addr = omap44xx_l3_main_1_addrs, |
9b4021be | 313 | .user = OCP_USER_MPU, |
55d2cb08 BC |
314 | }; |
315 | ||
316 | /* l3_main_1 slave ports */ | |
317 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { | |
8f25bdc5 | 318 | &omap44xx_dsp__l3_main_1, |
d63bd74f | 319 | &omap44xx_dss__l3_main_1, |
55d2cb08 BC |
320 | &omap44xx_l3_main_2__l3_main_1, |
321 | &omap44xx_l4_cfg__l3_main_1, | |
407a6888 BC |
322 | &omap44xx_mmc1__l3_main_1, |
323 | &omap44xx_mmc2__l3_main_1, | |
55d2cb08 BC |
324 | &omap44xx_mpu__l3_main_1, |
325 | }; | |
326 | ||
327 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |
328 | .name = "l3_main_1", | |
329 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 330 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 331 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
332 | .prcm = { |
333 | .omap4 = { | |
334 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 335 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
336 | }, |
337 | }, | |
55d2cb08 BC |
338 | .slaves = omap44xx_l3_main_1_slaves, |
339 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | |
55d2cb08 BC |
340 | }; |
341 | ||
7e69ed97 | 342 | /* l3_main_2 */ |
d7cf5f33 BC |
343 | /* dma_system -> l3_main_2 */ |
344 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
345 | .master = &omap44xx_dma_system_hwmod, | |
346 | .slave = &omap44xx_l3_main_2_hwmod, | |
347 | .clk = "l3_div_ck", | |
348 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
349 | }; | |
350 | ||
407a6888 BC |
351 | /* hsi -> l3_main_2 */ |
352 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
353 | .master = &omap44xx_hsi_hwmod, | |
354 | .slave = &omap44xx_l3_main_2_hwmod, | |
355 | .clk = "l3_div_ck", | |
356 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
357 | }; | |
358 | ||
359 | /* ipu -> l3_main_2 */ | |
360 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
361 | .master = &omap44xx_ipu_hwmod, | |
362 | .slave = &omap44xx_l3_main_2_hwmod, | |
363 | .clk = "l3_div_ck", | |
364 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
365 | }; | |
366 | ||
367 | /* iss -> l3_main_2 */ | |
368 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
369 | .master = &omap44xx_iss_hwmod, | |
370 | .slave = &omap44xx_l3_main_2_hwmod, | |
371 | .clk = "l3_div_ck", | |
372 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
373 | }; | |
374 | ||
8f25bdc5 BC |
375 | /* iva -> l3_main_2 */ |
376 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
377 | .master = &omap44xx_iva_hwmod, | |
378 | .slave = &omap44xx_l3_main_2_hwmod, | |
379 | .clk = "l3_div_ck", | |
380 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
381 | }; | |
382 | ||
c4645234 | 383 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { |
384 | { | |
385 | .pa_start = 0x44800000, | |
386 | .pa_end = 0x44801fff, | |
9b4021be | 387 | .flags = ADDR_TYPE_RT |
c4645234 | 388 | }, |
78183f3f | 389 | { } |
c4645234 | 390 | }; |
391 | ||
55d2cb08 BC |
392 | /* l3_main_1 -> l3_main_2 */ |
393 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
394 | .master = &omap44xx_l3_main_1_hwmod, | |
395 | .slave = &omap44xx_l3_main_2_hwmod, | |
396 | .clk = "l3_div_ck", | |
c4645234 | 397 | .addr = omap44xx_l3_main_2_addrs, |
9b4021be | 398 | .user = OCP_USER_MPU, |
55d2cb08 BC |
399 | }; |
400 | ||
401 | /* l4_cfg -> l3_main_2 */ | |
402 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
403 | .master = &omap44xx_l4_cfg_hwmod, | |
404 | .slave = &omap44xx_l3_main_2_hwmod, | |
405 | .clk = "l4_div_ck", | |
406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
407 | }; | |
408 | ||
5844c4ea BC |
409 | /* usb_otg_hs -> l3_main_2 */ |
410 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
411 | .master = &omap44xx_usb_otg_hs_hwmod, | |
412 | .slave = &omap44xx_l3_main_2_hwmod, | |
413 | .clk = "l3_div_ck", | |
414 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
415 | }; | |
416 | ||
55d2cb08 BC |
417 | /* l3_main_2 slave ports */ |
418 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { | |
531ce0d5 | 419 | &omap44xx_dma_system__l3_main_2, |
407a6888 BC |
420 | &omap44xx_hsi__l3_main_2, |
421 | &omap44xx_ipu__l3_main_2, | |
422 | &omap44xx_iss__l3_main_2, | |
8f25bdc5 | 423 | &omap44xx_iva__l3_main_2, |
55d2cb08 BC |
424 | &omap44xx_l3_main_1__l3_main_2, |
425 | &omap44xx_l4_cfg__l3_main_2, | |
5844c4ea | 426 | &omap44xx_usb_otg_hs__l3_main_2, |
55d2cb08 BC |
427 | }; |
428 | ||
429 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { | |
430 | .name = "l3_main_2", | |
431 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 432 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
433 | .prcm = { |
434 | .omap4 = { | |
435 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 436 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
437 | }, |
438 | }, | |
55d2cb08 BC |
439 | .slaves = omap44xx_l3_main_2_slaves, |
440 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), | |
55d2cb08 BC |
441 | }; |
442 | ||
7e69ed97 | 443 | /* l3_main_3 */ |
c4645234 | 444 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { |
445 | { | |
446 | .pa_start = 0x45000000, | |
447 | .pa_end = 0x45000fff, | |
9b4021be | 448 | .flags = ADDR_TYPE_RT |
c4645234 | 449 | }, |
78183f3f | 450 | { } |
c4645234 | 451 | }; |
452 | ||
55d2cb08 BC |
453 | /* l3_main_1 -> l3_main_3 */ |
454 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
455 | .master = &omap44xx_l3_main_1_hwmod, | |
456 | .slave = &omap44xx_l3_main_3_hwmod, | |
457 | .clk = "l3_div_ck", | |
c4645234 | 458 | .addr = omap44xx_l3_main_3_addrs, |
9b4021be | 459 | .user = OCP_USER_MPU, |
55d2cb08 BC |
460 | }; |
461 | ||
462 | /* l3_main_2 -> l3_main_3 */ | |
463 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
464 | .master = &omap44xx_l3_main_2_hwmod, | |
465 | .slave = &omap44xx_l3_main_3_hwmod, | |
466 | .clk = "l3_div_ck", | |
467 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
468 | }; | |
469 | ||
470 | /* l4_cfg -> l3_main_3 */ | |
471 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
472 | .master = &omap44xx_l4_cfg_hwmod, | |
473 | .slave = &omap44xx_l3_main_3_hwmod, | |
474 | .clk = "l4_div_ck", | |
475 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
476 | }; | |
477 | ||
478 | /* l3_main_3 slave ports */ | |
479 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { | |
480 | &omap44xx_l3_main_1__l3_main_3, | |
481 | &omap44xx_l3_main_2__l3_main_3, | |
482 | &omap44xx_l4_cfg__l3_main_3, | |
483 | }; | |
484 | ||
485 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |
486 | .name = "l3_main_3", | |
487 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 488 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
489 | .prcm = { |
490 | .omap4 = { | |
491 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 492 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 493 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
494 | }, |
495 | }, | |
55d2cb08 BC |
496 | .slaves = omap44xx_l3_main_3_slaves, |
497 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), | |
55d2cb08 BC |
498 | }; |
499 | ||
500 | /* | |
501 | * 'l4' class | |
502 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
503 | */ | |
504 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 505 | .name = "l4", |
55d2cb08 BC |
506 | }; |
507 | ||
7e69ed97 | 508 | /* l4_abe */ |
407a6888 BC |
509 | /* aess -> l4_abe */ |
510 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { | |
511 | .master = &omap44xx_aess_hwmod, | |
512 | .slave = &omap44xx_l4_abe_hwmod, | |
513 | .clk = "ocp_abe_iclk", | |
514 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
515 | }; | |
516 | ||
8f25bdc5 BC |
517 | /* dsp -> l4_abe */ |
518 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
519 | .master = &omap44xx_dsp_hwmod, | |
520 | .slave = &omap44xx_l4_abe_hwmod, | |
521 | .clk = "ocp_abe_iclk", | |
522 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
523 | }; | |
524 | ||
55d2cb08 BC |
525 | /* l3_main_1 -> l4_abe */ |
526 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
527 | .master = &omap44xx_l3_main_1_hwmod, | |
528 | .slave = &omap44xx_l4_abe_hwmod, | |
529 | .clk = "l3_div_ck", | |
530 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
531 | }; | |
532 | ||
533 | /* mpu -> l4_abe */ | |
534 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
535 | .master = &omap44xx_mpu_hwmod, | |
536 | .slave = &omap44xx_l4_abe_hwmod, | |
537 | .clk = "ocp_abe_iclk", | |
538 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
539 | }; | |
540 | ||
541 | /* l4_abe slave ports */ | |
542 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { | |
407a6888 | 543 | &omap44xx_aess__l4_abe, |
8f25bdc5 | 544 | &omap44xx_dsp__l4_abe, |
55d2cb08 BC |
545 | &omap44xx_l3_main_1__l4_abe, |
546 | &omap44xx_mpu__l4_abe, | |
547 | }; | |
548 | ||
549 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { | |
550 | .name = "l4_abe", | |
551 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 552 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
553 | .prcm = { |
554 | .omap4 = { | |
555 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
556 | }, | |
557 | }, | |
55d2cb08 BC |
558 | .slaves = omap44xx_l4_abe_slaves, |
559 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), | |
55d2cb08 BC |
560 | }; |
561 | ||
7e69ed97 | 562 | /* l4_cfg */ |
55d2cb08 BC |
563 | /* l3_main_1 -> l4_cfg */ |
564 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
565 | .master = &omap44xx_l3_main_1_hwmod, | |
566 | .slave = &omap44xx_l4_cfg_hwmod, | |
567 | .clk = "l3_div_ck", | |
568 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
569 | }; | |
570 | ||
571 | /* l4_cfg slave ports */ | |
572 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { | |
573 | &omap44xx_l3_main_1__l4_cfg, | |
574 | }; | |
575 | ||
576 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { | |
577 | .name = "l4_cfg", | |
578 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 579 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
580 | .prcm = { |
581 | .omap4 = { | |
582 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 583 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
584 | }, |
585 | }, | |
55d2cb08 BC |
586 | .slaves = omap44xx_l4_cfg_slaves, |
587 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), | |
55d2cb08 BC |
588 | }; |
589 | ||
7e69ed97 | 590 | /* l4_per */ |
55d2cb08 BC |
591 | /* l3_main_2 -> l4_per */ |
592 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
593 | .master = &omap44xx_l3_main_2_hwmod, | |
594 | .slave = &omap44xx_l4_per_hwmod, | |
595 | .clk = "l3_div_ck", | |
596 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
597 | }; | |
598 | ||
599 | /* l4_per slave ports */ | |
600 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { | |
601 | &omap44xx_l3_main_2__l4_per, | |
602 | }; | |
603 | ||
604 | static struct omap_hwmod omap44xx_l4_per_hwmod = { | |
605 | .name = "l4_per", | |
606 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 607 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
608 | .prcm = { |
609 | .omap4 = { | |
610 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 611 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
612 | }, |
613 | }, | |
55d2cb08 BC |
614 | .slaves = omap44xx_l4_per_slaves, |
615 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), | |
55d2cb08 BC |
616 | }; |
617 | ||
7e69ed97 | 618 | /* l4_wkup */ |
55d2cb08 BC |
619 | /* l4_cfg -> l4_wkup */ |
620 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
621 | .master = &omap44xx_l4_cfg_hwmod, | |
622 | .slave = &omap44xx_l4_wkup_hwmod, | |
623 | .clk = "l4_div_ck", | |
624 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
625 | }; | |
626 | ||
627 | /* l4_wkup slave ports */ | |
628 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { | |
629 | &omap44xx_l4_cfg__l4_wkup, | |
630 | }; | |
631 | ||
632 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |
633 | .name = "l4_wkup", | |
634 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 635 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
636 | .prcm = { |
637 | .omap4 = { | |
638 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 639 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
640 | }, |
641 | }, | |
55d2cb08 BC |
642 | .slaves = omap44xx_l4_wkup_slaves, |
643 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), | |
55d2cb08 BC |
644 | }; |
645 | ||
f776471f | 646 | /* |
3b54baad BC |
647 | * 'mpu_bus' class |
648 | * instance(s): mpu_private | |
f776471f | 649 | */ |
3b54baad | 650 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 651 | .name = "mpu_bus", |
3b54baad | 652 | }; |
f776471f | 653 | |
7e69ed97 | 654 | /* mpu_private */ |
3b54baad BC |
655 | /* mpu -> mpu_private */ |
656 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
657 | .master = &omap44xx_mpu_hwmod, | |
658 | .slave = &omap44xx_mpu_private_hwmod, | |
659 | .clk = "l3_div_ck", | |
660 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
661 | }; | |
662 | ||
663 | /* mpu_private slave ports */ | |
664 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { | |
665 | &omap44xx_mpu__mpu_private, | |
666 | }; | |
667 | ||
668 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |
669 | .name = "mpu_private", | |
670 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 671 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
672 | .slaves = omap44xx_mpu_private_slaves, |
673 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), | |
3b54baad BC |
674 | }; |
675 | ||
676 | /* | |
677 | * Modules omap_hwmod structures | |
678 | * | |
679 | * The following IPs are excluded for the moment because: | |
680 | * - They do not need an explicit SW control using omap_hwmod API. | |
681 | * - They still need to be validated with the driver | |
682 | * properly adapted to omap_hwmod / omap_device | |
683 | * | |
3b54baad BC |
684 | * c2c |
685 | * c2c_target_fw | |
686 | * cm_core | |
687 | * cm_core_aon | |
3b54baad BC |
688 | * ctrl_module_core |
689 | * ctrl_module_pad_core | |
690 | * ctrl_module_pad_wkup | |
691 | * ctrl_module_wkup | |
692 | * debugss | |
3b54baad BC |
693 | * efuse_ctrl_cust |
694 | * efuse_ctrl_std | |
695 | * elm | |
696 | * emif1 | |
697 | * emif2 | |
698 | * fdif | |
699 | * gpmc | |
700 | * gpu | |
701 | * hdq1w | |
00fe610b BC |
702 | * mcasp |
703 | * mpu_c0 | |
704 | * mpu_c1 | |
3b54baad BC |
705 | * ocmc_ram |
706 | * ocp2scp_usb_phy | |
707 | * ocp_wp_noc | |
3b54baad BC |
708 | * prcm_mpu |
709 | * prm | |
710 | * scrm | |
711 | * sl2if | |
712 | * slimbus1 | |
713 | * slimbus2 | |
3b54baad BC |
714 | * usb_host_fs |
715 | * usb_host_hs | |
3b54baad BC |
716 | * usb_phy_cm |
717 | * usb_tll_hs | |
718 | * usim | |
719 | */ | |
720 | ||
407a6888 BC |
721 | /* |
722 | * 'aess' class | |
723 | * audio engine sub system | |
724 | */ | |
725 | ||
726 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
727 | .rev_offs = 0x0000, | |
728 | .sysc_offs = 0x0010, | |
729 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
730 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
731 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
732 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
733 | .sysc_fields = &omap_hwmod_sysc_type2, |
734 | }; | |
735 | ||
736 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
737 | .name = "aess", | |
738 | .sysc = &omap44xx_aess_sysc, | |
739 | }; | |
740 | ||
741 | /* aess */ | |
742 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
743 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 744 | { .irq = -1 } |
407a6888 BC |
745 | }; |
746 | ||
747 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
748 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
749 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
750 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
751 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
752 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
753 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
754 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
755 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 756 | { .dma_req = -1 } |
407a6888 BC |
757 | }; |
758 | ||
759 | /* aess master ports */ | |
760 | static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { | |
761 | &omap44xx_aess__l4_abe, | |
762 | }; | |
763 | ||
764 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { | |
765 | { | |
766 | .pa_start = 0x401f1000, | |
767 | .pa_end = 0x401f13ff, | |
768 | .flags = ADDR_TYPE_RT | |
769 | }, | |
78183f3f | 770 | { } |
407a6888 BC |
771 | }; |
772 | ||
773 | /* l4_abe -> aess */ | |
774 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { | |
775 | .master = &omap44xx_l4_abe_hwmod, | |
776 | .slave = &omap44xx_aess_hwmod, | |
777 | .clk = "ocp_abe_iclk", | |
778 | .addr = omap44xx_aess_addrs, | |
407a6888 BC |
779 | .user = OCP_USER_MPU, |
780 | }; | |
781 | ||
782 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
783 | { | |
784 | .pa_start = 0x490f1000, | |
785 | .pa_end = 0x490f13ff, | |
786 | .flags = ADDR_TYPE_RT | |
787 | }, | |
78183f3f | 788 | { } |
407a6888 BC |
789 | }; |
790 | ||
791 | /* l4_abe -> aess (dma) */ | |
792 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { | |
793 | .master = &omap44xx_l4_abe_hwmod, | |
794 | .slave = &omap44xx_aess_hwmod, | |
795 | .clk = "ocp_abe_iclk", | |
796 | .addr = omap44xx_aess_dma_addrs, | |
407a6888 BC |
797 | .user = OCP_USER_SDMA, |
798 | }; | |
799 | ||
800 | /* aess slave ports */ | |
801 | static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { | |
802 | &omap44xx_l4_abe__aess, | |
803 | &omap44xx_l4_abe__aess_dma, | |
804 | }; | |
805 | ||
806 | static struct omap_hwmod omap44xx_aess_hwmod = { | |
807 | .name = "aess", | |
808 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 809 | .clkdm_name = "abe_clkdm", |
407a6888 | 810 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 811 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 812 | .main_clk = "aess_fck", |
00fe610b | 813 | .prcm = { |
407a6888 | 814 | .omap4 = { |
d0f0631d | 815 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 816 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 817 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
818 | }, |
819 | }, | |
820 | .slaves = omap44xx_aess_slaves, | |
821 | .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), | |
822 | .masters = omap44xx_aess_masters, | |
823 | .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), | |
407a6888 BC |
824 | }; |
825 | ||
826 | /* | |
827 | * 'bandgap' class | |
828 | * bangap reference for ldo regulators | |
829 | */ | |
830 | ||
831 | static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { | |
832 | .name = "bandgap", | |
833 | }; | |
834 | ||
835 | /* bandgap */ | |
836 | static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { | |
837 | { .role = "fclk", .clk = "bandgap_fclk" }, | |
838 | }; | |
839 | ||
840 | static struct omap_hwmod omap44xx_bandgap_hwmod = { | |
841 | .name = "bandgap", | |
842 | .class = &omap44xx_bandgap_hwmod_class, | |
a5322c6f | 843 | .clkdm_name = "l4_wkup_clkdm", |
00fe610b | 844 | .prcm = { |
407a6888 | 845 | .omap4 = { |
d0f0631d | 846 | .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, |
407a6888 BC |
847 | }, |
848 | }, | |
849 | .opt_clks = bandgap_opt_clks, | |
850 | .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), | |
407a6888 BC |
851 | }; |
852 | ||
853 | /* | |
854 | * 'counter' class | |
855 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
856 | */ | |
857 | ||
858 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
859 | .rev_offs = 0x0000, | |
860 | .sysc_offs = 0x0004, | |
861 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
862 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
863 | SIDLE_SMART_WKUP), | |
864 | .sysc_fields = &omap_hwmod_sysc_type1, | |
865 | }; | |
866 | ||
867 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
868 | .name = "counter", | |
869 | .sysc = &omap44xx_counter_sysc, | |
870 | }; | |
871 | ||
872 | /* counter_32k */ | |
873 | static struct omap_hwmod omap44xx_counter_32k_hwmod; | |
874 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { | |
875 | { | |
876 | .pa_start = 0x4a304000, | |
877 | .pa_end = 0x4a30401f, | |
878 | .flags = ADDR_TYPE_RT | |
879 | }, | |
78183f3f | 880 | { } |
407a6888 BC |
881 | }; |
882 | ||
883 | /* l4_wkup -> counter_32k */ | |
884 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
885 | .master = &omap44xx_l4_wkup_hwmod, | |
886 | .slave = &omap44xx_counter_32k_hwmod, | |
887 | .clk = "l4_wkup_clk_mux_ck", | |
888 | .addr = omap44xx_counter_32k_addrs, | |
407a6888 BC |
889 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
890 | }; | |
891 | ||
892 | /* counter_32k slave ports */ | |
893 | static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { | |
894 | &omap44xx_l4_wkup__counter_32k, | |
895 | }; | |
896 | ||
897 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { | |
898 | .name = "counter_32k", | |
899 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 900 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
901 | .flags = HWMOD_SWSUP_SIDLE, |
902 | .main_clk = "sys_32k_ck", | |
00fe610b | 903 | .prcm = { |
407a6888 | 904 | .omap4 = { |
d0f0631d | 905 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 906 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
907 | }, |
908 | }, | |
909 | .slaves = omap44xx_counter_32k_slaves, | |
910 | .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), | |
407a6888 BC |
911 | }; |
912 | ||
d7cf5f33 BC |
913 | /* |
914 | * 'dma' class | |
915 | * dma controller for data exchange between memory to memory (i.e. internal or | |
916 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
917 | */ | |
918 | ||
919 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
920 | .rev_offs = 0x0000, | |
921 | .sysc_offs = 0x002c, | |
922 | .syss_offs = 0x0028, | |
923 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
924 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
925 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
926 | SYSS_HAS_RESET_STATUS), | |
927 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
928 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
929 | .sysc_fields = &omap_hwmod_sysc_type1, | |
930 | }; | |
931 | ||
932 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
933 | .name = "dma", | |
934 | .sysc = &omap44xx_dma_sysc, | |
935 | }; | |
936 | ||
937 | /* dma dev_attr */ | |
938 | static struct omap_dma_dev_attr dma_dev_attr = { | |
939 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
940 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
941 | .lch_count = 32, | |
942 | }; | |
943 | ||
944 | /* dma_system */ | |
945 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
946 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
947 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
948 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
949 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 950 | { .irq = -1 } |
d7cf5f33 BC |
951 | }; |
952 | ||
953 | /* dma_system master ports */ | |
954 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { | |
955 | &omap44xx_dma_system__l3_main_2, | |
956 | }; | |
957 | ||
958 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
959 | { | |
960 | .pa_start = 0x4a056000, | |
1286eeb2 | 961 | .pa_end = 0x4a056fff, |
d7cf5f33 BC |
962 | .flags = ADDR_TYPE_RT |
963 | }, | |
78183f3f | 964 | { } |
d7cf5f33 BC |
965 | }; |
966 | ||
967 | /* l4_cfg -> dma_system */ | |
968 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
969 | .master = &omap44xx_l4_cfg_hwmod, | |
970 | .slave = &omap44xx_dma_system_hwmod, | |
971 | .clk = "l4_div_ck", | |
972 | .addr = omap44xx_dma_system_addrs, | |
d7cf5f33 BC |
973 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
974 | }; | |
975 | ||
976 | /* dma_system slave ports */ | |
977 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { | |
978 | &omap44xx_l4_cfg__dma_system, | |
979 | }; | |
980 | ||
981 | static struct omap_hwmod omap44xx_dma_system_hwmod = { | |
982 | .name = "dma_system", | |
983 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 984 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 985 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
986 | .main_clk = "l3_div_ck", |
987 | .prcm = { | |
988 | .omap4 = { | |
d0f0631d | 989 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 990 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
991 | }, |
992 | }, | |
993 | .dev_attr = &dma_dev_attr, | |
994 | .slaves = omap44xx_dma_system_slaves, | |
995 | .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), | |
996 | .masters = omap44xx_dma_system_masters, | |
997 | .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), | |
d7cf5f33 BC |
998 | }; |
999 | ||
8ca476da BC |
1000 | /* |
1001 | * 'dmic' class | |
1002 | * digital microphone controller | |
1003 | */ | |
1004 | ||
1005 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
1006 | .rev_offs = 0x0000, | |
1007 | .sysc_offs = 0x0010, | |
1008 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1009 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1010 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1011 | SIDLE_SMART_WKUP), | |
1012 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1013 | }; | |
1014 | ||
1015 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
1016 | .name = "dmic", | |
1017 | .sysc = &omap44xx_dmic_sysc, | |
1018 | }; | |
1019 | ||
1020 | /* dmic */ | |
1021 | static struct omap_hwmod omap44xx_dmic_hwmod; | |
1022 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { | |
1023 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1024 | { .irq = -1 } |
8ca476da BC |
1025 | }; |
1026 | ||
1027 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
1028 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1029 | { .dma_req = -1 } |
8ca476da BC |
1030 | }; |
1031 | ||
1032 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
1033 | { | |
6af486e2 | 1034 | .name = "mpu", |
8ca476da BC |
1035 | .pa_start = 0x4012e000, |
1036 | .pa_end = 0x4012e07f, | |
1037 | .flags = ADDR_TYPE_RT | |
1038 | }, | |
78183f3f | 1039 | { } |
8ca476da BC |
1040 | }; |
1041 | ||
1042 | /* l4_abe -> dmic */ | |
1043 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
1044 | .master = &omap44xx_l4_abe_hwmod, | |
1045 | .slave = &omap44xx_dmic_hwmod, | |
1046 | .clk = "ocp_abe_iclk", | |
1047 | .addr = omap44xx_dmic_addrs, | |
8ca476da BC |
1048 | .user = OCP_USER_MPU, |
1049 | }; | |
1050 | ||
1051 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
1052 | { | |
6af486e2 | 1053 | .name = "dma", |
8ca476da BC |
1054 | .pa_start = 0x4902e000, |
1055 | .pa_end = 0x4902e07f, | |
1056 | .flags = ADDR_TYPE_RT | |
1057 | }, | |
78183f3f | 1058 | { } |
8ca476da BC |
1059 | }; |
1060 | ||
1061 | /* l4_abe -> dmic (dma) */ | |
1062 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
1063 | .master = &omap44xx_l4_abe_hwmod, | |
1064 | .slave = &omap44xx_dmic_hwmod, | |
1065 | .clk = "ocp_abe_iclk", | |
1066 | .addr = omap44xx_dmic_dma_addrs, | |
8ca476da BC |
1067 | .user = OCP_USER_SDMA, |
1068 | }; | |
1069 | ||
1070 | /* dmic slave ports */ | |
1071 | static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { | |
1072 | &omap44xx_l4_abe__dmic, | |
1073 | &omap44xx_l4_abe__dmic_dma, | |
1074 | }; | |
1075 | ||
1076 | static struct omap_hwmod omap44xx_dmic_hwmod = { | |
1077 | .name = "dmic", | |
1078 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 1079 | .clkdm_name = "abe_clkdm", |
8ca476da | 1080 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 1081 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 1082 | .main_clk = "dmic_fck", |
00fe610b | 1083 | .prcm = { |
8ca476da | 1084 | .omap4 = { |
d0f0631d | 1085 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 1086 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 1087 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
1088 | }, |
1089 | }, | |
1090 | .slaves = omap44xx_dmic_slaves, | |
1091 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), | |
8ca476da BC |
1092 | }; |
1093 | ||
8f25bdc5 BC |
1094 | /* |
1095 | * 'dsp' class | |
1096 | * dsp sub-system | |
1097 | */ | |
1098 | ||
1099 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 1100 | .name = "dsp", |
8f25bdc5 BC |
1101 | }; |
1102 | ||
1103 | /* dsp */ | |
1104 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
1105 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1106 | { .irq = -1 } |
8f25bdc5 BC |
1107 | }; |
1108 | ||
1109 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
1110 | { .name = "mmu_cache", .rst_shift = 1 }, | |
1111 | }; | |
1112 | ||
1113 | static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { | |
1114 | { .name = "dsp", .rst_shift = 0 }, | |
1115 | }; | |
1116 | ||
1117 | /* dsp -> iva */ | |
1118 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
1119 | .master = &omap44xx_dsp_hwmod, | |
1120 | .slave = &omap44xx_iva_hwmod, | |
1121 | .clk = "dpll_iva_m5x2_ck", | |
1122 | }; | |
1123 | ||
1124 | /* dsp master ports */ | |
1125 | static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { | |
1126 | &omap44xx_dsp__l3_main_1, | |
1127 | &omap44xx_dsp__l4_abe, | |
1128 | &omap44xx_dsp__iva, | |
1129 | }; | |
1130 | ||
1131 | /* l4_cfg -> dsp */ | |
1132 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
1133 | .master = &omap44xx_l4_cfg_hwmod, | |
1134 | .slave = &omap44xx_dsp_hwmod, | |
1135 | .clk = "l4_div_ck", | |
1136 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1137 | }; | |
1138 | ||
1139 | /* dsp slave ports */ | |
1140 | static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { | |
1141 | &omap44xx_l4_cfg__dsp, | |
1142 | }; | |
1143 | ||
1144 | /* Pseudo hwmod for reset control purpose only */ | |
1145 | static struct omap_hwmod omap44xx_dsp_c0_hwmod = { | |
1146 | .name = "dsp_c0", | |
1147 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 1148 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 BC |
1149 | .flags = HWMOD_INIT_NO_RESET, |
1150 | .rst_lines = omap44xx_dsp_c0_resets, | |
1151 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), | |
1152 | .prcm = { | |
1153 | .omap4 = { | |
eaac329d | 1154 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
8f25bdc5 BC |
1155 | }, |
1156 | }, | |
8f25bdc5 BC |
1157 | }; |
1158 | ||
1159 | static struct omap_hwmod omap44xx_dsp_hwmod = { | |
1160 | .name = "dsp", | |
1161 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 1162 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 1163 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
1164 | .rst_lines = omap44xx_dsp_resets, |
1165 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
1166 | .main_clk = "dsp_fck", | |
1167 | .prcm = { | |
1168 | .omap4 = { | |
d0f0631d | 1169 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 1170 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 1171 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 1172 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1173 | }, |
1174 | }, | |
1175 | .slaves = omap44xx_dsp_slaves, | |
1176 | .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), | |
1177 | .masters = omap44xx_dsp_masters, | |
1178 | .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), | |
8f25bdc5 BC |
1179 | }; |
1180 | ||
d63bd74f BC |
1181 | /* |
1182 | * 'dss' class | |
1183 | * display sub-system | |
1184 | */ | |
1185 | ||
1186 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
1187 | .rev_offs = 0x0000, | |
1188 | .syss_offs = 0x0014, | |
1189 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
1190 | }; | |
1191 | ||
1192 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
1193 | .name = "dss", | |
1194 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 1195 | .reset = omap_dss_reset, |
d63bd74f BC |
1196 | }; |
1197 | ||
1198 | /* dss */ | |
1199 | /* dss master ports */ | |
1200 | static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { | |
1201 | &omap44xx_dss__l3_main_1, | |
1202 | }; | |
1203 | ||
1204 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
1205 | { | |
1206 | .pa_start = 0x58000000, | |
1207 | .pa_end = 0x5800007f, | |
1208 | .flags = ADDR_TYPE_RT | |
1209 | }, | |
78183f3f | 1210 | { } |
d63bd74f BC |
1211 | }; |
1212 | ||
1213 | /* l3_main_2 -> dss */ | |
1214 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
1215 | .master = &omap44xx_l3_main_2_hwmod, | |
1216 | .slave = &omap44xx_dss_hwmod, | |
da7cdfac | 1217 | .clk = "dss_fck", |
d63bd74f | 1218 | .addr = omap44xx_dss_dma_addrs, |
d63bd74f BC |
1219 | .user = OCP_USER_SDMA, |
1220 | }; | |
1221 | ||
1222 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
1223 | { | |
1224 | .pa_start = 0x48040000, | |
1225 | .pa_end = 0x4804007f, | |
1226 | .flags = ADDR_TYPE_RT | |
1227 | }, | |
78183f3f | 1228 | { } |
d63bd74f BC |
1229 | }; |
1230 | ||
1231 | /* l4_per -> dss */ | |
1232 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
1233 | .master = &omap44xx_l4_per_hwmod, | |
1234 | .slave = &omap44xx_dss_hwmod, | |
1235 | .clk = "l4_div_ck", | |
1236 | .addr = omap44xx_dss_addrs, | |
d63bd74f BC |
1237 | .user = OCP_USER_MPU, |
1238 | }; | |
1239 | ||
1240 | /* dss slave ports */ | |
1241 | static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { | |
1242 | &omap44xx_l3_main_2__dss, | |
1243 | &omap44xx_l4_per__dss, | |
1244 | }; | |
1245 | ||
1246 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
1247 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1248 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 1249 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
1250 | }; |
1251 | ||
1252 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
1253 | .name = "dss_core", | |
37ad0855 | 1254 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 1255 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 1256 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 1257 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1258 | .prcm = { |
1259 | .omap4 = { | |
d0f0631d | 1260 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1261 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1262 | }, |
1263 | }, | |
1264 | .opt_clks = dss_opt_clks, | |
1265 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1266 | .slaves = omap44xx_dss_slaves, | |
1267 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), | |
1268 | .masters = omap44xx_dss_masters, | |
1269 | .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), | |
d63bd74f BC |
1270 | }; |
1271 | ||
1272 | /* | |
1273 | * 'dispc' class | |
1274 | * display controller | |
1275 | */ | |
1276 | ||
1277 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
1278 | .rev_offs = 0x0000, | |
1279 | .sysc_offs = 0x0010, | |
1280 | .syss_offs = 0x0014, | |
1281 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1282 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
1283 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1284 | SYSS_HAS_RESET_STATUS), | |
1285 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1286 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1287 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1288 | }; | |
1289 | ||
1290 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
1291 | .name = "dispc", | |
1292 | .sysc = &omap44xx_dispc_sysc, | |
1293 | }; | |
1294 | ||
1295 | /* dss_dispc */ | |
1296 | static struct omap_hwmod omap44xx_dss_dispc_hwmod; | |
1297 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { | |
1298 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1299 | { .irq = -1 } |
d63bd74f BC |
1300 | }; |
1301 | ||
1302 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
1303 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1304 | { .dma_req = -1 } |
d63bd74f BC |
1305 | }; |
1306 | ||
1307 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
1308 | { | |
1309 | .pa_start = 0x58001000, | |
1310 | .pa_end = 0x58001fff, | |
1311 | .flags = ADDR_TYPE_RT | |
1312 | }, | |
78183f3f | 1313 | { } |
d63bd74f BC |
1314 | }; |
1315 | ||
1316 | /* l3_main_2 -> dss_dispc */ | |
1317 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
1318 | .master = &omap44xx_l3_main_2_hwmod, | |
1319 | .slave = &omap44xx_dss_dispc_hwmod, | |
da7cdfac | 1320 | .clk = "dss_fck", |
d63bd74f | 1321 | .addr = omap44xx_dss_dispc_dma_addrs, |
d63bd74f BC |
1322 | .user = OCP_USER_SDMA, |
1323 | }; | |
1324 | ||
1325 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
1326 | { | |
1327 | .pa_start = 0x48041000, | |
1328 | .pa_end = 0x48041fff, | |
1329 | .flags = ADDR_TYPE_RT | |
1330 | }, | |
78183f3f | 1331 | { } |
d63bd74f BC |
1332 | }; |
1333 | ||
b923d40d AT |
1334 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
1335 | .manager_count = 3, | |
1336 | .has_framedonetv_irq = 1 | |
1337 | }; | |
1338 | ||
d63bd74f BC |
1339 | /* l4_per -> dss_dispc */ |
1340 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
1341 | .master = &omap44xx_l4_per_hwmod, | |
1342 | .slave = &omap44xx_dss_dispc_hwmod, | |
1343 | .clk = "l4_div_ck", | |
1344 | .addr = omap44xx_dss_dispc_addrs, | |
d63bd74f BC |
1345 | .user = OCP_USER_MPU, |
1346 | }; | |
1347 | ||
1348 | /* dss_dispc slave ports */ | |
1349 | static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { | |
1350 | &omap44xx_l3_main_2__dss_dispc, | |
1351 | &omap44xx_l4_per__dss_dispc, | |
1352 | }; | |
1353 | ||
1354 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { | |
1355 | .name = "dss_dispc", | |
1356 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 1357 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1358 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 1359 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 1360 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1361 | .prcm = { |
1362 | .omap4 = { | |
d0f0631d | 1363 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1364 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1365 | }, |
1366 | }, | |
1367 | .slaves = omap44xx_dss_dispc_slaves, | |
1368 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), | |
b923d40d | 1369 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
1370 | }; |
1371 | ||
1372 | /* | |
1373 | * 'dsi' class | |
1374 | * display serial interface controller | |
1375 | */ | |
1376 | ||
1377 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
1378 | .rev_offs = 0x0000, | |
1379 | .sysc_offs = 0x0010, | |
1380 | .syss_offs = 0x0014, | |
1381 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1382 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1383 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1384 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1385 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1386 | }; | |
1387 | ||
1388 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
1389 | .name = "dsi", | |
1390 | .sysc = &omap44xx_dsi_sysc, | |
1391 | }; | |
1392 | ||
1393 | /* dss_dsi1 */ | |
1394 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod; | |
1395 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { | |
1396 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1397 | { .irq = -1 } |
d63bd74f BC |
1398 | }; |
1399 | ||
1400 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
1401 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1402 | { .dma_req = -1 } |
d63bd74f BC |
1403 | }; |
1404 | ||
1405 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
1406 | { | |
1407 | .pa_start = 0x58004000, | |
1408 | .pa_end = 0x580041ff, | |
1409 | .flags = ADDR_TYPE_RT | |
1410 | }, | |
78183f3f | 1411 | { } |
d63bd74f BC |
1412 | }; |
1413 | ||
1414 | /* l3_main_2 -> dss_dsi1 */ | |
1415 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
1416 | .master = &omap44xx_l3_main_2_hwmod, | |
1417 | .slave = &omap44xx_dss_dsi1_hwmod, | |
da7cdfac | 1418 | .clk = "dss_fck", |
d63bd74f | 1419 | .addr = omap44xx_dss_dsi1_dma_addrs, |
d63bd74f BC |
1420 | .user = OCP_USER_SDMA, |
1421 | }; | |
1422 | ||
1423 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
1424 | { | |
1425 | .pa_start = 0x48044000, | |
1426 | .pa_end = 0x480441ff, | |
1427 | .flags = ADDR_TYPE_RT | |
1428 | }, | |
78183f3f | 1429 | { } |
d63bd74f BC |
1430 | }; |
1431 | ||
1432 | /* l4_per -> dss_dsi1 */ | |
1433 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
1434 | .master = &omap44xx_l4_per_hwmod, | |
1435 | .slave = &omap44xx_dss_dsi1_hwmod, | |
1436 | .clk = "l4_div_ck", | |
1437 | .addr = omap44xx_dss_dsi1_addrs, | |
d63bd74f BC |
1438 | .user = OCP_USER_MPU, |
1439 | }; | |
1440 | ||
1441 | /* dss_dsi1 slave ports */ | |
1442 | static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { | |
1443 | &omap44xx_l3_main_2__dss_dsi1, | |
1444 | &omap44xx_l4_per__dss_dsi1, | |
1445 | }; | |
1446 | ||
3a23aafc TV |
1447 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
1448 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1449 | }; | |
1450 | ||
d63bd74f BC |
1451 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
1452 | .name = "dss_dsi1", | |
1453 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 1454 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1455 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 1456 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 1457 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1458 | .prcm = { |
1459 | .omap4 = { | |
d0f0631d | 1460 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1461 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1462 | }, |
1463 | }, | |
3a23aafc TV |
1464 | .opt_clks = dss_dsi1_opt_clks, |
1465 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
1466 | .slaves = omap44xx_dss_dsi1_slaves, |
1467 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), | |
d63bd74f BC |
1468 | }; |
1469 | ||
1470 | /* dss_dsi2 */ | |
1471 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod; | |
1472 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { | |
1473 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1474 | { .irq = -1 } |
d63bd74f BC |
1475 | }; |
1476 | ||
1477 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
1478 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1479 | { .dma_req = -1 } |
d63bd74f BC |
1480 | }; |
1481 | ||
1482 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
1483 | { | |
1484 | .pa_start = 0x58005000, | |
1485 | .pa_end = 0x580051ff, | |
1486 | .flags = ADDR_TYPE_RT | |
1487 | }, | |
78183f3f | 1488 | { } |
d63bd74f BC |
1489 | }; |
1490 | ||
1491 | /* l3_main_2 -> dss_dsi2 */ | |
1492 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
1493 | .master = &omap44xx_l3_main_2_hwmod, | |
1494 | .slave = &omap44xx_dss_dsi2_hwmod, | |
da7cdfac | 1495 | .clk = "dss_fck", |
d63bd74f | 1496 | .addr = omap44xx_dss_dsi2_dma_addrs, |
d63bd74f BC |
1497 | .user = OCP_USER_SDMA, |
1498 | }; | |
1499 | ||
1500 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
1501 | { | |
1502 | .pa_start = 0x48045000, | |
1503 | .pa_end = 0x480451ff, | |
1504 | .flags = ADDR_TYPE_RT | |
1505 | }, | |
78183f3f | 1506 | { } |
d63bd74f BC |
1507 | }; |
1508 | ||
1509 | /* l4_per -> dss_dsi2 */ | |
1510 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
1511 | .master = &omap44xx_l4_per_hwmod, | |
1512 | .slave = &omap44xx_dss_dsi2_hwmod, | |
1513 | .clk = "l4_div_ck", | |
1514 | .addr = omap44xx_dss_dsi2_addrs, | |
d63bd74f BC |
1515 | .user = OCP_USER_MPU, |
1516 | }; | |
1517 | ||
1518 | /* dss_dsi2 slave ports */ | |
1519 | static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { | |
1520 | &omap44xx_l3_main_2__dss_dsi2, | |
1521 | &omap44xx_l4_per__dss_dsi2, | |
1522 | }; | |
1523 | ||
3a23aafc TV |
1524 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
1525 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1526 | }; | |
1527 | ||
d63bd74f BC |
1528 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
1529 | .name = "dss_dsi2", | |
1530 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 1531 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1532 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 1533 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 1534 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1535 | .prcm = { |
1536 | .omap4 = { | |
d0f0631d | 1537 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1538 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1539 | }, |
1540 | }, | |
3a23aafc TV |
1541 | .opt_clks = dss_dsi2_opt_clks, |
1542 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
1543 | .slaves = omap44xx_dss_dsi2_slaves, |
1544 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), | |
d63bd74f BC |
1545 | }; |
1546 | ||
1547 | /* | |
1548 | * 'hdmi' class | |
1549 | * hdmi controller | |
1550 | */ | |
1551 | ||
1552 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
1553 | .rev_offs = 0x0000, | |
1554 | .sysc_offs = 0x0010, | |
1555 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1556 | SYSC_HAS_SOFTRESET), | |
1557 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1558 | SIDLE_SMART_WKUP), | |
1559 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1560 | }; | |
1561 | ||
1562 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
1563 | .name = "hdmi", | |
1564 | .sysc = &omap44xx_hdmi_sysc, | |
1565 | }; | |
1566 | ||
1567 | /* dss_hdmi */ | |
1568 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod; | |
1569 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { | |
1570 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1571 | { .irq = -1 } |
d63bd74f BC |
1572 | }; |
1573 | ||
1574 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
1575 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1576 | { .dma_req = -1 } |
d63bd74f BC |
1577 | }; |
1578 | ||
1579 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
1580 | { | |
1581 | .pa_start = 0x58006000, | |
1582 | .pa_end = 0x58006fff, | |
1583 | .flags = ADDR_TYPE_RT | |
1584 | }, | |
78183f3f | 1585 | { } |
d63bd74f BC |
1586 | }; |
1587 | ||
1588 | /* l3_main_2 -> dss_hdmi */ | |
1589 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
1590 | .master = &omap44xx_l3_main_2_hwmod, | |
1591 | .slave = &omap44xx_dss_hdmi_hwmod, | |
da7cdfac | 1592 | .clk = "dss_fck", |
d63bd74f | 1593 | .addr = omap44xx_dss_hdmi_dma_addrs, |
d63bd74f BC |
1594 | .user = OCP_USER_SDMA, |
1595 | }; | |
1596 | ||
1597 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
1598 | { | |
1599 | .pa_start = 0x48046000, | |
1600 | .pa_end = 0x48046fff, | |
1601 | .flags = ADDR_TYPE_RT | |
1602 | }, | |
78183f3f | 1603 | { } |
d63bd74f BC |
1604 | }; |
1605 | ||
1606 | /* l4_per -> dss_hdmi */ | |
1607 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
1608 | .master = &omap44xx_l4_per_hwmod, | |
1609 | .slave = &omap44xx_dss_hdmi_hwmod, | |
1610 | .clk = "l4_div_ck", | |
1611 | .addr = omap44xx_dss_hdmi_addrs, | |
d63bd74f BC |
1612 | .user = OCP_USER_MPU, |
1613 | }; | |
1614 | ||
1615 | /* dss_hdmi slave ports */ | |
1616 | static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { | |
1617 | &omap44xx_l3_main_2__dss_hdmi, | |
1618 | &omap44xx_l4_per__dss_hdmi, | |
1619 | }; | |
1620 | ||
3a23aafc TV |
1621 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
1622 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1623 | }; | |
1624 | ||
d63bd74f BC |
1625 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
1626 | .name = "dss_hdmi", | |
1627 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 1628 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1629 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 1630 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 1631 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
1632 | .prcm = { |
1633 | .omap4 = { | |
d0f0631d | 1634 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1635 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1636 | }, |
1637 | }, | |
3a23aafc TV |
1638 | .opt_clks = dss_hdmi_opt_clks, |
1639 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
1640 | .slaves = omap44xx_dss_hdmi_slaves, |
1641 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), | |
d63bd74f BC |
1642 | }; |
1643 | ||
1644 | /* | |
1645 | * 'rfbi' class | |
1646 | * remote frame buffer interface | |
1647 | */ | |
1648 | ||
1649 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
1650 | .rev_offs = 0x0000, | |
1651 | .sysc_offs = 0x0010, | |
1652 | .syss_offs = 0x0014, | |
1653 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1654 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1655 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1656 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1657 | }; | |
1658 | ||
1659 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
1660 | .name = "rfbi", | |
1661 | .sysc = &omap44xx_rfbi_sysc, | |
1662 | }; | |
1663 | ||
1664 | /* dss_rfbi */ | |
1665 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod; | |
1666 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { | |
1667 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1668 | { .dma_req = -1 } |
d63bd74f BC |
1669 | }; |
1670 | ||
1671 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
1672 | { | |
1673 | .pa_start = 0x58002000, | |
1674 | .pa_end = 0x580020ff, | |
1675 | .flags = ADDR_TYPE_RT | |
1676 | }, | |
78183f3f | 1677 | { } |
d63bd74f BC |
1678 | }; |
1679 | ||
1680 | /* l3_main_2 -> dss_rfbi */ | |
1681 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
1682 | .master = &omap44xx_l3_main_2_hwmod, | |
1683 | .slave = &omap44xx_dss_rfbi_hwmod, | |
da7cdfac | 1684 | .clk = "dss_fck", |
d63bd74f | 1685 | .addr = omap44xx_dss_rfbi_dma_addrs, |
d63bd74f BC |
1686 | .user = OCP_USER_SDMA, |
1687 | }; | |
1688 | ||
1689 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
1690 | { | |
1691 | .pa_start = 0x48042000, | |
1692 | .pa_end = 0x480420ff, | |
1693 | .flags = ADDR_TYPE_RT | |
1694 | }, | |
78183f3f | 1695 | { } |
d63bd74f BC |
1696 | }; |
1697 | ||
1698 | /* l4_per -> dss_rfbi */ | |
1699 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
1700 | .master = &omap44xx_l4_per_hwmod, | |
1701 | .slave = &omap44xx_dss_rfbi_hwmod, | |
1702 | .clk = "l4_div_ck", | |
1703 | .addr = omap44xx_dss_rfbi_addrs, | |
d63bd74f BC |
1704 | .user = OCP_USER_MPU, |
1705 | }; | |
1706 | ||
1707 | /* dss_rfbi slave ports */ | |
1708 | static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { | |
1709 | &omap44xx_l3_main_2__dss_rfbi, | |
1710 | &omap44xx_l4_per__dss_rfbi, | |
1711 | }; | |
1712 | ||
3a23aafc TV |
1713 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
1714 | { .role = "ick", .clk = "dss_fck" }, | |
1715 | }; | |
1716 | ||
d63bd74f BC |
1717 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
1718 | .name = "dss_rfbi", | |
1719 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 1720 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1721 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 1722 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1723 | .prcm = { |
1724 | .omap4 = { | |
d0f0631d | 1725 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1726 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1727 | }, |
1728 | }, | |
3a23aafc TV |
1729 | .opt_clks = dss_rfbi_opt_clks, |
1730 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
1731 | .slaves = omap44xx_dss_rfbi_slaves, |
1732 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), | |
d63bd74f BC |
1733 | }; |
1734 | ||
1735 | /* | |
1736 | * 'venc' class | |
1737 | * video encoder | |
1738 | */ | |
1739 | ||
1740 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
1741 | .name = "venc", | |
1742 | }; | |
1743 | ||
1744 | /* dss_venc */ | |
1745 | static struct omap_hwmod omap44xx_dss_venc_hwmod; | |
1746 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
1747 | { | |
1748 | .pa_start = 0x58003000, | |
1749 | .pa_end = 0x580030ff, | |
1750 | .flags = ADDR_TYPE_RT | |
1751 | }, | |
78183f3f | 1752 | { } |
d63bd74f BC |
1753 | }; |
1754 | ||
1755 | /* l3_main_2 -> dss_venc */ | |
1756 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
1757 | .master = &omap44xx_l3_main_2_hwmod, | |
1758 | .slave = &omap44xx_dss_venc_hwmod, | |
da7cdfac | 1759 | .clk = "dss_fck", |
d63bd74f | 1760 | .addr = omap44xx_dss_venc_dma_addrs, |
d63bd74f BC |
1761 | .user = OCP_USER_SDMA, |
1762 | }; | |
1763 | ||
1764 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
1765 | { | |
1766 | .pa_start = 0x48043000, | |
1767 | .pa_end = 0x480430ff, | |
1768 | .flags = ADDR_TYPE_RT | |
1769 | }, | |
78183f3f | 1770 | { } |
d63bd74f BC |
1771 | }; |
1772 | ||
1773 | /* l4_per -> dss_venc */ | |
1774 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
1775 | .master = &omap44xx_l4_per_hwmod, | |
1776 | .slave = &omap44xx_dss_venc_hwmod, | |
1777 | .clk = "l4_div_ck", | |
1778 | .addr = omap44xx_dss_venc_addrs, | |
d63bd74f BC |
1779 | .user = OCP_USER_MPU, |
1780 | }; | |
1781 | ||
1782 | /* dss_venc slave ports */ | |
1783 | static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { | |
1784 | &omap44xx_l3_main_2__dss_venc, | |
1785 | &omap44xx_l4_per__dss_venc, | |
1786 | }; | |
1787 | ||
1788 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { | |
1789 | .name = "dss_venc", | |
1790 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 1791 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 1792 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
1793 | .prcm = { |
1794 | .omap4 = { | |
d0f0631d | 1795 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1796 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1797 | }, |
1798 | }, | |
1799 | .slaves = omap44xx_dss_venc_slaves, | |
1800 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), | |
d63bd74f BC |
1801 | }; |
1802 | ||
3b54baad BC |
1803 | /* |
1804 | * 'gpio' class | |
1805 | * general purpose io module | |
1806 | */ | |
1807 | ||
1808 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1809 | .rev_offs = 0x0000, | |
f776471f | 1810 | .sysc_offs = 0x0010, |
3b54baad | 1811 | .syss_offs = 0x0114, |
0cfe8751 BC |
1812 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1813 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1814 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1815 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1816 | SIDLE_SMART_WKUP), | |
f776471f BC |
1817 | .sysc_fields = &omap_hwmod_sysc_type1, |
1818 | }; | |
1819 | ||
3b54baad | 1820 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1821 | .name = "gpio", |
1822 | .sysc = &omap44xx_gpio_sysc, | |
1823 | .rev = 2, | |
f776471f BC |
1824 | }; |
1825 | ||
3b54baad BC |
1826 | /* gpio dev_attr */ |
1827 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1828 | .bank_width = 32, |
1829 | .dbck_flag = true, | |
f776471f BC |
1830 | }; |
1831 | ||
3b54baad BC |
1832 | /* gpio1 */ |
1833 | static struct omap_hwmod omap44xx_gpio1_hwmod; | |
1834 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | |
1835 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1836 | { .irq = -1 } |
f776471f BC |
1837 | }; |
1838 | ||
3b54baad | 1839 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
f776471f | 1840 | { |
3b54baad BC |
1841 | .pa_start = 0x4a310000, |
1842 | .pa_end = 0x4a3101ff, | |
f776471f BC |
1843 | .flags = ADDR_TYPE_RT |
1844 | }, | |
78183f3f | 1845 | { } |
f776471f BC |
1846 | }; |
1847 | ||
3b54baad BC |
1848 | /* l4_wkup -> gpio1 */ |
1849 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
1850 | .master = &omap44xx_l4_wkup_hwmod, | |
1851 | .slave = &omap44xx_gpio1_hwmod, | |
b399bca8 | 1852 | .clk = "l4_wkup_clk_mux_ck", |
3b54baad | 1853 | .addr = omap44xx_gpio1_addrs, |
f776471f BC |
1854 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1855 | }; | |
1856 | ||
3b54baad BC |
1857 | /* gpio1 slave ports */ |
1858 | static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { | |
1859 | &omap44xx_l4_wkup__gpio1, | |
f776471f BC |
1860 | }; |
1861 | ||
3b54baad | 1862 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1863 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1864 | }; |
1865 | ||
1866 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1867 | .name = "gpio1", | |
1868 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1869 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1870 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1871 | .main_clk = "gpio1_ick", |
f776471f BC |
1872 | .prcm = { |
1873 | .omap4 = { | |
d0f0631d | 1874 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1875 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1876 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1877 | }, |
1878 | }, | |
3b54baad BC |
1879 | .opt_clks = gpio1_opt_clks, |
1880 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1881 | .dev_attr = &gpio_dev_attr, | |
1882 | .slaves = omap44xx_gpio1_slaves, | |
1883 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), | |
f776471f BC |
1884 | }; |
1885 | ||
3b54baad BC |
1886 | /* gpio2 */ |
1887 | static struct omap_hwmod omap44xx_gpio2_hwmod; | |
1888 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | |
1889 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1890 | { .irq = -1 } |
f776471f BC |
1891 | }; |
1892 | ||
3b54baad | 1893 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
f776471f | 1894 | { |
3b54baad BC |
1895 | .pa_start = 0x48055000, |
1896 | .pa_end = 0x480551ff, | |
f776471f BC |
1897 | .flags = ADDR_TYPE_RT |
1898 | }, | |
78183f3f | 1899 | { } |
f776471f BC |
1900 | }; |
1901 | ||
3b54baad BC |
1902 | /* l4_per -> gpio2 */ |
1903 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
f776471f | 1904 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1905 | .slave = &omap44xx_gpio2_hwmod, |
b399bca8 | 1906 | .clk = "l4_div_ck", |
3b54baad | 1907 | .addr = omap44xx_gpio2_addrs, |
f776471f BC |
1908 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1909 | }; | |
1910 | ||
3b54baad BC |
1911 | /* gpio2 slave ports */ |
1912 | static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { | |
1913 | &omap44xx_l4_per__gpio2, | |
f776471f BC |
1914 | }; |
1915 | ||
3b54baad | 1916 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1917 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1918 | }; |
1919 | ||
1920 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1921 | .name = "gpio2", | |
1922 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1923 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1924 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1925 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1926 | .main_clk = "gpio2_ick", |
f776471f BC |
1927 | .prcm = { |
1928 | .omap4 = { | |
d0f0631d | 1929 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1930 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1931 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1932 | }, |
1933 | }, | |
3b54baad BC |
1934 | .opt_clks = gpio2_opt_clks, |
1935 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1936 | .dev_attr = &gpio_dev_attr, | |
1937 | .slaves = omap44xx_gpio2_slaves, | |
1938 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), | |
f776471f BC |
1939 | }; |
1940 | ||
3b54baad BC |
1941 | /* gpio3 */ |
1942 | static struct omap_hwmod omap44xx_gpio3_hwmod; | |
1943 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | |
1944 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1945 | { .irq = -1 } |
f776471f BC |
1946 | }; |
1947 | ||
3b54baad | 1948 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
f776471f | 1949 | { |
3b54baad BC |
1950 | .pa_start = 0x48057000, |
1951 | .pa_end = 0x480571ff, | |
f776471f BC |
1952 | .flags = ADDR_TYPE_RT |
1953 | }, | |
78183f3f | 1954 | { } |
f776471f BC |
1955 | }; |
1956 | ||
3b54baad BC |
1957 | /* l4_per -> gpio3 */ |
1958 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
f776471f | 1959 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1960 | .slave = &omap44xx_gpio3_hwmod, |
b399bca8 | 1961 | .clk = "l4_div_ck", |
3b54baad | 1962 | .addr = omap44xx_gpio3_addrs, |
f776471f BC |
1963 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1964 | }; | |
1965 | ||
3b54baad BC |
1966 | /* gpio3 slave ports */ |
1967 | static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { | |
1968 | &omap44xx_l4_per__gpio3, | |
f776471f BC |
1969 | }; |
1970 | ||
3b54baad | 1971 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1972 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1973 | }; |
1974 | ||
1975 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1976 | .name = "gpio3", | |
1977 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1978 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1979 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1980 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1981 | .main_clk = "gpio3_ick", |
f776471f BC |
1982 | .prcm = { |
1983 | .omap4 = { | |
d0f0631d | 1984 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1985 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1986 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1987 | }, |
1988 | }, | |
3b54baad BC |
1989 | .opt_clks = gpio3_opt_clks, |
1990 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1991 | .dev_attr = &gpio_dev_attr, | |
1992 | .slaves = omap44xx_gpio3_slaves, | |
1993 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), | |
f776471f BC |
1994 | }; |
1995 | ||
3b54baad BC |
1996 | /* gpio4 */ |
1997 | static struct omap_hwmod omap44xx_gpio4_hwmod; | |
1998 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | |
1999 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2000 | { .irq = -1 } |
f776471f BC |
2001 | }; |
2002 | ||
3b54baad | 2003 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
f776471f | 2004 | { |
3b54baad BC |
2005 | .pa_start = 0x48059000, |
2006 | .pa_end = 0x480591ff, | |
f776471f BC |
2007 | .flags = ADDR_TYPE_RT |
2008 | }, | |
78183f3f | 2009 | { } |
f776471f BC |
2010 | }; |
2011 | ||
3b54baad BC |
2012 | /* l4_per -> gpio4 */ |
2013 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
f776471f | 2014 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2015 | .slave = &omap44xx_gpio4_hwmod, |
b399bca8 | 2016 | .clk = "l4_div_ck", |
3b54baad | 2017 | .addr = omap44xx_gpio4_addrs, |
f776471f BC |
2018 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2019 | }; | |
2020 | ||
3b54baad BC |
2021 | /* gpio4 slave ports */ |
2022 | static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { | |
2023 | &omap44xx_l4_per__gpio4, | |
f776471f BC |
2024 | }; |
2025 | ||
3b54baad | 2026 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 2027 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
2028 | }; |
2029 | ||
2030 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
2031 | .name = "gpio4", | |
2032 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2033 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2034 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2035 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 2036 | .main_clk = "gpio4_ick", |
f776471f BC |
2037 | .prcm = { |
2038 | .omap4 = { | |
d0f0631d | 2039 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 2040 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 2041 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
2042 | }, |
2043 | }, | |
3b54baad BC |
2044 | .opt_clks = gpio4_opt_clks, |
2045 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
2046 | .dev_attr = &gpio_dev_attr, | |
2047 | .slaves = omap44xx_gpio4_slaves, | |
2048 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), | |
f776471f BC |
2049 | }; |
2050 | ||
3b54baad BC |
2051 | /* gpio5 */ |
2052 | static struct omap_hwmod omap44xx_gpio5_hwmod; | |
2053 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | |
2054 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2055 | { .irq = -1 } |
55d2cb08 BC |
2056 | }; |
2057 | ||
3b54baad BC |
2058 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
2059 | { | |
2060 | .pa_start = 0x4805b000, | |
2061 | .pa_end = 0x4805b1ff, | |
2062 | .flags = ADDR_TYPE_RT | |
2063 | }, | |
78183f3f | 2064 | { } |
55d2cb08 BC |
2065 | }; |
2066 | ||
3b54baad BC |
2067 | /* l4_per -> gpio5 */ |
2068 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
2069 | .master = &omap44xx_l4_per_hwmod, | |
2070 | .slave = &omap44xx_gpio5_hwmod, | |
b399bca8 | 2071 | .clk = "l4_div_ck", |
3b54baad | 2072 | .addr = omap44xx_gpio5_addrs, |
3b54baad | 2073 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
55d2cb08 BC |
2074 | }; |
2075 | ||
3b54baad BC |
2076 | /* gpio5 slave ports */ |
2077 | static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { | |
2078 | &omap44xx_l4_per__gpio5, | |
55d2cb08 BC |
2079 | }; |
2080 | ||
3b54baad | 2081 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
b399bca8 | 2082 | { .role = "dbclk", .clk = "gpio5_dbclk" }, |
55d2cb08 BC |
2083 | }; |
2084 | ||
3b54baad BC |
2085 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
2086 | .name = "gpio5", | |
2087 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2088 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2089 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2090 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 2091 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
2092 | .prcm = { |
2093 | .omap4 = { | |
d0f0631d | 2094 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 2095 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 2096 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
2097 | }, |
2098 | }, | |
3b54baad BC |
2099 | .opt_clks = gpio5_opt_clks, |
2100 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
2101 | .dev_attr = &gpio_dev_attr, | |
2102 | .slaves = omap44xx_gpio5_slaves, | |
2103 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), | |
55d2cb08 BC |
2104 | }; |
2105 | ||
3b54baad BC |
2106 | /* gpio6 */ |
2107 | static struct omap_hwmod omap44xx_gpio6_hwmod; | |
2108 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | |
2109 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2110 | { .irq = -1 } |
92b18d1c BC |
2111 | }; |
2112 | ||
3b54baad | 2113 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
92b18d1c | 2114 | { |
3b54baad BC |
2115 | .pa_start = 0x4805d000, |
2116 | .pa_end = 0x4805d1ff, | |
92b18d1c BC |
2117 | .flags = ADDR_TYPE_RT |
2118 | }, | |
78183f3f | 2119 | { } |
92b18d1c BC |
2120 | }; |
2121 | ||
3b54baad BC |
2122 | /* l4_per -> gpio6 */ |
2123 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
2124 | .master = &omap44xx_l4_per_hwmod, | |
2125 | .slave = &omap44xx_gpio6_hwmod, | |
b399bca8 | 2126 | .clk = "l4_div_ck", |
3b54baad | 2127 | .addr = omap44xx_gpio6_addrs, |
3b54baad | 2128 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
db12ba53 BC |
2129 | }; |
2130 | ||
3b54baad BC |
2131 | /* gpio6 slave ports */ |
2132 | static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { | |
2133 | &omap44xx_l4_per__gpio6, | |
db12ba53 BC |
2134 | }; |
2135 | ||
3b54baad | 2136 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 2137 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
2138 | }; |
2139 | ||
3b54baad BC |
2140 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
2141 | .name = "gpio6", | |
2142 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2143 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2144 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2145 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
2146 | .main_clk = "gpio6_ick", |
2147 | .prcm = { | |
2148 | .omap4 = { | |
d0f0631d | 2149 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 2150 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 2151 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 2152 | }, |
db12ba53 | 2153 | }, |
3b54baad BC |
2154 | .opt_clks = gpio6_opt_clks, |
2155 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
2156 | .dev_attr = &gpio_dev_attr, | |
2157 | .slaves = omap44xx_gpio6_slaves, | |
2158 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), | |
db12ba53 BC |
2159 | }; |
2160 | ||
407a6888 BC |
2161 | /* |
2162 | * 'hsi' class | |
2163 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
2164 | * serial if) | |
2165 | */ | |
2166 | ||
2167 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
2168 | .rev_offs = 0x0000, | |
2169 | .sysc_offs = 0x0010, | |
2170 | .syss_offs = 0x0014, | |
2171 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
2172 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2173 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2174 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2175 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2176 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2177 | .sysc_fields = &omap_hwmod_sysc_type1, |
2178 | }; | |
2179 | ||
2180 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
2181 | .name = "hsi", | |
2182 | .sysc = &omap44xx_hsi_sysc, | |
2183 | }; | |
2184 | ||
2185 | /* hsi */ | |
2186 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
2187 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
2188 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
2189 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2190 | { .irq = -1 } |
407a6888 BC |
2191 | }; |
2192 | ||
2193 | /* hsi master ports */ | |
2194 | static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { | |
2195 | &omap44xx_hsi__l3_main_2, | |
2196 | }; | |
2197 | ||
2198 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { | |
2199 | { | |
2200 | .pa_start = 0x4a058000, | |
2201 | .pa_end = 0x4a05bfff, | |
2202 | .flags = ADDR_TYPE_RT | |
2203 | }, | |
78183f3f | 2204 | { } |
407a6888 BC |
2205 | }; |
2206 | ||
2207 | /* l4_cfg -> hsi */ | |
2208 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
2209 | .master = &omap44xx_l4_cfg_hwmod, | |
2210 | .slave = &omap44xx_hsi_hwmod, | |
2211 | .clk = "l4_div_ck", | |
2212 | .addr = omap44xx_hsi_addrs, | |
407a6888 BC |
2213 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2214 | }; | |
2215 | ||
2216 | /* hsi slave ports */ | |
2217 | static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { | |
2218 | &omap44xx_l4_cfg__hsi, | |
2219 | }; | |
2220 | ||
2221 | static struct omap_hwmod omap44xx_hsi_hwmod = { | |
2222 | .name = "hsi", | |
2223 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 2224 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2225 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 2226 | .main_clk = "hsi_fck", |
00fe610b | 2227 | .prcm = { |
407a6888 | 2228 | .omap4 = { |
d0f0631d | 2229 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 2230 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 2231 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
2232 | }, |
2233 | }, | |
2234 | .slaves = omap44xx_hsi_slaves, | |
2235 | .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), | |
2236 | .masters = omap44xx_hsi_masters, | |
2237 | .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), | |
407a6888 BC |
2238 | }; |
2239 | ||
3b54baad BC |
2240 | /* |
2241 | * 'i2c' class | |
2242 | * multimaster high-speed i2c controller | |
2243 | */ | |
db12ba53 | 2244 | |
3b54baad BC |
2245 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
2246 | .sysc_offs = 0x0010, | |
2247 | .syss_offs = 0x0090, | |
2248 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2249 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 2250 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
2251 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2252 | SIDLE_SMART_WKUP), | |
3e47dc6a | 2253 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 2254 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
2255 | }; |
2256 | ||
3b54baad | 2257 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
2258 | .name = "i2c", |
2259 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 2260 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 2261 | .reset = &omap_i2c_reset, |
db12ba53 BC |
2262 | }; |
2263 | ||
4d4441a6 AG |
2264 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2265 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
2266 | }; | |
2267 | ||
3b54baad BC |
2268 | /* i2c1 */ |
2269 | static struct omap_hwmod omap44xx_i2c1_hwmod; | |
2270 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | |
2271 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2272 | { .irq = -1 } |
db12ba53 BC |
2273 | }; |
2274 | ||
3b54baad BC |
2275 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
2276 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
2277 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2278 | { .dma_req = -1 } |
db12ba53 BC |
2279 | }; |
2280 | ||
3b54baad | 2281 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
db12ba53 | 2282 | { |
3b54baad BC |
2283 | .pa_start = 0x48070000, |
2284 | .pa_end = 0x480700ff, | |
db12ba53 BC |
2285 | .flags = ADDR_TYPE_RT |
2286 | }, | |
78183f3f | 2287 | { } |
db12ba53 BC |
2288 | }; |
2289 | ||
3b54baad BC |
2290 | /* l4_per -> i2c1 */ |
2291 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
2292 | .master = &omap44xx_l4_per_hwmod, | |
2293 | .slave = &omap44xx_i2c1_hwmod, | |
2294 | .clk = "l4_div_ck", | |
2295 | .addr = omap44xx_i2c1_addrs, | |
92b18d1c BC |
2296 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2297 | }; | |
2298 | ||
3b54baad BC |
2299 | /* i2c1 slave ports */ |
2300 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | |
2301 | &omap44xx_l4_per__i2c1, | |
92b18d1c BC |
2302 | }; |
2303 | ||
3b54baad BC |
2304 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
2305 | .name = "i2c1", | |
2306 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2307 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2308 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2309 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 2310 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 2311 | .main_clk = "i2c1_fck", |
92b18d1c BC |
2312 | .prcm = { |
2313 | .omap4 = { | |
d0f0631d | 2314 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 2315 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 2316 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
2317 | }, |
2318 | }, | |
3b54baad BC |
2319 | .slaves = omap44xx_i2c1_slaves, |
2320 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | |
4d4441a6 | 2321 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
2322 | }; |
2323 | ||
3b54baad BC |
2324 | /* i2c2 */ |
2325 | static struct omap_hwmod omap44xx_i2c2_hwmod; | |
2326 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | |
2327 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2328 | { .irq = -1 } |
92b18d1c BC |
2329 | }; |
2330 | ||
3b54baad BC |
2331 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
2332 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
2333 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2334 | { .dma_req = -1 } |
3b54baad BC |
2335 | }; |
2336 | ||
2337 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
92b18d1c | 2338 | { |
3b54baad BC |
2339 | .pa_start = 0x48072000, |
2340 | .pa_end = 0x480720ff, | |
92b18d1c BC |
2341 | .flags = ADDR_TYPE_RT |
2342 | }, | |
78183f3f | 2343 | { } |
92b18d1c BC |
2344 | }; |
2345 | ||
3b54baad BC |
2346 | /* l4_per -> i2c2 */ |
2347 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
db12ba53 | 2348 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2349 | .slave = &omap44xx_i2c2_hwmod, |
db12ba53 | 2350 | .clk = "l4_div_ck", |
3b54baad | 2351 | .addr = omap44xx_i2c2_addrs, |
db12ba53 BC |
2352 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2353 | }; | |
2354 | ||
3b54baad BC |
2355 | /* i2c2 slave ports */ |
2356 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | |
2357 | &omap44xx_l4_per__i2c2, | |
db12ba53 BC |
2358 | }; |
2359 | ||
3b54baad BC |
2360 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
2361 | .name = "i2c2", | |
2362 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2363 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2364 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2365 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 2366 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 2367 | .main_clk = "i2c2_fck", |
db12ba53 BC |
2368 | .prcm = { |
2369 | .omap4 = { | |
d0f0631d | 2370 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 2371 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 2372 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
2373 | }, |
2374 | }, | |
3b54baad BC |
2375 | .slaves = omap44xx_i2c2_slaves, |
2376 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | |
4d4441a6 | 2377 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
2378 | }; |
2379 | ||
3b54baad BC |
2380 | /* i2c3 */ |
2381 | static struct omap_hwmod omap44xx_i2c3_hwmod; | |
2382 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | |
2383 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2384 | { .irq = -1 } |
db12ba53 BC |
2385 | }; |
2386 | ||
3b54baad BC |
2387 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
2388 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
2389 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2390 | { .dma_req = -1 } |
92b18d1c BC |
2391 | }; |
2392 | ||
3b54baad | 2393 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
92b18d1c | 2394 | { |
3b54baad BC |
2395 | .pa_start = 0x48060000, |
2396 | .pa_end = 0x480600ff, | |
92b18d1c BC |
2397 | .flags = ADDR_TYPE_RT |
2398 | }, | |
78183f3f | 2399 | { } |
92b18d1c BC |
2400 | }; |
2401 | ||
3b54baad BC |
2402 | /* l4_per -> i2c3 */ |
2403 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
db12ba53 | 2404 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2405 | .slave = &omap44xx_i2c3_hwmod, |
db12ba53 | 2406 | .clk = "l4_div_ck", |
3b54baad | 2407 | .addr = omap44xx_i2c3_addrs, |
db12ba53 BC |
2408 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2409 | }; | |
2410 | ||
3b54baad BC |
2411 | /* i2c3 slave ports */ |
2412 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | |
2413 | &omap44xx_l4_per__i2c3, | |
db12ba53 BC |
2414 | }; |
2415 | ||
3b54baad BC |
2416 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
2417 | .name = "i2c3", | |
2418 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2419 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2420 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2421 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 2422 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 2423 | .main_clk = "i2c3_fck", |
db12ba53 BC |
2424 | .prcm = { |
2425 | .omap4 = { | |
d0f0631d | 2426 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 2427 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 2428 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
2429 | }, |
2430 | }, | |
3b54baad BC |
2431 | .slaves = omap44xx_i2c3_slaves, |
2432 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | |
4d4441a6 | 2433 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
2434 | }; |
2435 | ||
3b54baad BC |
2436 | /* i2c4 */ |
2437 | static struct omap_hwmod omap44xx_i2c4_hwmod; | |
2438 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | |
2439 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2440 | { .irq = -1 } |
db12ba53 BC |
2441 | }; |
2442 | ||
3b54baad BC |
2443 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
2444 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
2445 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2446 | { .dma_req = -1 } |
db12ba53 BC |
2447 | }; |
2448 | ||
3b54baad | 2449 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
db12ba53 | 2450 | { |
3b54baad BC |
2451 | .pa_start = 0x48350000, |
2452 | .pa_end = 0x483500ff, | |
db12ba53 BC |
2453 | .flags = ADDR_TYPE_RT |
2454 | }, | |
78183f3f | 2455 | { } |
db12ba53 BC |
2456 | }; |
2457 | ||
3b54baad BC |
2458 | /* l4_per -> i2c4 */ |
2459 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
2460 | .master = &omap44xx_l4_per_hwmod, | |
2461 | .slave = &omap44xx_i2c4_hwmod, | |
2462 | .clk = "l4_div_ck", | |
2463 | .addr = omap44xx_i2c4_addrs, | |
3b54baad | 2464 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
92b18d1c BC |
2465 | }; |
2466 | ||
3b54baad BC |
2467 | /* i2c4 slave ports */ |
2468 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | |
2469 | &omap44xx_l4_per__i2c4, | |
92b18d1c BC |
2470 | }; |
2471 | ||
3b54baad BC |
2472 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
2473 | .name = "i2c4", | |
2474 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2475 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2476 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2477 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 2478 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 2479 | .main_clk = "i2c4_fck", |
92b18d1c BC |
2480 | .prcm = { |
2481 | .omap4 = { | |
d0f0631d | 2482 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 2483 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 2484 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
2485 | }, |
2486 | }, | |
3b54baad BC |
2487 | .slaves = omap44xx_i2c4_slaves, |
2488 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | |
4d4441a6 | 2489 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
2490 | }; |
2491 | ||
407a6888 BC |
2492 | /* |
2493 | * 'ipu' class | |
2494 | * imaging processor unit | |
2495 | */ | |
2496 | ||
2497 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
2498 | .name = "ipu", | |
2499 | }; | |
2500 | ||
2501 | /* ipu */ | |
2502 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
2503 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2504 | { .irq = -1 } |
407a6888 BC |
2505 | }; |
2506 | ||
2507 | static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { | |
2508 | { .name = "cpu0", .rst_shift = 0 }, | |
2509 | }; | |
2510 | ||
2511 | static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { | |
2512 | { .name = "cpu1", .rst_shift = 1 }, | |
2513 | }; | |
2514 | ||
2515 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { | |
2516 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2517 | }; | |
2518 | ||
2519 | /* ipu master ports */ | |
2520 | static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { | |
2521 | &omap44xx_ipu__l3_main_2, | |
2522 | }; | |
2523 | ||
2524 | /* l3_main_2 -> ipu */ | |
2525 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
2526 | .master = &omap44xx_l3_main_2_hwmod, | |
2527 | .slave = &omap44xx_ipu_hwmod, | |
2528 | .clk = "l3_div_ck", | |
2529 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2530 | }; | |
2531 | ||
2532 | /* ipu slave ports */ | |
2533 | static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { | |
2534 | &omap44xx_l3_main_2__ipu, | |
2535 | }; | |
2536 | ||
2537 | /* Pseudo hwmod for reset control purpose only */ | |
2538 | static struct omap_hwmod omap44xx_ipu_c0_hwmod = { | |
2539 | .name = "ipu_c0", | |
2540 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2541 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
2542 | .flags = HWMOD_INIT_NO_RESET, |
2543 | .rst_lines = omap44xx_ipu_c0_resets, | |
2544 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), | |
00fe610b | 2545 | .prcm = { |
407a6888 | 2546 | .omap4 = { |
eaac329d | 2547 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
407a6888 BC |
2548 | }, |
2549 | }, | |
407a6888 BC |
2550 | }; |
2551 | ||
2552 | /* Pseudo hwmod for reset control purpose only */ | |
2553 | static struct omap_hwmod omap44xx_ipu_c1_hwmod = { | |
2554 | .name = "ipu_c1", | |
2555 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2556 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
2557 | .flags = HWMOD_INIT_NO_RESET, |
2558 | .rst_lines = omap44xx_ipu_c1_resets, | |
2559 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), | |
00fe610b | 2560 | .prcm = { |
407a6888 | 2561 | .omap4 = { |
eaac329d | 2562 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
407a6888 BC |
2563 | }, |
2564 | }, | |
407a6888 BC |
2565 | }; |
2566 | ||
2567 | static struct omap_hwmod omap44xx_ipu_hwmod = { | |
2568 | .name = "ipu", | |
2569 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2570 | .clkdm_name = "ducati_clkdm", |
407a6888 | 2571 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
2572 | .rst_lines = omap44xx_ipu_resets, |
2573 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
2574 | .main_clk = "ipu_fck", | |
00fe610b | 2575 | .prcm = { |
407a6888 | 2576 | .omap4 = { |
d0f0631d | 2577 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 2578 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 2579 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 2580 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
2581 | }, |
2582 | }, | |
2583 | .slaves = omap44xx_ipu_slaves, | |
2584 | .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), | |
2585 | .masters = omap44xx_ipu_masters, | |
2586 | .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), | |
407a6888 BC |
2587 | }; |
2588 | ||
2589 | /* | |
2590 | * 'iss' class | |
2591 | * external images sensor pixel data processor | |
2592 | */ | |
2593 | ||
2594 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
2595 | .rev_offs = 0x0000, | |
2596 | .sysc_offs = 0x0010, | |
2597 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
2598 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2599 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2600 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2601 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2602 | .sysc_fields = &omap_hwmod_sysc_type2, |
2603 | }; | |
2604 | ||
2605 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
2606 | .name = "iss", | |
2607 | .sysc = &omap44xx_iss_sysc, | |
2608 | }; | |
2609 | ||
2610 | /* iss */ | |
2611 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
2612 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2613 | { .irq = -1 } |
407a6888 BC |
2614 | }; |
2615 | ||
2616 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
2617 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
2618 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
2619 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
2620 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2621 | { .dma_req = -1 } |
407a6888 BC |
2622 | }; |
2623 | ||
2624 | /* iss master ports */ | |
2625 | static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { | |
2626 | &omap44xx_iss__l3_main_2, | |
2627 | }; | |
2628 | ||
2629 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
2630 | { | |
2631 | .pa_start = 0x52000000, | |
2632 | .pa_end = 0x520000ff, | |
2633 | .flags = ADDR_TYPE_RT | |
2634 | }, | |
78183f3f | 2635 | { } |
407a6888 BC |
2636 | }; |
2637 | ||
2638 | /* l3_main_2 -> iss */ | |
2639 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
2640 | .master = &omap44xx_l3_main_2_hwmod, | |
2641 | .slave = &omap44xx_iss_hwmod, | |
2642 | .clk = "l3_div_ck", | |
2643 | .addr = omap44xx_iss_addrs, | |
407a6888 BC |
2644 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2645 | }; | |
2646 | ||
2647 | /* iss slave ports */ | |
2648 | static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { | |
2649 | &omap44xx_l3_main_2__iss, | |
2650 | }; | |
2651 | ||
2652 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { | |
2653 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
2654 | }; | |
2655 | ||
2656 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
2657 | .name = "iss", | |
2658 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 2659 | .clkdm_name = "iss_clkdm", |
407a6888 | 2660 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 2661 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 2662 | .main_clk = "iss_fck", |
00fe610b | 2663 | .prcm = { |
407a6888 | 2664 | .omap4 = { |
d0f0631d | 2665 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 2666 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 2667 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2668 | }, |
2669 | }, | |
2670 | .opt_clks = iss_opt_clks, | |
2671 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
2672 | .slaves = omap44xx_iss_slaves, | |
2673 | .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), | |
2674 | .masters = omap44xx_iss_masters, | |
2675 | .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), | |
407a6888 BC |
2676 | }; |
2677 | ||
8f25bdc5 BC |
2678 | /* |
2679 | * 'iva' class | |
2680 | * multi-standard video encoder/decoder hardware accelerator | |
2681 | */ | |
2682 | ||
2683 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 2684 | .name = "iva", |
8f25bdc5 BC |
2685 | }; |
2686 | ||
2687 | /* iva */ | |
2688 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
2689 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
2690 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
2691 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2692 | { .irq = -1 } |
8f25bdc5 BC |
2693 | }; |
2694 | ||
2695 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
2696 | { .name = "logic", .rst_shift = 2 }, | |
2697 | }; | |
2698 | ||
2699 | static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { | |
2700 | { .name = "seq0", .rst_shift = 0 }, | |
2701 | }; | |
2702 | ||
2703 | static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { | |
2704 | { .name = "seq1", .rst_shift = 1 }, | |
2705 | }; | |
2706 | ||
2707 | /* iva master ports */ | |
2708 | static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { | |
2709 | &omap44xx_iva__l3_main_2, | |
2710 | &omap44xx_iva__l3_instr, | |
2711 | }; | |
2712 | ||
2713 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { | |
2714 | { | |
2715 | .pa_start = 0x5a000000, | |
2716 | .pa_end = 0x5a07ffff, | |
2717 | .flags = ADDR_TYPE_RT | |
2718 | }, | |
78183f3f | 2719 | { } |
8f25bdc5 BC |
2720 | }; |
2721 | ||
2722 | /* l3_main_2 -> iva */ | |
2723 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
2724 | .master = &omap44xx_l3_main_2_hwmod, | |
2725 | .slave = &omap44xx_iva_hwmod, | |
2726 | .clk = "l3_div_ck", | |
2727 | .addr = omap44xx_iva_addrs, | |
8f25bdc5 BC |
2728 | .user = OCP_USER_MPU, |
2729 | }; | |
2730 | ||
2731 | /* iva slave ports */ | |
2732 | static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { | |
2733 | &omap44xx_dsp__iva, | |
2734 | &omap44xx_l3_main_2__iva, | |
2735 | }; | |
2736 | ||
2737 | /* Pseudo hwmod for reset control purpose only */ | |
2738 | static struct omap_hwmod omap44xx_iva_seq0_hwmod = { | |
2739 | .name = "iva_seq0", | |
2740 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2741 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
2742 | .flags = HWMOD_INIT_NO_RESET, |
2743 | .rst_lines = omap44xx_iva_seq0_resets, | |
2744 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), | |
2745 | .prcm = { | |
2746 | .omap4 = { | |
eaac329d | 2747 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
8f25bdc5 BC |
2748 | }, |
2749 | }, | |
8f25bdc5 BC |
2750 | }; |
2751 | ||
2752 | /* Pseudo hwmod for reset control purpose only */ | |
2753 | static struct omap_hwmod omap44xx_iva_seq1_hwmod = { | |
2754 | .name = "iva_seq1", | |
2755 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2756 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
2757 | .flags = HWMOD_INIT_NO_RESET, |
2758 | .rst_lines = omap44xx_iva_seq1_resets, | |
2759 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), | |
2760 | .prcm = { | |
2761 | .omap4 = { | |
eaac329d | 2762 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
8f25bdc5 BC |
2763 | }, |
2764 | }, | |
8f25bdc5 BC |
2765 | }; |
2766 | ||
2767 | static struct omap_hwmod omap44xx_iva_hwmod = { | |
2768 | .name = "iva", | |
2769 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2770 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 2771 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
2772 | .rst_lines = omap44xx_iva_resets, |
2773 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
2774 | .main_clk = "iva_fck", | |
2775 | .prcm = { | |
2776 | .omap4 = { | |
d0f0631d | 2777 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 2778 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 2779 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 2780 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
2781 | }, |
2782 | }, | |
2783 | .slaves = omap44xx_iva_slaves, | |
2784 | .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), | |
2785 | .masters = omap44xx_iva_masters, | |
2786 | .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), | |
8f25bdc5 BC |
2787 | }; |
2788 | ||
407a6888 BC |
2789 | /* |
2790 | * 'kbd' class | |
2791 | * keyboard controller | |
2792 | */ | |
2793 | ||
2794 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
2795 | .rev_offs = 0x0000, | |
2796 | .sysc_offs = 0x0010, | |
2797 | .syss_offs = 0x0014, | |
2798 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2799 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2800 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2801 | SYSS_HAS_RESET_STATUS), | |
2802 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2803 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2804 | }; | |
2805 | ||
2806 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
2807 | .name = "kbd", | |
2808 | .sysc = &omap44xx_kbd_sysc, | |
2809 | }; | |
2810 | ||
2811 | /* kbd */ | |
2812 | static struct omap_hwmod omap44xx_kbd_hwmod; | |
2813 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { | |
2814 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2815 | { .irq = -1 } |
407a6888 BC |
2816 | }; |
2817 | ||
2818 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
2819 | { | |
2820 | .pa_start = 0x4a31c000, | |
2821 | .pa_end = 0x4a31c07f, | |
2822 | .flags = ADDR_TYPE_RT | |
2823 | }, | |
78183f3f | 2824 | { } |
407a6888 BC |
2825 | }; |
2826 | ||
2827 | /* l4_wkup -> kbd */ | |
2828 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
2829 | .master = &omap44xx_l4_wkup_hwmod, | |
2830 | .slave = &omap44xx_kbd_hwmod, | |
2831 | .clk = "l4_wkup_clk_mux_ck", | |
2832 | .addr = omap44xx_kbd_addrs, | |
407a6888 BC |
2833 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2834 | }; | |
2835 | ||
2836 | /* kbd slave ports */ | |
2837 | static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { | |
2838 | &omap44xx_l4_wkup__kbd, | |
2839 | }; | |
2840 | ||
2841 | static struct omap_hwmod omap44xx_kbd_hwmod = { | |
2842 | .name = "kbd", | |
2843 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 2844 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 2845 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 2846 | .main_clk = "kbd_fck", |
00fe610b | 2847 | .prcm = { |
407a6888 | 2848 | .omap4 = { |
d0f0631d | 2849 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 2850 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 2851 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2852 | }, |
2853 | }, | |
2854 | .slaves = omap44xx_kbd_slaves, | |
2855 | .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), | |
407a6888 BC |
2856 | }; |
2857 | ||
ec5df927 BC |
2858 | /* |
2859 | * 'mailbox' class | |
2860 | * mailbox module allowing communication between the on-chip processors using a | |
2861 | * queued mailbox-interrupt mechanism. | |
2862 | */ | |
2863 | ||
2864 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
2865 | .rev_offs = 0x0000, | |
2866 | .sysc_offs = 0x0010, | |
2867 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2868 | SYSC_HAS_SOFTRESET), | |
2869 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2870 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2871 | }; | |
2872 | ||
2873 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
2874 | .name = "mailbox", | |
2875 | .sysc = &omap44xx_mailbox_sysc, | |
2876 | }; | |
2877 | ||
2878 | /* mailbox */ | |
2879 | static struct omap_hwmod omap44xx_mailbox_hwmod; | |
2880 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { | |
2881 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2882 | { .irq = -1 } |
ec5df927 BC |
2883 | }; |
2884 | ||
2885 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
2886 | { | |
2887 | .pa_start = 0x4a0f4000, | |
2888 | .pa_end = 0x4a0f41ff, | |
2889 | .flags = ADDR_TYPE_RT | |
2890 | }, | |
78183f3f | 2891 | { } |
ec5df927 BC |
2892 | }; |
2893 | ||
2894 | /* l4_cfg -> mailbox */ | |
2895 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
2896 | .master = &omap44xx_l4_cfg_hwmod, | |
2897 | .slave = &omap44xx_mailbox_hwmod, | |
2898 | .clk = "l4_div_ck", | |
2899 | .addr = omap44xx_mailbox_addrs, | |
ec5df927 BC |
2900 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2901 | }; | |
2902 | ||
2903 | /* mailbox slave ports */ | |
2904 | static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { | |
2905 | &omap44xx_l4_cfg__mailbox, | |
2906 | }; | |
2907 | ||
2908 | static struct omap_hwmod omap44xx_mailbox_hwmod = { | |
2909 | .name = "mailbox", | |
2910 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 2911 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 2912 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 2913 | .prcm = { |
ec5df927 | 2914 | .omap4 = { |
d0f0631d | 2915 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 2916 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
2917 | }, |
2918 | }, | |
2919 | .slaves = omap44xx_mailbox_slaves, | |
2920 | .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), | |
ec5df927 BC |
2921 | }; |
2922 | ||
4ddff493 BC |
2923 | /* |
2924 | * 'mcbsp' class | |
2925 | * multi channel buffered serial port controller | |
2926 | */ | |
2927 | ||
2928 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
2929 | .sysc_offs = 0x008c, | |
2930 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
2931 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2932 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2933 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2934 | }; | |
2935 | ||
2936 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
2937 | .name = "mcbsp", | |
2938 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 2939 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
2940 | }; |
2941 | ||
2942 | /* mcbsp1 */ | |
2943 | static struct omap_hwmod omap44xx_mcbsp1_hwmod; | |
2944 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { | |
2945 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2946 | { .irq = -1 } |
4ddff493 BC |
2947 | }; |
2948 | ||
2949 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
2950 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
2951 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2952 | { .dma_req = -1 } |
4ddff493 BC |
2953 | }; |
2954 | ||
2955 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { | |
2956 | { | |
cb7e9ded | 2957 | .name = "mpu", |
4ddff493 BC |
2958 | .pa_start = 0x40122000, |
2959 | .pa_end = 0x401220ff, | |
2960 | .flags = ADDR_TYPE_RT | |
2961 | }, | |
78183f3f | 2962 | { } |
4ddff493 BC |
2963 | }; |
2964 | ||
2965 | /* l4_abe -> mcbsp1 */ | |
2966 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
2967 | .master = &omap44xx_l4_abe_hwmod, | |
2968 | .slave = &omap44xx_mcbsp1_hwmod, | |
2969 | .clk = "ocp_abe_iclk", | |
2970 | .addr = omap44xx_mcbsp1_addrs, | |
4ddff493 BC |
2971 | .user = OCP_USER_MPU, |
2972 | }; | |
2973 | ||
2974 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
2975 | { | |
cb7e9ded | 2976 | .name = "dma", |
4ddff493 BC |
2977 | .pa_start = 0x49022000, |
2978 | .pa_end = 0x490220ff, | |
2979 | .flags = ADDR_TYPE_RT | |
2980 | }, | |
78183f3f | 2981 | { } |
4ddff493 BC |
2982 | }; |
2983 | ||
2984 | /* l4_abe -> mcbsp1 (dma) */ | |
2985 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
2986 | .master = &omap44xx_l4_abe_hwmod, | |
2987 | .slave = &omap44xx_mcbsp1_hwmod, | |
2988 | .clk = "ocp_abe_iclk", | |
2989 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4ddff493 BC |
2990 | .user = OCP_USER_SDMA, |
2991 | }; | |
2992 | ||
2993 | /* mcbsp1 slave ports */ | |
2994 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { | |
2995 | &omap44xx_l4_abe__mcbsp1, | |
2996 | &omap44xx_l4_abe__mcbsp1_dma, | |
2997 | }; | |
2998 | ||
2999 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |
3000 | .name = "mcbsp1", | |
3001 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3002 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3003 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 3004 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
3005 | .main_clk = "mcbsp1_fck", |
3006 | .prcm = { | |
3007 | .omap4 = { | |
d0f0631d | 3008 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 3009 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 3010 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3011 | }, |
3012 | }, | |
3013 | .slaves = omap44xx_mcbsp1_slaves, | |
3014 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), | |
4ddff493 BC |
3015 | }; |
3016 | ||
3017 | /* mcbsp2 */ | |
3018 | static struct omap_hwmod omap44xx_mcbsp2_hwmod; | |
3019 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { | |
3020 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3021 | { .irq = -1 } |
4ddff493 BC |
3022 | }; |
3023 | ||
3024 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
3025 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
3026 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3027 | { .dma_req = -1 } |
4ddff493 BC |
3028 | }; |
3029 | ||
3030 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
3031 | { | |
cb7e9ded | 3032 | .name = "mpu", |
4ddff493 BC |
3033 | .pa_start = 0x40124000, |
3034 | .pa_end = 0x401240ff, | |
3035 | .flags = ADDR_TYPE_RT | |
3036 | }, | |
78183f3f | 3037 | { } |
4ddff493 BC |
3038 | }; |
3039 | ||
3040 | /* l4_abe -> mcbsp2 */ | |
3041 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
3042 | .master = &omap44xx_l4_abe_hwmod, | |
3043 | .slave = &omap44xx_mcbsp2_hwmod, | |
3044 | .clk = "ocp_abe_iclk", | |
3045 | .addr = omap44xx_mcbsp2_addrs, | |
4ddff493 BC |
3046 | .user = OCP_USER_MPU, |
3047 | }; | |
3048 | ||
3049 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
3050 | { | |
cb7e9ded | 3051 | .name = "dma", |
4ddff493 BC |
3052 | .pa_start = 0x49024000, |
3053 | .pa_end = 0x490240ff, | |
3054 | .flags = ADDR_TYPE_RT | |
3055 | }, | |
78183f3f | 3056 | { } |
4ddff493 BC |
3057 | }; |
3058 | ||
3059 | /* l4_abe -> mcbsp2 (dma) */ | |
3060 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
3061 | .master = &omap44xx_l4_abe_hwmod, | |
3062 | .slave = &omap44xx_mcbsp2_hwmod, | |
3063 | .clk = "ocp_abe_iclk", | |
3064 | .addr = omap44xx_mcbsp2_dma_addrs, | |
4ddff493 BC |
3065 | .user = OCP_USER_SDMA, |
3066 | }; | |
3067 | ||
3068 | /* mcbsp2 slave ports */ | |
3069 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { | |
3070 | &omap44xx_l4_abe__mcbsp2, | |
3071 | &omap44xx_l4_abe__mcbsp2_dma, | |
3072 | }; | |
3073 | ||
3074 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |
3075 | .name = "mcbsp2", | |
3076 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3077 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3078 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 3079 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
3080 | .main_clk = "mcbsp2_fck", |
3081 | .prcm = { | |
3082 | .omap4 = { | |
d0f0631d | 3083 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 3084 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 3085 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3086 | }, |
3087 | }, | |
3088 | .slaves = omap44xx_mcbsp2_slaves, | |
3089 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), | |
4ddff493 BC |
3090 | }; |
3091 | ||
3092 | /* mcbsp3 */ | |
3093 | static struct omap_hwmod omap44xx_mcbsp3_hwmod; | |
3094 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { | |
3095 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3096 | { .irq = -1 } |
4ddff493 BC |
3097 | }; |
3098 | ||
3099 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
3100 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
3101 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3102 | { .dma_req = -1 } |
4ddff493 BC |
3103 | }; |
3104 | ||
3105 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
3106 | { | |
cb7e9ded | 3107 | .name = "mpu", |
4ddff493 BC |
3108 | .pa_start = 0x40126000, |
3109 | .pa_end = 0x401260ff, | |
3110 | .flags = ADDR_TYPE_RT | |
3111 | }, | |
78183f3f | 3112 | { } |
4ddff493 BC |
3113 | }; |
3114 | ||
3115 | /* l4_abe -> mcbsp3 */ | |
3116 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
3117 | .master = &omap44xx_l4_abe_hwmod, | |
3118 | .slave = &omap44xx_mcbsp3_hwmod, | |
3119 | .clk = "ocp_abe_iclk", | |
3120 | .addr = omap44xx_mcbsp3_addrs, | |
4ddff493 BC |
3121 | .user = OCP_USER_MPU, |
3122 | }; | |
3123 | ||
3124 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
3125 | { | |
cb7e9ded | 3126 | .name = "dma", |
4ddff493 BC |
3127 | .pa_start = 0x49026000, |
3128 | .pa_end = 0x490260ff, | |
3129 | .flags = ADDR_TYPE_RT | |
3130 | }, | |
78183f3f | 3131 | { } |
4ddff493 BC |
3132 | }; |
3133 | ||
3134 | /* l4_abe -> mcbsp3 (dma) */ | |
3135 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
3136 | .master = &omap44xx_l4_abe_hwmod, | |
3137 | .slave = &omap44xx_mcbsp3_hwmod, | |
3138 | .clk = "ocp_abe_iclk", | |
3139 | .addr = omap44xx_mcbsp3_dma_addrs, | |
4ddff493 BC |
3140 | .user = OCP_USER_SDMA, |
3141 | }; | |
3142 | ||
3143 | /* mcbsp3 slave ports */ | |
3144 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { | |
3145 | &omap44xx_l4_abe__mcbsp3, | |
3146 | &omap44xx_l4_abe__mcbsp3_dma, | |
3147 | }; | |
3148 | ||
3149 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |
3150 | .name = "mcbsp3", | |
3151 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3152 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3153 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 3154 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
3155 | .main_clk = "mcbsp3_fck", |
3156 | .prcm = { | |
3157 | .omap4 = { | |
d0f0631d | 3158 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 3159 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 3160 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3161 | }, |
3162 | }, | |
3163 | .slaves = omap44xx_mcbsp3_slaves, | |
3164 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), | |
4ddff493 BC |
3165 | }; |
3166 | ||
3167 | /* mcbsp4 */ | |
3168 | static struct omap_hwmod omap44xx_mcbsp4_hwmod; | |
3169 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { | |
3170 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3171 | { .irq = -1 } |
4ddff493 BC |
3172 | }; |
3173 | ||
3174 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
3175 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
3176 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3177 | { .dma_req = -1 } |
4ddff493 BC |
3178 | }; |
3179 | ||
3180 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
3181 | { | |
3182 | .pa_start = 0x48096000, | |
3183 | .pa_end = 0x480960ff, | |
3184 | .flags = ADDR_TYPE_RT | |
3185 | }, | |
78183f3f | 3186 | { } |
4ddff493 BC |
3187 | }; |
3188 | ||
3189 | /* l4_per -> mcbsp4 */ | |
3190 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
3191 | .master = &omap44xx_l4_per_hwmod, | |
3192 | .slave = &omap44xx_mcbsp4_hwmod, | |
3193 | .clk = "l4_div_ck", | |
3194 | .addr = omap44xx_mcbsp4_addrs, | |
4ddff493 BC |
3195 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3196 | }; | |
3197 | ||
3198 | /* mcbsp4 slave ports */ | |
3199 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { | |
3200 | &omap44xx_l4_per__mcbsp4, | |
3201 | }; | |
3202 | ||
3203 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { | |
3204 | .name = "mcbsp4", | |
3205 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3206 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 3207 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 3208 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
3209 | .main_clk = "mcbsp4_fck", |
3210 | .prcm = { | |
3211 | .omap4 = { | |
d0f0631d | 3212 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 3213 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 3214 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3215 | }, |
3216 | }, | |
3217 | .slaves = omap44xx_mcbsp4_slaves, | |
3218 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), | |
4ddff493 BC |
3219 | }; |
3220 | ||
407a6888 BC |
3221 | /* |
3222 | * 'mcpdm' class | |
3223 | * multi channel pdm controller (proprietary interface with phoenix power | |
3224 | * ic) | |
3225 | */ | |
3226 | ||
3227 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
3228 | .rev_offs = 0x0000, | |
3229 | .sysc_offs = 0x0010, | |
3230 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3231 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3232 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3233 | SIDLE_SMART_WKUP), | |
3234 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3235 | }; | |
3236 | ||
3237 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
3238 | .name = "mcpdm", | |
3239 | .sysc = &omap44xx_mcpdm_sysc, | |
3240 | }; | |
3241 | ||
3242 | /* mcpdm */ | |
3243 | static struct omap_hwmod omap44xx_mcpdm_hwmod; | |
3244 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { | |
3245 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3246 | { .irq = -1 } |
407a6888 BC |
3247 | }; |
3248 | ||
3249 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
3250 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
3251 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3252 | { .dma_req = -1 } |
407a6888 BC |
3253 | }; |
3254 | ||
3255 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
3256 | { | |
3257 | .pa_start = 0x40132000, | |
3258 | .pa_end = 0x4013207f, | |
3259 | .flags = ADDR_TYPE_RT | |
3260 | }, | |
78183f3f | 3261 | { } |
407a6888 BC |
3262 | }; |
3263 | ||
3264 | /* l4_abe -> mcpdm */ | |
3265 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
3266 | .master = &omap44xx_l4_abe_hwmod, | |
3267 | .slave = &omap44xx_mcpdm_hwmod, | |
3268 | .clk = "ocp_abe_iclk", | |
3269 | .addr = omap44xx_mcpdm_addrs, | |
407a6888 BC |
3270 | .user = OCP_USER_MPU, |
3271 | }; | |
3272 | ||
3273 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
3274 | { | |
3275 | .pa_start = 0x49032000, | |
3276 | .pa_end = 0x4903207f, | |
3277 | .flags = ADDR_TYPE_RT | |
3278 | }, | |
78183f3f | 3279 | { } |
407a6888 BC |
3280 | }; |
3281 | ||
3282 | /* l4_abe -> mcpdm (dma) */ | |
3283 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
3284 | .master = &omap44xx_l4_abe_hwmod, | |
3285 | .slave = &omap44xx_mcpdm_hwmod, | |
3286 | .clk = "ocp_abe_iclk", | |
3287 | .addr = omap44xx_mcpdm_dma_addrs, | |
407a6888 BC |
3288 | .user = OCP_USER_SDMA, |
3289 | }; | |
3290 | ||
3291 | /* mcpdm slave ports */ | |
3292 | static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { | |
3293 | &omap44xx_l4_abe__mcpdm, | |
3294 | &omap44xx_l4_abe__mcpdm_dma, | |
3295 | }; | |
3296 | ||
3297 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |
3298 | .name = "mcpdm", | |
3299 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 3300 | .clkdm_name = "abe_clkdm", |
407a6888 | 3301 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 3302 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 3303 | .main_clk = "mcpdm_fck", |
00fe610b | 3304 | .prcm = { |
407a6888 | 3305 | .omap4 = { |
d0f0631d | 3306 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 3307 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 3308 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3309 | }, |
3310 | }, | |
3311 | .slaves = omap44xx_mcpdm_slaves, | |
3312 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), | |
407a6888 BC |
3313 | }; |
3314 | ||
9bcbd7f0 BC |
3315 | /* |
3316 | * 'mcspi' class | |
3317 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
3318 | * bus | |
3319 | */ | |
3320 | ||
3321 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
3322 | .rev_offs = 0x0000, | |
3323 | .sysc_offs = 0x0010, | |
3324 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3325 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3326 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3327 | SIDLE_SMART_WKUP), | |
3328 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3329 | }; | |
3330 | ||
3331 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
3332 | .name = "mcspi", | |
3333 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 3334 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
3335 | }; |
3336 | ||
3337 | /* mcspi1 */ | |
3338 | static struct omap_hwmod omap44xx_mcspi1_hwmod; | |
3339 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { | |
3340 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3341 | { .irq = -1 } |
9bcbd7f0 BC |
3342 | }; |
3343 | ||
3344 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
3345 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
3346 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
3347 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
3348 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
3349 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
3350 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
3351 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
3352 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3353 | { .dma_req = -1 } |
9bcbd7f0 BC |
3354 | }; |
3355 | ||
3356 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
3357 | { | |
3358 | .pa_start = 0x48098000, | |
3359 | .pa_end = 0x480981ff, | |
3360 | .flags = ADDR_TYPE_RT | |
3361 | }, | |
78183f3f | 3362 | { } |
9bcbd7f0 BC |
3363 | }; |
3364 | ||
3365 | /* l4_per -> mcspi1 */ | |
3366 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
3367 | .master = &omap44xx_l4_per_hwmod, | |
3368 | .slave = &omap44xx_mcspi1_hwmod, | |
3369 | .clk = "l4_div_ck", | |
3370 | .addr = omap44xx_mcspi1_addrs, | |
9bcbd7f0 BC |
3371 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3372 | }; | |
3373 | ||
3374 | /* mcspi1 slave ports */ | |
3375 | static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { | |
3376 | &omap44xx_l4_per__mcspi1, | |
3377 | }; | |
3378 | ||
905a74d9 BC |
3379 | /* mcspi1 dev_attr */ |
3380 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
3381 | .num_chipselect = 4, | |
3382 | }; | |
3383 | ||
9bcbd7f0 BC |
3384 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
3385 | .name = "mcspi1", | |
3386 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3387 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3388 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 3389 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
3390 | .main_clk = "mcspi1_fck", |
3391 | .prcm = { | |
3392 | .omap4 = { | |
d0f0631d | 3393 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 3394 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 3395 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3396 | }, |
3397 | }, | |
905a74d9 | 3398 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
3399 | .slaves = omap44xx_mcspi1_slaves, |
3400 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), | |
9bcbd7f0 BC |
3401 | }; |
3402 | ||
3403 | /* mcspi2 */ | |
3404 | static struct omap_hwmod omap44xx_mcspi2_hwmod; | |
3405 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { | |
3406 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3407 | { .irq = -1 } |
9bcbd7f0 BC |
3408 | }; |
3409 | ||
3410 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
3411 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
3412 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
3413 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
3414 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3415 | { .dma_req = -1 } |
9bcbd7f0 BC |
3416 | }; |
3417 | ||
3418 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
3419 | { | |
3420 | .pa_start = 0x4809a000, | |
3421 | .pa_end = 0x4809a1ff, | |
3422 | .flags = ADDR_TYPE_RT | |
3423 | }, | |
78183f3f | 3424 | { } |
9bcbd7f0 BC |
3425 | }; |
3426 | ||
3427 | /* l4_per -> mcspi2 */ | |
3428 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
3429 | .master = &omap44xx_l4_per_hwmod, | |
3430 | .slave = &omap44xx_mcspi2_hwmod, | |
3431 | .clk = "l4_div_ck", | |
3432 | .addr = omap44xx_mcspi2_addrs, | |
9bcbd7f0 BC |
3433 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3434 | }; | |
3435 | ||
3436 | /* mcspi2 slave ports */ | |
3437 | static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { | |
3438 | &omap44xx_l4_per__mcspi2, | |
3439 | }; | |
3440 | ||
905a74d9 BC |
3441 | /* mcspi2 dev_attr */ |
3442 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
3443 | .num_chipselect = 2, | |
3444 | }; | |
3445 | ||
9bcbd7f0 BC |
3446 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
3447 | .name = "mcspi2", | |
3448 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3449 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3450 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 3451 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
3452 | .main_clk = "mcspi2_fck", |
3453 | .prcm = { | |
3454 | .omap4 = { | |
d0f0631d | 3455 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 3456 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 3457 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3458 | }, |
3459 | }, | |
905a74d9 | 3460 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
3461 | .slaves = omap44xx_mcspi2_slaves, |
3462 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), | |
9bcbd7f0 BC |
3463 | }; |
3464 | ||
3465 | /* mcspi3 */ | |
3466 | static struct omap_hwmod omap44xx_mcspi3_hwmod; | |
3467 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { | |
3468 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3469 | { .irq = -1 } |
9bcbd7f0 BC |
3470 | }; |
3471 | ||
3472 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
3473 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
3474 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
3475 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
3476 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3477 | { .dma_req = -1 } |
9bcbd7f0 BC |
3478 | }; |
3479 | ||
3480 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
3481 | { | |
3482 | .pa_start = 0x480b8000, | |
3483 | .pa_end = 0x480b81ff, | |
3484 | .flags = ADDR_TYPE_RT | |
3485 | }, | |
78183f3f | 3486 | { } |
9bcbd7f0 BC |
3487 | }; |
3488 | ||
3489 | /* l4_per -> mcspi3 */ | |
3490 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
3491 | .master = &omap44xx_l4_per_hwmod, | |
3492 | .slave = &omap44xx_mcspi3_hwmod, | |
3493 | .clk = "l4_div_ck", | |
3494 | .addr = omap44xx_mcspi3_addrs, | |
9bcbd7f0 BC |
3495 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3496 | }; | |
3497 | ||
3498 | /* mcspi3 slave ports */ | |
3499 | static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { | |
3500 | &omap44xx_l4_per__mcspi3, | |
3501 | }; | |
3502 | ||
905a74d9 BC |
3503 | /* mcspi3 dev_attr */ |
3504 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
3505 | .num_chipselect = 2, | |
3506 | }; | |
3507 | ||
9bcbd7f0 BC |
3508 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
3509 | .name = "mcspi3", | |
3510 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3511 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3512 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 3513 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
3514 | .main_clk = "mcspi3_fck", |
3515 | .prcm = { | |
3516 | .omap4 = { | |
d0f0631d | 3517 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 3518 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 3519 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3520 | }, |
3521 | }, | |
905a74d9 | 3522 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
3523 | .slaves = omap44xx_mcspi3_slaves, |
3524 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), | |
9bcbd7f0 BC |
3525 | }; |
3526 | ||
3527 | /* mcspi4 */ | |
3528 | static struct omap_hwmod omap44xx_mcspi4_hwmod; | |
3529 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { | |
3530 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3531 | { .irq = -1 } |
9bcbd7f0 BC |
3532 | }; |
3533 | ||
3534 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
3535 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
3536 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3537 | { .dma_req = -1 } |
9bcbd7f0 BC |
3538 | }; |
3539 | ||
3540 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
3541 | { | |
3542 | .pa_start = 0x480ba000, | |
3543 | .pa_end = 0x480ba1ff, | |
3544 | .flags = ADDR_TYPE_RT | |
3545 | }, | |
78183f3f | 3546 | { } |
9bcbd7f0 BC |
3547 | }; |
3548 | ||
3549 | /* l4_per -> mcspi4 */ | |
3550 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
3551 | .master = &omap44xx_l4_per_hwmod, | |
3552 | .slave = &omap44xx_mcspi4_hwmod, | |
3553 | .clk = "l4_div_ck", | |
3554 | .addr = omap44xx_mcspi4_addrs, | |
9bcbd7f0 BC |
3555 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3556 | }; | |
3557 | ||
3558 | /* mcspi4 slave ports */ | |
3559 | static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { | |
3560 | &omap44xx_l4_per__mcspi4, | |
3561 | }; | |
3562 | ||
905a74d9 BC |
3563 | /* mcspi4 dev_attr */ |
3564 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
3565 | .num_chipselect = 1, | |
3566 | }; | |
3567 | ||
9bcbd7f0 BC |
3568 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
3569 | .name = "mcspi4", | |
3570 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3571 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3572 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 3573 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
3574 | .main_clk = "mcspi4_fck", |
3575 | .prcm = { | |
3576 | .omap4 = { | |
d0f0631d | 3577 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 3578 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 3579 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3580 | }, |
3581 | }, | |
905a74d9 | 3582 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
3583 | .slaves = omap44xx_mcspi4_slaves, |
3584 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), | |
9bcbd7f0 BC |
3585 | }; |
3586 | ||
407a6888 BC |
3587 | /* |
3588 | * 'mmc' class | |
3589 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
3590 | */ | |
3591 | ||
3592 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
3593 | .rev_offs = 0x0000, | |
3594 | .sysc_offs = 0x0010, | |
3595 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
3596 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
3597 | SYSC_HAS_SOFTRESET), | |
3598 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3599 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 3600 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
3601 | .sysc_fields = &omap_hwmod_sysc_type2, |
3602 | }; | |
3603 | ||
3604 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
3605 | .name = "mmc", | |
3606 | .sysc = &omap44xx_mmc_sysc, | |
3607 | }; | |
3608 | ||
3609 | /* mmc1 */ | |
3610 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
3611 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3612 | { .irq = -1 } |
407a6888 BC |
3613 | }; |
3614 | ||
3615 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
3616 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
3617 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3618 | { .dma_req = -1 } |
407a6888 BC |
3619 | }; |
3620 | ||
3621 | /* mmc1 master ports */ | |
3622 | static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { | |
3623 | &omap44xx_mmc1__l3_main_1, | |
3624 | }; | |
3625 | ||
3626 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
3627 | { | |
3628 | .pa_start = 0x4809c000, | |
3629 | .pa_end = 0x4809c3ff, | |
3630 | .flags = ADDR_TYPE_RT | |
3631 | }, | |
78183f3f | 3632 | { } |
407a6888 BC |
3633 | }; |
3634 | ||
3635 | /* l4_per -> mmc1 */ | |
3636 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
3637 | .master = &omap44xx_l4_per_hwmod, | |
3638 | .slave = &omap44xx_mmc1_hwmod, | |
3639 | .clk = "l4_div_ck", | |
3640 | .addr = omap44xx_mmc1_addrs, | |
407a6888 BC |
3641 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3642 | }; | |
3643 | ||
3644 | /* mmc1 slave ports */ | |
3645 | static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { | |
3646 | &omap44xx_l4_per__mmc1, | |
3647 | }; | |
3648 | ||
6ab8946f KK |
3649 | /* mmc1 dev_attr */ |
3650 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
3651 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
3652 | }; | |
3653 | ||
407a6888 BC |
3654 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
3655 | .name = "mmc1", | |
3656 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3657 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 3658 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 3659 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 3660 | .main_clk = "mmc1_fck", |
00fe610b | 3661 | .prcm = { |
407a6888 | 3662 | .omap4 = { |
d0f0631d | 3663 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 3664 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 3665 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3666 | }, |
3667 | }, | |
6ab8946f | 3668 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
3669 | .slaves = omap44xx_mmc1_slaves, |
3670 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), | |
3671 | .masters = omap44xx_mmc1_masters, | |
3672 | .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), | |
407a6888 BC |
3673 | }; |
3674 | ||
3675 | /* mmc2 */ | |
3676 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
3677 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3678 | { .irq = -1 } |
407a6888 BC |
3679 | }; |
3680 | ||
3681 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
3682 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
3683 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3684 | { .dma_req = -1 } |
407a6888 BC |
3685 | }; |
3686 | ||
3687 | /* mmc2 master ports */ | |
3688 | static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { | |
3689 | &omap44xx_mmc2__l3_main_1, | |
3690 | }; | |
3691 | ||
3692 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
3693 | { | |
3694 | .pa_start = 0x480b4000, | |
3695 | .pa_end = 0x480b43ff, | |
3696 | .flags = ADDR_TYPE_RT | |
3697 | }, | |
78183f3f | 3698 | { } |
407a6888 BC |
3699 | }; |
3700 | ||
3701 | /* l4_per -> mmc2 */ | |
3702 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
3703 | .master = &omap44xx_l4_per_hwmod, | |
3704 | .slave = &omap44xx_mmc2_hwmod, | |
3705 | .clk = "l4_div_ck", | |
3706 | .addr = omap44xx_mmc2_addrs, | |
407a6888 BC |
3707 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3708 | }; | |
3709 | ||
3710 | /* mmc2 slave ports */ | |
3711 | static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { | |
3712 | &omap44xx_l4_per__mmc2, | |
3713 | }; | |
3714 | ||
3715 | static struct omap_hwmod omap44xx_mmc2_hwmod = { | |
3716 | .name = "mmc2", | |
3717 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3718 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 3719 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 3720 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 3721 | .main_clk = "mmc2_fck", |
00fe610b | 3722 | .prcm = { |
407a6888 | 3723 | .omap4 = { |
d0f0631d | 3724 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 3725 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 3726 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3727 | }, |
3728 | }, | |
3729 | .slaves = omap44xx_mmc2_slaves, | |
3730 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), | |
3731 | .masters = omap44xx_mmc2_masters, | |
3732 | .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), | |
407a6888 BC |
3733 | }; |
3734 | ||
3735 | /* mmc3 */ | |
3736 | static struct omap_hwmod omap44xx_mmc3_hwmod; | |
3737 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { | |
3738 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3739 | { .irq = -1 } |
407a6888 BC |
3740 | }; |
3741 | ||
3742 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
3743 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
3744 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3745 | { .dma_req = -1 } |
407a6888 BC |
3746 | }; |
3747 | ||
3748 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
3749 | { | |
3750 | .pa_start = 0x480ad000, | |
3751 | .pa_end = 0x480ad3ff, | |
3752 | .flags = ADDR_TYPE_RT | |
3753 | }, | |
78183f3f | 3754 | { } |
407a6888 BC |
3755 | }; |
3756 | ||
3757 | /* l4_per -> mmc3 */ | |
3758 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
3759 | .master = &omap44xx_l4_per_hwmod, | |
3760 | .slave = &omap44xx_mmc3_hwmod, | |
3761 | .clk = "l4_div_ck", | |
3762 | .addr = omap44xx_mmc3_addrs, | |
407a6888 BC |
3763 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3764 | }; | |
3765 | ||
3766 | /* mmc3 slave ports */ | |
3767 | static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { | |
3768 | &omap44xx_l4_per__mmc3, | |
3769 | }; | |
3770 | ||
3771 | static struct omap_hwmod omap44xx_mmc3_hwmod = { | |
3772 | .name = "mmc3", | |
3773 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3774 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3775 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 3776 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 3777 | .main_clk = "mmc3_fck", |
00fe610b | 3778 | .prcm = { |
407a6888 | 3779 | .omap4 = { |
d0f0631d | 3780 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 3781 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 3782 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3783 | }, |
3784 | }, | |
3785 | .slaves = omap44xx_mmc3_slaves, | |
3786 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), | |
407a6888 BC |
3787 | }; |
3788 | ||
3789 | /* mmc4 */ | |
3790 | static struct omap_hwmod omap44xx_mmc4_hwmod; | |
3791 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { | |
3792 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3793 | { .irq = -1 } |
407a6888 BC |
3794 | }; |
3795 | ||
3796 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
3797 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
3798 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3799 | { .dma_req = -1 } |
407a6888 BC |
3800 | }; |
3801 | ||
3802 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
3803 | { | |
3804 | .pa_start = 0x480d1000, | |
3805 | .pa_end = 0x480d13ff, | |
3806 | .flags = ADDR_TYPE_RT | |
3807 | }, | |
78183f3f | 3808 | { } |
407a6888 BC |
3809 | }; |
3810 | ||
3811 | /* l4_per -> mmc4 */ | |
3812 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
3813 | .master = &omap44xx_l4_per_hwmod, | |
3814 | .slave = &omap44xx_mmc4_hwmod, | |
3815 | .clk = "l4_div_ck", | |
3816 | .addr = omap44xx_mmc4_addrs, | |
407a6888 BC |
3817 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3818 | }; | |
3819 | ||
3820 | /* mmc4 slave ports */ | |
3821 | static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { | |
3822 | &omap44xx_l4_per__mmc4, | |
3823 | }; | |
3824 | ||
3825 | static struct omap_hwmod omap44xx_mmc4_hwmod = { | |
3826 | .name = "mmc4", | |
3827 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3828 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3829 | .mpu_irqs = omap44xx_mmc4_irqs, |
212738a4 | 3830 | |
407a6888 | 3831 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 3832 | .main_clk = "mmc4_fck", |
00fe610b | 3833 | .prcm = { |
407a6888 | 3834 | .omap4 = { |
d0f0631d | 3835 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 3836 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 3837 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3838 | }, |
3839 | }, | |
3840 | .slaves = omap44xx_mmc4_slaves, | |
3841 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), | |
407a6888 BC |
3842 | }; |
3843 | ||
3844 | /* mmc5 */ | |
3845 | static struct omap_hwmod omap44xx_mmc5_hwmod; | |
3846 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { | |
3847 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3848 | { .irq = -1 } |
407a6888 BC |
3849 | }; |
3850 | ||
3851 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
3852 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
3853 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3854 | { .dma_req = -1 } |
407a6888 BC |
3855 | }; |
3856 | ||
3857 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
3858 | { | |
3859 | .pa_start = 0x480d5000, | |
3860 | .pa_end = 0x480d53ff, | |
3861 | .flags = ADDR_TYPE_RT | |
3862 | }, | |
78183f3f | 3863 | { } |
407a6888 BC |
3864 | }; |
3865 | ||
3866 | /* l4_per -> mmc5 */ | |
3867 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
3868 | .master = &omap44xx_l4_per_hwmod, | |
3869 | .slave = &omap44xx_mmc5_hwmod, | |
3870 | .clk = "l4_div_ck", | |
3871 | .addr = omap44xx_mmc5_addrs, | |
407a6888 BC |
3872 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3873 | }; | |
3874 | ||
3875 | /* mmc5 slave ports */ | |
3876 | static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { | |
3877 | &omap44xx_l4_per__mmc5, | |
3878 | }; | |
3879 | ||
3880 | static struct omap_hwmod omap44xx_mmc5_hwmod = { | |
3881 | .name = "mmc5", | |
3882 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3883 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3884 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 3885 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 3886 | .main_clk = "mmc5_fck", |
00fe610b | 3887 | .prcm = { |
407a6888 | 3888 | .omap4 = { |
d0f0631d | 3889 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 3890 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 3891 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3892 | }, |
3893 | }, | |
3894 | .slaves = omap44xx_mmc5_slaves, | |
3895 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), | |
407a6888 BC |
3896 | }; |
3897 | ||
3b54baad BC |
3898 | /* |
3899 | * 'mpu' class | |
3900 | * mpu sub-system | |
3901 | */ | |
3902 | ||
3903 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 3904 | .name = "mpu", |
db12ba53 BC |
3905 | }; |
3906 | ||
3b54baad BC |
3907 | /* mpu */ |
3908 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
3909 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
3910 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
3911 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3912 | { .irq = -1 } |
db12ba53 BC |
3913 | }; |
3914 | ||
3b54baad BC |
3915 | /* mpu master ports */ |
3916 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { | |
3917 | &omap44xx_mpu__l3_main_1, | |
3918 | &omap44xx_mpu__l4_abe, | |
3919 | &omap44xx_mpu__dmm, | |
3920 | }; | |
3921 | ||
3922 | static struct omap_hwmod omap44xx_mpu_hwmod = { | |
3923 | .name = "mpu", | |
3924 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 3925 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 3926 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3927 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 3928 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
3929 | .prcm = { |
3930 | .omap4 = { | |
d0f0631d | 3931 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 3932 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
3933 | }, |
3934 | }, | |
3b54baad BC |
3935 | .masters = omap44xx_mpu_masters, |
3936 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), | |
db12ba53 BC |
3937 | }; |
3938 | ||
1f6a717f BC |
3939 | /* |
3940 | * 'smartreflex' class | |
3941 | * smartreflex module (monitor silicon performance and outputs a measure of | |
3942 | * performance error) | |
3943 | */ | |
3944 | ||
3945 | /* The IP is not compliant to type1 / type2 scheme */ | |
3946 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
3947 | .sidle_shift = 24, | |
3948 | .enwkup_shift = 26, | |
3949 | }; | |
3950 | ||
3951 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
3952 | .sysc_offs = 0x0038, | |
3953 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
3954 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3955 | SIDLE_SMART_WKUP), | |
3956 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
3957 | }; | |
3958 | ||
3959 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
3960 | .name = "smartreflex", |
3961 | .sysc = &omap44xx_smartreflex_sysc, | |
3962 | .rev = 2, | |
1f6a717f BC |
3963 | }; |
3964 | ||
3965 | /* smartreflex_core */ | |
cea6b942 SG |
3966 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
3967 | .sensor_voltdm_name = "core", | |
3968 | }; | |
3969 | ||
1f6a717f BC |
3970 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod; |
3971 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { | |
3972 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3973 | { .irq = -1 } |
1f6a717f BC |
3974 | }; |
3975 | ||
3976 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { | |
3977 | { | |
3978 | .pa_start = 0x4a0dd000, | |
3979 | .pa_end = 0x4a0dd03f, | |
3980 | .flags = ADDR_TYPE_RT | |
3981 | }, | |
78183f3f | 3982 | { } |
1f6a717f BC |
3983 | }; |
3984 | ||
3985 | /* l4_cfg -> smartreflex_core */ | |
3986 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
3987 | .master = &omap44xx_l4_cfg_hwmod, | |
3988 | .slave = &omap44xx_smartreflex_core_hwmod, | |
3989 | .clk = "l4_div_ck", | |
3990 | .addr = omap44xx_smartreflex_core_addrs, | |
1f6a717f BC |
3991 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3992 | }; | |
3993 | ||
3994 | /* smartreflex_core slave ports */ | |
3995 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { | |
3996 | &omap44xx_l4_cfg__smartreflex_core, | |
3997 | }; | |
3998 | ||
3999 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | |
4000 | .name = "smartreflex_core", | |
4001 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4002 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4003 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 4004 | |
1f6a717f | 4005 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
4006 | .prcm = { |
4007 | .omap4 = { | |
d0f0631d | 4008 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 4009 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 4010 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4011 | }, |
4012 | }, | |
4013 | .slaves = omap44xx_smartreflex_core_slaves, | |
4014 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), | |
cea6b942 | 4015 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
4016 | }; |
4017 | ||
4018 | /* smartreflex_iva */ | |
cea6b942 SG |
4019 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
4020 | .sensor_voltdm_name = "iva", | |
4021 | }; | |
4022 | ||
1f6a717f BC |
4023 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; |
4024 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { | |
4025 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4026 | { .irq = -1 } |
1f6a717f BC |
4027 | }; |
4028 | ||
4029 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
4030 | { | |
4031 | .pa_start = 0x4a0db000, | |
4032 | .pa_end = 0x4a0db03f, | |
4033 | .flags = ADDR_TYPE_RT | |
4034 | }, | |
78183f3f | 4035 | { } |
1f6a717f BC |
4036 | }; |
4037 | ||
4038 | /* l4_cfg -> smartreflex_iva */ | |
4039 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
4040 | .master = &omap44xx_l4_cfg_hwmod, | |
4041 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
4042 | .clk = "l4_div_ck", | |
4043 | .addr = omap44xx_smartreflex_iva_addrs, | |
1f6a717f BC |
4044 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4045 | }; | |
4046 | ||
4047 | /* smartreflex_iva slave ports */ | |
4048 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { | |
4049 | &omap44xx_l4_cfg__smartreflex_iva, | |
4050 | }; | |
4051 | ||
4052 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | |
4053 | .name = "smartreflex_iva", | |
4054 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4055 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4056 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 4057 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
4058 | .prcm = { |
4059 | .omap4 = { | |
d0f0631d | 4060 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 4061 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 4062 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4063 | }, |
4064 | }, | |
4065 | .slaves = omap44xx_smartreflex_iva_slaves, | |
4066 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), | |
cea6b942 | 4067 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
4068 | }; |
4069 | ||
4070 | /* smartreflex_mpu */ | |
cea6b942 SG |
4071 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
4072 | .sensor_voltdm_name = "mpu", | |
4073 | }; | |
4074 | ||
1f6a717f BC |
4075 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; |
4076 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { | |
4077 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4078 | { .irq = -1 } |
1f6a717f BC |
4079 | }; |
4080 | ||
4081 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
4082 | { | |
4083 | .pa_start = 0x4a0d9000, | |
4084 | .pa_end = 0x4a0d903f, | |
4085 | .flags = ADDR_TYPE_RT | |
4086 | }, | |
78183f3f | 4087 | { } |
1f6a717f BC |
4088 | }; |
4089 | ||
4090 | /* l4_cfg -> smartreflex_mpu */ | |
4091 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
4092 | .master = &omap44xx_l4_cfg_hwmod, | |
4093 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
4094 | .clk = "l4_div_ck", | |
4095 | .addr = omap44xx_smartreflex_mpu_addrs, | |
1f6a717f BC |
4096 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4097 | }; | |
4098 | ||
4099 | /* smartreflex_mpu slave ports */ | |
4100 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { | |
4101 | &omap44xx_l4_cfg__smartreflex_mpu, | |
4102 | }; | |
4103 | ||
4104 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | |
4105 | .name = "smartreflex_mpu", | |
4106 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4107 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4108 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 4109 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
4110 | .prcm = { |
4111 | .omap4 = { | |
d0f0631d | 4112 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 4113 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 4114 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4115 | }, |
4116 | }, | |
4117 | .slaves = omap44xx_smartreflex_mpu_slaves, | |
4118 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), | |
cea6b942 | 4119 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
4120 | }; |
4121 | ||
d11c217f BC |
4122 | /* |
4123 | * 'spinlock' class | |
4124 | * spinlock provides hardware assistance for synchronizing the processes | |
4125 | * running on multiple processors | |
4126 | */ | |
4127 | ||
4128 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
4129 | .rev_offs = 0x0000, | |
4130 | .sysc_offs = 0x0010, | |
4131 | .syss_offs = 0x0014, | |
4132 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
4133 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
4134 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
4135 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
4136 | SIDLE_SMART_WKUP), | |
4137 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4138 | }; | |
4139 | ||
4140 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
4141 | .name = "spinlock", | |
4142 | .sysc = &omap44xx_spinlock_sysc, | |
4143 | }; | |
4144 | ||
4145 | /* spinlock */ | |
4146 | static struct omap_hwmod omap44xx_spinlock_hwmod; | |
4147 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
4148 | { | |
4149 | .pa_start = 0x4a0f6000, | |
4150 | .pa_end = 0x4a0f6fff, | |
4151 | .flags = ADDR_TYPE_RT | |
4152 | }, | |
78183f3f | 4153 | { } |
d11c217f BC |
4154 | }; |
4155 | ||
4156 | /* l4_cfg -> spinlock */ | |
4157 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
4158 | .master = &omap44xx_l4_cfg_hwmod, | |
4159 | .slave = &omap44xx_spinlock_hwmod, | |
4160 | .clk = "l4_div_ck", | |
4161 | .addr = omap44xx_spinlock_addrs, | |
d11c217f BC |
4162 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4163 | }; | |
4164 | ||
4165 | /* spinlock slave ports */ | |
4166 | static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { | |
4167 | &omap44xx_l4_cfg__spinlock, | |
4168 | }; | |
4169 | ||
4170 | static struct omap_hwmod omap44xx_spinlock_hwmod = { | |
4171 | .name = "spinlock", | |
4172 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 4173 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
4174 | .prcm = { |
4175 | .omap4 = { | |
d0f0631d | 4176 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 4177 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
4178 | }, |
4179 | }, | |
4180 | .slaves = omap44xx_spinlock_slaves, | |
4181 | .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), | |
d11c217f BC |
4182 | }; |
4183 | ||
35d1a66a BC |
4184 | /* |
4185 | * 'timer' class | |
4186 | * general purpose timer module with accurate 1ms tick | |
4187 | * This class contains several variants: ['timer_1ms', 'timer'] | |
4188 | */ | |
4189 | ||
4190 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
4191 | .rev_offs = 0x0000, | |
4192 | .sysc_offs = 0x0010, | |
4193 | .syss_offs = 0x0014, | |
4194 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
4195 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
4196 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
4197 | SYSS_HAS_RESET_STATUS), | |
4198 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
4199 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4200 | }; | |
4201 | ||
4202 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
4203 | .name = "timer", | |
4204 | .sysc = &omap44xx_timer_1ms_sysc, | |
4205 | }; | |
4206 | ||
4207 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
4208 | .rev_offs = 0x0000, | |
4209 | .sysc_offs = 0x0010, | |
4210 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
4211 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
4212 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
4213 | SIDLE_SMART_WKUP), | |
4214 | .sysc_fields = &omap_hwmod_sysc_type2, | |
4215 | }; | |
4216 | ||
4217 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
4218 | .name = "timer", | |
4219 | .sysc = &omap44xx_timer_sysc, | |
4220 | }; | |
4221 | ||
c345c8b0 TKD |
4222 | /* always-on timers dev attribute */ |
4223 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
4224 | .timer_capability = OMAP_TIMER_ALWON, | |
4225 | }; | |
4226 | ||
4227 | /* pwm timers dev attribute */ | |
4228 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
4229 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
4230 | }; | |
4231 | ||
35d1a66a BC |
4232 | /* timer1 */ |
4233 | static struct omap_hwmod omap44xx_timer1_hwmod; | |
4234 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { | |
4235 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4236 | { .irq = -1 } |
35d1a66a BC |
4237 | }; |
4238 | ||
4239 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
4240 | { | |
4241 | .pa_start = 0x4a318000, | |
4242 | .pa_end = 0x4a31807f, | |
4243 | .flags = ADDR_TYPE_RT | |
4244 | }, | |
78183f3f | 4245 | { } |
35d1a66a BC |
4246 | }; |
4247 | ||
4248 | /* l4_wkup -> timer1 */ | |
4249 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
4250 | .master = &omap44xx_l4_wkup_hwmod, | |
4251 | .slave = &omap44xx_timer1_hwmod, | |
4252 | .clk = "l4_wkup_clk_mux_ck", | |
4253 | .addr = omap44xx_timer1_addrs, | |
35d1a66a BC |
4254 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4255 | }; | |
4256 | ||
4257 | /* timer1 slave ports */ | |
4258 | static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { | |
4259 | &omap44xx_l4_wkup__timer1, | |
4260 | }; | |
4261 | ||
4262 | static struct omap_hwmod omap44xx_timer1_hwmod = { | |
4263 | .name = "timer1", | |
4264 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4265 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 4266 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
4267 | .main_clk = "timer1_fck", |
4268 | .prcm = { | |
4269 | .omap4 = { | |
d0f0631d | 4270 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 4271 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 4272 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4273 | }, |
4274 | }, | |
c345c8b0 | 4275 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4276 | .slaves = omap44xx_timer1_slaves, |
4277 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), | |
35d1a66a BC |
4278 | }; |
4279 | ||
4280 | /* timer2 */ | |
4281 | static struct omap_hwmod omap44xx_timer2_hwmod; | |
4282 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { | |
4283 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4284 | { .irq = -1 } |
35d1a66a BC |
4285 | }; |
4286 | ||
4287 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
4288 | { | |
4289 | .pa_start = 0x48032000, | |
4290 | .pa_end = 0x4803207f, | |
4291 | .flags = ADDR_TYPE_RT | |
4292 | }, | |
78183f3f | 4293 | { } |
35d1a66a BC |
4294 | }; |
4295 | ||
4296 | /* l4_per -> timer2 */ | |
4297 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
4298 | .master = &omap44xx_l4_per_hwmod, | |
4299 | .slave = &omap44xx_timer2_hwmod, | |
4300 | .clk = "l4_div_ck", | |
4301 | .addr = omap44xx_timer2_addrs, | |
35d1a66a BC |
4302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4303 | }; | |
4304 | ||
4305 | /* timer2 slave ports */ | |
4306 | static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { | |
4307 | &omap44xx_l4_per__timer2, | |
4308 | }; | |
4309 | ||
4310 | static struct omap_hwmod omap44xx_timer2_hwmod = { | |
4311 | .name = "timer2", | |
4312 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4313 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4314 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
4315 | .main_clk = "timer2_fck", |
4316 | .prcm = { | |
4317 | .omap4 = { | |
d0f0631d | 4318 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 4319 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 4320 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4321 | }, |
4322 | }, | |
c345c8b0 | 4323 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4324 | .slaves = omap44xx_timer2_slaves, |
4325 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), | |
35d1a66a BC |
4326 | }; |
4327 | ||
4328 | /* timer3 */ | |
4329 | static struct omap_hwmod omap44xx_timer3_hwmod; | |
4330 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { | |
4331 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4332 | { .irq = -1 } |
35d1a66a BC |
4333 | }; |
4334 | ||
4335 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
4336 | { | |
4337 | .pa_start = 0x48034000, | |
4338 | .pa_end = 0x4803407f, | |
4339 | .flags = ADDR_TYPE_RT | |
4340 | }, | |
78183f3f | 4341 | { } |
35d1a66a BC |
4342 | }; |
4343 | ||
4344 | /* l4_per -> timer3 */ | |
4345 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
4346 | .master = &omap44xx_l4_per_hwmod, | |
4347 | .slave = &omap44xx_timer3_hwmod, | |
4348 | .clk = "l4_div_ck", | |
4349 | .addr = omap44xx_timer3_addrs, | |
35d1a66a BC |
4350 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4351 | }; | |
4352 | ||
4353 | /* timer3 slave ports */ | |
4354 | static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { | |
4355 | &omap44xx_l4_per__timer3, | |
4356 | }; | |
4357 | ||
4358 | static struct omap_hwmod omap44xx_timer3_hwmod = { | |
4359 | .name = "timer3", | |
4360 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4361 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4362 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
4363 | .main_clk = "timer3_fck", |
4364 | .prcm = { | |
4365 | .omap4 = { | |
d0f0631d | 4366 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 4367 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 4368 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4369 | }, |
4370 | }, | |
c345c8b0 | 4371 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4372 | .slaves = omap44xx_timer3_slaves, |
4373 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), | |
35d1a66a BC |
4374 | }; |
4375 | ||
4376 | /* timer4 */ | |
4377 | static struct omap_hwmod omap44xx_timer4_hwmod; | |
4378 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { | |
4379 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4380 | { .irq = -1 } |
35d1a66a BC |
4381 | }; |
4382 | ||
4383 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
4384 | { | |
4385 | .pa_start = 0x48036000, | |
4386 | .pa_end = 0x4803607f, | |
4387 | .flags = ADDR_TYPE_RT | |
4388 | }, | |
78183f3f | 4389 | { } |
35d1a66a BC |
4390 | }; |
4391 | ||
4392 | /* l4_per -> timer4 */ | |
4393 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
4394 | .master = &omap44xx_l4_per_hwmod, | |
4395 | .slave = &omap44xx_timer4_hwmod, | |
4396 | .clk = "l4_div_ck", | |
4397 | .addr = omap44xx_timer4_addrs, | |
35d1a66a BC |
4398 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4399 | }; | |
4400 | ||
4401 | /* timer4 slave ports */ | |
4402 | static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { | |
4403 | &omap44xx_l4_per__timer4, | |
4404 | }; | |
4405 | ||
4406 | static struct omap_hwmod omap44xx_timer4_hwmod = { | |
4407 | .name = "timer4", | |
4408 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4409 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4410 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
4411 | .main_clk = "timer4_fck", |
4412 | .prcm = { | |
4413 | .omap4 = { | |
d0f0631d | 4414 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 4415 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 4416 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4417 | }, |
4418 | }, | |
c345c8b0 | 4419 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4420 | .slaves = omap44xx_timer4_slaves, |
4421 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), | |
35d1a66a BC |
4422 | }; |
4423 | ||
4424 | /* timer5 */ | |
4425 | static struct omap_hwmod omap44xx_timer5_hwmod; | |
4426 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { | |
4427 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4428 | { .irq = -1 } |
35d1a66a BC |
4429 | }; |
4430 | ||
4431 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
4432 | { | |
4433 | .pa_start = 0x40138000, | |
4434 | .pa_end = 0x4013807f, | |
4435 | .flags = ADDR_TYPE_RT | |
4436 | }, | |
78183f3f | 4437 | { } |
35d1a66a BC |
4438 | }; |
4439 | ||
4440 | /* l4_abe -> timer5 */ | |
4441 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
4442 | .master = &omap44xx_l4_abe_hwmod, | |
4443 | .slave = &omap44xx_timer5_hwmod, | |
4444 | .clk = "ocp_abe_iclk", | |
4445 | .addr = omap44xx_timer5_addrs, | |
35d1a66a BC |
4446 | .user = OCP_USER_MPU, |
4447 | }; | |
4448 | ||
4449 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
4450 | { | |
4451 | .pa_start = 0x49038000, | |
4452 | .pa_end = 0x4903807f, | |
4453 | .flags = ADDR_TYPE_RT | |
4454 | }, | |
78183f3f | 4455 | { } |
35d1a66a BC |
4456 | }; |
4457 | ||
4458 | /* l4_abe -> timer5 (dma) */ | |
4459 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
4460 | .master = &omap44xx_l4_abe_hwmod, | |
4461 | .slave = &omap44xx_timer5_hwmod, | |
4462 | .clk = "ocp_abe_iclk", | |
4463 | .addr = omap44xx_timer5_dma_addrs, | |
35d1a66a BC |
4464 | .user = OCP_USER_SDMA, |
4465 | }; | |
4466 | ||
4467 | /* timer5 slave ports */ | |
4468 | static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { | |
4469 | &omap44xx_l4_abe__timer5, | |
4470 | &omap44xx_l4_abe__timer5_dma, | |
4471 | }; | |
4472 | ||
4473 | static struct omap_hwmod omap44xx_timer5_hwmod = { | |
4474 | .name = "timer5", | |
4475 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4476 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4477 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
4478 | .main_clk = "timer5_fck", |
4479 | .prcm = { | |
4480 | .omap4 = { | |
d0f0631d | 4481 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 4482 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 4483 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4484 | }, |
4485 | }, | |
c345c8b0 | 4486 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4487 | .slaves = omap44xx_timer5_slaves, |
4488 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), | |
35d1a66a BC |
4489 | }; |
4490 | ||
4491 | /* timer6 */ | |
4492 | static struct omap_hwmod omap44xx_timer6_hwmod; | |
4493 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { | |
4494 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4495 | { .irq = -1 } |
35d1a66a BC |
4496 | }; |
4497 | ||
4498 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
4499 | { | |
4500 | .pa_start = 0x4013a000, | |
4501 | .pa_end = 0x4013a07f, | |
4502 | .flags = ADDR_TYPE_RT | |
4503 | }, | |
78183f3f | 4504 | { } |
35d1a66a BC |
4505 | }; |
4506 | ||
4507 | /* l4_abe -> timer6 */ | |
4508 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
4509 | .master = &omap44xx_l4_abe_hwmod, | |
4510 | .slave = &omap44xx_timer6_hwmod, | |
4511 | .clk = "ocp_abe_iclk", | |
4512 | .addr = omap44xx_timer6_addrs, | |
35d1a66a BC |
4513 | .user = OCP_USER_MPU, |
4514 | }; | |
4515 | ||
4516 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
4517 | { | |
4518 | .pa_start = 0x4903a000, | |
4519 | .pa_end = 0x4903a07f, | |
4520 | .flags = ADDR_TYPE_RT | |
4521 | }, | |
78183f3f | 4522 | { } |
35d1a66a BC |
4523 | }; |
4524 | ||
4525 | /* l4_abe -> timer6 (dma) */ | |
4526 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
4527 | .master = &omap44xx_l4_abe_hwmod, | |
4528 | .slave = &omap44xx_timer6_hwmod, | |
4529 | .clk = "ocp_abe_iclk", | |
4530 | .addr = omap44xx_timer6_dma_addrs, | |
35d1a66a BC |
4531 | .user = OCP_USER_SDMA, |
4532 | }; | |
4533 | ||
4534 | /* timer6 slave ports */ | |
4535 | static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { | |
4536 | &omap44xx_l4_abe__timer6, | |
4537 | &omap44xx_l4_abe__timer6_dma, | |
4538 | }; | |
4539 | ||
4540 | static struct omap_hwmod omap44xx_timer6_hwmod = { | |
4541 | .name = "timer6", | |
4542 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4543 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4544 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 4545 | |
35d1a66a BC |
4546 | .main_clk = "timer6_fck", |
4547 | .prcm = { | |
4548 | .omap4 = { | |
d0f0631d | 4549 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 4550 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 4551 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4552 | }, |
4553 | }, | |
c345c8b0 | 4554 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4555 | .slaves = omap44xx_timer6_slaves, |
4556 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), | |
35d1a66a BC |
4557 | }; |
4558 | ||
4559 | /* timer7 */ | |
4560 | static struct omap_hwmod omap44xx_timer7_hwmod; | |
4561 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { | |
4562 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4563 | { .irq = -1 } |
35d1a66a BC |
4564 | }; |
4565 | ||
4566 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
4567 | { | |
4568 | .pa_start = 0x4013c000, | |
4569 | .pa_end = 0x4013c07f, | |
4570 | .flags = ADDR_TYPE_RT | |
4571 | }, | |
78183f3f | 4572 | { } |
35d1a66a BC |
4573 | }; |
4574 | ||
4575 | /* l4_abe -> timer7 */ | |
4576 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
4577 | .master = &omap44xx_l4_abe_hwmod, | |
4578 | .slave = &omap44xx_timer7_hwmod, | |
4579 | .clk = "ocp_abe_iclk", | |
4580 | .addr = omap44xx_timer7_addrs, | |
35d1a66a BC |
4581 | .user = OCP_USER_MPU, |
4582 | }; | |
4583 | ||
4584 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
4585 | { | |
4586 | .pa_start = 0x4903c000, | |
4587 | .pa_end = 0x4903c07f, | |
4588 | .flags = ADDR_TYPE_RT | |
4589 | }, | |
78183f3f | 4590 | { } |
35d1a66a BC |
4591 | }; |
4592 | ||
4593 | /* l4_abe -> timer7 (dma) */ | |
4594 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
4595 | .master = &omap44xx_l4_abe_hwmod, | |
4596 | .slave = &omap44xx_timer7_hwmod, | |
4597 | .clk = "ocp_abe_iclk", | |
4598 | .addr = omap44xx_timer7_dma_addrs, | |
35d1a66a BC |
4599 | .user = OCP_USER_SDMA, |
4600 | }; | |
4601 | ||
4602 | /* timer7 slave ports */ | |
4603 | static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { | |
4604 | &omap44xx_l4_abe__timer7, | |
4605 | &omap44xx_l4_abe__timer7_dma, | |
4606 | }; | |
4607 | ||
4608 | static struct omap_hwmod omap44xx_timer7_hwmod = { | |
4609 | .name = "timer7", | |
4610 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4611 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4612 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
4613 | .main_clk = "timer7_fck", |
4614 | .prcm = { | |
4615 | .omap4 = { | |
d0f0631d | 4616 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 4617 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 4618 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4619 | }, |
4620 | }, | |
c345c8b0 | 4621 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4622 | .slaves = omap44xx_timer7_slaves, |
4623 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), | |
35d1a66a BC |
4624 | }; |
4625 | ||
4626 | /* timer8 */ | |
4627 | static struct omap_hwmod omap44xx_timer8_hwmod; | |
4628 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { | |
4629 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4630 | { .irq = -1 } |
35d1a66a BC |
4631 | }; |
4632 | ||
4633 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
4634 | { | |
4635 | .pa_start = 0x4013e000, | |
4636 | .pa_end = 0x4013e07f, | |
4637 | .flags = ADDR_TYPE_RT | |
4638 | }, | |
78183f3f | 4639 | { } |
35d1a66a BC |
4640 | }; |
4641 | ||
4642 | /* l4_abe -> timer8 */ | |
4643 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
4644 | .master = &omap44xx_l4_abe_hwmod, | |
4645 | .slave = &omap44xx_timer8_hwmod, | |
4646 | .clk = "ocp_abe_iclk", | |
4647 | .addr = omap44xx_timer8_addrs, | |
35d1a66a BC |
4648 | .user = OCP_USER_MPU, |
4649 | }; | |
4650 | ||
4651 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
4652 | { | |
4653 | .pa_start = 0x4903e000, | |
4654 | .pa_end = 0x4903e07f, | |
4655 | .flags = ADDR_TYPE_RT | |
4656 | }, | |
78183f3f | 4657 | { } |
35d1a66a BC |
4658 | }; |
4659 | ||
4660 | /* l4_abe -> timer8 (dma) */ | |
4661 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
4662 | .master = &omap44xx_l4_abe_hwmod, | |
4663 | .slave = &omap44xx_timer8_hwmod, | |
4664 | .clk = "ocp_abe_iclk", | |
4665 | .addr = omap44xx_timer8_dma_addrs, | |
35d1a66a BC |
4666 | .user = OCP_USER_SDMA, |
4667 | }; | |
4668 | ||
4669 | /* timer8 slave ports */ | |
4670 | static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { | |
4671 | &omap44xx_l4_abe__timer8, | |
4672 | &omap44xx_l4_abe__timer8_dma, | |
4673 | }; | |
4674 | ||
4675 | static struct omap_hwmod omap44xx_timer8_hwmod = { | |
4676 | .name = "timer8", | |
4677 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4678 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4679 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
4680 | .main_clk = "timer8_fck", |
4681 | .prcm = { | |
4682 | .omap4 = { | |
d0f0631d | 4683 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 4684 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 4685 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4686 | }, |
4687 | }, | |
c345c8b0 | 4688 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4689 | .slaves = omap44xx_timer8_slaves, |
4690 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), | |
35d1a66a BC |
4691 | }; |
4692 | ||
4693 | /* timer9 */ | |
4694 | static struct omap_hwmod omap44xx_timer9_hwmod; | |
4695 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { | |
4696 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4697 | { .irq = -1 } |
35d1a66a BC |
4698 | }; |
4699 | ||
4700 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
4701 | { | |
4702 | .pa_start = 0x4803e000, | |
4703 | .pa_end = 0x4803e07f, | |
4704 | .flags = ADDR_TYPE_RT | |
4705 | }, | |
78183f3f | 4706 | { } |
35d1a66a BC |
4707 | }; |
4708 | ||
4709 | /* l4_per -> timer9 */ | |
4710 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
4711 | .master = &omap44xx_l4_per_hwmod, | |
4712 | .slave = &omap44xx_timer9_hwmod, | |
4713 | .clk = "l4_div_ck", | |
4714 | .addr = omap44xx_timer9_addrs, | |
35d1a66a BC |
4715 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4716 | }; | |
4717 | ||
4718 | /* timer9 slave ports */ | |
4719 | static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { | |
4720 | &omap44xx_l4_per__timer9, | |
4721 | }; | |
4722 | ||
4723 | static struct omap_hwmod omap44xx_timer9_hwmod = { | |
4724 | .name = "timer9", | |
4725 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4726 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4727 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
4728 | .main_clk = "timer9_fck", |
4729 | .prcm = { | |
4730 | .omap4 = { | |
d0f0631d | 4731 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 4732 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 4733 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4734 | }, |
4735 | }, | |
c345c8b0 | 4736 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4737 | .slaves = omap44xx_timer9_slaves, |
4738 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), | |
35d1a66a BC |
4739 | }; |
4740 | ||
4741 | /* timer10 */ | |
4742 | static struct omap_hwmod omap44xx_timer10_hwmod; | |
4743 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { | |
4744 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4745 | { .irq = -1 } |
35d1a66a BC |
4746 | }; |
4747 | ||
4748 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
4749 | { | |
4750 | .pa_start = 0x48086000, | |
4751 | .pa_end = 0x4808607f, | |
4752 | .flags = ADDR_TYPE_RT | |
4753 | }, | |
78183f3f | 4754 | { } |
35d1a66a BC |
4755 | }; |
4756 | ||
4757 | /* l4_per -> timer10 */ | |
4758 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
4759 | .master = &omap44xx_l4_per_hwmod, | |
4760 | .slave = &omap44xx_timer10_hwmod, | |
4761 | .clk = "l4_div_ck", | |
4762 | .addr = omap44xx_timer10_addrs, | |
35d1a66a BC |
4763 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4764 | }; | |
4765 | ||
4766 | /* timer10 slave ports */ | |
4767 | static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { | |
4768 | &omap44xx_l4_per__timer10, | |
4769 | }; | |
4770 | ||
4771 | static struct omap_hwmod omap44xx_timer10_hwmod = { | |
4772 | .name = "timer10", | |
4773 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4774 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4775 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
4776 | .main_clk = "timer10_fck", |
4777 | .prcm = { | |
4778 | .omap4 = { | |
d0f0631d | 4779 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 4780 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 4781 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4782 | }, |
4783 | }, | |
c345c8b0 | 4784 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4785 | .slaves = omap44xx_timer10_slaves, |
4786 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), | |
35d1a66a BC |
4787 | }; |
4788 | ||
4789 | /* timer11 */ | |
4790 | static struct omap_hwmod omap44xx_timer11_hwmod; | |
4791 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { | |
4792 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4793 | { .irq = -1 } |
35d1a66a BC |
4794 | }; |
4795 | ||
4796 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
4797 | { | |
4798 | .pa_start = 0x48088000, | |
4799 | .pa_end = 0x4808807f, | |
4800 | .flags = ADDR_TYPE_RT | |
4801 | }, | |
78183f3f | 4802 | { } |
35d1a66a BC |
4803 | }; |
4804 | ||
4805 | /* l4_per -> timer11 */ | |
4806 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
4807 | .master = &omap44xx_l4_per_hwmod, | |
4808 | .slave = &omap44xx_timer11_hwmod, | |
4809 | .clk = "l4_div_ck", | |
4810 | .addr = omap44xx_timer11_addrs, | |
35d1a66a BC |
4811 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4812 | }; | |
4813 | ||
4814 | /* timer11 slave ports */ | |
4815 | static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { | |
4816 | &omap44xx_l4_per__timer11, | |
4817 | }; | |
4818 | ||
4819 | static struct omap_hwmod omap44xx_timer11_hwmod = { | |
4820 | .name = "timer11", | |
4821 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4822 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4823 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
4824 | .main_clk = "timer11_fck", |
4825 | .prcm = { | |
4826 | .omap4 = { | |
d0f0631d | 4827 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 4828 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 4829 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4830 | }, |
4831 | }, | |
c345c8b0 | 4832 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4833 | .slaves = omap44xx_timer11_slaves, |
4834 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), | |
35d1a66a BC |
4835 | }; |
4836 | ||
9780a9cf | 4837 | /* |
3b54baad BC |
4838 | * 'uart' class |
4839 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
4840 | */ |
4841 | ||
3b54baad BC |
4842 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
4843 | .rev_offs = 0x0050, | |
4844 | .sysc_offs = 0x0054, | |
4845 | .syss_offs = 0x0058, | |
4846 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
4847 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
4848 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
4849 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
4850 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
4851 | .sysc_fields = &omap_hwmod_sysc_type1, |
4852 | }; | |
4853 | ||
3b54baad | 4854 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
4855 | .name = "uart", |
4856 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
4857 | }; |
4858 | ||
3b54baad BC |
4859 | /* uart1 */ |
4860 | static struct omap_hwmod omap44xx_uart1_hwmod; | |
4861 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | |
4862 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4863 | { .irq = -1 } |
9780a9cf BC |
4864 | }; |
4865 | ||
3b54baad BC |
4866 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
4867 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
4868 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4869 | { .dma_req = -1 } |
9780a9cf BC |
4870 | }; |
4871 | ||
3b54baad | 4872 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
9780a9cf | 4873 | { |
3b54baad BC |
4874 | .pa_start = 0x4806a000, |
4875 | .pa_end = 0x4806a0ff, | |
9780a9cf BC |
4876 | .flags = ADDR_TYPE_RT |
4877 | }, | |
78183f3f | 4878 | { } |
9780a9cf BC |
4879 | }; |
4880 | ||
3b54baad BC |
4881 | /* l4_per -> uart1 */ |
4882 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
4883 | .master = &omap44xx_l4_per_hwmod, | |
4884 | .slave = &omap44xx_uart1_hwmod, | |
4885 | .clk = "l4_div_ck", | |
4886 | .addr = omap44xx_uart1_addrs, | |
9780a9cf BC |
4887 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4888 | }; | |
4889 | ||
3b54baad BC |
4890 | /* uart1 slave ports */ |
4891 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { | |
4892 | &omap44xx_l4_per__uart1, | |
9780a9cf BC |
4893 | }; |
4894 | ||
3b54baad BC |
4895 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
4896 | .name = "uart1", | |
4897 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 4898 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 4899 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 4900 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 4901 | .main_clk = "uart1_fck", |
9780a9cf BC |
4902 | .prcm = { |
4903 | .omap4 = { | |
d0f0631d | 4904 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 4905 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 4906 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
4907 | }, |
4908 | }, | |
3b54baad BC |
4909 | .slaves = omap44xx_uart1_slaves, |
4910 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), | |
9780a9cf BC |
4911 | }; |
4912 | ||
3b54baad BC |
4913 | /* uart2 */ |
4914 | static struct omap_hwmod omap44xx_uart2_hwmod; | |
4915 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | |
4916 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4917 | { .irq = -1 } |
9780a9cf BC |
4918 | }; |
4919 | ||
3b54baad BC |
4920 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
4921 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
4922 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4923 | { .dma_req = -1 } |
3b54baad BC |
4924 | }; |
4925 | ||
4926 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | |
9780a9cf | 4927 | { |
3b54baad BC |
4928 | .pa_start = 0x4806c000, |
4929 | .pa_end = 0x4806c0ff, | |
9780a9cf BC |
4930 | .flags = ADDR_TYPE_RT |
4931 | }, | |
78183f3f | 4932 | { } |
9780a9cf BC |
4933 | }; |
4934 | ||
3b54baad BC |
4935 | /* l4_per -> uart2 */ |
4936 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
9780a9cf | 4937 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
4938 | .slave = &omap44xx_uart2_hwmod, |
4939 | .clk = "l4_div_ck", | |
4940 | .addr = omap44xx_uart2_addrs, | |
9780a9cf BC |
4941 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4942 | }; | |
4943 | ||
3b54baad BC |
4944 | /* uart2 slave ports */ |
4945 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { | |
4946 | &omap44xx_l4_per__uart2, | |
9780a9cf BC |
4947 | }; |
4948 | ||
3b54baad BC |
4949 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
4950 | .name = "uart2", | |
4951 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 4952 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 4953 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 4954 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 4955 | .main_clk = "uart2_fck", |
9780a9cf BC |
4956 | .prcm = { |
4957 | .omap4 = { | |
d0f0631d | 4958 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 4959 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 4960 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
4961 | }, |
4962 | }, | |
3b54baad BC |
4963 | .slaves = omap44xx_uart2_slaves, |
4964 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), | |
9780a9cf BC |
4965 | }; |
4966 | ||
3b54baad BC |
4967 | /* uart3 */ |
4968 | static struct omap_hwmod omap44xx_uart3_hwmod; | |
4969 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | |
4970 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4971 | { .irq = -1 } |
9780a9cf BC |
4972 | }; |
4973 | ||
3b54baad BC |
4974 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
4975 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
4976 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4977 | { .dma_req = -1 } |
3b54baad BC |
4978 | }; |
4979 | ||
4980 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | |
9780a9cf | 4981 | { |
3b54baad BC |
4982 | .pa_start = 0x48020000, |
4983 | .pa_end = 0x480200ff, | |
9780a9cf BC |
4984 | .flags = ADDR_TYPE_RT |
4985 | }, | |
78183f3f | 4986 | { } |
9780a9cf BC |
4987 | }; |
4988 | ||
3b54baad BC |
4989 | /* l4_per -> uart3 */ |
4990 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
9780a9cf | 4991 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
4992 | .slave = &omap44xx_uart3_hwmod, |
4993 | .clk = "l4_div_ck", | |
4994 | .addr = omap44xx_uart3_addrs, | |
9780a9cf BC |
4995 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4996 | }; | |
4997 | ||
3b54baad BC |
4998 | /* uart3 slave ports */ |
4999 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { | |
5000 | &omap44xx_l4_per__uart3, | |
5001 | }; | |
5002 | ||
5003 | static struct omap_hwmod omap44xx_uart3_hwmod = { | |
5004 | .name = "uart3", | |
5005 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 5006 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 5007 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 5008 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 5009 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 5010 | .main_clk = "uart3_fck", |
9780a9cf BC |
5011 | .prcm = { |
5012 | .omap4 = { | |
d0f0631d | 5013 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 5014 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 5015 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5016 | }, |
5017 | }, | |
3b54baad BC |
5018 | .slaves = omap44xx_uart3_slaves, |
5019 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), | |
9780a9cf BC |
5020 | }; |
5021 | ||
3b54baad BC |
5022 | /* uart4 */ |
5023 | static struct omap_hwmod omap44xx_uart4_hwmod; | |
5024 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | |
5025 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5026 | { .irq = -1 } |
9780a9cf BC |
5027 | }; |
5028 | ||
3b54baad BC |
5029 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
5030 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
5031 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 5032 | { .dma_req = -1 } |
3b54baad BC |
5033 | }; |
5034 | ||
5035 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | |
9780a9cf | 5036 | { |
3b54baad BC |
5037 | .pa_start = 0x4806e000, |
5038 | .pa_end = 0x4806e0ff, | |
9780a9cf BC |
5039 | .flags = ADDR_TYPE_RT |
5040 | }, | |
78183f3f | 5041 | { } |
9780a9cf BC |
5042 | }; |
5043 | ||
3b54baad BC |
5044 | /* l4_per -> uart4 */ |
5045 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
9780a9cf | 5046 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
5047 | .slave = &omap44xx_uart4_hwmod, |
5048 | .clk = "l4_div_ck", | |
5049 | .addr = omap44xx_uart4_addrs, | |
9780a9cf BC |
5050 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5051 | }; | |
5052 | ||
3b54baad BC |
5053 | /* uart4 slave ports */ |
5054 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { | |
5055 | &omap44xx_l4_per__uart4, | |
9780a9cf BC |
5056 | }; |
5057 | ||
3b54baad BC |
5058 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
5059 | .name = "uart4", | |
5060 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 5061 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 5062 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 5063 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 5064 | .main_clk = "uart4_fck", |
9780a9cf BC |
5065 | .prcm = { |
5066 | .omap4 = { | |
d0f0631d | 5067 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 5068 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 5069 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5070 | }, |
5071 | }, | |
3b54baad BC |
5072 | .slaves = omap44xx_uart4_slaves, |
5073 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), | |
9780a9cf BC |
5074 | }; |
5075 | ||
5844c4ea BC |
5076 | /* |
5077 | * 'usb_otg_hs' class | |
5078 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
5079 | */ | |
5080 | ||
5081 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
5082 | .rev_offs = 0x0400, | |
5083 | .sysc_offs = 0x0404, | |
5084 | .syss_offs = 0x0408, | |
5085 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
5086 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
5087 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
5088 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
5089 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
5090 | MSTANDBY_SMART), | |
5091 | .sysc_fields = &omap_hwmod_sysc_type1, | |
5092 | }; | |
5093 | ||
5094 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
00fe610b BC |
5095 | .name = "usb_otg_hs", |
5096 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
5844c4ea BC |
5097 | }; |
5098 | ||
5099 | /* usb_otg_hs */ | |
5100 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
5101 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
5102 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5103 | { .irq = -1 } |
5844c4ea BC |
5104 | }; |
5105 | ||
5106 | /* usb_otg_hs master ports */ | |
5107 | static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { | |
5108 | &omap44xx_usb_otg_hs__l3_main_2, | |
5109 | }; | |
5110 | ||
5111 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
5112 | { | |
5113 | .pa_start = 0x4a0ab000, | |
5114 | .pa_end = 0x4a0ab003, | |
5115 | .flags = ADDR_TYPE_RT | |
5116 | }, | |
78183f3f | 5117 | { } |
5844c4ea BC |
5118 | }; |
5119 | ||
5120 | /* l4_cfg -> usb_otg_hs */ | |
5121 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
5122 | .master = &omap44xx_l4_cfg_hwmod, | |
5123 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
5124 | .clk = "l4_div_ck", | |
5125 | .addr = omap44xx_usb_otg_hs_addrs, | |
5844c4ea BC |
5126 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5127 | }; | |
5128 | ||
5129 | /* usb_otg_hs slave ports */ | |
5130 | static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { | |
5131 | &omap44xx_l4_cfg__usb_otg_hs, | |
5132 | }; | |
5133 | ||
5134 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
5135 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
5136 | }; | |
5137 | ||
5138 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
5139 | .name = "usb_otg_hs", | |
5140 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
a5322c6f | 5141 | .clkdm_name = "l3_init_clkdm", |
5844c4ea BC |
5142 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
5143 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
5844c4ea BC |
5144 | .main_clk = "usb_otg_hs_ick", |
5145 | .prcm = { | |
5146 | .omap4 = { | |
d0f0631d | 5147 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, |
27bb00b5 | 5148 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, |
03fdefe5 | 5149 | .modulemode = MODULEMODE_HWCTRL, |
5844c4ea BC |
5150 | }, |
5151 | }, | |
5152 | .opt_clks = usb_otg_hs_opt_clks, | |
00fe610b | 5153 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), |
5844c4ea BC |
5154 | .slaves = omap44xx_usb_otg_hs_slaves, |
5155 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), | |
5156 | .masters = omap44xx_usb_otg_hs_masters, | |
5157 | .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), | |
5844c4ea BC |
5158 | }; |
5159 | ||
3b54baad BC |
5160 | /* |
5161 | * 'wd_timer' class | |
5162 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
5163 | * overflow condition | |
5164 | */ | |
5165 | ||
5166 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
5167 | .rev_offs = 0x0000, | |
5168 | .sysc_offs = 0x0010, | |
5169 | .syss_offs = 0x0014, | |
5170 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 5171 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
5172 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
5173 | SIDLE_SMART_WKUP), | |
3b54baad | 5174 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
5175 | }; |
5176 | ||
3b54baad BC |
5177 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
5178 | .name = "wd_timer", | |
5179 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 5180 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
5181 | }; |
5182 | ||
5183 | /* wd_timer2 */ | |
5184 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | |
5185 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | |
5186 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5187 | { .irq = -1 } |
3b54baad BC |
5188 | }; |
5189 | ||
5190 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | |
9780a9cf | 5191 | { |
3b54baad BC |
5192 | .pa_start = 0x4a314000, |
5193 | .pa_end = 0x4a31407f, | |
9780a9cf BC |
5194 | .flags = ADDR_TYPE_RT |
5195 | }, | |
78183f3f | 5196 | { } |
9780a9cf BC |
5197 | }; |
5198 | ||
3b54baad BC |
5199 | /* l4_wkup -> wd_timer2 */ |
5200 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
5201 | .master = &omap44xx_l4_wkup_hwmod, | |
5202 | .slave = &omap44xx_wd_timer2_hwmod, | |
5203 | .clk = "l4_wkup_clk_mux_ck", | |
5204 | .addr = omap44xx_wd_timer2_addrs, | |
9780a9cf BC |
5205 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5206 | }; | |
5207 | ||
3b54baad BC |
5208 | /* wd_timer2 slave ports */ |
5209 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | |
5210 | &omap44xx_l4_wkup__wd_timer2, | |
9780a9cf BC |
5211 | }; |
5212 | ||
3b54baad BC |
5213 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
5214 | .name = "wd_timer2", | |
5215 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 5216 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 5217 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 5218 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
5219 | .prcm = { |
5220 | .omap4 = { | |
d0f0631d | 5221 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 5222 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 5223 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5224 | }, |
5225 | }, | |
3b54baad BC |
5226 | .slaves = omap44xx_wd_timer2_slaves, |
5227 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | |
9780a9cf BC |
5228 | }; |
5229 | ||
3b54baad BC |
5230 | /* wd_timer3 */ |
5231 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | |
5232 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | |
5233 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5234 | { .irq = -1 } |
9780a9cf BC |
5235 | }; |
5236 | ||
3b54baad | 5237 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
9780a9cf | 5238 | { |
3b54baad BC |
5239 | .pa_start = 0x40130000, |
5240 | .pa_end = 0x4013007f, | |
9780a9cf BC |
5241 | .flags = ADDR_TYPE_RT |
5242 | }, | |
78183f3f | 5243 | { } |
9780a9cf BC |
5244 | }; |
5245 | ||
3b54baad BC |
5246 | /* l4_abe -> wd_timer3 */ |
5247 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
5248 | .master = &omap44xx_l4_abe_hwmod, | |
5249 | .slave = &omap44xx_wd_timer3_hwmod, | |
5250 | .clk = "ocp_abe_iclk", | |
5251 | .addr = omap44xx_wd_timer3_addrs, | |
3b54baad | 5252 | .user = OCP_USER_MPU, |
9780a9cf BC |
5253 | }; |
5254 | ||
3b54baad BC |
5255 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
5256 | { | |
5257 | .pa_start = 0x49030000, | |
5258 | .pa_end = 0x4903007f, | |
5259 | .flags = ADDR_TYPE_RT | |
5260 | }, | |
78183f3f | 5261 | { } |
9780a9cf BC |
5262 | }; |
5263 | ||
3b54baad BC |
5264 | /* l4_abe -> wd_timer3 (dma) */ |
5265 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
5266 | .master = &omap44xx_l4_abe_hwmod, | |
5267 | .slave = &omap44xx_wd_timer3_hwmod, | |
5268 | .clk = "ocp_abe_iclk", | |
5269 | .addr = omap44xx_wd_timer3_dma_addrs, | |
3b54baad | 5270 | .user = OCP_USER_SDMA, |
9780a9cf BC |
5271 | }; |
5272 | ||
3b54baad BC |
5273 | /* wd_timer3 slave ports */ |
5274 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | |
5275 | &omap44xx_l4_abe__wd_timer3, | |
5276 | &omap44xx_l4_abe__wd_timer3_dma, | |
5277 | }; | |
5278 | ||
5279 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |
5280 | .name = "wd_timer3", | |
5281 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 5282 | .clkdm_name = "abe_clkdm", |
3b54baad | 5283 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 5284 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
5285 | .prcm = { |
5286 | .omap4 = { | |
d0f0631d | 5287 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 5288 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 5289 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5290 | }, |
5291 | }, | |
3b54baad BC |
5292 | .slaves = omap44xx_wd_timer3_slaves, |
5293 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | |
9780a9cf | 5294 | }; |
531ce0d5 | 5295 | |
af88fa9a BC |
5296 | /* |
5297 | * 'usb_host_hs' class | |
5298 | * high-speed multi-port usb host controller | |
5299 | */ | |
5300 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
5301 | .master = &omap44xx_usb_host_hs_hwmod, | |
5302 | .slave = &omap44xx_l3_main_2_hwmod, | |
5303 | .clk = "l3_div_ck", | |
5304 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5305 | }; | |
5306 | ||
5307 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { | |
5308 | .rev_offs = 0x0000, | |
5309 | .sysc_offs = 0x0010, | |
5310 | .syss_offs = 0x0014, | |
5311 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
5312 | SYSC_HAS_SOFTRESET), | |
5313 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
5314 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
5315 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
5316 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5317 | }; | |
5318 | ||
5319 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { | |
5320 | .name = "usb_host_hs", | |
5321 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5322 | }; | |
5323 | ||
5324 | static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { | |
5325 | &omap44xx_usb_host_hs__l3_main_2, | |
5326 | }; | |
5327 | ||
5328 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { | |
5329 | { | |
5330 | .name = "uhh", | |
5331 | .pa_start = 0x4a064000, | |
5332 | .pa_end = 0x4a0647ff, | |
5333 | .flags = ADDR_TYPE_RT | |
5334 | }, | |
5335 | { | |
5336 | .name = "ohci", | |
5337 | .pa_start = 0x4a064800, | |
5338 | .pa_end = 0x4a064bff, | |
5339 | }, | |
5340 | { | |
5341 | .name = "ehci", | |
5342 | .pa_start = 0x4a064c00, | |
5343 | .pa_end = 0x4a064fff, | |
5344 | }, | |
5345 | {} | |
5346 | }; | |
5347 | ||
5348 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
5349 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
5350 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
5351 | { .irq = -1 } | |
5352 | }; | |
5353 | ||
5354 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
5355 | .master = &omap44xx_l4_cfg_hwmod, | |
5356 | .slave = &omap44xx_usb_host_hs_hwmod, | |
5357 | .clk = "l4_div_ck", | |
5358 | .addr = omap44xx_usb_host_hs_addrs, | |
5359 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5360 | }; | |
5361 | ||
5362 | static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { | |
5363 | &omap44xx_l4_cfg__usb_host_hs, | |
5364 | }; | |
5365 | ||
5366 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { | |
5367 | .name = "usb_host_hs", | |
5368 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
5369 | .clkdm_name = "l3_init_clkdm", | |
5370 | .main_clk = "usb_host_hs_fck", | |
5371 | .prcm = { | |
5372 | .omap4 = { | |
5373 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, | |
5374 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
5375 | .modulemode = MODULEMODE_SWCTRL, | |
5376 | }, | |
5377 | }, | |
5378 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
5379 | .slaves = omap44xx_usb_host_hs_slaves, | |
5380 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), | |
5381 | .masters = omap44xx_usb_host_hs_masters, | |
5382 | .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), | |
5383 | ||
5384 | /* | |
5385 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
5386 | * id: i660 | |
5387 | * | |
5388 | * Description: | |
5389 | * In the following configuration : | |
5390 | * - USBHOST module is set to smart-idle mode | |
5391 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
5392 | * happens when the system is going to a low power mode : all ports | |
5393 | * have been suspended, the master part of the USBHOST module has | |
5394 | * entered the standby state, and SW has cut the functional clocks) | |
5395 | * - an USBHOST interrupt occurs before the module is able to answer | |
5396 | * idle_ack, typically a remote wakeup IRQ. | |
5397 | * Then the USB HOST module will enter a deadlock situation where it | |
5398 | * is no more accessible nor functional. | |
5399 | * | |
5400 | * Workaround: | |
5401 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
5402 | */ | |
5403 | ||
5404 | /* | |
5405 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
5406 | * Id: i571 | |
5407 | * | |
5408 | * Description: | |
5409 | * When the USBHOST module is set to smart-standby mode, and when it is | |
5410 | * ready to enter the standby state (i.e. all ports are suspended and | |
5411 | * all attached devices are in suspend mode), then it can wrongly assert | |
5412 | * the Mstandby signal too early while there are still some residual OCP | |
5413 | * transactions ongoing. If this condition occurs, the internal state | |
5414 | * machine may go to an undefined state and the USB link may be stuck | |
5415 | * upon the next resume. | |
5416 | * | |
5417 | * Workaround: | |
5418 | * Don't use smart standby; use only force standby, | |
5419 | * hence HWMOD_SWSUP_MSTANDBY | |
5420 | */ | |
5421 | ||
5422 | /* | |
5423 | * During system boot; If the hwmod framework resets the module | |
5424 | * the module will have smart idle settings; which can lead to deadlock | |
5425 | * (above Errata Id:i660); so, dont reset the module during boot; | |
5426 | * Use HWMOD_INIT_NO_RESET. | |
5427 | */ | |
5428 | ||
5429 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
5430 | HWMOD_INIT_NO_RESET, | |
5431 | }; | |
5432 | ||
5433 | /* | |
5434 | * 'usb_tll_hs' class | |
5435 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
5436 | */ | |
5437 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
5438 | .rev_offs = 0x0000, | |
5439 | .sysc_offs = 0x0010, | |
5440 | .syss_offs = 0x0014, | |
5441 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
5442 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
5443 | SYSC_HAS_AUTOIDLE), | |
5444 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
5445 | .sysc_fields = &omap_hwmod_sysc_type1, | |
5446 | }; | |
5447 | ||
5448 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
5449 | .name = "usb_tll_hs", | |
5450 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
5451 | }; | |
5452 | ||
5453 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
5454 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
5455 | { .irq = -1 } | |
5456 | }; | |
5457 | ||
5458 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
5459 | { | |
5460 | .name = "tll", | |
5461 | .pa_start = 0x4a062000, | |
5462 | .pa_end = 0x4a063fff, | |
5463 | .flags = ADDR_TYPE_RT | |
5464 | }, | |
5465 | {} | |
5466 | }; | |
5467 | ||
5468 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { | |
5469 | .master = &omap44xx_l4_cfg_hwmod, | |
5470 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
5471 | .clk = "l4_div_ck", | |
5472 | .addr = omap44xx_usb_tll_hs_addrs, | |
5473 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5474 | }; | |
5475 | ||
5476 | static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { | |
5477 | &omap44xx_l4_cfg__usb_tll_hs, | |
5478 | }; | |
5479 | ||
5480 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
5481 | .name = "usb_tll_hs", | |
5482 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
5483 | .clkdm_name = "l3_init_clkdm", | |
5484 | .main_clk = "usb_tll_hs_ick", | |
5485 | .prcm = { | |
5486 | .omap4 = { | |
5487 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
5488 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
5489 | .modulemode = MODULEMODE_HWCTRL, | |
5490 | }, | |
5491 | }, | |
5492 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
5493 | .slaves = omap44xx_usb_tll_hs_slaves, | |
5494 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), | |
5495 | }; | |
5496 | ||
55d2cb08 | 5497 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
fe13471c | 5498 | |
55d2cb08 BC |
5499 | /* dmm class */ |
5500 | &omap44xx_dmm_hwmod, | |
3b54baad | 5501 | |
55d2cb08 BC |
5502 | /* emif_fw class */ |
5503 | &omap44xx_emif_fw_hwmod, | |
3b54baad | 5504 | |
55d2cb08 BC |
5505 | /* l3 class */ |
5506 | &omap44xx_l3_instr_hwmod, | |
5507 | &omap44xx_l3_main_1_hwmod, | |
5508 | &omap44xx_l3_main_2_hwmod, | |
5509 | &omap44xx_l3_main_3_hwmod, | |
3b54baad | 5510 | |
55d2cb08 BC |
5511 | /* l4 class */ |
5512 | &omap44xx_l4_abe_hwmod, | |
5513 | &omap44xx_l4_cfg_hwmod, | |
5514 | &omap44xx_l4_per_hwmod, | |
5515 | &omap44xx_l4_wkup_hwmod, | |
531ce0d5 | 5516 | |
55d2cb08 BC |
5517 | /* mpu_bus class */ |
5518 | &omap44xx_mpu_private_hwmod, | |
5519 | ||
407a6888 BC |
5520 | /* aess class */ |
5521 | /* &omap44xx_aess_hwmod, */ | |
5522 | ||
5523 | /* bandgap class */ | |
5524 | &omap44xx_bandgap_hwmod, | |
5525 | ||
5526 | /* counter class */ | |
5527 | /* &omap44xx_counter_32k_hwmod, */ | |
5528 | ||
d7cf5f33 BC |
5529 | /* dma class */ |
5530 | &omap44xx_dma_system_hwmod, | |
5531 | ||
8ca476da BC |
5532 | /* dmic class */ |
5533 | &omap44xx_dmic_hwmod, | |
5534 | ||
8f25bdc5 BC |
5535 | /* dsp class */ |
5536 | &omap44xx_dsp_hwmod, | |
5537 | &omap44xx_dsp_c0_hwmod, | |
5538 | ||
d63bd74f BC |
5539 | /* dss class */ |
5540 | &omap44xx_dss_hwmod, | |
5541 | &omap44xx_dss_dispc_hwmod, | |
5542 | &omap44xx_dss_dsi1_hwmod, | |
5543 | &omap44xx_dss_dsi2_hwmod, | |
5544 | &omap44xx_dss_hdmi_hwmod, | |
5545 | &omap44xx_dss_rfbi_hwmod, | |
5546 | &omap44xx_dss_venc_hwmod, | |
5547 | ||
9780a9cf BC |
5548 | /* gpio class */ |
5549 | &omap44xx_gpio1_hwmod, | |
5550 | &omap44xx_gpio2_hwmod, | |
5551 | &omap44xx_gpio3_hwmod, | |
5552 | &omap44xx_gpio4_hwmod, | |
5553 | &omap44xx_gpio5_hwmod, | |
5554 | &omap44xx_gpio6_hwmod, | |
5555 | ||
407a6888 BC |
5556 | /* hsi class */ |
5557 | /* &omap44xx_hsi_hwmod, */ | |
5558 | ||
3b54baad BC |
5559 | /* i2c class */ |
5560 | &omap44xx_i2c1_hwmod, | |
5561 | &omap44xx_i2c2_hwmod, | |
5562 | &omap44xx_i2c3_hwmod, | |
5563 | &omap44xx_i2c4_hwmod, | |
5564 | ||
407a6888 BC |
5565 | /* ipu class */ |
5566 | &omap44xx_ipu_hwmod, | |
5567 | &omap44xx_ipu_c0_hwmod, | |
5568 | &omap44xx_ipu_c1_hwmod, | |
5569 | ||
5570 | /* iss class */ | |
5571 | /* &omap44xx_iss_hwmod, */ | |
5572 | ||
8f25bdc5 BC |
5573 | /* iva class */ |
5574 | &omap44xx_iva_hwmod, | |
5575 | &omap44xx_iva_seq0_hwmod, | |
5576 | &omap44xx_iva_seq1_hwmod, | |
5577 | ||
407a6888 | 5578 | /* kbd class */ |
4998b245 | 5579 | &omap44xx_kbd_hwmod, |
407a6888 | 5580 | |
ec5df927 BC |
5581 | /* mailbox class */ |
5582 | &omap44xx_mailbox_hwmod, | |
5583 | ||
4ddff493 BC |
5584 | /* mcbsp class */ |
5585 | &omap44xx_mcbsp1_hwmod, | |
5586 | &omap44xx_mcbsp2_hwmod, | |
5587 | &omap44xx_mcbsp3_hwmod, | |
5588 | &omap44xx_mcbsp4_hwmod, | |
5589 | ||
407a6888 | 5590 | /* mcpdm class */ |
d05e2ea8 | 5591 | &omap44xx_mcpdm_hwmod, |
407a6888 | 5592 | |
9bcbd7f0 BC |
5593 | /* mcspi class */ |
5594 | &omap44xx_mcspi1_hwmod, | |
5595 | &omap44xx_mcspi2_hwmod, | |
5596 | &omap44xx_mcspi3_hwmod, | |
5597 | &omap44xx_mcspi4_hwmod, | |
5598 | ||
407a6888 | 5599 | /* mmc class */ |
17203bda AG |
5600 | &omap44xx_mmc1_hwmod, |
5601 | &omap44xx_mmc2_hwmod, | |
5602 | &omap44xx_mmc3_hwmod, | |
5603 | &omap44xx_mmc4_hwmod, | |
5604 | &omap44xx_mmc5_hwmod, | |
407a6888 | 5605 | |
55d2cb08 BC |
5606 | /* mpu class */ |
5607 | &omap44xx_mpu_hwmod, | |
db12ba53 | 5608 | |
1f6a717f BC |
5609 | /* smartreflex class */ |
5610 | &omap44xx_smartreflex_core_hwmod, | |
5611 | &omap44xx_smartreflex_iva_hwmod, | |
5612 | &omap44xx_smartreflex_mpu_hwmod, | |
5613 | ||
d11c217f BC |
5614 | /* spinlock class */ |
5615 | &omap44xx_spinlock_hwmod, | |
5616 | ||
35d1a66a BC |
5617 | /* timer class */ |
5618 | &omap44xx_timer1_hwmod, | |
5619 | &omap44xx_timer2_hwmod, | |
5620 | &omap44xx_timer3_hwmod, | |
5621 | &omap44xx_timer4_hwmod, | |
5622 | &omap44xx_timer5_hwmod, | |
5623 | &omap44xx_timer6_hwmod, | |
5624 | &omap44xx_timer7_hwmod, | |
5625 | &omap44xx_timer8_hwmod, | |
5626 | &omap44xx_timer9_hwmod, | |
5627 | &omap44xx_timer10_hwmod, | |
5628 | &omap44xx_timer11_hwmod, | |
5629 | ||
db12ba53 BC |
5630 | /* uart class */ |
5631 | &omap44xx_uart1_hwmod, | |
5632 | &omap44xx_uart2_hwmod, | |
5633 | &omap44xx_uart3_hwmod, | |
5634 | &omap44xx_uart4_hwmod, | |
3b54baad | 5635 | |
af88fa9a BC |
5636 | /* usb host class */ |
5637 | &omap44xx_usb_host_hs_hwmod, | |
5638 | &omap44xx_usb_tll_hs_hwmod, | |
5639 | ||
5844c4ea BC |
5640 | /* usb_otg_hs class */ |
5641 | &omap44xx_usb_otg_hs_hwmod, | |
5642 | ||
3b54baad BC |
5643 | /* wd_timer class */ |
5644 | &omap44xx_wd_timer2_hwmod, | |
5645 | &omap44xx_wd_timer3_hwmod, | |
55d2cb08 BC |
5646 | NULL, |
5647 | }; | |
5648 | ||
5649 | int __init omap44xx_hwmod_init(void) | |
5650 | { | |
550c8092 | 5651 | return omap_hwmod_register(omap44xx_hwmods); |
55d2cb08 BC |
5652 | } |
5653 |