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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
6d3c55fd | 25 | #include <plat/i2c.h> |
9780a9cf | 26 | #include <plat/gpio.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
c345c8b0 | 31 | #include <plat/dmtimer.h> |
13662dc5 | 32 | #include <plat/common.h> |
55d2cb08 BC |
33 | |
34 | #include "omap_hwmod_common_data.h" | |
35 | ||
cea6b942 | 36 | #include "smartreflex.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
ff2516fb | 41 | #include "wd_timer.h" |
55d2cb08 BC |
42 | |
43 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
44 | #define OMAP44XX_IRQ_GIC_START 32 | |
45 | ||
46 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 47 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
48 | |
49 | /* | |
844a3b63 | 50 | * IP blocks |
55d2cb08 BC |
51 | */ |
52 | ||
42b9e387 PW |
53 | /* |
54 | * 'c2c_target_fw' class | |
55 | * instance(s): c2c_target_fw | |
56 | */ | |
57 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | |
58 | .name = "c2c_target_fw", | |
59 | }; | |
60 | ||
61 | /* c2c_target_fw */ | |
62 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | |
63 | .name = "c2c_target_fw", | |
64 | .class = &omap44xx_c2c_target_fw_hwmod_class, | |
65 | .clkdm_name = "d2d_clkdm", | |
66 | .prcm = { | |
67 | .omap4 = { | |
68 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | |
69 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | |
70 | }, | |
71 | }, | |
72 | }; | |
73 | ||
55d2cb08 BC |
74 | /* |
75 | * 'dmm' class | |
76 | * instance(s): dmm | |
77 | */ | |
78 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 79 | .name = "dmm", |
55d2cb08 BC |
80 | }; |
81 | ||
7e69ed97 BC |
82 | /* dmm */ |
83 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
84 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
85 | { .irq = -1 } | |
86 | }; | |
87 | ||
55d2cb08 BC |
88 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
89 | .name = "dmm", | |
90 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 91 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 92 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
93 | .prcm = { |
94 | .omap4 = { | |
95 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 96 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
97 | }, |
98 | }, | |
55d2cb08 BC |
99 | }; |
100 | ||
101 | /* | |
102 | * 'emif_fw' class | |
103 | * instance(s): emif_fw | |
104 | */ | |
105 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 106 | .name = "emif_fw", |
55d2cb08 BC |
107 | }; |
108 | ||
7e69ed97 | 109 | /* emif_fw */ |
55d2cb08 BC |
110 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
111 | .name = "emif_fw", | |
112 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 113 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
114 | .prcm = { |
115 | .omap4 = { | |
116 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 117 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
118 | }, |
119 | }, | |
55d2cb08 BC |
120 | }; |
121 | ||
122 | /* | |
123 | * 'l3' class | |
124 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
125 | */ | |
126 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 127 | .name = "l3", |
55d2cb08 BC |
128 | }; |
129 | ||
7e69ed97 | 130 | /* l3_instr */ |
55d2cb08 BC |
131 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
132 | .name = "l3_instr", | |
133 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 134 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
135 | .prcm = { |
136 | .omap4 = { | |
137 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 138 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 139 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
140 | }, |
141 | }, | |
55d2cb08 BC |
142 | }; |
143 | ||
7e69ed97 | 144 | /* l3_main_1 */ |
9b4021be BC |
145 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
146 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
147 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
148 | { .irq = -1 } | |
149 | }; | |
150 | ||
55d2cb08 BC |
151 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
152 | .name = "l3_main_1", | |
153 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 154 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 155 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
156 | .prcm = { |
157 | .omap4 = { | |
158 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 159 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
160 | }, |
161 | }, | |
55d2cb08 BC |
162 | }; |
163 | ||
7e69ed97 | 164 | /* l3_main_2 */ |
55d2cb08 BC |
165 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
166 | .name = "l3_main_2", | |
167 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 168 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
169 | .prcm = { |
170 | .omap4 = { | |
171 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 172 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
173 | }, |
174 | }, | |
55d2cb08 BC |
175 | }; |
176 | ||
7e69ed97 | 177 | /* l3_main_3 */ |
55d2cb08 BC |
178 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
179 | .name = "l3_main_3", | |
180 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 181 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
182 | .prcm = { |
183 | .omap4 = { | |
184 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 185 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 186 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
187 | }, |
188 | }, | |
55d2cb08 BC |
189 | }; |
190 | ||
191 | /* | |
192 | * 'l4' class | |
193 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
194 | */ | |
195 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 196 | .name = "l4", |
55d2cb08 BC |
197 | }; |
198 | ||
7e69ed97 | 199 | /* l4_abe */ |
55d2cb08 BC |
200 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
201 | .name = "l4_abe", | |
202 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 203 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
204 | .prcm = { |
205 | .omap4 = { | |
206 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
207 | }, | |
208 | }, | |
55d2cb08 BC |
209 | }; |
210 | ||
7e69ed97 | 211 | /* l4_cfg */ |
55d2cb08 BC |
212 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
213 | .name = "l4_cfg", | |
214 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 215 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
216 | .prcm = { |
217 | .omap4 = { | |
218 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 219 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
220 | }, |
221 | }, | |
55d2cb08 BC |
222 | }; |
223 | ||
7e69ed97 | 224 | /* l4_per */ |
55d2cb08 BC |
225 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
226 | .name = "l4_per", | |
227 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 228 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
229 | .prcm = { |
230 | .omap4 = { | |
231 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 232 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
233 | }, |
234 | }, | |
55d2cb08 BC |
235 | }; |
236 | ||
7e69ed97 | 237 | /* l4_wkup */ |
55d2cb08 BC |
238 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
239 | .name = "l4_wkup", | |
240 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 241 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
242 | .prcm = { |
243 | .omap4 = { | |
244 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 245 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
246 | }, |
247 | }, | |
55d2cb08 BC |
248 | }; |
249 | ||
f776471f | 250 | /* |
3b54baad BC |
251 | * 'mpu_bus' class |
252 | * instance(s): mpu_private | |
f776471f | 253 | */ |
3b54baad | 254 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 255 | .name = "mpu_bus", |
3b54baad | 256 | }; |
f776471f | 257 | |
7e69ed97 | 258 | /* mpu_private */ |
3b54baad BC |
259 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
260 | .name = "mpu_private", | |
261 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 262 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
263 | }; |
264 | ||
265 | /* | |
266 | * Modules omap_hwmod structures | |
267 | * | |
268 | * The following IPs are excluded for the moment because: | |
269 | * - They do not need an explicit SW control using omap_hwmod API. | |
270 | * - They still need to be validated with the driver | |
271 | * properly adapted to omap_hwmod / omap_device | |
272 | * | |
3b54baad BC |
273 | * cm_core |
274 | * cm_core_aon | |
3b54baad BC |
275 | * ctrl_module_core |
276 | * ctrl_module_pad_core | |
277 | * ctrl_module_pad_wkup | |
278 | * ctrl_module_wkup | |
279 | * debugss | |
3b54baad BC |
280 | * efuse_ctrl_cust |
281 | * efuse_ctrl_std | |
00fe610b BC |
282 | * mpu_c0 |
283 | * mpu_c1 | |
3b54baad | 284 | * ocp_wp_noc |
3b54baad BC |
285 | * prcm_mpu |
286 | * prm | |
287 | * scrm | |
3b54baad | 288 | * usb_phy_cm |
3b54baad BC |
289 | * usim |
290 | */ | |
291 | ||
407a6888 BC |
292 | /* |
293 | * 'aess' class | |
294 | * audio engine sub system | |
295 | */ | |
296 | ||
297 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
298 | .rev_offs = 0x0000, | |
299 | .sysc_offs = 0x0010, | |
300 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
301 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
302 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
303 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
304 | .sysc_fields = &omap_hwmod_sysc_type2, |
305 | }; | |
306 | ||
307 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
308 | .name = "aess", | |
309 | .sysc = &omap44xx_aess_sysc, | |
310 | }; | |
311 | ||
312 | /* aess */ | |
313 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
314 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 315 | { .irq = -1 } |
407a6888 BC |
316 | }; |
317 | ||
318 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
319 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
320 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
321 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
322 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
323 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
324 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
325 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
326 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 327 | { .dma_req = -1 } |
407a6888 BC |
328 | }; |
329 | ||
407a6888 BC |
330 | static struct omap_hwmod omap44xx_aess_hwmod = { |
331 | .name = "aess", | |
332 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 333 | .clkdm_name = "abe_clkdm", |
407a6888 | 334 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 335 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 336 | .main_clk = "aess_fck", |
00fe610b | 337 | .prcm = { |
407a6888 | 338 | .omap4 = { |
d0f0631d | 339 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 340 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 341 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
342 | }, |
343 | }, | |
407a6888 BC |
344 | }; |
345 | ||
42b9e387 PW |
346 | /* |
347 | * 'c2c' class | |
348 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
349 | * soc | |
350 | */ | |
351 | ||
352 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
353 | .name = "c2c", | |
354 | }; | |
355 | ||
356 | /* c2c */ | |
357 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | |
358 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | |
359 | { .irq = -1 } | |
360 | }; | |
361 | ||
362 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | |
363 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | |
364 | { .dma_req = -1 } | |
365 | }; | |
366 | ||
367 | static struct omap_hwmod omap44xx_c2c_hwmod = { | |
368 | .name = "c2c", | |
369 | .class = &omap44xx_c2c_hwmod_class, | |
370 | .clkdm_name = "d2d_clkdm", | |
371 | .mpu_irqs = omap44xx_c2c_irqs, | |
372 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | |
373 | .prcm = { | |
374 | .omap4 = { | |
375 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
376 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
377 | }, | |
378 | }, | |
379 | }; | |
380 | ||
407a6888 BC |
381 | /* |
382 | * 'counter' class | |
383 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
384 | */ | |
385 | ||
386 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
387 | .rev_offs = 0x0000, | |
388 | .sysc_offs = 0x0004, | |
389 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
390 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
391 | SIDLE_SMART_WKUP), | |
392 | .sysc_fields = &omap_hwmod_sysc_type1, | |
393 | }; | |
394 | ||
395 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
396 | .name = "counter", | |
397 | .sysc = &omap44xx_counter_sysc, | |
398 | }; | |
399 | ||
400 | /* counter_32k */ | |
407a6888 BC |
401 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
402 | .name = "counter_32k", | |
403 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 404 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
405 | .flags = HWMOD_SWSUP_SIDLE, |
406 | .main_clk = "sys_32k_ck", | |
00fe610b | 407 | .prcm = { |
407a6888 | 408 | .omap4 = { |
d0f0631d | 409 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 410 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
411 | }, |
412 | }, | |
407a6888 BC |
413 | }; |
414 | ||
d7cf5f33 BC |
415 | /* |
416 | * 'dma' class | |
417 | * dma controller for data exchange between memory to memory (i.e. internal or | |
418 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
419 | */ | |
420 | ||
421 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
422 | .rev_offs = 0x0000, | |
423 | .sysc_offs = 0x002c, | |
424 | .syss_offs = 0x0028, | |
425 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
426 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
427 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
428 | SYSS_HAS_RESET_STATUS), | |
429 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
430 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
431 | .sysc_fields = &omap_hwmod_sysc_type1, | |
432 | }; | |
433 | ||
434 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
435 | .name = "dma", | |
436 | .sysc = &omap44xx_dma_sysc, | |
437 | }; | |
438 | ||
439 | /* dma dev_attr */ | |
440 | static struct omap_dma_dev_attr dma_dev_attr = { | |
441 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
442 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
443 | .lch_count = 32, | |
444 | }; | |
445 | ||
446 | /* dma_system */ | |
447 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
448 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
449 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
450 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
451 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 452 | { .irq = -1 } |
d7cf5f33 BC |
453 | }; |
454 | ||
d7cf5f33 BC |
455 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
456 | .name = "dma_system", | |
457 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 458 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 459 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
460 | .main_clk = "l3_div_ck", |
461 | .prcm = { | |
462 | .omap4 = { | |
d0f0631d | 463 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 464 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
465 | }, |
466 | }, | |
467 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
468 | }; |
469 | ||
8ca476da BC |
470 | /* |
471 | * 'dmic' class | |
472 | * digital microphone controller | |
473 | */ | |
474 | ||
475 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
476 | .rev_offs = 0x0000, | |
477 | .sysc_offs = 0x0010, | |
478 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
479 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
480 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
481 | SIDLE_SMART_WKUP), | |
482 | .sysc_fields = &omap_hwmod_sysc_type2, | |
483 | }; | |
484 | ||
485 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
486 | .name = "dmic", | |
487 | .sysc = &omap44xx_dmic_sysc, | |
488 | }; | |
489 | ||
490 | /* dmic */ | |
8ca476da BC |
491 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
492 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 493 | { .irq = -1 } |
8ca476da BC |
494 | }; |
495 | ||
496 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
497 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 498 | { .dma_req = -1 } |
8ca476da BC |
499 | }; |
500 | ||
8ca476da BC |
501 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
502 | .name = "dmic", | |
503 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 504 | .clkdm_name = "abe_clkdm", |
8ca476da | 505 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 506 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 507 | .main_clk = "dmic_fck", |
00fe610b | 508 | .prcm = { |
8ca476da | 509 | .omap4 = { |
d0f0631d | 510 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 511 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 512 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
513 | }, |
514 | }, | |
8ca476da BC |
515 | }; |
516 | ||
8f25bdc5 BC |
517 | /* |
518 | * 'dsp' class | |
519 | * dsp sub-system | |
520 | */ | |
521 | ||
522 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 523 | .name = "dsp", |
8f25bdc5 BC |
524 | }; |
525 | ||
526 | /* dsp */ | |
527 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
528 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 529 | { .irq = -1 } |
8f25bdc5 BC |
530 | }; |
531 | ||
532 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 | 533 | { .name = "dsp", .rst_shift = 0 }, |
f2f5736c | 534 | { .name = "mmu_cache", .rst_shift = 1 }, |
8f25bdc5 BC |
535 | }; |
536 | ||
8f25bdc5 BC |
537 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
538 | .name = "dsp", | |
539 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 540 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 541 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
542 | .rst_lines = omap44xx_dsp_resets, |
543 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
544 | .main_clk = "dsp_fck", | |
545 | .prcm = { | |
546 | .omap4 = { | |
d0f0631d | 547 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 548 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 549 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 550 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
551 | }, |
552 | }, | |
8f25bdc5 BC |
553 | }; |
554 | ||
d63bd74f BC |
555 | /* |
556 | * 'dss' class | |
557 | * display sub-system | |
558 | */ | |
559 | ||
560 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
561 | .rev_offs = 0x0000, | |
562 | .syss_offs = 0x0014, | |
563 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
564 | }; | |
565 | ||
566 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
567 | .name = "dss", | |
568 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 569 | .reset = omap_dss_reset, |
d63bd74f BC |
570 | }; |
571 | ||
572 | /* dss */ | |
d63bd74f BC |
573 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
574 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
575 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 576 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
577 | }; |
578 | ||
579 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
580 | .name = "dss_core", | |
37ad0855 | 581 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 582 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 583 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 584 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
585 | .prcm = { |
586 | .omap4 = { | |
d0f0631d | 587 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 588 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
589 | }, |
590 | }, | |
591 | .opt_clks = dss_opt_clks, | |
592 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
593 | }; |
594 | ||
595 | /* | |
596 | * 'dispc' class | |
597 | * display controller | |
598 | */ | |
599 | ||
600 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
601 | .rev_offs = 0x0000, | |
602 | .sysc_offs = 0x0010, | |
603 | .syss_offs = 0x0014, | |
604 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
605 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
606 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
607 | SYSS_HAS_RESET_STATUS), | |
608 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
609 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
610 | .sysc_fields = &omap_hwmod_sysc_type1, | |
611 | }; | |
612 | ||
613 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
614 | .name = "dispc", | |
615 | .sysc = &omap44xx_dispc_sysc, | |
616 | }; | |
617 | ||
618 | /* dss_dispc */ | |
d63bd74f BC |
619 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
620 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 621 | { .irq = -1 } |
d63bd74f BC |
622 | }; |
623 | ||
624 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
625 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 626 | { .dma_req = -1 } |
d63bd74f BC |
627 | }; |
628 | ||
b923d40d AT |
629 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
630 | .manager_count = 3, | |
631 | .has_framedonetv_irq = 1 | |
632 | }; | |
633 | ||
d63bd74f BC |
634 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
635 | .name = "dss_dispc", | |
636 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 637 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 638 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 639 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 640 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
641 | .prcm = { |
642 | .omap4 = { | |
d0f0631d | 643 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 644 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
645 | }, |
646 | }, | |
b923d40d | 647 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
648 | }; |
649 | ||
650 | /* | |
651 | * 'dsi' class | |
652 | * display serial interface controller | |
653 | */ | |
654 | ||
655 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
656 | .rev_offs = 0x0000, | |
657 | .sysc_offs = 0x0010, | |
658 | .syss_offs = 0x0014, | |
659 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
660 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
661 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
662 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
663 | .sysc_fields = &omap_hwmod_sysc_type1, | |
664 | }; | |
665 | ||
666 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
667 | .name = "dsi", | |
668 | .sysc = &omap44xx_dsi_sysc, | |
669 | }; | |
670 | ||
671 | /* dss_dsi1 */ | |
d63bd74f BC |
672 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
673 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 674 | { .irq = -1 } |
d63bd74f BC |
675 | }; |
676 | ||
677 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
678 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 679 | { .dma_req = -1 } |
d63bd74f BC |
680 | }; |
681 | ||
3a23aafc TV |
682 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
683 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
684 | }; | |
685 | ||
d63bd74f BC |
686 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
687 | .name = "dss_dsi1", | |
688 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 689 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 690 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 691 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 692 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
693 | .prcm = { |
694 | .omap4 = { | |
d0f0631d | 695 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 696 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
697 | }, |
698 | }, | |
3a23aafc TV |
699 | .opt_clks = dss_dsi1_opt_clks, |
700 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
701 | }; |
702 | ||
703 | /* dss_dsi2 */ | |
d63bd74f BC |
704 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
705 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 706 | { .irq = -1 } |
d63bd74f BC |
707 | }; |
708 | ||
709 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
710 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 711 | { .dma_req = -1 } |
d63bd74f BC |
712 | }; |
713 | ||
3a23aafc TV |
714 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
715 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
716 | }; | |
717 | ||
d63bd74f BC |
718 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
719 | .name = "dss_dsi2", | |
720 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 721 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 722 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 723 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 724 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
725 | .prcm = { |
726 | .omap4 = { | |
d0f0631d | 727 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 728 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
729 | }, |
730 | }, | |
3a23aafc TV |
731 | .opt_clks = dss_dsi2_opt_clks, |
732 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
733 | }; |
734 | ||
735 | /* | |
736 | * 'hdmi' class | |
737 | * hdmi controller | |
738 | */ | |
739 | ||
740 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
741 | .rev_offs = 0x0000, | |
742 | .sysc_offs = 0x0010, | |
743 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
744 | SYSC_HAS_SOFTRESET), | |
745 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
746 | SIDLE_SMART_WKUP), | |
747 | .sysc_fields = &omap_hwmod_sysc_type2, | |
748 | }; | |
749 | ||
750 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
751 | .name = "hdmi", | |
752 | .sysc = &omap44xx_hdmi_sysc, | |
753 | }; | |
754 | ||
755 | /* dss_hdmi */ | |
d63bd74f BC |
756 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
757 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 758 | { .irq = -1 } |
d63bd74f BC |
759 | }; |
760 | ||
761 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
762 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 763 | { .dma_req = -1 } |
d63bd74f BC |
764 | }; |
765 | ||
3a23aafc TV |
766 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
767 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
768 | }; | |
769 | ||
d63bd74f BC |
770 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
771 | .name = "dss_hdmi", | |
772 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 773 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 774 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 775 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 776 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
777 | .prcm = { |
778 | .omap4 = { | |
d0f0631d | 779 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 780 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
781 | }, |
782 | }, | |
3a23aafc TV |
783 | .opt_clks = dss_hdmi_opt_clks, |
784 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
785 | }; |
786 | ||
787 | /* | |
788 | * 'rfbi' class | |
789 | * remote frame buffer interface | |
790 | */ | |
791 | ||
792 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
793 | .rev_offs = 0x0000, | |
794 | .sysc_offs = 0x0010, | |
795 | .syss_offs = 0x0014, | |
796 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
797 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
798 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
799 | .sysc_fields = &omap_hwmod_sysc_type1, | |
800 | }; | |
801 | ||
802 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
803 | .name = "rfbi", | |
804 | .sysc = &omap44xx_rfbi_sysc, | |
805 | }; | |
806 | ||
807 | /* dss_rfbi */ | |
d63bd74f BC |
808 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
809 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 810 | { .dma_req = -1 } |
d63bd74f BC |
811 | }; |
812 | ||
3a23aafc TV |
813 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
814 | { .role = "ick", .clk = "dss_fck" }, | |
815 | }; | |
816 | ||
d63bd74f BC |
817 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
818 | .name = "dss_rfbi", | |
819 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 820 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 821 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 822 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
823 | .prcm = { |
824 | .omap4 = { | |
d0f0631d | 825 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 826 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
827 | }, |
828 | }, | |
3a23aafc TV |
829 | .opt_clks = dss_rfbi_opt_clks, |
830 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
831 | }; |
832 | ||
833 | /* | |
834 | * 'venc' class | |
835 | * video encoder | |
836 | */ | |
837 | ||
838 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
839 | .name = "venc", | |
840 | }; | |
841 | ||
842 | /* dss_venc */ | |
d63bd74f BC |
843 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
844 | .name = "dss_venc", | |
845 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 846 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 847 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
848 | .prcm = { |
849 | .omap4 = { | |
d0f0631d | 850 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 851 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
852 | }, |
853 | }, | |
d63bd74f BC |
854 | }; |
855 | ||
42b9e387 PW |
856 | /* |
857 | * 'elm' class | |
858 | * bch error location module | |
859 | */ | |
860 | ||
861 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
862 | .rev_offs = 0x0000, | |
863 | .sysc_offs = 0x0010, | |
864 | .syss_offs = 0x0014, | |
865 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
866 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
867 | SYSS_HAS_RESET_STATUS), | |
868 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
869 | .sysc_fields = &omap_hwmod_sysc_type1, | |
870 | }; | |
871 | ||
872 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
873 | .name = "elm", | |
874 | .sysc = &omap44xx_elm_sysc, | |
875 | }; | |
876 | ||
877 | /* elm */ | |
878 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | |
879 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | |
880 | { .irq = -1 } | |
881 | }; | |
882 | ||
883 | static struct omap_hwmod omap44xx_elm_hwmod = { | |
884 | .name = "elm", | |
885 | .class = &omap44xx_elm_hwmod_class, | |
886 | .clkdm_name = "l4_per_clkdm", | |
887 | .mpu_irqs = omap44xx_elm_irqs, | |
888 | .prcm = { | |
889 | .omap4 = { | |
890 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
891 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
892 | }, | |
893 | }, | |
894 | }; | |
895 | ||
bf30f950 PW |
896 | /* |
897 | * 'emif' class | |
898 | * external memory interface no1 | |
899 | */ | |
900 | ||
901 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
902 | .rev_offs = 0x0000, | |
903 | }; | |
904 | ||
905 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
906 | .name = "emif", | |
907 | .sysc = &omap44xx_emif_sysc, | |
908 | }; | |
909 | ||
910 | /* emif1 */ | |
911 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | |
912 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | |
913 | { .irq = -1 } | |
914 | }; | |
915 | ||
916 | static struct omap_hwmod omap44xx_emif1_hwmod = { | |
917 | .name = "emif1", | |
918 | .class = &omap44xx_emif_hwmod_class, | |
919 | .clkdm_name = "l3_emif_clkdm", | |
920 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
921 | .mpu_irqs = omap44xx_emif1_irqs, | |
922 | .main_clk = "ddrphy_ck", | |
923 | .prcm = { | |
924 | .omap4 = { | |
925 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
926 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
927 | .modulemode = MODULEMODE_HWCTRL, | |
928 | }, | |
929 | }, | |
930 | }; | |
931 | ||
932 | /* emif2 */ | |
933 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | |
934 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | |
935 | { .irq = -1 } | |
936 | }; | |
937 | ||
938 | static struct omap_hwmod omap44xx_emif2_hwmod = { | |
939 | .name = "emif2", | |
940 | .class = &omap44xx_emif_hwmod_class, | |
941 | .clkdm_name = "l3_emif_clkdm", | |
942 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
943 | .mpu_irqs = omap44xx_emif2_irqs, | |
944 | .main_clk = "ddrphy_ck", | |
945 | .prcm = { | |
946 | .omap4 = { | |
947 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
948 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
949 | .modulemode = MODULEMODE_HWCTRL, | |
950 | }, | |
951 | }, | |
952 | }; | |
953 | ||
b050f688 ML |
954 | /* |
955 | * 'fdif' class | |
956 | * face detection hw accelerator module | |
957 | */ | |
958 | ||
959 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
960 | .rev_offs = 0x0000, | |
961 | .sysc_offs = 0x0010, | |
962 | /* | |
963 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
964 | * accessing sysconfig again. | |
965 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
966 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
967 | * | |
968 | * TODO: Indicate errata when available. | |
969 | */ | |
970 | .srst_udelay = 2, | |
971 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
972 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
973 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
974 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
975 | .sysc_fields = &omap_hwmod_sysc_type2, | |
976 | }; | |
977 | ||
978 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
979 | .name = "fdif", | |
980 | .sysc = &omap44xx_fdif_sysc, | |
981 | }; | |
982 | ||
983 | /* fdif */ | |
984 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
985 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
986 | { .irq = -1 } | |
987 | }; | |
988 | ||
989 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
990 | .name = "fdif", | |
991 | .class = &omap44xx_fdif_hwmod_class, | |
992 | .clkdm_name = "iss_clkdm", | |
993 | .mpu_irqs = omap44xx_fdif_irqs, | |
994 | .main_clk = "fdif_fck", | |
995 | .prcm = { | |
996 | .omap4 = { | |
997 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
998 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
999 | .modulemode = MODULEMODE_SWCTRL, | |
1000 | }, | |
1001 | }, | |
1002 | }; | |
1003 | ||
3b54baad BC |
1004 | /* |
1005 | * 'gpio' class | |
1006 | * general purpose io module | |
1007 | */ | |
1008 | ||
1009 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1010 | .rev_offs = 0x0000, | |
f776471f | 1011 | .sysc_offs = 0x0010, |
3b54baad | 1012 | .syss_offs = 0x0114, |
0cfe8751 BC |
1013 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1014 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1015 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1016 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1017 | SIDLE_SMART_WKUP), | |
f776471f BC |
1018 | .sysc_fields = &omap_hwmod_sysc_type1, |
1019 | }; | |
1020 | ||
3b54baad | 1021 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1022 | .name = "gpio", |
1023 | .sysc = &omap44xx_gpio_sysc, | |
1024 | .rev = 2, | |
f776471f BC |
1025 | }; |
1026 | ||
3b54baad BC |
1027 | /* gpio dev_attr */ |
1028 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1029 | .bank_width = 32, |
1030 | .dbck_flag = true, | |
f776471f BC |
1031 | }; |
1032 | ||
3b54baad | 1033 | /* gpio1 */ |
3b54baad BC |
1034 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1035 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1036 | { .irq = -1 } |
f776471f BC |
1037 | }; |
1038 | ||
3b54baad | 1039 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1040 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1041 | }; |
1042 | ||
1043 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1044 | .name = "gpio1", | |
1045 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1046 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1047 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1048 | .main_clk = "gpio1_ick", |
f776471f BC |
1049 | .prcm = { |
1050 | .omap4 = { | |
d0f0631d | 1051 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1052 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1053 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1054 | }, |
1055 | }, | |
3b54baad BC |
1056 | .opt_clks = gpio1_opt_clks, |
1057 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1058 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1059 | }; |
1060 | ||
3b54baad | 1061 | /* gpio2 */ |
3b54baad BC |
1062 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1063 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1064 | { .irq = -1 } |
f776471f BC |
1065 | }; |
1066 | ||
3b54baad | 1067 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1068 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1069 | }; |
1070 | ||
1071 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1072 | .name = "gpio2", | |
1073 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1074 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1075 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1076 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1077 | .main_clk = "gpio2_ick", |
f776471f BC |
1078 | .prcm = { |
1079 | .omap4 = { | |
d0f0631d | 1080 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1081 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1082 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1083 | }, |
1084 | }, | |
3b54baad BC |
1085 | .opt_clks = gpio2_opt_clks, |
1086 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1087 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1088 | }; |
1089 | ||
3b54baad | 1090 | /* gpio3 */ |
3b54baad BC |
1091 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1092 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1093 | { .irq = -1 } |
f776471f BC |
1094 | }; |
1095 | ||
3b54baad | 1096 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1097 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1098 | }; |
1099 | ||
1100 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1101 | .name = "gpio3", | |
1102 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1103 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1104 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1105 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1106 | .main_clk = "gpio3_ick", |
f776471f BC |
1107 | .prcm = { |
1108 | .omap4 = { | |
d0f0631d | 1109 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1110 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1111 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1112 | }, |
1113 | }, | |
3b54baad BC |
1114 | .opt_clks = gpio3_opt_clks, |
1115 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1116 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1117 | }; |
1118 | ||
3b54baad | 1119 | /* gpio4 */ |
3b54baad BC |
1120 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1121 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1122 | { .irq = -1 } |
f776471f BC |
1123 | }; |
1124 | ||
3b54baad | 1125 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1126 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1127 | }; |
1128 | ||
1129 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1130 | .name = "gpio4", | |
1131 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1132 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1133 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1134 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 1135 | .main_clk = "gpio4_ick", |
f776471f BC |
1136 | .prcm = { |
1137 | .omap4 = { | |
d0f0631d | 1138 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1139 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1140 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1141 | }, |
1142 | }, | |
3b54baad BC |
1143 | .opt_clks = gpio4_opt_clks, |
1144 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1145 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1146 | }; |
1147 | ||
3b54baad | 1148 | /* gpio5 */ |
3b54baad BC |
1149 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1150 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1151 | { .irq = -1 } |
55d2cb08 BC |
1152 | }; |
1153 | ||
844a3b63 PW |
1154 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1155 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1156 | }; |
1157 | ||
3b54baad BC |
1158 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1159 | .name = "gpio5", | |
1160 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1161 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1162 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1163 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 1164 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
1165 | .prcm = { |
1166 | .omap4 = { | |
d0f0631d | 1167 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1168 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1169 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1170 | }, |
1171 | }, | |
3b54baad BC |
1172 | .opt_clks = gpio5_opt_clks, |
1173 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1174 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1175 | }; |
1176 | ||
3b54baad | 1177 | /* gpio6 */ |
3b54baad BC |
1178 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1179 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1180 | { .irq = -1 } |
92b18d1c BC |
1181 | }; |
1182 | ||
3b54baad | 1183 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1184 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1185 | }; |
1186 | ||
3b54baad BC |
1187 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1188 | .name = "gpio6", | |
1189 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1190 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1191 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1192 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
1193 | .main_clk = "gpio6_ick", |
1194 | .prcm = { | |
1195 | .omap4 = { | |
d0f0631d | 1196 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1197 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1198 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1199 | }, |
db12ba53 | 1200 | }, |
3b54baad BC |
1201 | .opt_clks = gpio6_opt_clks, |
1202 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1203 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1204 | }; |
1205 | ||
eb42b5d3 BC |
1206 | /* |
1207 | * 'gpmc' class | |
1208 | * general purpose memory controller | |
1209 | */ | |
1210 | ||
1211 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1212 | .rev_offs = 0x0000, | |
1213 | .sysc_offs = 0x0010, | |
1214 | .syss_offs = 0x0014, | |
1215 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1216 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1217 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1218 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1219 | }; | |
1220 | ||
1221 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1222 | .name = "gpmc", | |
1223 | .sysc = &omap44xx_gpmc_sysc, | |
1224 | }; | |
1225 | ||
1226 | /* gpmc */ | |
1227 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1228 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1229 | { .irq = -1 } | |
1230 | }; | |
1231 | ||
1232 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1233 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1234 | { .dma_req = -1 } | |
1235 | }; | |
1236 | ||
1237 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1238 | .name = "gpmc", | |
1239 | .class = &omap44xx_gpmc_hwmod_class, | |
1240 | .clkdm_name = "l3_2_clkdm", | |
1241 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1242 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1243 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1244 | .prcm = { | |
1245 | .omap4 = { | |
1246 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1247 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1248 | .modulemode = MODULEMODE_HWCTRL, | |
1249 | }, | |
1250 | }, | |
1251 | }; | |
1252 | ||
9def390e PW |
1253 | /* |
1254 | * 'gpu' class | |
1255 | * 2d/3d graphics accelerator | |
1256 | */ | |
1257 | ||
1258 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1259 | .rev_offs = 0x1fc00, | |
1260 | .sysc_offs = 0x1fc10, | |
1261 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1262 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1263 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1264 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1265 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1266 | }; | |
1267 | ||
1268 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1269 | .name = "gpu", | |
1270 | .sysc = &omap44xx_gpu_sysc, | |
1271 | }; | |
1272 | ||
1273 | /* gpu */ | |
1274 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | |
1275 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | |
1276 | { .irq = -1 } | |
1277 | }; | |
1278 | ||
1279 | static struct omap_hwmod omap44xx_gpu_hwmod = { | |
1280 | .name = "gpu", | |
1281 | .class = &omap44xx_gpu_hwmod_class, | |
1282 | .clkdm_name = "l3_gfx_clkdm", | |
1283 | .mpu_irqs = omap44xx_gpu_irqs, | |
1284 | .main_clk = "gpu_fck", | |
1285 | .prcm = { | |
1286 | .omap4 = { | |
1287 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1288 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1289 | .modulemode = MODULEMODE_SWCTRL, | |
1290 | }, | |
1291 | }, | |
1292 | }; | |
1293 | ||
a091c08e PW |
1294 | /* |
1295 | * 'hdq1w' class | |
1296 | * hdq / 1-wire serial interface controller | |
1297 | */ | |
1298 | ||
1299 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1300 | .rev_offs = 0x0000, | |
1301 | .sysc_offs = 0x0014, | |
1302 | .syss_offs = 0x0018, | |
1303 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1304 | SYSS_HAS_RESET_STATUS), | |
1305 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1306 | }; | |
1307 | ||
1308 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1309 | .name = "hdq1w", | |
1310 | .sysc = &omap44xx_hdq1w_sysc, | |
1311 | }; | |
1312 | ||
1313 | /* hdq1w */ | |
1314 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1315 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1316 | { .irq = -1 } | |
1317 | }; | |
1318 | ||
1319 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1320 | .name = "hdq1w", | |
1321 | .class = &omap44xx_hdq1w_hwmod_class, | |
1322 | .clkdm_name = "l4_per_clkdm", | |
1323 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1324 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
1325 | .main_clk = "hdq1w_fck", | |
1326 | .prcm = { | |
1327 | .omap4 = { | |
1328 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1329 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1330 | .modulemode = MODULEMODE_SWCTRL, | |
1331 | }, | |
1332 | }, | |
1333 | }; | |
1334 | ||
407a6888 BC |
1335 | /* |
1336 | * 'hsi' class | |
1337 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1338 | * serial if) | |
1339 | */ | |
1340 | ||
1341 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1342 | .rev_offs = 0x0000, | |
1343 | .sysc_offs = 0x0010, | |
1344 | .syss_offs = 0x0014, | |
1345 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1346 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1347 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1348 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1349 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1350 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1351 | .sysc_fields = &omap_hwmod_sysc_type1, |
1352 | }; | |
1353 | ||
1354 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1355 | .name = "hsi", | |
1356 | .sysc = &omap44xx_hsi_sysc, | |
1357 | }; | |
1358 | ||
1359 | /* hsi */ | |
1360 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1361 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1362 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1363 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1364 | { .irq = -1 } |
407a6888 BC |
1365 | }; |
1366 | ||
407a6888 BC |
1367 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1368 | .name = "hsi", | |
1369 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1370 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1371 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1372 | .main_clk = "hsi_fck", |
00fe610b | 1373 | .prcm = { |
407a6888 | 1374 | .omap4 = { |
d0f0631d | 1375 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1376 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1377 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1378 | }, |
1379 | }, | |
407a6888 BC |
1380 | }; |
1381 | ||
3b54baad BC |
1382 | /* |
1383 | * 'i2c' class | |
1384 | * multimaster high-speed i2c controller | |
1385 | */ | |
db12ba53 | 1386 | |
3b54baad BC |
1387 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1388 | .sysc_offs = 0x0010, | |
1389 | .syss_offs = 0x0090, | |
1390 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1391 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1392 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1393 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1394 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1395 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1396 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1397 | }; |
1398 | ||
3b54baad | 1399 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1400 | .name = "i2c", |
1401 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1402 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1403 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1404 | }; |
1405 | ||
4d4441a6 AG |
1406 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
1407 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
1408 | }; | |
1409 | ||
3b54baad | 1410 | /* i2c1 */ |
3b54baad BC |
1411 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1412 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1413 | { .irq = -1 } |
db12ba53 BC |
1414 | }; |
1415 | ||
3b54baad BC |
1416 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1417 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1418 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1419 | { .dma_req = -1 } |
db12ba53 BC |
1420 | }; |
1421 | ||
3b54baad BC |
1422 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1423 | .name = "i2c1", | |
1424 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1425 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1426 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1427 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1428 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 1429 | .main_clk = "i2c1_fck", |
92b18d1c BC |
1430 | .prcm = { |
1431 | .omap4 = { | |
d0f0631d | 1432 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1433 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1434 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1435 | }, |
1436 | }, | |
4d4441a6 | 1437 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1438 | }; |
1439 | ||
3b54baad | 1440 | /* i2c2 */ |
3b54baad BC |
1441 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1442 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1443 | { .irq = -1 } |
92b18d1c BC |
1444 | }; |
1445 | ||
3b54baad BC |
1446 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1447 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1448 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1449 | { .dma_req = -1 } |
3b54baad BC |
1450 | }; |
1451 | ||
3b54baad BC |
1452 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1453 | .name = "i2c2", | |
1454 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1455 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1456 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1457 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1458 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 1459 | .main_clk = "i2c2_fck", |
db12ba53 BC |
1460 | .prcm = { |
1461 | .omap4 = { | |
d0f0631d | 1462 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1463 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1464 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1465 | }, |
1466 | }, | |
4d4441a6 | 1467 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1468 | }; |
1469 | ||
3b54baad | 1470 | /* i2c3 */ |
3b54baad BC |
1471 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1472 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1473 | { .irq = -1 } |
db12ba53 BC |
1474 | }; |
1475 | ||
3b54baad BC |
1476 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1477 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1478 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1479 | { .dma_req = -1 } |
92b18d1c BC |
1480 | }; |
1481 | ||
3b54baad BC |
1482 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1483 | .name = "i2c3", | |
1484 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1485 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1486 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1487 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1488 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 1489 | .main_clk = "i2c3_fck", |
db12ba53 BC |
1490 | .prcm = { |
1491 | .omap4 = { | |
d0f0631d | 1492 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1493 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1494 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1495 | }, |
1496 | }, | |
4d4441a6 | 1497 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1498 | }; |
1499 | ||
3b54baad | 1500 | /* i2c4 */ |
3b54baad BC |
1501 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1502 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1503 | { .irq = -1 } |
db12ba53 BC |
1504 | }; |
1505 | ||
3b54baad BC |
1506 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1507 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1508 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1509 | { .dma_req = -1 } |
db12ba53 BC |
1510 | }; |
1511 | ||
3b54baad BC |
1512 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1513 | .name = "i2c4", | |
1514 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1515 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1516 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1517 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1518 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 1519 | .main_clk = "i2c4_fck", |
92b18d1c BC |
1520 | .prcm = { |
1521 | .omap4 = { | |
d0f0631d | 1522 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1523 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1524 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1525 | }, |
1526 | }, | |
4d4441a6 | 1527 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1528 | }; |
1529 | ||
407a6888 BC |
1530 | /* |
1531 | * 'ipu' class | |
1532 | * imaging processor unit | |
1533 | */ | |
1534 | ||
1535 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1536 | .name = "ipu", | |
1537 | }; | |
1538 | ||
1539 | /* ipu */ | |
1540 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1541 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1542 | { .irq = -1 } |
407a6888 BC |
1543 | }; |
1544 | ||
f2f5736c | 1545 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1546 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1547 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1548 | { .name = "mmu_cache", .rst_shift = 2 }, |
1549 | }; | |
1550 | ||
407a6888 BC |
1551 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1552 | .name = "ipu", | |
1553 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1554 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1555 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1556 | .rst_lines = omap44xx_ipu_resets, |
1557 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
1558 | .main_clk = "ipu_fck", | |
00fe610b | 1559 | .prcm = { |
407a6888 | 1560 | .omap4 = { |
d0f0631d | 1561 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1562 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1563 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1564 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1565 | }, |
1566 | }, | |
407a6888 BC |
1567 | }; |
1568 | ||
1569 | /* | |
1570 | * 'iss' class | |
1571 | * external images sensor pixel data processor | |
1572 | */ | |
1573 | ||
1574 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1575 | .rev_offs = 0x0000, | |
1576 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1577 | /* |
1578 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1579 | * accessing sysconfig again. | |
1580 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1581 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1582 | * | |
1583 | * TODO: Indicate errata when available. | |
1584 | */ | |
1585 | .srst_udelay = 2, | |
407a6888 BC |
1586 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1587 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1588 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1589 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1590 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1591 | .sysc_fields = &omap_hwmod_sysc_type2, |
1592 | }; | |
1593 | ||
1594 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1595 | .name = "iss", | |
1596 | .sysc = &omap44xx_iss_sysc, | |
1597 | }; | |
1598 | ||
1599 | /* iss */ | |
1600 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1601 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1602 | { .irq = -1 } |
407a6888 BC |
1603 | }; |
1604 | ||
1605 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1606 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1607 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1608 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1609 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1610 | { .dma_req = -1 } |
407a6888 BC |
1611 | }; |
1612 | ||
407a6888 BC |
1613 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1614 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1615 | }; | |
1616 | ||
1617 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1618 | .name = "iss", | |
1619 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1620 | .clkdm_name = "iss_clkdm", |
407a6888 | 1621 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1622 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 1623 | .main_clk = "iss_fck", |
00fe610b | 1624 | .prcm = { |
407a6888 | 1625 | .omap4 = { |
d0f0631d | 1626 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1627 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1628 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1629 | }, |
1630 | }, | |
1631 | .opt_clks = iss_opt_clks, | |
1632 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1633 | }; |
1634 | ||
8f25bdc5 BC |
1635 | /* |
1636 | * 'iva' class | |
1637 | * multi-standard video encoder/decoder hardware accelerator | |
1638 | */ | |
1639 | ||
1640 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1641 | .name = "iva", |
8f25bdc5 BC |
1642 | }; |
1643 | ||
1644 | /* iva */ | |
1645 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1646 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1647 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1648 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1649 | { .irq = -1 } |
8f25bdc5 BC |
1650 | }; |
1651 | ||
1652 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1653 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1654 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1655 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1656 | }; |
1657 | ||
8f25bdc5 BC |
1658 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1659 | .name = "iva", | |
1660 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1661 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1662 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1663 | .rst_lines = omap44xx_iva_resets, |
1664 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1665 | .main_clk = "iva_fck", | |
1666 | .prcm = { | |
1667 | .omap4 = { | |
d0f0631d | 1668 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1669 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1670 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1671 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1672 | }, |
1673 | }, | |
8f25bdc5 BC |
1674 | }; |
1675 | ||
407a6888 BC |
1676 | /* |
1677 | * 'kbd' class | |
1678 | * keyboard controller | |
1679 | */ | |
1680 | ||
1681 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1682 | .rev_offs = 0x0000, | |
1683 | .sysc_offs = 0x0010, | |
1684 | .syss_offs = 0x0014, | |
1685 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1686 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1687 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1688 | SYSS_HAS_RESET_STATUS), | |
1689 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1690 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1691 | }; | |
1692 | ||
1693 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1694 | .name = "kbd", | |
1695 | .sysc = &omap44xx_kbd_sysc, | |
1696 | }; | |
1697 | ||
1698 | /* kbd */ | |
407a6888 BC |
1699 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1700 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1701 | { .irq = -1 } |
407a6888 BC |
1702 | }; |
1703 | ||
407a6888 BC |
1704 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1705 | .name = "kbd", | |
1706 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1707 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1708 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 1709 | .main_clk = "kbd_fck", |
00fe610b | 1710 | .prcm = { |
407a6888 | 1711 | .omap4 = { |
d0f0631d | 1712 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1713 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1714 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1715 | }, |
1716 | }, | |
407a6888 BC |
1717 | }; |
1718 | ||
ec5df927 BC |
1719 | /* |
1720 | * 'mailbox' class | |
1721 | * mailbox module allowing communication between the on-chip processors using a | |
1722 | * queued mailbox-interrupt mechanism. | |
1723 | */ | |
1724 | ||
1725 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1726 | .rev_offs = 0x0000, | |
1727 | .sysc_offs = 0x0010, | |
1728 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1729 | SYSC_HAS_SOFTRESET), | |
1730 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1731 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1732 | }; | |
1733 | ||
1734 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1735 | .name = "mailbox", | |
1736 | .sysc = &omap44xx_mailbox_sysc, | |
1737 | }; | |
1738 | ||
1739 | /* mailbox */ | |
ec5df927 BC |
1740 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1741 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1742 | { .irq = -1 } |
ec5df927 BC |
1743 | }; |
1744 | ||
ec5df927 BC |
1745 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1746 | .name = "mailbox", | |
1747 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1748 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1749 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1750 | .prcm = { |
ec5df927 | 1751 | .omap4 = { |
d0f0631d | 1752 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1753 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1754 | }, |
1755 | }, | |
ec5df927 BC |
1756 | }; |
1757 | ||
896d4e98 BC |
1758 | /* |
1759 | * 'mcasp' class | |
1760 | * multi-channel audio serial port controller | |
1761 | */ | |
1762 | ||
1763 | /* The IP is not compliant to type1 / type2 scheme */ | |
1764 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1765 | .sidle_shift = 0, | |
1766 | }; | |
1767 | ||
1768 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1769 | .sysc_offs = 0x0004, | |
1770 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1771 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1772 | SIDLE_SMART_WKUP), | |
1773 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1774 | }; | |
1775 | ||
1776 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1777 | .name = "mcasp", | |
1778 | .sysc = &omap44xx_mcasp_sysc, | |
1779 | }; | |
1780 | ||
1781 | /* mcasp */ | |
1782 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | |
1783 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | |
1784 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | |
1785 | { .irq = -1 } | |
1786 | }; | |
1787 | ||
1788 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | |
1789 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | |
1790 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | |
1791 | { .dma_req = -1 } | |
1792 | }; | |
1793 | ||
1794 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | |
1795 | .name = "mcasp", | |
1796 | .class = &omap44xx_mcasp_hwmod_class, | |
1797 | .clkdm_name = "abe_clkdm", | |
1798 | .mpu_irqs = omap44xx_mcasp_irqs, | |
1799 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | |
1800 | .main_clk = "mcasp_fck", | |
1801 | .prcm = { | |
1802 | .omap4 = { | |
1803 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1804 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1805 | .modulemode = MODULEMODE_SWCTRL, | |
1806 | }, | |
1807 | }, | |
1808 | }; | |
1809 | ||
4ddff493 BC |
1810 | /* |
1811 | * 'mcbsp' class | |
1812 | * multi channel buffered serial port controller | |
1813 | */ | |
1814 | ||
1815 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1816 | .sysc_offs = 0x008c, | |
1817 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1818 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1819 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1820 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1821 | }; | |
1822 | ||
1823 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1824 | .name = "mcbsp", | |
1825 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1826 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1827 | }; |
1828 | ||
1829 | /* mcbsp1 */ | |
4ddff493 BC |
1830 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
1831 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1832 | { .irq = -1 } |
4ddff493 BC |
1833 | }; |
1834 | ||
1835 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1836 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1837 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1838 | { .dma_req = -1 } |
4ddff493 BC |
1839 | }; |
1840 | ||
503d0ea2 PW |
1841 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1842 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1843 | { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, | |
1844 | }; | |
1845 | ||
4ddff493 BC |
1846 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1847 | .name = "mcbsp1", | |
1848 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1849 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1850 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1851 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
1852 | .main_clk = "mcbsp1_fck", |
1853 | .prcm = { | |
1854 | .omap4 = { | |
d0f0631d | 1855 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1856 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1857 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1858 | }, |
1859 | }, | |
503d0ea2 PW |
1860 | .opt_clks = mcbsp1_opt_clks, |
1861 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1862 | }; |
1863 | ||
1864 | /* mcbsp2 */ | |
4ddff493 BC |
1865 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
1866 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1867 | { .irq = -1 } |
4ddff493 BC |
1868 | }; |
1869 | ||
1870 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1871 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1872 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1873 | { .dma_req = -1 } |
4ddff493 BC |
1874 | }; |
1875 | ||
844a3b63 PW |
1876 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1877 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1878 | { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, | |
503d0ea2 PW |
1879 | }; |
1880 | ||
4ddff493 BC |
1881 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1882 | .name = "mcbsp2", | |
1883 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1884 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1885 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 1886 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
1887 | .main_clk = "mcbsp2_fck", |
1888 | .prcm = { | |
1889 | .omap4 = { | |
d0f0631d | 1890 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1891 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1892 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1893 | }, |
1894 | }, | |
503d0ea2 PW |
1895 | .opt_clks = mcbsp2_opt_clks, |
1896 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1897 | }; |
1898 | ||
1899 | /* mcbsp3 */ | |
4ddff493 BC |
1900 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
1901 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1902 | { .irq = -1 } |
4ddff493 BC |
1903 | }; |
1904 | ||
1905 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
1906 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
1907 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1908 | { .dma_req = -1 } |
4ddff493 BC |
1909 | }; |
1910 | ||
503d0ea2 PW |
1911 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1912 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1913 | { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, | |
1914 | }; | |
1915 | ||
4ddff493 BC |
1916 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1917 | .name = "mcbsp3", | |
1918 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1919 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1920 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 1921 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
1922 | .main_clk = "mcbsp3_fck", |
1923 | .prcm = { | |
1924 | .omap4 = { | |
d0f0631d | 1925 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1926 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1927 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1928 | }, |
1929 | }, | |
503d0ea2 PW |
1930 | .opt_clks = mcbsp3_opt_clks, |
1931 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1932 | }; |
1933 | ||
1934 | /* mcbsp4 */ | |
4ddff493 BC |
1935 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
1936 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1937 | { .irq = -1 } |
4ddff493 BC |
1938 | }; |
1939 | ||
1940 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
1941 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
1942 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1943 | { .dma_req = -1 } |
4ddff493 BC |
1944 | }; |
1945 | ||
503d0ea2 PW |
1946 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
1947 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1948 | { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, | |
1949 | }; | |
1950 | ||
4ddff493 BC |
1951 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
1952 | .name = "mcbsp4", | |
1953 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1954 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 1955 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 1956 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
1957 | .main_clk = "mcbsp4_fck", |
1958 | .prcm = { | |
1959 | .omap4 = { | |
d0f0631d | 1960 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 1961 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 1962 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1963 | }, |
1964 | }, | |
503d0ea2 PW |
1965 | .opt_clks = mcbsp4_opt_clks, |
1966 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
1967 | }; |
1968 | ||
407a6888 BC |
1969 | /* |
1970 | * 'mcpdm' class | |
1971 | * multi channel pdm controller (proprietary interface with phoenix power | |
1972 | * ic) | |
1973 | */ | |
1974 | ||
1975 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
1976 | .rev_offs = 0x0000, | |
1977 | .sysc_offs = 0x0010, | |
1978 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1979 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1980 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1981 | SIDLE_SMART_WKUP), | |
1982 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1983 | }; | |
1984 | ||
1985 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
1986 | .name = "mcpdm", | |
1987 | .sysc = &omap44xx_mcpdm_sysc, | |
1988 | }; | |
1989 | ||
1990 | /* mcpdm */ | |
407a6888 BC |
1991 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
1992 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1993 | { .irq = -1 } |
407a6888 BC |
1994 | }; |
1995 | ||
1996 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
1997 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
1998 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1999 | { .dma_req = -1 } |
407a6888 BC |
2000 | }; |
2001 | ||
407a6888 BC |
2002 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
2003 | .name = "mcpdm", | |
2004 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 2005 | .clkdm_name = "abe_clkdm", |
407a6888 | 2006 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 2007 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 2008 | .main_clk = "mcpdm_fck", |
00fe610b | 2009 | .prcm = { |
407a6888 | 2010 | .omap4 = { |
d0f0631d | 2011 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 2012 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 2013 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2014 | }, |
2015 | }, | |
407a6888 BC |
2016 | }; |
2017 | ||
9bcbd7f0 BC |
2018 | /* |
2019 | * 'mcspi' class | |
2020 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2021 | * bus | |
2022 | */ | |
2023 | ||
2024 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
2025 | .rev_offs = 0x0000, | |
2026 | .sysc_offs = 0x0010, | |
2027 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2028 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2029 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2030 | SIDLE_SMART_WKUP), | |
2031 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2032 | }; | |
2033 | ||
2034 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
2035 | .name = "mcspi", | |
2036 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 2037 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
2038 | }; |
2039 | ||
2040 | /* mcspi1 */ | |
9bcbd7f0 BC |
2041 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
2042 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2043 | { .irq = -1 } |
9bcbd7f0 BC |
2044 | }; |
2045 | ||
2046 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
2047 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
2048 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
2049 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
2050 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
2051 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
2052 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
2053 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
2054 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2055 | { .dma_req = -1 } |
9bcbd7f0 BC |
2056 | }; |
2057 | ||
905a74d9 BC |
2058 | /* mcspi1 dev_attr */ |
2059 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
2060 | .num_chipselect = 4, | |
2061 | }; | |
2062 | ||
9bcbd7f0 BC |
2063 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
2064 | .name = "mcspi1", | |
2065 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2066 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2067 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 2068 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
2069 | .main_clk = "mcspi1_fck", |
2070 | .prcm = { | |
2071 | .omap4 = { | |
d0f0631d | 2072 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 2073 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 2074 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2075 | }, |
2076 | }, | |
905a74d9 | 2077 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
2078 | }; |
2079 | ||
2080 | /* mcspi2 */ | |
9bcbd7f0 BC |
2081 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
2082 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2083 | { .irq = -1 } |
9bcbd7f0 BC |
2084 | }; |
2085 | ||
2086 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
2087 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
2088 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
2089 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
2090 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2091 | { .dma_req = -1 } |
9bcbd7f0 BC |
2092 | }; |
2093 | ||
905a74d9 BC |
2094 | /* mcspi2 dev_attr */ |
2095 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
2096 | .num_chipselect = 2, | |
2097 | }; | |
2098 | ||
9bcbd7f0 BC |
2099 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
2100 | .name = "mcspi2", | |
2101 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2102 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2103 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 2104 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
2105 | .main_clk = "mcspi2_fck", |
2106 | .prcm = { | |
2107 | .omap4 = { | |
d0f0631d | 2108 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 2109 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 2110 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2111 | }, |
2112 | }, | |
905a74d9 | 2113 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
2114 | }; |
2115 | ||
2116 | /* mcspi3 */ | |
9bcbd7f0 BC |
2117 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
2118 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2119 | { .irq = -1 } |
9bcbd7f0 BC |
2120 | }; |
2121 | ||
2122 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
2123 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
2124 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
2125 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
2126 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2127 | { .dma_req = -1 } |
9bcbd7f0 BC |
2128 | }; |
2129 | ||
905a74d9 BC |
2130 | /* mcspi3 dev_attr */ |
2131 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
2132 | .num_chipselect = 2, | |
2133 | }; | |
2134 | ||
9bcbd7f0 BC |
2135 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
2136 | .name = "mcspi3", | |
2137 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2138 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2139 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 2140 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
2141 | .main_clk = "mcspi3_fck", |
2142 | .prcm = { | |
2143 | .omap4 = { | |
d0f0631d | 2144 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 2145 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 2146 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2147 | }, |
2148 | }, | |
905a74d9 | 2149 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2150 | }; |
2151 | ||
2152 | /* mcspi4 */ | |
9bcbd7f0 BC |
2153 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
2154 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2155 | { .irq = -1 } |
9bcbd7f0 BC |
2156 | }; |
2157 | ||
2158 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
2159 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2160 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2161 | { .dma_req = -1 } |
9bcbd7f0 BC |
2162 | }; |
2163 | ||
905a74d9 BC |
2164 | /* mcspi4 dev_attr */ |
2165 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2166 | .num_chipselect = 1, | |
2167 | }; | |
2168 | ||
9bcbd7f0 BC |
2169 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2170 | .name = "mcspi4", | |
2171 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2172 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2173 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 2174 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
2175 | .main_clk = "mcspi4_fck", |
2176 | .prcm = { | |
2177 | .omap4 = { | |
d0f0631d | 2178 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2179 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2180 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2181 | }, |
2182 | }, | |
905a74d9 | 2183 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2184 | }; |
2185 | ||
407a6888 BC |
2186 | /* |
2187 | * 'mmc' class | |
2188 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2189 | */ | |
2190 | ||
2191 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2192 | .rev_offs = 0x0000, | |
2193 | .sysc_offs = 0x0010, | |
2194 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2195 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2196 | SYSC_HAS_SOFTRESET), | |
2197 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2198 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2199 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2200 | .sysc_fields = &omap_hwmod_sysc_type2, |
2201 | }; | |
2202 | ||
2203 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2204 | .name = "mmc", | |
2205 | .sysc = &omap44xx_mmc_sysc, | |
2206 | }; | |
2207 | ||
2208 | /* mmc1 */ | |
2209 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
2210 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2211 | { .irq = -1 } |
407a6888 BC |
2212 | }; |
2213 | ||
2214 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
2215 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2216 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2217 | { .dma_req = -1 } |
407a6888 BC |
2218 | }; |
2219 | ||
6ab8946f KK |
2220 | /* mmc1 dev_attr */ |
2221 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
2222 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2223 | }; | |
2224 | ||
407a6888 BC |
2225 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2226 | .name = "mmc1", | |
2227 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2228 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2229 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 2230 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 2231 | .main_clk = "mmc1_fck", |
00fe610b | 2232 | .prcm = { |
407a6888 | 2233 | .omap4 = { |
d0f0631d | 2234 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2235 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2236 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2237 | }, |
2238 | }, | |
6ab8946f | 2239 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2240 | }; |
2241 | ||
2242 | /* mmc2 */ | |
2243 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2244 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2245 | { .irq = -1 } |
407a6888 BC |
2246 | }; |
2247 | ||
2248 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2249 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2250 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2251 | { .dma_req = -1 } |
407a6888 BC |
2252 | }; |
2253 | ||
407a6888 BC |
2254 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2255 | .name = "mmc2", | |
2256 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2257 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2258 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2259 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 2260 | .main_clk = "mmc2_fck", |
00fe610b | 2261 | .prcm = { |
407a6888 | 2262 | .omap4 = { |
d0f0631d | 2263 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2264 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2265 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2266 | }, |
2267 | }, | |
407a6888 BC |
2268 | }; |
2269 | ||
2270 | /* mmc3 */ | |
407a6888 BC |
2271 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2272 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2273 | { .irq = -1 } |
407a6888 BC |
2274 | }; |
2275 | ||
2276 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2277 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2278 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2279 | { .dma_req = -1 } |
407a6888 BC |
2280 | }; |
2281 | ||
407a6888 BC |
2282 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2283 | .name = "mmc3", | |
2284 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2285 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2286 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2287 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 2288 | .main_clk = "mmc3_fck", |
00fe610b | 2289 | .prcm = { |
407a6888 | 2290 | .omap4 = { |
d0f0631d | 2291 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2292 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2293 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2294 | }, |
2295 | }, | |
407a6888 BC |
2296 | }; |
2297 | ||
2298 | /* mmc4 */ | |
407a6888 BC |
2299 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2300 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2301 | { .irq = -1 } |
407a6888 BC |
2302 | }; |
2303 | ||
2304 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2305 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2306 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2307 | { .dma_req = -1 } |
407a6888 BC |
2308 | }; |
2309 | ||
407a6888 BC |
2310 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2311 | .name = "mmc4", | |
2312 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2313 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2314 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2315 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 2316 | .main_clk = "mmc4_fck", |
00fe610b | 2317 | .prcm = { |
407a6888 | 2318 | .omap4 = { |
d0f0631d | 2319 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2320 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2321 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2322 | }, |
2323 | }, | |
407a6888 BC |
2324 | }; |
2325 | ||
2326 | /* mmc5 */ | |
407a6888 BC |
2327 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2328 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2329 | { .irq = -1 } |
407a6888 BC |
2330 | }; |
2331 | ||
2332 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2333 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2334 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2335 | { .dma_req = -1 } |
407a6888 BC |
2336 | }; |
2337 | ||
407a6888 BC |
2338 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2339 | .name = "mmc5", | |
2340 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2341 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2342 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2343 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 2344 | .main_clk = "mmc5_fck", |
00fe610b | 2345 | .prcm = { |
407a6888 | 2346 | .omap4 = { |
d0f0631d | 2347 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2348 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2349 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2350 | }, |
2351 | }, | |
407a6888 BC |
2352 | }; |
2353 | ||
3b54baad BC |
2354 | /* |
2355 | * 'mpu' class | |
2356 | * mpu sub-system | |
2357 | */ | |
2358 | ||
2359 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2360 | .name = "mpu", |
db12ba53 BC |
2361 | }; |
2362 | ||
3b54baad BC |
2363 | /* mpu */ |
2364 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
2365 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
2366 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2367 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2368 | { .irq = -1 } |
db12ba53 BC |
2369 | }; |
2370 | ||
3b54baad BC |
2371 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2372 | .name = "mpu", | |
2373 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2374 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2375 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2376 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2377 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2378 | .prcm = { |
2379 | .omap4 = { | |
d0f0631d | 2380 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2381 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2382 | }, |
2383 | }, | |
db12ba53 BC |
2384 | }; |
2385 | ||
e17f18c0 PW |
2386 | /* |
2387 | * 'ocmc_ram' class | |
2388 | * top-level core on-chip ram | |
2389 | */ | |
2390 | ||
2391 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2392 | .name = "ocmc_ram", | |
2393 | }; | |
2394 | ||
2395 | /* ocmc_ram */ | |
2396 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2397 | .name = "ocmc_ram", | |
2398 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2399 | .clkdm_name = "l3_2_clkdm", | |
2400 | .prcm = { | |
2401 | .omap4 = { | |
2402 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2403 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2404 | }, | |
2405 | }, | |
2406 | }; | |
2407 | ||
0c668875 BC |
2408 | /* |
2409 | * 'ocp2scp' class | |
2410 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2411 | * protocol | |
2412 | */ | |
2413 | ||
2414 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { | |
2415 | .name = "ocp2scp", | |
2416 | }; | |
2417 | ||
2418 | /* ocp2scp_usb_phy */ | |
2419 | static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { | |
2420 | { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, | |
2421 | }; | |
2422 | ||
2423 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | |
2424 | .name = "ocp2scp_usb_phy", | |
2425 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2426 | .clkdm_name = "l3_init_clkdm", | |
2427 | .prcm = { | |
2428 | .omap4 = { | |
2429 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2430 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2431 | .modulemode = MODULEMODE_HWCTRL, | |
2432 | }, | |
2433 | }, | |
2434 | .opt_clks = ocp2scp_usb_phy_opt_clks, | |
2435 | .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), | |
2436 | }; | |
2437 | ||
42b9e387 PW |
2438 | /* |
2439 | * 'sl2if' class | |
2440 | * shared level 2 memory interface | |
2441 | */ | |
2442 | ||
2443 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2444 | .name = "sl2if", | |
2445 | }; | |
2446 | ||
2447 | /* sl2if */ | |
2448 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2449 | .name = "sl2if", | |
2450 | .class = &omap44xx_sl2if_hwmod_class, | |
2451 | .clkdm_name = "ivahd_clkdm", | |
2452 | .prcm = { | |
2453 | .omap4 = { | |
2454 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2455 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2456 | .modulemode = MODULEMODE_HWCTRL, | |
2457 | }, | |
2458 | }, | |
2459 | }; | |
2460 | ||
1e3b5e59 BC |
2461 | /* |
2462 | * 'slimbus' class | |
2463 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2464 | * the device and external components | |
2465 | */ | |
2466 | ||
2467 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2468 | .rev_offs = 0x0000, | |
2469 | .sysc_offs = 0x0010, | |
2470 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2471 | SYSC_HAS_SOFTRESET), | |
2472 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2473 | SIDLE_SMART_WKUP), | |
2474 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2475 | }; | |
2476 | ||
2477 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2478 | .name = "slimbus", | |
2479 | .sysc = &omap44xx_slimbus_sysc, | |
2480 | }; | |
2481 | ||
2482 | /* slimbus1 */ | |
2483 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | |
2484 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | |
2485 | { .irq = -1 } | |
2486 | }; | |
2487 | ||
2488 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | |
2489 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | |
2490 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | |
2491 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | |
2492 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | |
2493 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | |
2494 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | |
2495 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | |
2496 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | |
2497 | { .dma_req = -1 } | |
2498 | }; | |
2499 | ||
2500 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | |
2501 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2502 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2503 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2504 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2505 | }; | |
2506 | ||
2507 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2508 | .name = "slimbus1", | |
2509 | .class = &omap44xx_slimbus_hwmod_class, | |
2510 | .clkdm_name = "abe_clkdm", | |
2511 | .mpu_irqs = omap44xx_slimbus1_irqs, | |
2512 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | |
2513 | .prcm = { | |
2514 | .omap4 = { | |
2515 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2516 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2517 | .modulemode = MODULEMODE_SWCTRL, | |
2518 | }, | |
2519 | }, | |
2520 | .opt_clks = slimbus1_opt_clks, | |
2521 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2522 | }; | |
2523 | ||
2524 | /* slimbus2 */ | |
2525 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | |
2526 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | |
2527 | { .irq = -1 } | |
2528 | }; | |
2529 | ||
2530 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | |
2531 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | |
2532 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | |
2533 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | |
2534 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | |
2535 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | |
2536 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | |
2537 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | |
2538 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | |
2539 | { .dma_req = -1 } | |
2540 | }; | |
2541 | ||
2542 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | |
2543 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2544 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2545 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2546 | }; | |
2547 | ||
2548 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2549 | .name = "slimbus2", | |
2550 | .class = &omap44xx_slimbus_hwmod_class, | |
2551 | .clkdm_name = "l4_per_clkdm", | |
2552 | .mpu_irqs = omap44xx_slimbus2_irqs, | |
2553 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | |
2554 | .prcm = { | |
2555 | .omap4 = { | |
2556 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2557 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2558 | .modulemode = MODULEMODE_SWCTRL, | |
2559 | }, | |
2560 | }, | |
2561 | .opt_clks = slimbus2_opt_clks, | |
2562 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2563 | }; | |
2564 | ||
1f6a717f BC |
2565 | /* |
2566 | * 'smartreflex' class | |
2567 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2568 | * performance error) | |
2569 | */ | |
2570 | ||
2571 | /* The IP is not compliant to type1 / type2 scheme */ | |
2572 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2573 | .sidle_shift = 24, | |
2574 | .enwkup_shift = 26, | |
2575 | }; | |
2576 | ||
2577 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2578 | .sysc_offs = 0x0038, | |
2579 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2580 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2581 | SIDLE_SMART_WKUP), | |
2582 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2583 | }; | |
2584 | ||
2585 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2586 | .name = "smartreflex", |
2587 | .sysc = &omap44xx_smartreflex_sysc, | |
2588 | .rev = 2, | |
1f6a717f BC |
2589 | }; |
2590 | ||
2591 | /* smartreflex_core */ | |
cea6b942 SG |
2592 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2593 | .sensor_voltdm_name = "core", | |
2594 | }; | |
2595 | ||
1f6a717f BC |
2596 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2597 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2598 | { .irq = -1 } |
1f6a717f BC |
2599 | }; |
2600 | ||
1f6a717f BC |
2601 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2602 | .name = "smartreflex_core", | |
2603 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2604 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2605 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2606 | |
1f6a717f | 2607 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2608 | .prcm = { |
2609 | .omap4 = { | |
d0f0631d | 2610 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2611 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2612 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2613 | }, |
2614 | }, | |
cea6b942 | 2615 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2616 | }; |
2617 | ||
2618 | /* smartreflex_iva */ | |
cea6b942 SG |
2619 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2620 | .sensor_voltdm_name = "iva", | |
2621 | }; | |
2622 | ||
1f6a717f BC |
2623 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
2624 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2625 | { .irq = -1 } |
1f6a717f BC |
2626 | }; |
2627 | ||
1f6a717f BC |
2628 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2629 | .name = "smartreflex_iva", | |
2630 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2631 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2632 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 2633 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2634 | .prcm = { |
2635 | .omap4 = { | |
d0f0631d | 2636 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2637 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2638 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2639 | }, |
2640 | }, | |
cea6b942 | 2641 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2642 | }; |
2643 | ||
2644 | /* smartreflex_mpu */ | |
cea6b942 SG |
2645 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2646 | .sensor_voltdm_name = "mpu", | |
2647 | }; | |
2648 | ||
1f6a717f BC |
2649 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
2650 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2651 | { .irq = -1 } |
1f6a717f BC |
2652 | }; |
2653 | ||
1f6a717f BC |
2654 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2655 | .name = "smartreflex_mpu", | |
2656 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2657 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2658 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 2659 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2660 | .prcm = { |
2661 | .omap4 = { | |
d0f0631d | 2662 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2663 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2664 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2665 | }, |
2666 | }, | |
cea6b942 | 2667 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2668 | }; |
2669 | ||
d11c217f BC |
2670 | /* |
2671 | * 'spinlock' class | |
2672 | * spinlock provides hardware assistance for synchronizing the processes | |
2673 | * running on multiple processors | |
2674 | */ | |
2675 | ||
2676 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2677 | .rev_offs = 0x0000, | |
2678 | .sysc_offs = 0x0010, | |
2679 | .syss_offs = 0x0014, | |
2680 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2681 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2682 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2683 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2684 | SIDLE_SMART_WKUP), | |
2685 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2686 | }; | |
2687 | ||
2688 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2689 | .name = "spinlock", | |
2690 | .sysc = &omap44xx_spinlock_sysc, | |
2691 | }; | |
2692 | ||
2693 | /* spinlock */ | |
d11c217f BC |
2694 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2695 | .name = "spinlock", | |
2696 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2697 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2698 | .prcm = { |
2699 | .omap4 = { | |
d0f0631d | 2700 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2701 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2702 | }, |
2703 | }, | |
d11c217f BC |
2704 | }; |
2705 | ||
35d1a66a BC |
2706 | /* |
2707 | * 'timer' class | |
2708 | * general purpose timer module with accurate 1ms tick | |
2709 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2710 | */ | |
2711 | ||
2712 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2713 | .rev_offs = 0x0000, | |
2714 | .sysc_offs = 0x0010, | |
2715 | .syss_offs = 0x0014, | |
2716 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2717 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2718 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2719 | SYSS_HAS_RESET_STATUS), | |
2720 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2721 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2722 | }; | |
2723 | ||
2724 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2725 | .name = "timer", | |
2726 | .sysc = &omap44xx_timer_1ms_sysc, | |
2727 | }; | |
2728 | ||
2729 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2730 | .rev_offs = 0x0000, | |
2731 | .sysc_offs = 0x0010, | |
2732 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2733 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2734 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2735 | SIDLE_SMART_WKUP), | |
2736 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2737 | }; | |
2738 | ||
2739 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2740 | .name = "timer", | |
2741 | .sysc = &omap44xx_timer_sysc, | |
2742 | }; | |
2743 | ||
c345c8b0 TKD |
2744 | /* always-on timers dev attribute */ |
2745 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2746 | .timer_capability = OMAP_TIMER_ALWON, | |
2747 | }; | |
2748 | ||
2749 | /* pwm timers dev attribute */ | |
2750 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2751 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2752 | }; | |
2753 | ||
35d1a66a | 2754 | /* timer1 */ |
35d1a66a BC |
2755 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
2756 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2757 | { .irq = -1 } |
35d1a66a BC |
2758 | }; |
2759 | ||
35d1a66a BC |
2760 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2761 | .name = "timer1", | |
2762 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2763 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 2764 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
2765 | .main_clk = "timer1_fck", |
2766 | .prcm = { | |
2767 | .omap4 = { | |
d0f0631d | 2768 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2769 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2770 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2771 | }, |
2772 | }, | |
c345c8b0 | 2773 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2774 | }; |
2775 | ||
2776 | /* timer2 */ | |
35d1a66a BC |
2777 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
2778 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2779 | { .irq = -1 } |
35d1a66a BC |
2780 | }; |
2781 | ||
35d1a66a BC |
2782 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2783 | .name = "timer2", | |
2784 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2785 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2786 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
2787 | .main_clk = "timer2_fck", |
2788 | .prcm = { | |
2789 | .omap4 = { | |
d0f0631d | 2790 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2791 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2792 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2793 | }, |
2794 | }, | |
c345c8b0 | 2795 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2796 | }; |
2797 | ||
2798 | /* timer3 */ | |
35d1a66a BC |
2799 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
2800 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2801 | { .irq = -1 } |
35d1a66a BC |
2802 | }; |
2803 | ||
35d1a66a BC |
2804 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2805 | .name = "timer3", | |
2806 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2807 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2808 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
2809 | .main_clk = "timer3_fck", |
2810 | .prcm = { | |
2811 | .omap4 = { | |
d0f0631d | 2812 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2813 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2814 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2815 | }, |
2816 | }, | |
c345c8b0 | 2817 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2818 | }; |
2819 | ||
2820 | /* timer4 */ | |
35d1a66a BC |
2821 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
2822 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2823 | { .irq = -1 } |
35d1a66a BC |
2824 | }; |
2825 | ||
35d1a66a BC |
2826 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2827 | .name = "timer4", | |
2828 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2829 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2830 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
2831 | .main_clk = "timer4_fck", |
2832 | .prcm = { | |
2833 | .omap4 = { | |
d0f0631d | 2834 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2835 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2836 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2837 | }, |
2838 | }, | |
c345c8b0 | 2839 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2840 | }; |
2841 | ||
2842 | /* timer5 */ | |
35d1a66a BC |
2843 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
2844 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2845 | { .irq = -1 } |
35d1a66a BC |
2846 | }; |
2847 | ||
35d1a66a BC |
2848 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2849 | .name = "timer5", | |
2850 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2851 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2852 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
2853 | .main_clk = "timer5_fck", |
2854 | .prcm = { | |
2855 | .omap4 = { | |
d0f0631d | 2856 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2857 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2858 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2859 | }, |
2860 | }, | |
c345c8b0 | 2861 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2862 | }; |
2863 | ||
2864 | /* timer6 */ | |
35d1a66a BC |
2865 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
2866 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2867 | { .irq = -1 } |
35d1a66a BC |
2868 | }; |
2869 | ||
35d1a66a BC |
2870 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
2871 | .name = "timer6", | |
2872 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2873 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2874 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 2875 | |
35d1a66a BC |
2876 | .main_clk = "timer6_fck", |
2877 | .prcm = { | |
2878 | .omap4 = { | |
d0f0631d | 2879 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 2880 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 2881 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2882 | }, |
2883 | }, | |
c345c8b0 | 2884 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2885 | }; |
2886 | ||
2887 | /* timer7 */ | |
35d1a66a BC |
2888 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
2889 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2890 | { .irq = -1 } |
35d1a66a BC |
2891 | }; |
2892 | ||
35d1a66a BC |
2893 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
2894 | .name = "timer7", | |
2895 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2896 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2897 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
2898 | .main_clk = "timer7_fck", |
2899 | .prcm = { | |
2900 | .omap4 = { | |
d0f0631d | 2901 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 2902 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 2903 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2904 | }, |
2905 | }, | |
c345c8b0 | 2906 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2907 | }; |
2908 | ||
2909 | /* timer8 */ | |
35d1a66a BC |
2910 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
2911 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2912 | { .irq = -1 } |
35d1a66a BC |
2913 | }; |
2914 | ||
35d1a66a BC |
2915 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
2916 | .name = "timer8", | |
2917 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2918 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2919 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
2920 | .main_clk = "timer8_fck", |
2921 | .prcm = { | |
2922 | .omap4 = { | |
d0f0631d | 2923 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 2924 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 2925 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2926 | }, |
2927 | }, | |
c345c8b0 | 2928 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2929 | }; |
2930 | ||
2931 | /* timer9 */ | |
35d1a66a BC |
2932 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
2933 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2934 | { .irq = -1 } |
35d1a66a BC |
2935 | }; |
2936 | ||
35d1a66a BC |
2937 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
2938 | .name = "timer9", | |
2939 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2940 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2941 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
2942 | .main_clk = "timer9_fck", |
2943 | .prcm = { | |
2944 | .omap4 = { | |
d0f0631d | 2945 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 2946 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 2947 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2948 | }, |
2949 | }, | |
c345c8b0 | 2950 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2951 | }; |
2952 | ||
2953 | /* timer10 */ | |
35d1a66a BC |
2954 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
2955 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2956 | { .irq = -1 } |
35d1a66a BC |
2957 | }; |
2958 | ||
35d1a66a BC |
2959 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
2960 | .name = "timer10", | |
2961 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2962 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2963 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
2964 | .main_clk = "timer10_fck", |
2965 | .prcm = { | |
2966 | .omap4 = { | |
d0f0631d | 2967 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 2968 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 2969 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2970 | }, |
2971 | }, | |
c345c8b0 | 2972 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2973 | }; |
2974 | ||
2975 | /* timer11 */ | |
35d1a66a BC |
2976 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
2977 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2978 | { .irq = -1 } |
35d1a66a BC |
2979 | }; |
2980 | ||
35d1a66a BC |
2981 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
2982 | .name = "timer11", | |
2983 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2984 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2985 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
2986 | .main_clk = "timer11_fck", |
2987 | .prcm = { | |
2988 | .omap4 = { | |
d0f0631d | 2989 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 2990 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 2991 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2992 | }, |
2993 | }, | |
c345c8b0 | 2994 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2995 | }; |
2996 | ||
9780a9cf | 2997 | /* |
3b54baad BC |
2998 | * 'uart' class |
2999 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
3000 | */ |
3001 | ||
3b54baad BC |
3002 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
3003 | .rev_offs = 0x0050, | |
3004 | .sysc_offs = 0x0054, | |
3005 | .syss_offs = 0x0058, | |
3006 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
3007 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
3008 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
3009 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3010 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
3011 | .sysc_fields = &omap_hwmod_sysc_type1, |
3012 | }; | |
3013 | ||
3b54baad | 3014 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
3015 | .name = "uart", |
3016 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
3017 | }; |
3018 | ||
3b54baad | 3019 | /* uart1 */ |
3b54baad BC |
3020 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
3021 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3022 | { .irq = -1 } |
9780a9cf BC |
3023 | }; |
3024 | ||
3b54baad BC |
3025 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
3026 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
3027 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3028 | { .dma_req = -1 } |
9780a9cf BC |
3029 | }; |
3030 | ||
3b54baad BC |
3031 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
3032 | .name = "uart1", | |
3033 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3034 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3035 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 3036 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 3037 | .main_clk = "uart1_fck", |
9780a9cf BC |
3038 | .prcm = { |
3039 | .omap4 = { | |
d0f0631d | 3040 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 3041 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 3042 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3043 | }, |
3044 | }, | |
9780a9cf BC |
3045 | }; |
3046 | ||
3b54baad | 3047 | /* uart2 */ |
3b54baad BC |
3048 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
3049 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3050 | { .irq = -1 } |
9780a9cf BC |
3051 | }; |
3052 | ||
3b54baad BC |
3053 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
3054 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
3055 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3056 | { .dma_req = -1 } |
3b54baad BC |
3057 | }; |
3058 | ||
3b54baad BC |
3059 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
3060 | .name = "uart2", | |
3061 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3062 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3063 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 3064 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 3065 | .main_clk = "uart2_fck", |
9780a9cf BC |
3066 | .prcm = { |
3067 | .omap4 = { | |
d0f0631d | 3068 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 3069 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 3070 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3071 | }, |
3072 | }, | |
9780a9cf BC |
3073 | }; |
3074 | ||
3b54baad | 3075 | /* uart3 */ |
3b54baad BC |
3076 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
3077 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3078 | { .irq = -1 } |
9780a9cf BC |
3079 | }; |
3080 | ||
3b54baad BC |
3081 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
3082 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
3083 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3084 | { .dma_req = -1 } |
3b54baad BC |
3085 | }; |
3086 | ||
3b54baad BC |
3087 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
3088 | .name = "uart3", | |
3089 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3090 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 3091 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3092 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 3093 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 3094 | .main_clk = "uart3_fck", |
9780a9cf BC |
3095 | .prcm = { |
3096 | .omap4 = { | |
d0f0631d | 3097 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 3098 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 3099 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3100 | }, |
3101 | }, | |
9780a9cf BC |
3102 | }; |
3103 | ||
3b54baad | 3104 | /* uart4 */ |
3b54baad BC |
3105 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
3106 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3107 | { .irq = -1 } |
9780a9cf BC |
3108 | }; |
3109 | ||
3b54baad BC |
3110 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
3111 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
3112 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3113 | { .dma_req = -1 } |
3b54baad BC |
3114 | }; |
3115 | ||
3b54baad BC |
3116 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
3117 | .name = "uart4", | |
3118 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3119 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3120 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 3121 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 3122 | .main_clk = "uart4_fck", |
9780a9cf BC |
3123 | .prcm = { |
3124 | .omap4 = { | |
d0f0631d | 3125 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 3126 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 3127 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3128 | }, |
3129 | }, | |
9780a9cf BC |
3130 | }; |
3131 | ||
0c668875 BC |
3132 | /* |
3133 | * 'usb_host_fs' class | |
3134 | * full-speed usb host controller | |
3135 | */ | |
3136 | ||
3137 | /* The IP is not compliant to type1 / type2 scheme */ | |
3138 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
3139 | .midle_shift = 4, | |
3140 | .sidle_shift = 2, | |
3141 | .srst_shift = 1, | |
3142 | }; | |
3143 | ||
3144 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
3145 | .rev_offs = 0x0000, | |
3146 | .sysc_offs = 0x0210, | |
3147 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3148 | SYSC_HAS_SOFTRESET), | |
3149 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3150 | SIDLE_SMART_WKUP), | |
3151 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
3152 | }; | |
3153 | ||
3154 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
3155 | .name = "usb_host_fs", | |
3156 | .sysc = &omap44xx_usb_host_fs_sysc, | |
3157 | }; | |
3158 | ||
3159 | /* usb_host_fs */ | |
3160 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | |
3161 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | |
3162 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | |
3163 | { .irq = -1 } | |
3164 | }; | |
3165 | ||
3166 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | |
3167 | .name = "usb_host_fs", | |
3168 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
3169 | .clkdm_name = "l3_init_clkdm", | |
3170 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | |
3171 | .main_clk = "usb_host_fs_fck", | |
3172 | .prcm = { | |
3173 | .omap4 = { | |
3174 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
3175 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
3176 | .modulemode = MODULEMODE_SWCTRL, | |
3177 | }, | |
3178 | }, | |
3179 | }; | |
3180 | ||
5844c4ea | 3181 | /* |
844a3b63 PW |
3182 | * 'usb_host_hs' class |
3183 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3184 | */ |
3185 | ||
844a3b63 PW |
3186 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3187 | .rev_offs = 0x0000, | |
3188 | .sysc_offs = 0x0010, | |
3189 | .syss_offs = 0x0014, | |
3190 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3191 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
3192 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3193 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3194 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3195 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3196 | }; |
3197 | ||
844a3b63 PW |
3198 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3199 | .name = "usb_host_hs", | |
3200 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3201 | }; |
3202 | ||
844a3b63 PW |
3203 | /* usb_host_hs */ |
3204 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
3205 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
3206 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3207 | { .irq = -1 } |
5844c4ea BC |
3208 | }; |
3209 | ||
844a3b63 PW |
3210 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3211 | .name = "usb_host_hs", | |
3212 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3213 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3214 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3215 | .prcm = { |
3216 | .omap4 = { | |
844a3b63 PW |
3217 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3218 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3219 | .modulemode = MODULEMODE_SWCTRL, | |
3220 | }, | |
3221 | }, | |
3222 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
3223 | ||
3224 | /* | |
3225 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3226 | * id: i660 | |
3227 | * | |
3228 | * Description: | |
3229 | * In the following configuration : | |
3230 | * - USBHOST module is set to smart-idle mode | |
3231 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3232 | * happens when the system is going to a low power mode : all ports | |
3233 | * have been suspended, the master part of the USBHOST module has | |
3234 | * entered the standby state, and SW has cut the functional clocks) | |
3235 | * - an USBHOST interrupt occurs before the module is able to answer | |
3236 | * idle_ack, typically a remote wakeup IRQ. | |
3237 | * Then the USB HOST module will enter a deadlock situation where it | |
3238 | * is no more accessible nor functional. | |
3239 | * | |
3240 | * Workaround: | |
3241 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3242 | */ | |
3243 | ||
3244 | /* | |
3245 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3246 | * Id: i571 | |
3247 | * | |
3248 | * Description: | |
3249 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3250 | * ready to enter the standby state (i.e. all ports are suspended and | |
3251 | * all attached devices are in suspend mode), then it can wrongly assert | |
3252 | * the Mstandby signal too early while there are still some residual OCP | |
3253 | * transactions ongoing. If this condition occurs, the internal state | |
3254 | * machine may go to an undefined state and the USB link may be stuck | |
3255 | * upon the next resume. | |
3256 | * | |
3257 | * Workaround: | |
3258 | * Don't use smart standby; use only force standby, | |
3259 | * hence HWMOD_SWSUP_MSTANDBY | |
3260 | */ | |
3261 | ||
3262 | /* | |
3263 | * During system boot; If the hwmod framework resets the module | |
3264 | * the module will have smart idle settings; which can lead to deadlock | |
3265 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3266 | * Use HWMOD_INIT_NO_RESET. | |
3267 | */ | |
3268 | ||
3269 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3270 | HWMOD_INIT_NO_RESET, | |
3271 | }; | |
3272 | ||
3273 | /* | |
3274 | * 'usb_otg_hs' class | |
3275 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3276 | */ | |
3277 | ||
3278 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3279 | .rev_offs = 0x0400, | |
3280 | .sysc_offs = 0x0404, | |
3281 | .syss_offs = 0x0408, | |
3282 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3283 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3284 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3285 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3286 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3287 | MSTANDBY_SMART), | |
3288 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3289 | }; | |
3290 | ||
3291 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3292 | .name = "usb_otg_hs", | |
3293 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3294 | }; | |
3295 | ||
3296 | /* usb_otg_hs */ | |
3297 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
3298 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
3299 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
3300 | { .irq = -1 } | |
3301 | }; | |
3302 | ||
3303 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
3304 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3305 | }; | |
3306 | ||
3307 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3308 | .name = "usb_otg_hs", | |
3309 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3310 | .clkdm_name = "l3_init_clkdm", | |
3311 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
3312 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
3313 | .main_clk = "usb_otg_hs_ick", | |
3314 | .prcm = { | |
3315 | .omap4 = { | |
3316 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3317 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3318 | .modulemode = MODULEMODE_HWCTRL, | |
3319 | }, | |
3320 | }, | |
3321 | .opt_clks = usb_otg_hs_opt_clks, | |
3322 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3323 | }; | |
3324 | ||
3325 | /* | |
3326 | * 'usb_tll_hs' class | |
3327 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3328 | */ | |
3329 | ||
3330 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3331 | .rev_offs = 0x0000, | |
3332 | .sysc_offs = 0x0010, | |
3333 | .syss_offs = 0x0014, | |
3334 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3335 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3336 | SYSC_HAS_AUTOIDLE), | |
3337 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3338 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3339 | }; | |
3340 | ||
3341 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3342 | .name = "usb_tll_hs", | |
3343 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3344 | }; | |
3345 | ||
3346 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
3347 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
3348 | { .irq = -1 } | |
3349 | }; | |
3350 | ||
3351 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
3352 | .name = "usb_tll_hs", | |
3353 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3354 | .clkdm_name = "l3_init_clkdm", | |
3355 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
3356 | .main_clk = "usb_tll_hs_ick", | |
3357 | .prcm = { | |
3358 | .omap4 = { | |
3359 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3360 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3361 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3362 | }, |
3363 | }, | |
5844c4ea BC |
3364 | }; |
3365 | ||
3b54baad BC |
3366 | /* |
3367 | * 'wd_timer' class | |
3368 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3369 | * overflow condition | |
3370 | */ | |
3371 | ||
3372 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3373 | .rev_offs = 0x0000, | |
3374 | .sysc_offs = 0x0010, | |
3375 | .syss_offs = 0x0014, | |
3376 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3377 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3378 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3379 | SIDLE_SMART_WKUP), | |
3b54baad | 3380 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3381 | }; |
3382 | ||
3b54baad BC |
3383 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3384 | .name = "wd_timer", | |
3385 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3386 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
3387 | }; |
3388 | ||
3389 | /* wd_timer2 */ | |
3b54baad BC |
3390 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
3391 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3392 | { .irq = -1 } |
3b54baad BC |
3393 | }; |
3394 | ||
3b54baad BC |
3395 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3396 | .name = "wd_timer2", | |
3397 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3398 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 3399 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 3400 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
3401 | .prcm = { |
3402 | .omap4 = { | |
d0f0631d | 3403 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3404 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3405 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3406 | }, |
3407 | }, | |
9780a9cf BC |
3408 | }; |
3409 | ||
3b54baad | 3410 | /* wd_timer3 */ |
3b54baad BC |
3411 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
3412 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3413 | { .irq = -1 } |
9780a9cf BC |
3414 | }; |
3415 | ||
3b54baad BC |
3416 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3417 | .name = "wd_timer3", | |
3418 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3419 | .clkdm_name = "abe_clkdm", |
3b54baad | 3420 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 3421 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
3422 | .prcm = { |
3423 | .omap4 = { | |
d0f0631d | 3424 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3425 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3426 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3427 | }, |
3428 | }, | |
9780a9cf | 3429 | }; |
531ce0d5 | 3430 | |
844a3b63 | 3431 | |
af88fa9a | 3432 | /* |
844a3b63 | 3433 | * interfaces |
af88fa9a | 3434 | */ |
af88fa9a | 3435 | |
42b9e387 PW |
3436 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { |
3437 | { | |
3438 | .pa_start = 0x4a204000, | |
3439 | .pa_end = 0x4a2040ff, | |
3440 | .flags = ADDR_TYPE_RT | |
3441 | }, | |
3442 | { } | |
3443 | }; | |
3444 | ||
3445 | /* c2c -> c2c_target_fw */ | |
3446 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | |
3447 | .master = &omap44xx_c2c_hwmod, | |
3448 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3449 | .clk = "div_core_ck", | |
3450 | .addr = omap44xx_c2c_target_fw_addrs, | |
3451 | .user = OCP_USER_MPU, | |
3452 | }; | |
3453 | ||
3454 | /* l4_cfg -> c2c_target_fw */ | |
3455 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | |
3456 | .master = &omap44xx_l4_cfg_hwmod, | |
3457 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3458 | .clk = "l4_div_ck", | |
3459 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3460 | }; | |
3461 | ||
844a3b63 PW |
3462 | /* l3_main_1 -> dmm */ |
3463 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3464 | .master = &omap44xx_l3_main_1_hwmod, | |
3465 | .slave = &omap44xx_dmm_hwmod, | |
3466 | .clk = "l3_div_ck", | |
3467 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3468 | }; |
3469 | ||
844a3b63 | 3470 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 3471 | { |
844a3b63 PW |
3472 | .pa_start = 0x4e000000, |
3473 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
3474 | .flags = ADDR_TYPE_RT |
3475 | }, | |
844a3b63 | 3476 | { } |
af88fa9a BC |
3477 | }; |
3478 | ||
844a3b63 PW |
3479 | /* mpu -> dmm */ |
3480 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3481 | .master = &omap44xx_mpu_hwmod, | |
3482 | .slave = &omap44xx_dmm_hwmod, | |
3483 | .clk = "l3_div_ck", | |
3484 | .addr = omap44xx_dmm_addrs, | |
3485 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3486 | }; |
3487 | ||
42b9e387 PW |
3488 | /* c2c -> emif_fw */ |
3489 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | |
3490 | .master = &omap44xx_c2c_hwmod, | |
3491 | .slave = &omap44xx_emif_fw_hwmod, | |
3492 | .clk = "div_core_ck", | |
3493 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3494 | }; | |
3495 | ||
844a3b63 PW |
3496 | /* dmm -> emif_fw */ |
3497 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3498 | .master = &omap44xx_dmm_hwmod, | |
3499 | .slave = &omap44xx_emif_fw_hwmod, | |
3500 | .clk = "l3_div_ck", | |
3501 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3502 | }; | |
3503 | ||
3504 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3505 | { | |
3506 | .pa_start = 0x4a20c000, | |
3507 | .pa_end = 0x4a20c0ff, | |
3508 | .flags = ADDR_TYPE_RT | |
3509 | }, | |
3510 | { } | |
3511 | }; | |
3512 | ||
3513 | /* l4_cfg -> emif_fw */ | |
3514 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3515 | .master = &omap44xx_l4_cfg_hwmod, | |
3516 | .slave = &omap44xx_emif_fw_hwmod, | |
3517 | .clk = "l4_div_ck", | |
3518 | .addr = omap44xx_emif_fw_addrs, | |
3519 | .user = OCP_USER_MPU, | |
3520 | }; | |
3521 | ||
3522 | /* iva -> l3_instr */ | |
3523 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3524 | .master = &omap44xx_iva_hwmod, | |
3525 | .slave = &omap44xx_l3_instr_hwmod, | |
3526 | .clk = "l3_div_ck", | |
3527 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3528 | }; | |
3529 | ||
3530 | /* l3_main_3 -> l3_instr */ | |
3531 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3532 | .master = &omap44xx_l3_main_3_hwmod, | |
3533 | .slave = &omap44xx_l3_instr_hwmod, | |
3534 | .clk = "l3_div_ck", | |
3535 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3536 | }; | |
3537 | ||
3538 | /* dsp -> l3_main_1 */ | |
3539 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3540 | .master = &omap44xx_dsp_hwmod, | |
3541 | .slave = &omap44xx_l3_main_1_hwmod, | |
3542 | .clk = "l3_div_ck", | |
3543 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3544 | }; | |
3545 | ||
3546 | /* dss -> l3_main_1 */ | |
3547 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3548 | .master = &omap44xx_dss_hwmod, | |
3549 | .slave = &omap44xx_l3_main_1_hwmod, | |
3550 | .clk = "l3_div_ck", | |
3551 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3552 | }; | |
3553 | ||
3554 | /* l3_main_2 -> l3_main_1 */ | |
3555 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3556 | .master = &omap44xx_l3_main_2_hwmod, | |
3557 | .slave = &omap44xx_l3_main_1_hwmod, | |
3558 | .clk = "l3_div_ck", | |
3559 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3560 | }; | |
3561 | ||
3562 | /* l4_cfg -> l3_main_1 */ | |
3563 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3564 | .master = &omap44xx_l4_cfg_hwmod, | |
3565 | .slave = &omap44xx_l3_main_1_hwmod, | |
3566 | .clk = "l4_div_ck", | |
3567 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3568 | }; | |
3569 | ||
3570 | /* mmc1 -> l3_main_1 */ | |
3571 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3572 | .master = &omap44xx_mmc1_hwmod, | |
3573 | .slave = &omap44xx_l3_main_1_hwmod, | |
3574 | .clk = "l3_div_ck", | |
3575 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3576 | }; | |
3577 | ||
3578 | /* mmc2 -> l3_main_1 */ | |
3579 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3580 | .master = &omap44xx_mmc2_hwmod, | |
3581 | .slave = &omap44xx_l3_main_1_hwmod, | |
3582 | .clk = "l3_div_ck", | |
3583 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3584 | }; | |
3585 | ||
3586 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3587 | { | |
3588 | .pa_start = 0x44000000, | |
3589 | .pa_end = 0x44000fff, | |
3590 | .flags = ADDR_TYPE_RT | |
3591 | }, | |
3592 | { } | |
3593 | }; | |
3594 | ||
3595 | /* mpu -> l3_main_1 */ | |
3596 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3597 | .master = &omap44xx_mpu_hwmod, | |
3598 | .slave = &omap44xx_l3_main_1_hwmod, | |
3599 | .clk = "l3_div_ck", | |
3600 | .addr = omap44xx_l3_main_1_addrs, | |
3601 | .user = OCP_USER_MPU, | |
3602 | }; | |
3603 | ||
42b9e387 PW |
3604 | /* c2c_target_fw -> l3_main_2 */ |
3605 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | |
3606 | .master = &omap44xx_c2c_target_fw_hwmod, | |
3607 | .slave = &omap44xx_l3_main_2_hwmod, | |
3608 | .clk = "l3_div_ck", | |
3609 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3610 | }; | |
3611 | ||
844a3b63 PW |
3612 | /* dma_system -> l3_main_2 */ |
3613 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3614 | .master = &omap44xx_dma_system_hwmod, | |
3615 | .slave = &omap44xx_l3_main_2_hwmod, | |
3616 | .clk = "l3_div_ck", | |
3617 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3618 | }; | |
3619 | ||
b050f688 ML |
3620 | /* fdif -> l3_main_2 */ |
3621 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3622 | .master = &omap44xx_fdif_hwmod, | |
3623 | .slave = &omap44xx_l3_main_2_hwmod, | |
3624 | .clk = "l3_div_ck", | |
3625 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3626 | }; | |
3627 | ||
9def390e PW |
3628 | /* gpu -> l3_main_2 */ |
3629 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3630 | .master = &omap44xx_gpu_hwmod, | |
3631 | .slave = &omap44xx_l3_main_2_hwmod, | |
3632 | .clk = "l3_div_ck", | |
3633 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3634 | }; | |
3635 | ||
844a3b63 PW |
3636 | /* hsi -> l3_main_2 */ |
3637 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3638 | .master = &omap44xx_hsi_hwmod, | |
3639 | .slave = &omap44xx_l3_main_2_hwmod, | |
3640 | .clk = "l3_div_ck", | |
3641 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3642 | }; | |
3643 | ||
3644 | /* ipu -> l3_main_2 */ | |
3645 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3646 | .master = &omap44xx_ipu_hwmod, | |
3647 | .slave = &omap44xx_l3_main_2_hwmod, | |
3648 | .clk = "l3_div_ck", | |
3649 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3650 | }; | |
3651 | ||
3652 | /* iss -> l3_main_2 */ | |
3653 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3654 | .master = &omap44xx_iss_hwmod, | |
3655 | .slave = &omap44xx_l3_main_2_hwmod, | |
3656 | .clk = "l3_div_ck", | |
3657 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3658 | }; | |
3659 | ||
3660 | /* iva -> l3_main_2 */ | |
3661 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3662 | .master = &omap44xx_iva_hwmod, | |
3663 | .slave = &omap44xx_l3_main_2_hwmod, | |
3664 | .clk = "l3_div_ck", | |
3665 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3666 | }; | |
3667 | ||
3668 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
3669 | { | |
3670 | .pa_start = 0x44800000, | |
3671 | .pa_end = 0x44801fff, | |
3672 | .flags = ADDR_TYPE_RT | |
3673 | }, | |
3674 | { } | |
3675 | }; | |
3676 | ||
3677 | /* l3_main_1 -> l3_main_2 */ | |
3678 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3679 | .master = &omap44xx_l3_main_1_hwmod, | |
3680 | .slave = &omap44xx_l3_main_2_hwmod, | |
3681 | .clk = "l3_div_ck", | |
3682 | .addr = omap44xx_l3_main_2_addrs, | |
3683 | .user = OCP_USER_MPU, | |
3684 | }; | |
3685 | ||
3686 | /* l4_cfg -> l3_main_2 */ | |
3687 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3688 | .master = &omap44xx_l4_cfg_hwmod, | |
3689 | .slave = &omap44xx_l3_main_2_hwmod, | |
3690 | .clk = "l4_div_ck", | |
3691 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3692 | }; | |
3693 | ||
0c668875 BC |
3694 | /* usb_host_fs -> l3_main_2 */ |
3695 | static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = { | |
3696 | .master = &omap44xx_usb_host_fs_hwmod, | |
3697 | .slave = &omap44xx_l3_main_2_hwmod, | |
3698 | .clk = "l3_div_ck", | |
3699 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3700 | }; | |
3701 | ||
844a3b63 PW |
3702 | /* usb_host_hs -> l3_main_2 */ |
3703 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3704 | .master = &omap44xx_usb_host_hs_hwmod, | |
3705 | .slave = &omap44xx_l3_main_2_hwmod, | |
3706 | .clk = "l3_div_ck", | |
3707 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3708 | }; | |
3709 | ||
3710 | /* usb_otg_hs -> l3_main_2 */ | |
3711 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3712 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3713 | .slave = &omap44xx_l3_main_2_hwmod, | |
3714 | .clk = "l3_div_ck", | |
3715 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3716 | }; | |
3717 | ||
3718 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
3719 | { | |
3720 | .pa_start = 0x45000000, | |
3721 | .pa_end = 0x45000fff, | |
3722 | .flags = ADDR_TYPE_RT | |
3723 | }, | |
3724 | { } | |
3725 | }; | |
3726 | ||
3727 | /* l3_main_1 -> l3_main_3 */ | |
3728 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3729 | .master = &omap44xx_l3_main_1_hwmod, | |
3730 | .slave = &omap44xx_l3_main_3_hwmod, | |
3731 | .clk = "l3_div_ck", | |
3732 | .addr = omap44xx_l3_main_3_addrs, | |
3733 | .user = OCP_USER_MPU, | |
3734 | }; | |
3735 | ||
3736 | /* l3_main_2 -> l3_main_3 */ | |
3737 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3738 | .master = &omap44xx_l3_main_2_hwmod, | |
3739 | .slave = &omap44xx_l3_main_3_hwmod, | |
3740 | .clk = "l3_div_ck", | |
3741 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3742 | }; | |
3743 | ||
3744 | /* l4_cfg -> l3_main_3 */ | |
3745 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3746 | .master = &omap44xx_l4_cfg_hwmod, | |
3747 | .slave = &omap44xx_l3_main_3_hwmod, | |
3748 | .clk = "l4_div_ck", | |
3749 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3750 | }; | |
3751 | ||
3752 | /* aess -> l4_abe */ | |
3753 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { | |
3754 | .master = &omap44xx_aess_hwmod, | |
3755 | .slave = &omap44xx_l4_abe_hwmod, | |
3756 | .clk = "ocp_abe_iclk", | |
3757 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3758 | }; | |
3759 | ||
3760 | /* dsp -> l4_abe */ | |
3761 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3762 | .master = &omap44xx_dsp_hwmod, | |
3763 | .slave = &omap44xx_l4_abe_hwmod, | |
3764 | .clk = "ocp_abe_iclk", | |
3765 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3766 | }; | |
3767 | ||
3768 | /* l3_main_1 -> l4_abe */ | |
3769 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3770 | .master = &omap44xx_l3_main_1_hwmod, | |
3771 | .slave = &omap44xx_l4_abe_hwmod, | |
3772 | .clk = "l3_div_ck", | |
3773 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3774 | }; | |
3775 | ||
3776 | /* mpu -> l4_abe */ | |
3777 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3778 | .master = &omap44xx_mpu_hwmod, | |
3779 | .slave = &omap44xx_l4_abe_hwmod, | |
3780 | .clk = "ocp_abe_iclk", | |
3781 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3782 | }; | |
3783 | ||
3784 | /* l3_main_1 -> l4_cfg */ | |
3785 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3786 | .master = &omap44xx_l3_main_1_hwmod, | |
3787 | .slave = &omap44xx_l4_cfg_hwmod, | |
3788 | .clk = "l3_div_ck", | |
3789 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3790 | }; | |
3791 | ||
3792 | /* l3_main_2 -> l4_per */ | |
3793 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3794 | .master = &omap44xx_l3_main_2_hwmod, | |
3795 | .slave = &omap44xx_l4_per_hwmod, | |
3796 | .clk = "l3_div_ck", | |
3797 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3798 | }; | |
3799 | ||
3800 | /* l4_cfg -> l4_wkup */ | |
3801 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3802 | .master = &omap44xx_l4_cfg_hwmod, | |
3803 | .slave = &omap44xx_l4_wkup_hwmod, | |
3804 | .clk = "l4_div_ck", | |
3805 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3806 | }; | |
3807 | ||
3808 | /* mpu -> mpu_private */ | |
3809 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3810 | .master = &omap44xx_mpu_hwmod, | |
3811 | .slave = &omap44xx_mpu_private_hwmod, | |
3812 | .clk = "l3_div_ck", | |
3813 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3814 | }; | |
3815 | ||
3816 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { | |
3817 | { | |
3818 | .pa_start = 0x401f1000, | |
3819 | .pa_end = 0x401f13ff, | |
3820 | .flags = ADDR_TYPE_RT | |
3821 | }, | |
3822 | { } | |
3823 | }; | |
3824 | ||
3825 | /* l4_abe -> aess */ | |
3826 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { | |
3827 | .master = &omap44xx_l4_abe_hwmod, | |
3828 | .slave = &omap44xx_aess_hwmod, | |
3829 | .clk = "ocp_abe_iclk", | |
3830 | .addr = omap44xx_aess_addrs, | |
3831 | .user = OCP_USER_MPU, | |
3832 | }; | |
3833 | ||
3834 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
3835 | { | |
3836 | .pa_start = 0x490f1000, | |
3837 | .pa_end = 0x490f13ff, | |
3838 | .flags = ADDR_TYPE_RT | |
3839 | }, | |
3840 | { } | |
3841 | }; | |
3842 | ||
3843 | /* l4_abe -> aess (dma) */ | |
3844 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { | |
3845 | .master = &omap44xx_l4_abe_hwmod, | |
3846 | .slave = &omap44xx_aess_hwmod, | |
3847 | .clk = "ocp_abe_iclk", | |
3848 | .addr = omap44xx_aess_dma_addrs, | |
3849 | .user = OCP_USER_SDMA, | |
3850 | }; | |
3851 | ||
42b9e387 PW |
3852 | /* l3_main_2 -> c2c */ |
3853 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
3854 | .master = &omap44xx_l3_main_2_hwmod, | |
3855 | .slave = &omap44xx_c2c_hwmod, | |
3856 | .clk = "l3_div_ck", | |
3857 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3858 | }; | |
3859 | ||
844a3b63 PW |
3860 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
3861 | { | |
3862 | .pa_start = 0x4a304000, | |
3863 | .pa_end = 0x4a30401f, | |
3864 | .flags = ADDR_TYPE_RT | |
3865 | }, | |
3866 | { } | |
3867 | }; | |
3868 | ||
3869 | /* l4_wkup -> counter_32k */ | |
3870 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
3871 | .master = &omap44xx_l4_wkup_hwmod, | |
3872 | .slave = &omap44xx_counter_32k_hwmod, | |
3873 | .clk = "l4_wkup_clk_mux_ck", | |
3874 | .addr = omap44xx_counter_32k_addrs, | |
3875 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3876 | }; | |
3877 | ||
3878 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
3879 | { | |
3880 | .pa_start = 0x4a056000, | |
3881 | .pa_end = 0x4a056fff, | |
3882 | .flags = ADDR_TYPE_RT | |
3883 | }, | |
3884 | { } | |
3885 | }; | |
3886 | ||
3887 | /* l4_cfg -> dma_system */ | |
3888 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
3889 | .master = &omap44xx_l4_cfg_hwmod, | |
3890 | .slave = &omap44xx_dma_system_hwmod, | |
3891 | .clk = "l4_div_ck", | |
3892 | .addr = omap44xx_dma_system_addrs, | |
3893 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3894 | }; | |
3895 | ||
3896 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
3897 | { | |
3898 | .name = "mpu", | |
3899 | .pa_start = 0x4012e000, | |
3900 | .pa_end = 0x4012e07f, | |
3901 | .flags = ADDR_TYPE_RT | |
3902 | }, | |
3903 | { } | |
3904 | }; | |
3905 | ||
3906 | /* l4_abe -> dmic */ | |
3907 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
3908 | .master = &omap44xx_l4_abe_hwmod, | |
3909 | .slave = &omap44xx_dmic_hwmod, | |
3910 | .clk = "ocp_abe_iclk", | |
3911 | .addr = omap44xx_dmic_addrs, | |
3912 | .user = OCP_USER_MPU, | |
3913 | }; | |
3914 | ||
3915 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
3916 | { | |
3917 | .name = "dma", | |
3918 | .pa_start = 0x4902e000, | |
3919 | .pa_end = 0x4902e07f, | |
3920 | .flags = ADDR_TYPE_RT | |
3921 | }, | |
3922 | { } | |
3923 | }; | |
3924 | ||
3925 | /* l4_abe -> dmic (dma) */ | |
3926 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
3927 | .master = &omap44xx_l4_abe_hwmod, | |
3928 | .slave = &omap44xx_dmic_hwmod, | |
3929 | .clk = "ocp_abe_iclk", | |
3930 | .addr = omap44xx_dmic_dma_addrs, | |
3931 | .user = OCP_USER_SDMA, | |
3932 | }; | |
3933 | ||
3934 | /* dsp -> iva */ | |
3935 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
3936 | .master = &omap44xx_dsp_hwmod, | |
3937 | .slave = &omap44xx_iva_hwmod, | |
3938 | .clk = "dpll_iva_m5x2_ck", | |
3939 | .user = OCP_USER_DSP, | |
3940 | }; | |
3941 | ||
42b9e387 PW |
3942 | /* dsp -> sl2if */ |
3943 | static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { | |
3944 | .master = &omap44xx_dsp_hwmod, | |
3945 | .slave = &omap44xx_sl2if_hwmod, | |
3946 | .clk = "dpll_iva_m5x2_ck", | |
3947 | .user = OCP_USER_DSP, | |
3948 | }; | |
3949 | ||
844a3b63 PW |
3950 | /* l4_cfg -> dsp */ |
3951 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
3952 | .master = &omap44xx_l4_cfg_hwmod, | |
3953 | .slave = &omap44xx_dsp_hwmod, | |
3954 | .clk = "l4_div_ck", | |
3955 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3956 | }; | |
3957 | ||
3958 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
3959 | { | |
3960 | .pa_start = 0x58000000, | |
3961 | .pa_end = 0x5800007f, | |
3962 | .flags = ADDR_TYPE_RT | |
3963 | }, | |
3964 | { } | |
3965 | }; | |
3966 | ||
3967 | /* l3_main_2 -> dss */ | |
3968 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
3969 | .master = &omap44xx_l3_main_2_hwmod, | |
3970 | .slave = &omap44xx_dss_hwmod, | |
3971 | .clk = "dss_fck", | |
3972 | .addr = omap44xx_dss_dma_addrs, | |
3973 | .user = OCP_USER_SDMA, | |
3974 | }; | |
3975 | ||
3976 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
3977 | { | |
3978 | .pa_start = 0x48040000, | |
3979 | .pa_end = 0x4804007f, | |
3980 | .flags = ADDR_TYPE_RT | |
3981 | }, | |
3982 | { } | |
3983 | }; | |
3984 | ||
3985 | /* l4_per -> dss */ | |
3986 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
3987 | .master = &omap44xx_l4_per_hwmod, | |
3988 | .slave = &omap44xx_dss_hwmod, | |
3989 | .clk = "l4_div_ck", | |
3990 | .addr = omap44xx_dss_addrs, | |
3991 | .user = OCP_USER_MPU, | |
3992 | }; | |
3993 | ||
3994 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
3995 | { | |
3996 | .pa_start = 0x58001000, | |
3997 | .pa_end = 0x58001fff, | |
3998 | .flags = ADDR_TYPE_RT | |
3999 | }, | |
4000 | { } | |
4001 | }; | |
4002 | ||
4003 | /* l3_main_2 -> dss_dispc */ | |
4004 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
4005 | .master = &omap44xx_l3_main_2_hwmod, | |
4006 | .slave = &omap44xx_dss_dispc_hwmod, | |
4007 | .clk = "dss_fck", | |
4008 | .addr = omap44xx_dss_dispc_dma_addrs, | |
4009 | .user = OCP_USER_SDMA, | |
4010 | }; | |
4011 | ||
4012 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
4013 | { | |
4014 | .pa_start = 0x48041000, | |
4015 | .pa_end = 0x48041fff, | |
4016 | .flags = ADDR_TYPE_RT | |
4017 | }, | |
4018 | { } | |
4019 | }; | |
4020 | ||
4021 | /* l4_per -> dss_dispc */ | |
4022 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
4023 | .master = &omap44xx_l4_per_hwmod, | |
4024 | .slave = &omap44xx_dss_dispc_hwmod, | |
4025 | .clk = "l4_div_ck", | |
4026 | .addr = omap44xx_dss_dispc_addrs, | |
4027 | .user = OCP_USER_MPU, | |
4028 | }; | |
4029 | ||
4030 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
4031 | { | |
4032 | .pa_start = 0x58004000, | |
4033 | .pa_end = 0x580041ff, | |
4034 | .flags = ADDR_TYPE_RT | |
4035 | }, | |
4036 | { } | |
4037 | }; | |
4038 | ||
4039 | /* l3_main_2 -> dss_dsi1 */ | |
4040 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
4041 | .master = &omap44xx_l3_main_2_hwmod, | |
4042 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4043 | .clk = "dss_fck", | |
4044 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
4045 | .user = OCP_USER_SDMA, | |
4046 | }; | |
4047 | ||
4048 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
4049 | { | |
4050 | .pa_start = 0x48044000, | |
4051 | .pa_end = 0x480441ff, | |
4052 | .flags = ADDR_TYPE_RT | |
4053 | }, | |
4054 | { } | |
4055 | }; | |
4056 | ||
4057 | /* l4_per -> dss_dsi1 */ | |
4058 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
4059 | .master = &omap44xx_l4_per_hwmod, | |
4060 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4061 | .clk = "l4_div_ck", | |
4062 | .addr = omap44xx_dss_dsi1_addrs, | |
4063 | .user = OCP_USER_MPU, | |
4064 | }; | |
4065 | ||
4066 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
4067 | { | |
4068 | .pa_start = 0x58005000, | |
4069 | .pa_end = 0x580051ff, | |
4070 | .flags = ADDR_TYPE_RT | |
4071 | }, | |
4072 | { } | |
4073 | }; | |
4074 | ||
4075 | /* l3_main_2 -> dss_dsi2 */ | |
4076 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
4077 | .master = &omap44xx_l3_main_2_hwmod, | |
4078 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4079 | .clk = "dss_fck", | |
4080 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
4081 | .user = OCP_USER_SDMA, | |
4082 | }; | |
4083 | ||
4084 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
4085 | { | |
4086 | .pa_start = 0x48045000, | |
4087 | .pa_end = 0x480451ff, | |
4088 | .flags = ADDR_TYPE_RT | |
4089 | }, | |
4090 | { } | |
4091 | }; | |
4092 | ||
4093 | /* l4_per -> dss_dsi2 */ | |
4094 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
4095 | .master = &omap44xx_l4_per_hwmod, | |
4096 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4097 | .clk = "l4_div_ck", | |
4098 | .addr = omap44xx_dss_dsi2_addrs, | |
4099 | .user = OCP_USER_MPU, | |
4100 | }; | |
4101 | ||
4102 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
4103 | { | |
4104 | .pa_start = 0x58006000, | |
4105 | .pa_end = 0x58006fff, | |
4106 | .flags = ADDR_TYPE_RT | |
4107 | }, | |
4108 | { } | |
4109 | }; | |
4110 | ||
4111 | /* l3_main_2 -> dss_hdmi */ | |
4112 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
4113 | .master = &omap44xx_l3_main_2_hwmod, | |
4114 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4115 | .clk = "dss_fck", | |
4116 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
4117 | .user = OCP_USER_SDMA, | |
4118 | }; | |
4119 | ||
4120 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
4121 | { | |
4122 | .pa_start = 0x48046000, | |
4123 | .pa_end = 0x48046fff, | |
4124 | .flags = ADDR_TYPE_RT | |
4125 | }, | |
4126 | { } | |
4127 | }; | |
4128 | ||
4129 | /* l4_per -> dss_hdmi */ | |
4130 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
4131 | .master = &omap44xx_l4_per_hwmod, | |
4132 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4133 | .clk = "l4_div_ck", | |
4134 | .addr = omap44xx_dss_hdmi_addrs, | |
4135 | .user = OCP_USER_MPU, | |
4136 | }; | |
4137 | ||
4138 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
4139 | { | |
4140 | .pa_start = 0x58002000, | |
4141 | .pa_end = 0x580020ff, | |
4142 | .flags = ADDR_TYPE_RT | |
4143 | }, | |
4144 | { } | |
4145 | }; | |
4146 | ||
4147 | /* l3_main_2 -> dss_rfbi */ | |
4148 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
4149 | .master = &omap44xx_l3_main_2_hwmod, | |
4150 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4151 | .clk = "dss_fck", | |
4152 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
4153 | .user = OCP_USER_SDMA, | |
4154 | }; | |
4155 | ||
4156 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
4157 | { | |
4158 | .pa_start = 0x48042000, | |
4159 | .pa_end = 0x480420ff, | |
4160 | .flags = ADDR_TYPE_RT | |
4161 | }, | |
4162 | { } | |
4163 | }; | |
4164 | ||
4165 | /* l4_per -> dss_rfbi */ | |
4166 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
4167 | .master = &omap44xx_l4_per_hwmod, | |
4168 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4169 | .clk = "l4_div_ck", | |
4170 | .addr = omap44xx_dss_rfbi_addrs, | |
4171 | .user = OCP_USER_MPU, | |
4172 | }; | |
4173 | ||
4174 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
4175 | { | |
4176 | .pa_start = 0x58003000, | |
4177 | .pa_end = 0x580030ff, | |
4178 | .flags = ADDR_TYPE_RT | |
4179 | }, | |
4180 | { } | |
4181 | }; | |
4182 | ||
4183 | /* l3_main_2 -> dss_venc */ | |
4184 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
4185 | .master = &omap44xx_l3_main_2_hwmod, | |
4186 | .slave = &omap44xx_dss_venc_hwmod, | |
4187 | .clk = "dss_fck", | |
4188 | .addr = omap44xx_dss_venc_dma_addrs, | |
4189 | .user = OCP_USER_SDMA, | |
4190 | }; | |
4191 | ||
4192 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
4193 | { | |
4194 | .pa_start = 0x48043000, | |
4195 | .pa_end = 0x480430ff, | |
4196 | .flags = ADDR_TYPE_RT | |
4197 | }, | |
4198 | { } | |
4199 | }; | |
4200 | ||
4201 | /* l4_per -> dss_venc */ | |
4202 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
4203 | .master = &omap44xx_l4_per_hwmod, | |
4204 | .slave = &omap44xx_dss_venc_hwmod, | |
4205 | .clk = "l4_div_ck", | |
4206 | .addr = omap44xx_dss_venc_addrs, | |
4207 | .user = OCP_USER_MPU, | |
4208 | }; | |
4209 | ||
42b9e387 PW |
4210 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
4211 | { | |
4212 | .pa_start = 0x48078000, | |
4213 | .pa_end = 0x48078fff, | |
4214 | .flags = ADDR_TYPE_RT | |
4215 | }, | |
4216 | { } | |
4217 | }; | |
4218 | ||
4219 | /* l4_per -> elm */ | |
4220 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
4221 | .master = &omap44xx_l4_per_hwmod, | |
4222 | .slave = &omap44xx_elm_hwmod, | |
4223 | .clk = "l4_div_ck", | |
4224 | .addr = omap44xx_elm_addrs, | |
4225 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4226 | }; | |
4227 | ||
bf30f950 PW |
4228 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
4229 | { | |
4230 | .pa_start = 0x4c000000, | |
4231 | .pa_end = 0x4c0000ff, | |
4232 | .flags = ADDR_TYPE_RT | |
4233 | }, | |
4234 | { } | |
4235 | }; | |
4236 | ||
4237 | /* emif_fw -> emif1 */ | |
4238 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | |
4239 | .master = &omap44xx_emif_fw_hwmod, | |
4240 | .slave = &omap44xx_emif1_hwmod, | |
4241 | .clk = "l3_div_ck", | |
4242 | .addr = omap44xx_emif1_addrs, | |
4243 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4244 | }; | |
4245 | ||
4246 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | |
4247 | { | |
4248 | .pa_start = 0x4d000000, | |
4249 | .pa_end = 0x4d0000ff, | |
4250 | .flags = ADDR_TYPE_RT | |
4251 | }, | |
4252 | { } | |
4253 | }; | |
4254 | ||
4255 | /* emif_fw -> emif2 */ | |
4256 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | |
4257 | .master = &omap44xx_emif_fw_hwmod, | |
4258 | .slave = &omap44xx_emif2_hwmod, | |
4259 | .clk = "l3_div_ck", | |
4260 | .addr = omap44xx_emif2_addrs, | |
4261 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4262 | }; | |
4263 | ||
b050f688 ML |
4264 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
4265 | { | |
4266 | .pa_start = 0x4a10a000, | |
4267 | .pa_end = 0x4a10a1ff, | |
4268 | .flags = ADDR_TYPE_RT | |
4269 | }, | |
4270 | { } | |
4271 | }; | |
4272 | ||
4273 | /* l4_cfg -> fdif */ | |
4274 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4275 | .master = &omap44xx_l4_cfg_hwmod, | |
4276 | .slave = &omap44xx_fdif_hwmod, | |
4277 | .clk = "l4_div_ck", | |
4278 | .addr = omap44xx_fdif_addrs, | |
4279 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4280 | }; | |
4281 | ||
844a3b63 PW |
4282 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
4283 | { | |
4284 | .pa_start = 0x4a310000, | |
4285 | .pa_end = 0x4a3101ff, | |
4286 | .flags = ADDR_TYPE_RT | |
4287 | }, | |
4288 | { } | |
4289 | }; | |
4290 | ||
4291 | /* l4_wkup -> gpio1 */ | |
4292 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4293 | .master = &omap44xx_l4_wkup_hwmod, | |
4294 | .slave = &omap44xx_gpio1_hwmod, | |
4295 | .clk = "l4_wkup_clk_mux_ck", | |
4296 | .addr = omap44xx_gpio1_addrs, | |
4297 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4298 | }; | |
4299 | ||
4300 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
4301 | { | |
4302 | .pa_start = 0x48055000, | |
4303 | .pa_end = 0x480551ff, | |
4304 | .flags = ADDR_TYPE_RT | |
4305 | }, | |
4306 | { } | |
4307 | }; | |
4308 | ||
4309 | /* l4_per -> gpio2 */ | |
4310 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4311 | .master = &omap44xx_l4_per_hwmod, | |
4312 | .slave = &omap44xx_gpio2_hwmod, | |
4313 | .clk = "l4_div_ck", | |
4314 | .addr = omap44xx_gpio2_addrs, | |
4315 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4316 | }; | |
4317 | ||
4318 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
4319 | { | |
4320 | .pa_start = 0x48057000, | |
4321 | .pa_end = 0x480571ff, | |
4322 | .flags = ADDR_TYPE_RT | |
4323 | }, | |
4324 | { } | |
4325 | }; | |
4326 | ||
4327 | /* l4_per -> gpio3 */ | |
4328 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4329 | .master = &omap44xx_l4_per_hwmod, | |
4330 | .slave = &omap44xx_gpio3_hwmod, | |
4331 | .clk = "l4_div_ck", | |
4332 | .addr = omap44xx_gpio3_addrs, | |
4333 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4334 | }; | |
4335 | ||
4336 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
4337 | { | |
4338 | .pa_start = 0x48059000, | |
4339 | .pa_end = 0x480591ff, | |
4340 | .flags = ADDR_TYPE_RT | |
4341 | }, | |
4342 | { } | |
4343 | }; | |
4344 | ||
4345 | /* l4_per -> gpio4 */ | |
4346 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4347 | .master = &omap44xx_l4_per_hwmod, | |
4348 | .slave = &omap44xx_gpio4_hwmod, | |
4349 | .clk = "l4_div_ck", | |
4350 | .addr = omap44xx_gpio4_addrs, | |
4351 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4352 | }; | |
4353 | ||
4354 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
4355 | { | |
4356 | .pa_start = 0x4805b000, | |
4357 | .pa_end = 0x4805b1ff, | |
4358 | .flags = ADDR_TYPE_RT | |
4359 | }, | |
4360 | { } | |
4361 | }; | |
4362 | ||
4363 | /* l4_per -> gpio5 */ | |
4364 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4365 | .master = &omap44xx_l4_per_hwmod, | |
4366 | .slave = &omap44xx_gpio5_hwmod, | |
4367 | .clk = "l4_div_ck", | |
4368 | .addr = omap44xx_gpio5_addrs, | |
4369 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4370 | }; | |
4371 | ||
4372 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
4373 | { | |
4374 | .pa_start = 0x4805d000, | |
4375 | .pa_end = 0x4805d1ff, | |
4376 | .flags = ADDR_TYPE_RT | |
4377 | }, | |
4378 | { } | |
4379 | }; | |
4380 | ||
4381 | /* l4_per -> gpio6 */ | |
4382 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4383 | .master = &omap44xx_l4_per_hwmod, | |
4384 | .slave = &omap44xx_gpio6_hwmod, | |
4385 | .clk = "l4_div_ck", | |
4386 | .addr = omap44xx_gpio6_addrs, | |
4387 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4388 | }; | |
4389 | ||
eb42b5d3 BC |
4390 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
4391 | { | |
4392 | .pa_start = 0x50000000, | |
4393 | .pa_end = 0x500003ff, | |
4394 | .flags = ADDR_TYPE_RT | |
4395 | }, | |
4396 | { } | |
4397 | }; | |
4398 | ||
4399 | /* l3_main_2 -> gpmc */ | |
4400 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4401 | .master = &omap44xx_l3_main_2_hwmod, | |
4402 | .slave = &omap44xx_gpmc_hwmod, | |
4403 | .clk = "l3_div_ck", | |
4404 | .addr = omap44xx_gpmc_addrs, | |
4405 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4406 | }; | |
4407 | ||
9def390e PW |
4408 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4409 | { | |
4410 | .pa_start = 0x56000000, | |
4411 | .pa_end = 0x5600ffff, | |
4412 | .flags = ADDR_TYPE_RT | |
4413 | }, | |
4414 | { } | |
4415 | }; | |
4416 | ||
4417 | /* l3_main_2 -> gpu */ | |
4418 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4419 | .master = &omap44xx_l3_main_2_hwmod, | |
4420 | .slave = &omap44xx_gpu_hwmod, | |
4421 | .clk = "l3_div_ck", | |
4422 | .addr = omap44xx_gpu_addrs, | |
4423 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4424 | }; | |
4425 | ||
a091c08e PW |
4426 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4427 | { | |
4428 | .pa_start = 0x480b2000, | |
4429 | .pa_end = 0x480b201f, | |
4430 | .flags = ADDR_TYPE_RT | |
4431 | }, | |
4432 | { } | |
4433 | }; | |
4434 | ||
4435 | /* l4_per -> hdq1w */ | |
4436 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4437 | .master = &omap44xx_l4_per_hwmod, | |
4438 | .slave = &omap44xx_hdq1w_hwmod, | |
4439 | .clk = "l4_div_ck", | |
4440 | .addr = omap44xx_hdq1w_addrs, | |
4441 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4442 | }; | |
4443 | ||
844a3b63 PW |
4444 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4445 | { | |
4446 | .pa_start = 0x4a058000, | |
4447 | .pa_end = 0x4a05bfff, | |
4448 | .flags = ADDR_TYPE_RT | |
4449 | }, | |
4450 | { } | |
4451 | }; | |
4452 | ||
4453 | /* l4_cfg -> hsi */ | |
4454 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4455 | .master = &omap44xx_l4_cfg_hwmod, | |
4456 | .slave = &omap44xx_hsi_hwmod, | |
4457 | .clk = "l4_div_ck", | |
4458 | .addr = omap44xx_hsi_addrs, | |
4459 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4460 | }; | |
4461 | ||
4462 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
4463 | { | |
4464 | .pa_start = 0x48070000, | |
4465 | .pa_end = 0x480700ff, | |
4466 | .flags = ADDR_TYPE_RT | |
4467 | }, | |
4468 | { } | |
4469 | }; | |
4470 | ||
4471 | /* l4_per -> i2c1 */ | |
4472 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4473 | .master = &omap44xx_l4_per_hwmod, | |
4474 | .slave = &omap44xx_i2c1_hwmod, | |
4475 | .clk = "l4_div_ck", | |
4476 | .addr = omap44xx_i2c1_addrs, | |
4477 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4478 | }; | |
4479 | ||
4480 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
4481 | { | |
4482 | .pa_start = 0x48072000, | |
4483 | .pa_end = 0x480720ff, | |
4484 | .flags = ADDR_TYPE_RT | |
4485 | }, | |
4486 | { } | |
4487 | }; | |
4488 | ||
4489 | /* l4_per -> i2c2 */ | |
4490 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4491 | .master = &omap44xx_l4_per_hwmod, | |
4492 | .slave = &omap44xx_i2c2_hwmod, | |
4493 | .clk = "l4_div_ck", | |
4494 | .addr = omap44xx_i2c2_addrs, | |
4495 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4496 | }; | |
4497 | ||
4498 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
4499 | { | |
4500 | .pa_start = 0x48060000, | |
4501 | .pa_end = 0x480600ff, | |
4502 | .flags = ADDR_TYPE_RT | |
4503 | }, | |
4504 | { } | |
4505 | }; | |
4506 | ||
4507 | /* l4_per -> i2c3 */ | |
4508 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4509 | .master = &omap44xx_l4_per_hwmod, | |
4510 | .slave = &omap44xx_i2c3_hwmod, | |
4511 | .clk = "l4_div_ck", | |
4512 | .addr = omap44xx_i2c3_addrs, | |
4513 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4514 | }; | |
4515 | ||
4516 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
4517 | { | |
4518 | .pa_start = 0x48350000, | |
4519 | .pa_end = 0x483500ff, | |
4520 | .flags = ADDR_TYPE_RT | |
4521 | }, | |
4522 | { } | |
4523 | }; | |
4524 | ||
4525 | /* l4_per -> i2c4 */ | |
4526 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4527 | .master = &omap44xx_l4_per_hwmod, | |
4528 | .slave = &omap44xx_i2c4_hwmod, | |
4529 | .clk = "l4_div_ck", | |
4530 | .addr = omap44xx_i2c4_addrs, | |
4531 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4532 | }; | |
4533 | ||
4534 | /* l3_main_2 -> ipu */ | |
4535 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4536 | .master = &omap44xx_l3_main_2_hwmod, | |
4537 | .slave = &omap44xx_ipu_hwmod, | |
4538 | .clk = "l3_div_ck", | |
4539 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4540 | }; | |
4541 | ||
4542 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
4543 | { | |
4544 | .pa_start = 0x52000000, | |
4545 | .pa_end = 0x520000ff, | |
4546 | .flags = ADDR_TYPE_RT | |
4547 | }, | |
4548 | { } | |
4549 | }; | |
4550 | ||
4551 | /* l3_main_2 -> iss */ | |
4552 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
4553 | .master = &omap44xx_l3_main_2_hwmod, | |
4554 | .slave = &omap44xx_iss_hwmod, | |
4555 | .clk = "l3_div_ck", | |
4556 | .addr = omap44xx_iss_addrs, | |
4557 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4558 | }; | |
4559 | ||
42b9e387 PW |
4560 | /* iva -> sl2if */ |
4561 | static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { | |
4562 | .master = &omap44xx_iva_hwmod, | |
4563 | .slave = &omap44xx_sl2if_hwmod, | |
4564 | .clk = "dpll_iva_m5x2_ck", | |
4565 | .user = OCP_USER_IVA, | |
4566 | }; | |
4567 | ||
844a3b63 PW |
4568 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
4569 | { | |
4570 | .pa_start = 0x5a000000, | |
4571 | .pa_end = 0x5a07ffff, | |
4572 | .flags = ADDR_TYPE_RT | |
4573 | }, | |
4574 | { } | |
4575 | }; | |
4576 | ||
4577 | /* l3_main_2 -> iva */ | |
4578 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
4579 | .master = &omap44xx_l3_main_2_hwmod, | |
4580 | .slave = &omap44xx_iva_hwmod, | |
4581 | .clk = "l3_div_ck", | |
4582 | .addr = omap44xx_iva_addrs, | |
4583 | .user = OCP_USER_MPU, | |
4584 | }; | |
4585 | ||
4586 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
4587 | { | |
4588 | .pa_start = 0x4a31c000, | |
4589 | .pa_end = 0x4a31c07f, | |
4590 | .flags = ADDR_TYPE_RT | |
4591 | }, | |
4592 | { } | |
4593 | }; | |
4594 | ||
4595 | /* l4_wkup -> kbd */ | |
4596 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
4597 | .master = &omap44xx_l4_wkup_hwmod, | |
4598 | .slave = &omap44xx_kbd_hwmod, | |
4599 | .clk = "l4_wkup_clk_mux_ck", | |
4600 | .addr = omap44xx_kbd_addrs, | |
4601 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4602 | }; | |
4603 | ||
4604 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
4605 | { | |
4606 | .pa_start = 0x4a0f4000, | |
4607 | .pa_end = 0x4a0f41ff, | |
4608 | .flags = ADDR_TYPE_RT | |
4609 | }, | |
4610 | { } | |
4611 | }; | |
4612 | ||
4613 | /* l4_cfg -> mailbox */ | |
4614 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4615 | .master = &omap44xx_l4_cfg_hwmod, | |
4616 | .slave = &omap44xx_mailbox_hwmod, | |
4617 | .clk = "l4_div_ck", | |
4618 | .addr = omap44xx_mailbox_addrs, | |
4619 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4620 | }; | |
4621 | ||
896d4e98 BC |
4622 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
4623 | { | |
4624 | .pa_start = 0x40128000, | |
4625 | .pa_end = 0x401283ff, | |
4626 | .flags = ADDR_TYPE_RT | |
4627 | }, | |
4628 | { } | |
4629 | }; | |
4630 | ||
4631 | /* l4_abe -> mcasp */ | |
4632 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
4633 | .master = &omap44xx_l4_abe_hwmod, | |
4634 | .slave = &omap44xx_mcasp_hwmod, | |
4635 | .clk = "ocp_abe_iclk", | |
4636 | .addr = omap44xx_mcasp_addrs, | |
4637 | .user = OCP_USER_MPU, | |
4638 | }; | |
4639 | ||
4640 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
4641 | { | |
4642 | .pa_start = 0x49028000, | |
4643 | .pa_end = 0x490283ff, | |
4644 | .flags = ADDR_TYPE_RT | |
4645 | }, | |
4646 | { } | |
4647 | }; | |
4648 | ||
4649 | /* l4_abe -> mcasp (dma) */ | |
4650 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
4651 | .master = &omap44xx_l4_abe_hwmod, | |
4652 | .slave = &omap44xx_mcasp_hwmod, | |
4653 | .clk = "ocp_abe_iclk", | |
4654 | .addr = omap44xx_mcasp_dma_addrs, | |
4655 | .user = OCP_USER_SDMA, | |
4656 | }; | |
4657 | ||
844a3b63 PW |
4658 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
4659 | { | |
4660 | .name = "mpu", | |
4661 | .pa_start = 0x40122000, | |
4662 | .pa_end = 0x401220ff, | |
4663 | .flags = ADDR_TYPE_RT | |
4664 | }, | |
4665 | { } | |
4666 | }; | |
4667 | ||
4668 | /* l4_abe -> mcbsp1 */ | |
4669 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4670 | .master = &omap44xx_l4_abe_hwmod, | |
4671 | .slave = &omap44xx_mcbsp1_hwmod, | |
4672 | .clk = "ocp_abe_iclk", | |
4673 | .addr = omap44xx_mcbsp1_addrs, | |
4674 | .user = OCP_USER_MPU, | |
4675 | }; | |
4676 | ||
4677 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
4678 | { | |
4679 | .name = "dma", | |
4680 | .pa_start = 0x49022000, | |
4681 | .pa_end = 0x490220ff, | |
4682 | .flags = ADDR_TYPE_RT | |
4683 | }, | |
4684 | { } | |
4685 | }; | |
4686 | ||
4687 | /* l4_abe -> mcbsp1 (dma) */ | |
4688 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
4689 | .master = &omap44xx_l4_abe_hwmod, | |
4690 | .slave = &omap44xx_mcbsp1_hwmod, | |
4691 | .clk = "ocp_abe_iclk", | |
4692 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4693 | .user = OCP_USER_SDMA, | |
4694 | }; | |
4695 | ||
4696 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
4697 | { | |
4698 | .name = "mpu", | |
4699 | .pa_start = 0x40124000, | |
4700 | .pa_end = 0x401240ff, | |
4701 | .flags = ADDR_TYPE_RT | |
4702 | }, | |
4703 | { } | |
4704 | }; | |
4705 | ||
4706 | /* l4_abe -> mcbsp2 */ | |
4707 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4708 | .master = &omap44xx_l4_abe_hwmod, | |
4709 | .slave = &omap44xx_mcbsp2_hwmod, | |
4710 | .clk = "ocp_abe_iclk", | |
4711 | .addr = omap44xx_mcbsp2_addrs, | |
4712 | .user = OCP_USER_MPU, | |
4713 | }; | |
4714 | ||
4715 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
4716 | { | |
4717 | .name = "dma", | |
4718 | .pa_start = 0x49024000, | |
4719 | .pa_end = 0x490240ff, | |
4720 | .flags = ADDR_TYPE_RT | |
4721 | }, | |
4722 | { } | |
4723 | }; | |
4724 | ||
4725 | /* l4_abe -> mcbsp2 (dma) */ | |
4726 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
4727 | .master = &omap44xx_l4_abe_hwmod, | |
4728 | .slave = &omap44xx_mcbsp2_hwmod, | |
4729 | .clk = "ocp_abe_iclk", | |
4730 | .addr = omap44xx_mcbsp2_dma_addrs, | |
4731 | .user = OCP_USER_SDMA, | |
4732 | }; | |
4733 | ||
4734 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
4735 | { | |
4736 | .name = "mpu", | |
4737 | .pa_start = 0x40126000, | |
4738 | .pa_end = 0x401260ff, | |
4739 | .flags = ADDR_TYPE_RT | |
4740 | }, | |
4741 | { } | |
4742 | }; | |
4743 | ||
4744 | /* l4_abe -> mcbsp3 */ | |
4745 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
4746 | .master = &omap44xx_l4_abe_hwmod, | |
4747 | .slave = &omap44xx_mcbsp3_hwmod, | |
4748 | .clk = "ocp_abe_iclk", | |
4749 | .addr = omap44xx_mcbsp3_addrs, | |
4750 | .user = OCP_USER_MPU, | |
4751 | }; | |
4752 | ||
4753 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
4754 | { | |
4755 | .name = "dma", | |
4756 | .pa_start = 0x49026000, | |
4757 | .pa_end = 0x490260ff, | |
4758 | .flags = ADDR_TYPE_RT | |
4759 | }, | |
4760 | { } | |
4761 | }; | |
4762 | ||
4763 | /* l4_abe -> mcbsp3 (dma) */ | |
4764 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
4765 | .master = &omap44xx_l4_abe_hwmod, | |
4766 | .slave = &omap44xx_mcbsp3_hwmod, | |
4767 | .clk = "ocp_abe_iclk", | |
4768 | .addr = omap44xx_mcbsp3_dma_addrs, | |
4769 | .user = OCP_USER_SDMA, | |
4770 | }; | |
4771 | ||
4772 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
4773 | { | |
4774 | .pa_start = 0x48096000, | |
4775 | .pa_end = 0x480960ff, | |
4776 | .flags = ADDR_TYPE_RT | |
4777 | }, | |
4778 | { } | |
4779 | }; | |
4780 | ||
4781 | /* l4_per -> mcbsp4 */ | |
4782 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
4783 | .master = &omap44xx_l4_per_hwmod, | |
4784 | .slave = &omap44xx_mcbsp4_hwmod, | |
4785 | .clk = "l4_div_ck", | |
4786 | .addr = omap44xx_mcbsp4_addrs, | |
4787 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4788 | }; | |
4789 | ||
4790 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
4791 | { | |
4792 | .pa_start = 0x40132000, | |
4793 | .pa_end = 0x4013207f, | |
4794 | .flags = ADDR_TYPE_RT | |
4795 | }, | |
4796 | { } | |
4797 | }; | |
4798 | ||
4799 | /* l4_abe -> mcpdm */ | |
4800 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
4801 | .master = &omap44xx_l4_abe_hwmod, | |
4802 | .slave = &omap44xx_mcpdm_hwmod, | |
4803 | .clk = "ocp_abe_iclk", | |
4804 | .addr = omap44xx_mcpdm_addrs, | |
4805 | .user = OCP_USER_MPU, | |
4806 | }; | |
4807 | ||
4808 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
4809 | { | |
4810 | .pa_start = 0x49032000, | |
4811 | .pa_end = 0x4903207f, | |
4812 | .flags = ADDR_TYPE_RT | |
4813 | }, | |
4814 | { } | |
4815 | }; | |
4816 | ||
4817 | /* l4_abe -> mcpdm (dma) */ | |
4818 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
4819 | .master = &omap44xx_l4_abe_hwmod, | |
4820 | .slave = &omap44xx_mcpdm_hwmod, | |
4821 | .clk = "ocp_abe_iclk", | |
4822 | .addr = omap44xx_mcpdm_dma_addrs, | |
4823 | .user = OCP_USER_SDMA, | |
4824 | }; | |
4825 | ||
4826 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
4827 | { | |
4828 | .pa_start = 0x48098000, | |
4829 | .pa_end = 0x480981ff, | |
4830 | .flags = ADDR_TYPE_RT | |
4831 | }, | |
4832 | { } | |
4833 | }; | |
4834 | ||
4835 | /* l4_per -> mcspi1 */ | |
4836 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
4837 | .master = &omap44xx_l4_per_hwmod, | |
4838 | .slave = &omap44xx_mcspi1_hwmod, | |
4839 | .clk = "l4_div_ck", | |
4840 | .addr = omap44xx_mcspi1_addrs, | |
4841 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4842 | }; | |
4843 | ||
4844 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
4845 | { | |
4846 | .pa_start = 0x4809a000, | |
4847 | .pa_end = 0x4809a1ff, | |
4848 | .flags = ADDR_TYPE_RT | |
4849 | }, | |
4850 | { } | |
4851 | }; | |
4852 | ||
4853 | /* l4_per -> mcspi2 */ | |
4854 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
4855 | .master = &omap44xx_l4_per_hwmod, | |
4856 | .slave = &omap44xx_mcspi2_hwmod, | |
4857 | .clk = "l4_div_ck", | |
4858 | .addr = omap44xx_mcspi2_addrs, | |
4859 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4860 | }; | |
4861 | ||
4862 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
4863 | { | |
4864 | .pa_start = 0x480b8000, | |
4865 | .pa_end = 0x480b81ff, | |
4866 | .flags = ADDR_TYPE_RT | |
4867 | }, | |
4868 | { } | |
4869 | }; | |
4870 | ||
4871 | /* l4_per -> mcspi3 */ | |
4872 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
4873 | .master = &omap44xx_l4_per_hwmod, | |
4874 | .slave = &omap44xx_mcspi3_hwmod, | |
4875 | .clk = "l4_div_ck", | |
4876 | .addr = omap44xx_mcspi3_addrs, | |
4877 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4878 | }; | |
4879 | ||
4880 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
4881 | { | |
4882 | .pa_start = 0x480ba000, | |
4883 | .pa_end = 0x480ba1ff, | |
4884 | .flags = ADDR_TYPE_RT | |
4885 | }, | |
4886 | { } | |
4887 | }; | |
4888 | ||
4889 | /* l4_per -> mcspi4 */ | |
4890 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
4891 | .master = &omap44xx_l4_per_hwmod, | |
4892 | .slave = &omap44xx_mcspi4_hwmod, | |
4893 | .clk = "l4_div_ck", | |
4894 | .addr = omap44xx_mcspi4_addrs, | |
4895 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4896 | }; | |
4897 | ||
4898 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
4899 | { | |
4900 | .pa_start = 0x4809c000, | |
4901 | .pa_end = 0x4809c3ff, | |
4902 | .flags = ADDR_TYPE_RT | |
4903 | }, | |
4904 | { } | |
4905 | }; | |
4906 | ||
4907 | /* l4_per -> mmc1 */ | |
4908 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
4909 | .master = &omap44xx_l4_per_hwmod, | |
4910 | .slave = &omap44xx_mmc1_hwmod, | |
4911 | .clk = "l4_div_ck", | |
4912 | .addr = omap44xx_mmc1_addrs, | |
4913 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4914 | }; | |
4915 | ||
4916 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
4917 | { | |
4918 | .pa_start = 0x480b4000, | |
4919 | .pa_end = 0x480b43ff, | |
4920 | .flags = ADDR_TYPE_RT | |
4921 | }, | |
4922 | { } | |
4923 | }; | |
4924 | ||
4925 | /* l4_per -> mmc2 */ | |
4926 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
4927 | .master = &omap44xx_l4_per_hwmod, | |
4928 | .slave = &omap44xx_mmc2_hwmod, | |
4929 | .clk = "l4_div_ck", | |
4930 | .addr = omap44xx_mmc2_addrs, | |
4931 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4932 | }; | |
4933 | ||
4934 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
4935 | { | |
4936 | .pa_start = 0x480ad000, | |
4937 | .pa_end = 0x480ad3ff, | |
4938 | .flags = ADDR_TYPE_RT | |
4939 | }, | |
4940 | { } | |
4941 | }; | |
4942 | ||
4943 | /* l4_per -> mmc3 */ | |
4944 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
4945 | .master = &omap44xx_l4_per_hwmod, | |
4946 | .slave = &omap44xx_mmc3_hwmod, | |
4947 | .clk = "l4_div_ck", | |
4948 | .addr = omap44xx_mmc3_addrs, | |
4949 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4950 | }; | |
4951 | ||
4952 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
4953 | { | |
4954 | .pa_start = 0x480d1000, | |
4955 | .pa_end = 0x480d13ff, | |
4956 | .flags = ADDR_TYPE_RT | |
4957 | }, | |
4958 | { } | |
4959 | }; | |
4960 | ||
4961 | /* l4_per -> mmc4 */ | |
4962 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
4963 | .master = &omap44xx_l4_per_hwmod, | |
4964 | .slave = &omap44xx_mmc4_hwmod, | |
4965 | .clk = "l4_div_ck", | |
4966 | .addr = omap44xx_mmc4_addrs, | |
4967 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4968 | }; | |
4969 | ||
4970 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
4971 | { | |
4972 | .pa_start = 0x480d5000, | |
4973 | .pa_end = 0x480d53ff, | |
4974 | .flags = ADDR_TYPE_RT | |
4975 | }, | |
4976 | { } | |
4977 | }; | |
4978 | ||
4979 | /* l4_per -> mmc5 */ | |
4980 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
4981 | .master = &omap44xx_l4_per_hwmod, | |
4982 | .slave = &omap44xx_mmc5_hwmod, | |
4983 | .clk = "l4_div_ck", | |
4984 | .addr = omap44xx_mmc5_addrs, | |
4985 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4986 | }; | |
4987 | ||
e17f18c0 PW |
4988 | /* l3_main_2 -> ocmc_ram */ |
4989 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
4990 | .master = &omap44xx_l3_main_2_hwmod, | |
4991 | .slave = &omap44xx_ocmc_ram_hwmod, | |
4992 | .clk = "l3_div_ck", | |
4993 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4994 | }; | |
4995 | ||
0c668875 BC |
4996 | /* l4_cfg -> ocp2scp_usb_phy */ |
4997 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
4998 | .master = &omap44xx_l4_cfg_hwmod, | |
4999 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
5000 | .clk = "l4_div_ck", | |
5001 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5002 | }; | |
5003 | ||
42b9e387 PW |
5004 | /* l3_main_2 -> sl2if */ |
5005 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { | |
5006 | .master = &omap44xx_l3_main_2_hwmod, | |
5007 | .slave = &omap44xx_sl2if_hwmod, | |
5008 | .clk = "l3_div_ck", | |
5009 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5010 | }; | |
5011 | ||
1e3b5e59 BC |
5012 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
5013 | { | |
5014 | .pa_start = 0x4012c000, | |
5015 | .pa_end = 0x4012c3ff, | |
5016 | .flags = ADDR_TYPE_RT | |
5017 | }, | |
5018 | { } | |
5019 | }; | |
5020 | ||
5021 | /* l4_abe -> slimbus1 */ | |
5022 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
5023 | .master = &omap44xx_l4_abe_hwmod, | |
5024 | .slave = &omap44xx_slimbus1_hwmod, | |
5025 | .clk = "ocp_abe_iclk", | |
5026 | .addr = omap44xx_slimbus1_addrs, | |
5027 | .user = OCP_USER_MPU, | |
5028 | }; | |
5029 | ||
5030 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
5031 | { | |
5032 | .pa_start = 0x4902c000, | |
5033 | .pa_end = 0x4902c3ff, | |
5034 | .flags = ADDR_TYPE_RT | |
5035 | }, | |
5036 | { } | |
5037 | }; | |
5038 | ||
5039 | /* l4_abe -> slimbus1 (dma) */ | |
5040 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
5041 | .master = &omap44xx_l4_abe_hwmod, | |
5042 | .slave = &omap44xx_slimbus1_hwmod, | |
5043 | .clk = "ocp_abe_iclk", | |
5044 | .addr = omap44xx_slimbus1_dma_addrs, | |
5045 | .user = OCP_USER_SDMA, | |
5046 | }; | |
5047 | ||
5048 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
5049 | { | |
5050 | .pa_start = 0x48076000, | |
5051 | .pa_end = 0x480763ff, | |
5052 | .flags = ADDR_TYPE_RT | |
5053 | }, | |
5054 | { } | |
5055 | }; | |
5056 | ||
5057 | /* l4_per -> slimbus2 */ | |
5058 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
5059 | .master = &omap44xx_l4_per_hwmod, | |
5060 | .slave = &omap44xx_slimbus2_hwmod, | |
5061 | .clk = "l4_div_ck", | |
5062 | .addr = omap44xx_slimbus2_addrs, | |
5063 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5064 | }; | |
5065 | ||
844a3b63 PW |
5066 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
5067 | { | |
5068 | .pa_start = 0x4a0dd000, | |
5069 | .pa_end = 0x4a0dd03f, | |
5070 | .flags = ADDR_TYPE_RT | |
5071 | }, | |
5072 | { } | |
5073 | }; | |
5074 | ||
5075 | /* l4_cfg -> smartreflex_core */ | |
5076 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
5077 | .master = &omap44xx_l4_cfg_hwmod, | |
5078 | .slave = &omap44xx_smartreflex_core_hwmod, | |
5079 | .clk = "l4_div_ck", | |
5080 | .addr = omap44xx_smartreflex_core_addrs, | |
5081 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5082 | }; | |
5083 | ||
5084 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
5085 | { | |
5086 | .pa_start = 0x4a0db000, | |
5087 | .pa_end = 0x4a0db03f, | |
5088 | .flags = ADDR_TYPE_RT | |
5089 | }, | |
5090 | { } | |
5091 | }; | |
5092 | ||
5093 | /* l4_cfg -> smartreflex_iva */ | |
5094 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
5095 | .master = &omap44xx_l4_cfg_hwmod, | |
5096 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
5097 | .clk = "l4_div_ck", | |
5098 | .addr = omap44xx_smartreflex_iva_addrs, | |
5099 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5100 | }; | |
5101 | ||
5102 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
5103 | { | |
5104 | .pa_start = 0x4a0d9000, | |
5105 | .pa_end = 0x4a0d903f, | |
5106 | .flags = ADDR_TYPE_RT | |
5107 | }, | |
5108 | { } | |
5109 | }; | |
5110 | ||
5111 | /* l4_cfg -> smartreflex_mpu */ | |
5112 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
5113 | .master = &omap44xx_l4_cfg_hwmod, | |
5114 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
5115 | .clk = "l4_div_ck", | |
5116 | .addr = omap44xx_smartreflex_mpu_addrs, | |
5117 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5118 | }; | |
5119 | ||
5120 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
5121 | { | |
5122 | .pa_start = 0x4a0f6000, | |
5123 | .pa_end = 0x4a0f6fff, | |
5124 | .flags = ADDR_TYPE_RT | |
5125 | }, | |
5126 | { } | |
5127 | }; | |
5128 | ||
5129 | /* l4_cfg -> spinlock */ | |
5130 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
5131 | .master = &omap44xx_l4_cfg_hwmod, | |
5132 | .slave = &omap44xx_spinlock_hwmod, | |
5133 | .clk = "l4_div_ck", | |
5134 | .addr = omap44xx_spinlock_addrs, | |
5135 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5136 | }; | |
5137 | ||
5138 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
5139 | { | |
5140 | .pa_start = 0x4a318000, | |
5141 | .pa_end = 0x4a31807f, | |
5142 | .flags = ADDR_TYPE_RT | |
5143 | }, | |
5144 | { } | |
5145 | }; | |
5146 | ||
5147 | /* l4_wkup -> timer1 */ | |
5148 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
5149 | .master = &omap44xx_l4_wkup_hwmod, | |
5150 | .slave = &omap44xx_timer1_hwmod, | |
5151 | .clk = "l4_wkup_clk_mux_ck", | |
5152 | .addr = omap44xx_timer1_addrs, | |
5153 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5154 | }; | |
5155 | ||
5156 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
5157 | { | |
5158 | .pa_start = 0x48032000, | |
5159 | .pa_end = 0x4803207f, | |
5160 | .flags = ADDR_TYPE_RT | |
5161 | }, | |
5162 | { } | |
5163 | }; | |
5164 | ||
5165 | /* l4_per -> timer2 */ | |
5166 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
5167 | .master = &omap44xx_l4_per_hwmod, | |
5168 | .slave = &omap44xx_timer2_hwmod, | |
5169 | .clk = "l4_div_ck", | |
5170 | .addr = omap44xx_timer2_addrs, | |
5171 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5172 | }; | |
5173 | ||
5174 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
5175 | { | |
5176 | .pa_start = 0x48034000, | |
5177 | .pa_end = 0x4803407f, | |
5178 | .flags = ADDR_TYPE_RT | |
5179 | }, | |
5180 | { } | |
5181 | }; | |
5182 | ||
5183 | /* l4_per -> timer3 */ | |
5184 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
5185 | .master = &omap44xx_l4_per_hwmod, | |
5186 | .slave = &omap44xx_timer3_hwmod, | |
5187 | .clk = "l4_div_ck", | |
5188 | .addr = omap44xx_timer3_addrs, | |
5189 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5190 | }; | |
5191 | ||
5192 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
5193 | { | |
5194 | .pa_start = 0x48036000, | |
5195 | .pa_end = 0x4803607f, | |
5196 | .flags = ADDR_TYPE_RT | |
5197 | }, | |
5198 | { } | |
5199 | }; | |
5200 | ||
5201 | /* l4_per -> timer4 */ | |
5202 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
5203 | .master = &omap44xx_l4_per_hwmod, | |
5204 | .slave = &omap44xx_timer4_hwmod, | |
5205 | .clk = "l4_div_ck", | |
5206 | .addr = omap44xx_timer4_addrs, | |
5207 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5208 | }; | |
5209 | ||
5210 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
5211 | { | |
5212 | .pa_start = 0x40138000, | |
5213 | .pa_end = 0x4013807f, | |
5214 | .flags = ADDR_TYPE_RT | |
5215 | }, | |
5216 | { } | |
5217 | }; | |
5218 | ||
5219 | /* l4_abe -> timer5 */ | |
5220 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
5221 | .master = &omap44xx_l4_abe_hwmod, | |
5222 | .slave = &omap44xx_timer5_hwmod, | |
5223 | .clk = "ocp_abe_iclk", | |
5224 | .addr = omap44xx_timer5_addrs, | |
5225 | .user = OCP_USER_MPU, | |
5226 | }; | |
5227 | ||
5228 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
5229 | { | |
5230 | .pa_start = 0x49038000, | |
5231 | .pa_end = 0x4903807f, | |
5232 | .flags = ADDR_TYPE_RT | |
5233 | }, | |
5234 | { } | |
5235 | }; | |
5236 | ||
5237 | /* l4_abe -> timer5 (dma) */ | |
5238 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
5239 | .master = &omap44xx_l4_abe_hwmod, | |
5240 | .slave = &omap44xx_timer5_hwmod, | |
5241 | .clk = "ocp_abe_iclk", | |
5242 | .addr = omap44xx_timer5_dma_addrs, | |
5243 | .user = OCP_USER_SDMA, | |
5244 | }; | |
5245 | ||
5246 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
5247 | { | |
5248 | .pa_start = 0x4013a000, | |
5249 | .pa_end = 0x4013a07f, | |
5250 | .flags = ADDR_TYPE_RT | |
5251 | }, | |
5252 | { } | |
5253 | }; | |
5254 | ||
5255 | /* l4_abe -> timer6 */ | |
5256 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
5257 | .master = &omap44xx_l4_abe_hwmod, | |
5258 | .slave = &omap44xx_timer6_hwmod, | |
5259 | .clk = "ocp_abe_iclk", | |
5260 | .addr = omap44xx_timer6_addrs, | |
5261 | .user = OCP_USER_MPU, | |
5262 | }; | |
5263 | ||
5264 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
5265 | { | |
5266 | .pa_start = 0x4903a000, | |
5267 | .pa_end = 0x4903a07f, | |
5268 | .flags = ADDR_TYPE_RT | |
5269 | }, | |
5270 | { } | |
5271 | }; | |
5272 | ||
5273 | /* l4_abe -> timer6 (dma) */ | |
5274 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
5275 | .master = &omap44xx_l4_abe_hwmod, | |
5276 | .slave = &omap44xx_timer6_hwmod, | |
5277 | .clk = "ocp_abe_iclk", | |
5278 | .addr = omap44xx_timer6_dma_addrs, | |
5279 | .user = OCP_USER_SDMA, | |
5280 | }; | |
5281 | ||
5282 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
5283 | { | |
5284 | .pa_start = 0x4013c000, | |
5285 | .pa_end = 0x4013c07f, | |
5286 | .flags = ADDR_TYPE_RT | |
5287 | }, | |
5288 | { } | |
5289 | }; | |
5290 | ||
5291 | /* l4_abe -> timer7 */ | |
5292 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
5293 | .master = &omap44xx_l4_abe_hwmod, | |
5294 | .slave = &omap44xx_timer7_hwmod, | |
5295 | .clk = "ocp_abe_iclk", | |
5296 | .addr = omap44xx_timer7_addrs, | |
5297 | .user = OCP_USER_MPU, | |
5298 | }; | |
5299 | ||
5300 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
5301 | { | |
5302 | .pa_start = 0x4903c000, | |
5303 | .pa_end = 0x4903c07f, | |
5304 | .flags = ADDR_TYPE_RT | |
5305 | }, | |
5306 | { } | |
5307 | }; | |
5308 | ||
5309 | /* l4_abe -> timer7 (dma) */ | |
5310 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
5311 | .master = &omap44xx_l4_abe_hwmod, | |
5312 | .slave = &omap44xx_timer7_hwmod, | |
5313 | .clk = "ocp_abe_iclk", | |
5314 | .addr = omap44xx_timer7_dma_addrs, | |
5315 | .user = OCP_USER_SDMA, | |
5316 | }; | |
5317 | ||
5318 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
5319 | { | |
5320 | .pa_start = 0x4013e000, | |
5321 | .pa_end = 0x4013e07f, | |
5322 | .flags = ADDR_TYPE_RT | |
5323 | }, | |
5324 | { } | |
5325 | }; | |
5326 | ||
5327 | /* l4_abe -> timer8 */ | |
5328 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
5329 | .master = &omap44xx_l4_abe_hwmod, | |
5330 | .slave = &omap44xx_timer8_hwmod, | |
5331 | .clk = "ocp_abe_iclk", | |
5332 | .addr = omap44xx_timer8_addrs, | |
5333 | .user = OCP_USER_MPU, | |
5334 | }; | |
5335 | ||
5336 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
5337 | { | |
5338 | .pa_start = 0x4903e000, | |
5339 | .pa_end = 0x4903e07f, | |
5340 | .flags = ADDR_TYPE_RT | |
5341 | }, | |
5342 | { } | |
5343 | }; | |
5344 | ||
5345 | /* l4_abe -> timer8 (dma) */ | |
5346 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
5347 | .master = &omap44xx_l4_abe_hwmod, | |
5348 | .slave = &omap44xx_timer8_hwmod, | |
5349 | .clk = "ocp_abe_iclk", | |
5350 | .addr = omap44xx_timer8_dma_addrs, | |
5351 | .user = OCP_USER_SDMA, | |
5352 | }; | |
5353 | ||
5354 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
5355 | { | |
5356 | .pa_start = 0x4803e000, | |
5357 | .pa_end = 0x4803e07f, | |
5358 | .flags = ADDR_TYPE_RT | |
5359 | }, | |
5360 | { } | |
5361 | }; | |
5362 | ||
5363 | /* l4_per -> timer9 */ | |
5364 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
5365 | .master = &omap44xx_l4_per_hwmod, | |
5366 | .slave = &omap44xx_timer9_hwmod, | |
5367 | .clk = "l4_div_ck", | |
5368 | .addr = omap44xx_timer9_addrs, | |
5369 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5370 | }; | |
5371 | ||
5372 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
5373 | { | |
5374 | .pa_start = 0x48086000, | |
5375 | .pa_end = 0x4808607f, | |
5376 | .flags = ADDR_TYPE_RT | |
5377 | }, | |
5378 | { } | |
5379 | }; | |
5380 | ||
5381 | /* l4_per -> timer10 */ | |
5382 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
5383 | .master = &omap44xx_l4_per_hwmod, | |
5384 | .slave = &omap44xx_timer10_hwmod, | |
5385 | .clk = "l4_div_ck", | |
5386 | .addr = omap44xx_timer10_addrs, | |
5387 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5388 | }; | |
5389 | ||
5390 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
5391 | { | |
5392 | .pa_start = 0x48088000, | |
5393 | .pa_end = 0x4808807f, | |
5394 | .flags = ADDR_TYPE_RT | |
5395 | }, | |
5396 | { } | |
5397 | }; | |
5398 | ||
5399 | /* l4_per -> timer11 */ | |
5400 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
5401 | .master = &omap44xx_l4_per_hwmod, | |
5402 | .slave = &omap44xx_timer11_hwmod, | |
5403 | .clk = "l4_div_ck", | |
5404 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
5405 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5406 | }; | |
5407 | ||
844a3b63 PW |
5408 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
5409 | { | |
5410 | .pa_start = 0x4806a000, | |
5411 | .pa_end = 0x4806a0ff, | |
5412 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5413 | }, |
844a3b63 PW |
5414 | { } |
5415 | }; | |
af88fa9a | 5416 | |
844a3b63 PW |
5417 | /* l4_per -> uart1 */ |
5418 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
5419 | .master = &omap44xx_l4_per_hwmod, | |
5420 | .slave = &omap44xx_uart1_hwmod, | |
5421 | .clk = "l4_div_ck", | |
5422 | .addr = omap44xx_uart1_addrs, | |
5423 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5424 | }; | |
af88fa9a | 5425 | |
844a3b63 PW |
5426 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
5427 | { | |
5428 | .pa_start = 0x4806c000, | |
5429 | .pa_end = 0x4806c0ff, | |
5430 | .flags = ADDR_TYPE_RT | |
5431 | }, | |
5432 | { } | |
5433 | }; | |
af88fa9a | 5434 | |
844a3b63 PW |
5435 | /* l4_per -> uart2 */ |
5436 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
5437 | .master = &omap44xx_l4_per_hwmod, | |
5438 | .slave = &omap44xx_uart2_hwmod, | |
5439 | .clk = "l4_div_ck", | |
5440 | .addr = omap44xx_uart2_addrs, | |
5441 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5442 | }; | |
af88fa9a | 5443 | |
844a3b63 PW |
5444 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
5445 | { | |
5446 | .pa_start = 0x48020000, | |
5447 | .pa_end = 0x480200ff, | |
5448 | .flags = ADDR_TYPE_RT | |
5449 | }, | |
5450 | { } | |
af88fa9a BC |
5451 | }; |
5452 | ||
844a3b63 PW |
5453 | /* l4_per -> uart3 */ |
5454 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
5455 | .master = &omap44xx_l4_per_hwmod, | |
5456 | .slave = &omap44xx_uart3_hwmod, | |
5457 | .clk = "l4_div_ck", | |
5458 | .addr = omap44xx_uart3_addrs, | |
5459 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5460 | }; |
5461 | ||
844a3b63 PW |
5462 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
5463 | { | |
5464 | .pa_start = 0x4806e000, | |
5465 | .pa_end = 0x4806e0ff, | |
5466 | .flags = ADDR_TYPE_RT | |
5467 | }, | |
5468 | { } | |
af88fa9a BC |
5469 | }; |
5470 | ||
844a3b63 PW |
5471 | /* l4_per -> uart4 */ |
5472 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
5473 | .master = &omap44xx_l4_per_hwmod, | |
5474 | .slave = &omap44xx_uart4_hwmod, | |
5475 | .clk = "l4_div_ck", | |
5476 | .addr = omap44xx_uart4_addrs, | |
5477 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5478 | }; | |
5479 | ||
0c668875 BC |
5480 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { |
5481 | { | |
5482 | .pa_start = 0x4a0a9000, | |
5483 | .pa_end = 0x4a0a93ff, | |
5484 | .flags = ADDR_TYPE_RT | |
5485 | }, | |
5486 | { } | |
5487 | }; | |
5488 | ||
5489 | /* l4_cfg -> usb_host_fs */ | |
5490 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = { | |
5491 | .master = &omap44xx_l4_cfg_hwmod, | |
5492 | .slave = &omap44xx_usb_host_fs_hwmod, | |
5493 | .clk = "l4_div_ck", | |
5494 | .addr = omap44xx_usb_host_fs_addrs, | |
5495 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5496 | }; | |
5497 | ||
844a3b63 PW |
5498 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
5499 | { | |
5500 | .name = "uhh", | |
5501 | .pa_start = 0x4a064000, | |
5502 | .pa_end = 0x4a0647ff, | |
5503 | .flags = ADDR_TYPE_RT | |
5504 | }, | |
5505 | { | |
5506 | .name = "ohci", | |
5507 | .pa_start = 0x4a064800, | |
5508 | .pa_end = 0x4a064bff, | |
5509 | }, | |
5510 | { | |
5511 | .name = "ehci", | |
5512 | .pa_start = 0x4a064c00, | |
5513 | .pa_end = 0x4a064fff, | |
5514 | }, | |
5515 | {} | |
5516 | }; | |
5517 | ||
5518 | /* l4_cfg -> usb_host_hs */ | |
5519 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
5520 | .master = &omap44xx_l4_cfg_hwmod, | |
5521 | .slave = &omap44xx_usb_host_hs_hwmod, | |
5522 | .clk = "l4_div_ck", | |
5523 | .addr = omap44xx_usb_host_hs_addrs, | |
5524 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5525 | }; | |
5526 | ||
5527 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
5528 | { | |
5529 | .pa_start = 0x4a0ab000, | |
5530 | .pa_end = 0x4a0ab003, | |
5531 | .flags = ADDR_TYPE_RT | |
5532 | }, | |
5533 | { } | |
5534 | }; | |
5535 | ||
5536 | /* l4_cfg -> usb_otg_hs */ | |
5537 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
5538 | .master = &omap44xx_l4_cfg_hwmod, | |
5539 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
5540 | .clk = "l4_div_ck", | |
5541 | .addr = omap44xx_usb_otg_hs_addrs, | |
5542 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5543 | }; |
5544 | ||
5545 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
5546 | { | |
5547 | .name = "tll", | |
5548 | .pa_start = 0x4a062000, | |
5549 | .pa_end = 0x4a063fff, | |
5550 | .flags = ADDR_TYPE_RT | |
5551 | }, | |
5552 | {} | |
5553 | }; | |
5554 | ||
844a3b63 | 5555 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
5556 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
5557 | .master = &omap44xx_l4_cfg_hwmod, | |
5558 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
5559 | .clk = "l4_div_ck", | |
5560 | .addr = omap44xx_usb_tll_hs_addrs, | |
5561 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5562 | }; | |
5563 | ||
844a3b63 PW |
5564 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
5565 | { | |
5566 | .pa_start = 0x4a314000, | |
5567 | .pa_end = 0x4a31407f, | |
5568 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5569 | }, |
844a3b63 PW |
5570 | { } |
5571 | }; | |
5572 | ||
5573 | /* l4_wkup -> wd_timer2 */ | |
5574 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
5575 | .master = &omap44xx_l4_wkup_hwmod, | |
5576 | .slave = &omap44xx_wd_timer2_hwmod, | |
5577 | .clk = "l4_wkup_clk_mux_ck", | |
5578 | .addr = omap44xx_wd_timer2_addrs, | |
5579 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5580 | }; | |
5581 | ||
5582 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
5583 | { | |
5584 | .pa_start = 0x40130000, | |
5585 | .pa_end = 0x4013007f, | |
5586 | .flags = ADDR_TYPE_RT | |
5587 | }, | |
5588 | { } | |
5589 | }; | |
5590 | ||
5591 | /* l4_abe -> wd_timer3 */ | |
5592 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
5593 | .master = &omap44xx_l4_abe_hwmod, | |
5594 | .slave = &omap44xx_wd_timer3_hwmod, | |
5595 | .clk = "ocp_abe_iclk", | |
5596 | .addr = omap44xx_wd_timer3_addrs, | |
5597 | .user = OCP_USER_MPU, | |
5598 | }; | |
5599 | ||
5600 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
5601 | { | |
5602 | .pa_start = 0x49030000, | |
5603 | .pa_end = 0x4903007f, | |
5604 | .flags = ADDR_TYPE_RT | |
5605 | }, | |
5606 | { } | |
5607 | }; | |
5608 | ||
5609 | /* l4_abe -> wd_timer3 (dma) */ | |
5610 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
5611 | .master = &omap44xx_l4_abe_hwmod, | |
5612 | .slave = &omap44xx_wd_timer3_hwmod, | |
5613 | .clk = "ocp_abe_iclk", | |
5614 | .addr = omap44xx_wd_timer3_dma_addrs, | |
5615 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
5616 | }; |
5617 | ||
0a78c5c5 | 5618 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
42b9e387 PW |
5619 | &omap44xx_c2c__c2c_target_fw, |
5620 | &omap44xx_l4_cfg__c2c_target_fw, | |
0a78c5c5 PW |
5621 | &omap44xx_l3_main_1__dmm, |
5622 | &omap44xx_mpu__dmm, | |
42b9e387 | 5623 | &omap44xx_c2c__emif_fw, |
0a78c5c5 PW |
5624 | &omap44xx_dmm__emif_fw, |
5625 | &omap44xx_l4_cfg__emif_fw, | |
5626 | &omap44xx_iva__l3_instr, | |
5627 | &omap44xx_l3_main_3__l3_instr, | |
5628 | &omap44xx_dsp__l3_main_1, | |
5629 | &omap44xx_dss__l3_main_1, | |
5630 | &omap44xx_l3_main_2__l3_main_1, | |
5631 | &omap44xx_l4_cfg__l3_main_1, | |
5632 | &omap44xx_mmc1__l3_main_1, | |
5633 | &omap44xx_mmc2__l3_main_1, | |
5634 | &omap44xx_mpu__l3_main_1, | |
42b9e387 | 5635 | &omap44xx_c2c_target_fw__l3_main_2, |
0a78c5c5 | 5636 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 5637 | &omap44xx_fdif__l3_main_2, |
9def390e | 5638 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
5639 | &omap44xx_hsi__l3_main_2, |
5640 | &omap44xx_ipu__l3_main_2, | |
5641 | &omap44xx_iss__l3_main_2, | |
5642 | &omap44xx_iva__l3_main_2, | |
5643 | &omap44xx_l3_main_1__l3_main_2, | |
5644 | &omap44xx_l4_cfg__l3_main_2, | |
0c668875 | 5645 | &omap44xx_usb_host_fs__l3_main_2, |
0a78c5c5 PW |
5646 | &omap44xx_usb_host_hs__l3_main_2, |
5647 | &omap44xx_usb_otg_hs__l3_main_2, | |
5648 | &omap44xx_l3_main_1__l3_main_3, | |
5649 | &omap44xx_l3_main_2__l3_main_3, | |
5650 | &omap44xx_l4_cfg__l3_main_3, | |
5651 | &omap44xx_aess__l4_abe, | |
5652 | &omap44xx_dsp__l4_abe, | |
5653 | &omap44xx_l3_main_1__l4_abe, | |
5654 | &omap44xx_mpu__l4_abe, | |
5655 | &omap44xx_l3_main_1__l4_cfg, | |
5656 | &omap44xx_l3_main_2__l4_per, | |
5657 | &omap44xx_l4_cfg__l4_wkup, | |
5658 | &omap44xx_mpu__mpu_private, | |
5659 | &omap44xx_l4_abe__aess, | |
5660 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 5661 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 PW |
5662 | &omap44xx_l4_wkup__counter_32k, |
5663 | &omap44xx_l4_cfg__dma_system, | |
5664 | &omap44xx_l4_abe__dmic, | |
5665 | &omap44xx_l4_abe__dmic_dma, | |
5666 | &omap44xx_dsp__iva, | |
42b9e387 | 5667 | &omap44xx_dsp__sl2if, |
0a78c5c5 PW |
5668 | &omap44xx_l4_cfg__dsp, |
5669 | &omap44xx_l3_main_2__dss, | |
5670 | &omap44xx_l4_per__dss, | |
5671 | &omap44xx_l3_main_2__dss_dispc, | |
5672 | &omap44xx_l4_per__dss_dispc, | |
5673 | &omap44xx_l3_main_2__dss_dsi1, | |
5674 | &omap44xx_l4_per__dss_dsi1, | |
5675 | &omap44xx_l3_main_2__dss_dsi2, | |
5676 | &omap44xx_l4_per__dss_dsi2, | |
5677 | &omap44xx_l3_main_2__dss_hdmi, | |
5678 | &omap44xx_l4_per__dss_hdmi, | |
5679 | &omap44xx_l3_main_2__dss_rfbi, | |
5680 | &omap44xx_l4_per__dss_rfbi, | |
5681 | &omap44xx_l3_main_2__dss_venc, | |
5682 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 5683 | &omap44xx_l4_per__elm, |
bf30f950 PW |
5684 | &omap44xx_emif_fw__emif1, |
5685 | &omap44xx_emif_fw__emif2, | |
b050f688 | 5686 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
5687 | &omap44xx_l4_wkup__gpio1, |
5688 | &omap44xx_l4_per__gpio2, | |
5689 | &omap44xx_l4_per__gpio3, | |
5690 | &omap44xx_l4_per__gpio4, | |
5691 | &omap44xx_l4_per__gpio5, | |
5692 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 5693 | &omap44xx_l3_main_2__gpmc, |
9def390e | 5694 | &omap44xx_l3_main_2__gpu, |
a091c08e | 5695 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
5696 | &omap44xx_l4_cfg__hsi, |
5697 | &omap44xx_l4_per__i2c1, | |
5698 | &omap44xx_l4_per__i2c2, | |
5699 | &omap44xx_l4_per__i2c3, | |
5700 | &omap44xx_l4_per__i2c4, | |
5701 | &omap44xx_l3_main_2__ipu, | |
5702 | &omap44xx_l3_main_2__iss, | |
42b9e387 | 5703 | &omap44xx_iva__sl2if, |
0a78c5c5 PW |
5704 | &omap44xx_l3_main_2__iva, |
5705 | &omap44xx_l4_wkup__kbd, | |
5706 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
5707 | &omap44xx_l4_abe__mcasp, |
5708 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 PW |
5709 | &omap44xx_l4_abe__mcbsp1, |
5710 | &omap44xx_l4_abe__mcbsp1_dma, | |
5711 | &omap44xx_l4_abe__mcbsp2, | |
5712 | &omap44xx_l4_abe__mcbsp2_dma, | |
5713 | &omap44xx_l4_abe__mcbsp3, | |
5714 | &omap44xx_l4_abe__mcbsp3_dma, | |
5715 | &omap44xx_l4_per__mcbsp4, | |
5716 | &omap44xx_l4_abe__mcpdm, | |
5717 | &omap44xx_l4_abe__mcpdm_dma, | |
5718 | &omap44xx_l4_per__mcspi1, | |
5719 | &omap44xx_l4_per__mcspi2, | |
5720 | &omap44xx_l4_per__mcspi3, | |
5721 | &omap44xx_l4_per__mcspi4, | |
5722 | &omap44xx_l4_per__mmc1, | |
5723 | &omap44xx_l4_per__mmc2, | |
5724 | &omap44xx_l4_per__mmc3, | |
5725 | &omap44xx_l4_per__mmc4, | |
5726 | &omap44xx_l4_per__mmc5, | |
e17f18c0 | 5727 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 5728 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
42b9e387 | 5729 | &omap44xx_l3_main_2__sl2if, |
1e3b5e59 BC |
5730 | &omap44xx_l4_abe__slimbus1, |
5731 | &omap44xx_l4_abe__slimbus1_dma, | |
5732 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
5733 | &omap44xx_l4_cfg__smartreflex_core, |
5734 | &omap44xx_l4_cfg__smartreflex_iva, | |
5735 | &omap44xx_l4_cfg__smartreflex_mpu, | |
5736 | &omap44xx_l4_cfg__spinlock, | |
5737 | &omap44xx_l4_wkup__timer1, | |
5738 | &omap44xx_l4_per__timer2, | |
5739 | &omap44xx_l4_per__timer3, | |
5740 | &omap44xx_l4_per__timer4, | |
5741 | &omap44xx_l4_abe__timer5, | |
5742 | &omap44xx_l4_abe__timer5_dma, | |
5743 | &omap44xx_l4_abe__timer6, | |
5744 | &omap44xx_l4_abe__timer6_dma, | |
5745 | &omap44xx_l4_abe__timer7, | |
5746 | &omap44xx_l4_abe__timer7_dma, | |
5747 | &omap44xx_l4_abe__timer8, | |
5748 | &omap44xx_l4_abe__timer8_dma, | |
5749 | &omap44xx_l4_per__timer9, | |
5750 | &omap44xx_l4_per__timer10, | |
5751 | &omap44xx_l4_per__timer11, | |
5752 | &omap44xx_l4_per__uart1, | |
5753 | &omap44xx_l4_per__uart2, | |
5754 | &omap44xx_l4_per__uart3, | |
5755 | &omap44xx_l4_per__uart4, | |
0c668875 | 5756 | &omap44xx_l4_cfg__usb_host_fs, |
0a78c5c5 PW |
5757 | &omap44xx_l4_cfg__usb_host_hs, |
5758 | &omap44xx_l4_cfg__usb_otg_hs, | |
5759 | &omap44xx_l4_cfg__usb_tll_hs, | |
5760 | &omap44xx_l4_wkup__wd_timer2, | |
5761 | &omap44xx_l4_abe__wd_timer3, | |
5762 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
5763 | NULL, |
5764 | }; | |
5765 | ||
5766 | int __init omap44xx_hwmod_init(void) | |
5767 | { | |
0a78c5c5 | 5768 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
5769 | } |
5770 |