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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
6d3c55fd | 25 | #include <plat/i2c.h> |
9780a9cf | 26 | #include <plat/gpio.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
c345c8b0 | 31 | #include <plat/dmtimer.h> |
13662dc5 | 32 | #include <plat/common.h> |
55d2cb08 BC |
33 | |
34 | #include "omap_hwmod_common_data.h" | |
35 | ||
cea6b942 | 36 | #include "smartreflex.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
ff2516fb | 41 | #include "wd_timer.h" |
55d2cb08 BC |
42 | |
43 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
44 | #define OMAP44XX_IRQ_GIC_START 32 | |
45 | ||
46 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 47 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
48 | |
49 | /* | |
844a3b63 | 50 | * IP blocks |
55d2cb08 BC |
51 | */ |
52 | ||
53 | /* | |
54 | * 'dmm' class | |
55 | * instance(s): dmm | |
56 | */ | |
57 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 58 | .name = "dmm", |
55d2cb08 BC |
59 | }; |
60 | ||
7e69ed97 BC |
61 | /* dmm */ |
62 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
63 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
64 | { .irq = -1 } | |
65 | }; | |
66 | ||
55d2cb08 BC |
67 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
68 | .name = "dmm", | |
69 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 70 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 71 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
72 | .prcm = { |
73 | .omap4 = { | |
74 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 75 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
76 | }, |
77 | }, | |
55d2cb08 BC |
78 | }; |
79 | ||
80 | /* | |
81 | * 'emif_fw' class | |
82 | * instance(s): emif_fw | |
83 | */ | |
84 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 85 | .name = "emif_fw", |
55d2cb08 BC |
86 | }; |
87 | ||
7e69ed97 | 88 | /* emif_fw */ |
55d2cb08 BC |
89 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
90 | .name = "emif_fw", | |
91 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 92 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
93 | .prcm = { |
94 | .omap4 = { | |
95 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 96 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
97 | }, |
98 | }, | |
55d2cb08 BC |
99 | }; |
100 | ||
101 | /* | |
102 | * 'l3' class | |
103 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
104 | */ | |
105 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 106 | .name = "l3", |
55d2cb08 BC |
107 | }; |
108 | ||
7e69ed97 | 109 | /* l3_instr */ |
55d2cb08 BC |
110 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
111 | .name = "l3_instr", | |
112 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 113 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
114 | .prcm = { |
115 | .omap4 = { | |
116 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 117 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 118 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
119 | }, |
120 | }, | |
55d2cb08 BC |
121 | }; |
122 | ||
7e69ed97 | 123 | /* l3_main_1 */ |
9b4021be BC |
124 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
125 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
126 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
127 | { .irq = -1 } | |
128 | }; | |
129 | ||
55d2cb08 BC |
130 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
131 | .name = "l3_main_1", | |
132 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 133 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 134 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
135 | .prcm = { |
136 | .omap4 = { | |
137 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 138 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
139 | }, |
140 | }, | |
55d2cb08 BC |
141 | }; |
142 | ||
7e69ed97 | 143 | /* l3_main_2 */ |
55d2cb08 BC |
144 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
145 | .name = "l3_main_2", | |
146 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 147 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
148 | .prcm = { |
149 | .omap4 = { | |
150 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 151 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
152 | }, |
153 | }, | |
55d2cb08 BC |
154 | }; |
155 | ||
7e69ed97 | 156 | /* l3_main_3 */ |
55d2cb08 BC |
157 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
158 | .name = "l3_main_3", | |
159 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 160 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
161 | .prcm = { |
162 | .omap4 = { | |
163 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 164 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 165 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
166 | }, |
167 | }, | |
55d2cb08 BC |
168 | }; |
169 | ||
170 | /* | |
171 | * 'l4' class | |
172 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
173 | */ | |
174 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 175 | .name = "l4", |
55d2cb08 BC |
176 | }; |
177 | ||
7e69ed97 | 178 | /* l4_abe */ |
55d2cb08 BC |
179 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
180 | .name = "l4_abe", | |
181 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 182 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
183 | .prcm = { |
184 | .omap4 = { | |
185 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
186 | }, | |
187 | }, | |
55d2cb08 BC |
188 | }; |
189 | ||
7e69ed97 | 190 | /* l4_cfg */ |
55d2cb08 BC |
191 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
192 | .name = "l4_cfg", | |
193 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 194 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
195 | .prcm = { |
196 | .omap4 = { | |
197 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 198 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
199 | }, |
200 | }, | |
55d2cb08 BC |
201 | }; |
202 | ||
7e69ed97 | 203 | /* l4_per */ |
55d2cb08 BC |
204 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
205 | .name = "l4_per", | |
206 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 207 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
208 | .prcm = { |
209 | .omap4 = { | |
210 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 211 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
212 | }, |
213 | }, | |
55d2cb08 BC |
214 | }; |
215 | ||
7e69ed97 | 216 | /* l4_wkup */ |
55d2cb08 BC |
217 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
218 | .name = "l4_wkup", | |
219 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 220 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
221 | .prcm = { |
222 | .omap4 = { | |
223 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 224 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
225 | }, |
226 | }, | |
55d2cb08 BC |
227 | }; |
228 | ||
f776471f | 229 | /* |
3b54baad BC |
230 | * 'mpu_bus' class |
231 | * instance(s): mpu_private | |
f776471f | 232 | */ |
3b54baad | 233 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 234 | .name = "mpu_bus", |
3b54baad | 235 | }; |
f776471f | 236 | |
7e69ed97 | 237 | /* mpu_private */ |
3b54baad BC |
238 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
239 | .name = "mpu_private", | |
240 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 241 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
242 | }; |
243 | ||
244 | /* | |
245 | * Modules omap_hwmod structures | |
246 | * | |
247 | * The following IPs are excluded for the moment because: | |
248 | * - They do not need an explicit SW control using omap_hwmod API. | |
249 | * - They still need to be validated with the driver | |
250 | * properly adapted to omap_hwmod / omap_device | |
251 | * | |
3b54baad BC |
252 | * c2c |
253 | * c2c_target_fw | |
254 | * cm_core | |
255 | * cm_core_aon | |
3b54baad BC |
256 | * ctrl_module_core |
257 | * ctrl_module_pad_core | |
258 | * ctrl_module_pad_wkup | |
259 | * ctrl_module_wkup | |
260 | * debugss | |
3b54baad BC |
261 | * efuse_ctrl_cust |
262 | * efuse_ctrl_std | |
263 | * elm | |
264 | * emif1 | |
265 | * emif2 | |
3b54baad | 266 | * gpu |
00fe610b BC |
267 | * mcasp |
268 | * mpu_c0 | |
269 | * mpu_c1 | |
3b54baad BC |
270 | * ocmc_ram |
271 | * ocp2scp_usb_phy | |
272 | * ocp_wp_noc | |
3b54baad BC |
273 | * prcm_mpu |
274 | * prm | |
275 | * scrm | |
276 | * sl2if | |
277 | * slimbus1 | |
278 | * slimbus2 | |
3b54baad BC |
279 | * usb_host_fs |
280 | * usb_host_hs | |
3b54baad BC |
281 | * usb_phy_cm |
282 | * usb_tll_hs | |
283 | * usim | |
284 | */ | |
285 | ||
407a6888 BC |
286 | /* |
287 | * 'aess' class | |
288 | * audio engine sub system | |
289 | */ | |
290 | ||
291 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
292 | .rev_offs = 0x0000, | |
293 | .sysc_offs = 0x0010, | |
294 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
295 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
296 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
297 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
298 | .sysc_fields = &omap_hwmod_sysc_type2, |
299 | }; | |
300 | ||
301 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
302 | .name = "aess", | |
303 | .sysc = &omap44xx_aess_sysc, | |
304 | }; | |
305 | ||
306 | /* aess */ | |
307 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
308 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 309 | { .irq = -1 } |
407a6888 BC |
310 | }; |
311 | ||
312 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
313 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
314 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
315 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
316 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
317 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
318 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
319 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
320 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 321 | { .dma_req = -1 } |
407a6888 BC |
322 | }; |
323 | ||
407a6888 BC |
324 | static struct omap_hwmod omap44xx_aess_hwmod = { |
325 | .name = "aess", | |
326 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 327 | .clkdm_name = "abe_clkdm", |
407a6888 | 328 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 329 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 330 | .main_clk = "aess_fck", |
00fe610b | 331 | .prcm = { |
407a6888 | 332 | .omap4 = { |
d0f0631d | 333 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 334 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 335 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
336 | }, |
337 | }, | |
407a6888 BC |
338 | }; |
339 | ||
407a6888 BC |
340 | /* |
341 | * 'counter' class | |
342 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
343 | */ | |
344 | ||
345 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
346 | .rev_offs = 0x0000, | |
347 | .sysc_offs = 0x0004, | |
348 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
349 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
350 | SIDLE_SMART_WKUP), | |
351 | .sysc_fields = &omap_hwmod_sysc_type1, | |
352 | }; | |
353 | ||
354 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
355 | .name = "counter", | |
356 | .sysc = &omap44xx_counter_sysc, | |
357 | }; | |
358 | ||
359 | /* counter_32k */ | |
407a6888 BC |
360 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
361 | .name = "counter_32k", | |
362 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 363 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
364 | .flags = HWMOD_SWSUP_SIDLE, |
365 | .main_clk = "sys_32k_ck", | |
00fe610b | 366 | .prcm = { |
407a6888 | 367 | .omap4 = { |
d0f0631d | 368 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 369 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
370 | }, |
371 | }, | |
407a6888 BC |
372 | }; |
373 | ||
d7cf5f33 BC |
374 | /* |
375 | * 'dma' class | |
376 | * dma controller for data exchange between memory to memory (i.e. internal or | |
377 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
378 | */ | |
379 | ||
380 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
381 | .rev_offs = 0x0000, | |
382 | .sysc_offs = 0x002c, | |
383 | .syss_offs = 0x0028, | |
384 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
385 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
386 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
387 | SYSS_HAS_RESET_STATUS), | |
388 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
389 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
390 | .sysc_fields = &omap_hwmod_sysc_type1, | |
391 | }; | |
392 | ||
393 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
394 | .name = "dma", | |
395 | .sysc = &omap44xx_dma_sysc, | |
396 | }; | |
397 | ||
398 | /* dma dev_attr */ | |
399 | static struct omap_dma_dev_attr dma_dev_attr = { | |
400 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
401 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
402 | .lch_count = 32, | |
403 | }; | |
404 | ||
405 | /* dma_system */ | |
406 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
407 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
408 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
409 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
410 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 411 | { .irq = -1 } |
d7cf5f33 BC |
412 | }; |
413 | ||
d7cf5f33 BC |
414 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
415 | .name = "dma_system", | |
416 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 417 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 418 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
419 | .main_clk = "l3_div_ck", |
420 | .prcm = { | |
421 | .omap4 = { | |
d0f0631d | 422 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 423 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
424 | }, |
425 | }, | |
426 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
427 | }; |
428 | ||
8ca476da BC |
429 | /* |
430 | * 'dmic' class | |
431 | * digital microphone controller | |
432 | */ | |
433 | ||
434 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
435 | .rev_offs = 0x0000, | |
436 | .sysc_offs = 0x0010, | |
437 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
438 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
439 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
440 | SIDLE_SMART_WKUP), | |
441 | .sysc_fields = &omap_hwmod_sysc_type2, | |
442 | }; | |
443 | ||
444 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
445 | .name = "dmic", | |
446 | .sysc = &omap44xx_dmic_sysc, | |
447 | }; | |
448 | ||
449 | /* dmic */ | |
8ca476da BC |
450 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
451 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 452 | { .irq = -1 } |
8ca476da BC |
453 | }; |
454 | ||
455 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
456 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 457 | { .dma_req = -1 } |
8ca476da BC |
458 | }; |
459 | ||
8ca476da BC |
460 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
461 | .name = "dmic", | |
462 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 463 | .clkdm_name = "abe_clkdm", |
8ca476da | 464 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 465 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 466 | .main_clk = "dmic_fck", |
00fe610b | 467 | .prcm = { |
8ca476da | 468 | .omap4 = { |
d0f0631d | 469 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 470 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 471 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
472 | }, |
473 | }, | |
8ca476da BC |
474 | }; |
475 | ||
8f25bdc5 BC |
476 | /* |
477 | * 'dsp' class | |
478 | * dsp sub-system | |
479 | */ | |
480 | ||
481 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 482 | .name = "dsp", |
8f25bdc5 BC |
483 | }; |
484 | ||
485 | /* dsp */ | |
486 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
487 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 488 | { .irq = -1 } |
8f25bdc5 BC |
489 | }; |
490 | ||
491 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 | 492 | { .name = "dsp", .rst_shift = 0 }, |
f2f5736c | 493 | { .name = "mmu_cache", .rst_shift = 1 }, |
8f25bdc5 BC |
494 | }; |
495 | ||
8f25bdc5 BC |
496 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
497 | .name = "dsp", | |
498 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 499 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 500 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
501 | .rst_lines = omap44xx_dsp_resets, |
502 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
503 | .main_clk = "dsp_fck", | |
504 | .prcm = { | |
505 | .omap4 = { | |
d0f0631d | 506 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 507 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 508 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 509 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
510 | }, |
511 | }, | |
8f25bdc5 BC |
512 | }; |
513 | ||
d63bd74f BC |
514 | /* |
515 | * 'dss' class | |
516 | * display sub-system | |
517 | */ | |
518 | ||
519 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
520 | .rev_offs = 0x0000, | |
521 | .syss_offs = 0x0014, | |
522 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
523 | }; | |
524 | ||
525 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
526 | .name = "dss", | |
527 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 528 | .reset = omap_dss_reset, |
d63bd74f BC |
529 | }; |
530 | ||
531 | /* dss */ | |
d63bd74f BC |
532 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
533 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
534 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 535 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
536 | }; |
537 | ||
538 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
539 | .name = "dss_core", | |
37ad0855 | 540 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 541 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 542 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 543 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
544 | .prcm = { |
545 | .omap4 = { | |
d0f0631d | 546 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 547 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
548 | }, |
549 | }, | |
550 | .opt_clks = dss_opt_clks, | |
551 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
552 | }; |
553 | ||
554 | /* | |
555 | * 'dispc' class | |
556 | * display controller | |
557 | */ | |
558 | ||
559 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
560 | .rev_offs = 0x0000, | |
561 | .sysc_offs = 0x0010, | |
562 | .syss_offs = 0x0014, | |
563 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
564 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
565 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
566 | SYSS_HAS_RESET_STATUS), | |
567 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
568 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
569 | .sysc_fields = &omap_hwmod_sysc_type1, | |
570 | }; | |
571 | ||
572 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
573 | .name = "dispc", | |
574 | .sysc = &omap44xx_dispc_sysc, | |
575 | }; | |
576 | ||
577 | /* dss_dispc */ | |
d63bd74f BC |
578 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
579 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 580 | { .irq = -1 } |
d63bd74f BC |
581 | }; |
582 | ||
583 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
584 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 585 | { .dma_req = -1 } |
d63bd74f BC |
586 | }; |
587 | ||
b923d40d AT |
588 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
589 | .manager_count = 3, | |
590 | .has_framedonetv_irq = 1 | |
591 | }; | |
592 | ||
d63bd74f BC |
593 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
594 | .name = "dss_dispc", | |
595 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 596 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 597 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 598 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 599 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
600 | .prcm = { |
601 | .omap4 = { | |
d0f0631d | 602 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 603 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
604 | }, |
605 | }, | |
b923d40d | 606 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
607 | }; |
608 | ||
609 | /* | |
610 | * 'dsi' class | |
611 | * display serial interface controller | |
612 | */ | |
613 | ||
614 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
615 | .rev_offs = 0x0000, | |
616 | .sysc_offs = 0x0010, | |
617 | .syss_offs = 0x0014, | |
618 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
619 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
620 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
621 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
622 | .sysc_fields = &omap_hwmod_sysc_type1, | |
623 | }; | |
624 | ||
625 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
626 | .name = "dsi", | |
627 | .sysc = &omap44xx_dsi_sysc, | |
628 | }; | |
629 | ||
630 | /* dss_dsi1 */ | |
d63bd74f BC |
631 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
632 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 633 | { .irq = -1 } |
d63bd74f BC |
634 | }; |
635 | ||
636 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
637 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 638 | { .dma_req = -1 } |
d63bd74f BC |
639 | }; |
640 | ||
3a23aafc TV |
641 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
642 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
643 | }; | |
644 | ||
d63bd74f BC |
645 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
646 | .name = "dss_dsi1", | |
647 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 648 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 649 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 650 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 651 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
652 | .prcm = { |
653 | .omap4 = { | |
d0f0631d | 654 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 655 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
656 | }, |
657 | }, | |
3a23aafc TV |
658 | .opt_clks = dss_dsi1_opt_clks, |
659 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
660 | }; |
661 | ||
662 | /* dss_dsi2 */ | |
d63bd74f BC |
663 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
664 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 665 | { .irq = -1 } |
d63bd74f BC |
666 | }; |
667 | ||
668 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
669 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 670 | { .dma_req = -1 } |
d63bd74f BC |
671 | }; |
672 | ||
3a23aafc TV |
673 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
674 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
675 | }; | |
676 | ||
d63bd74f BC |
677 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
678 | .name = "dss_dsi2", | |
679 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 680 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 681 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 682 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 683 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
684 | .prcm = { |
685 | .omap4 = { | |
d0f0631d | 686 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 687 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
688 | }, |
689 | }, | |
3a23aafc TV |
690 | .opt_clks = dss_dsi2_opt_clks, |
691 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
692 | }; |
693 | ||
694 | /* | |
695 | * 'hdmi' class | |
696 | * hdmi controller | |
697 | */ | |
698 | ||
699 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
700 | .rev_offs = 0x0000, | |
701 | .sysc_offs = 0x0010, | |
702 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
703 | SYSC_HAS_SOFTRESET), | |
704 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
705 | SIDLE_SMART_WKUP), | |
706 | .sysc_fields = &omap_hwmod_sysc_type2, | |
707 | }; | |
708 | ||
709 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
710 | .name = "hdmi", | |
711 | .sysc = &omap44xx_hdmi_sysc, | |
712 | }; | |
713 | ||
714 | /* dss_hdmi */ | |
d63bd74f BC |
715 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
716 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 717 | { .irq = -1 } |
d63bd74f BC |
718 | }; |
719 | ||
720 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
721 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 722 | { .dma_req = -1 } |
d63bd74f BC |
723 | }; |
724 | ||
3a23aafc TV |
725 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
726 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
727 | }; | |
728 | ||
d63bd74f BC |
729 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
730 | .name = "dss_hdmi", | |
731 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 732 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 733 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 734 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 735 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
736 | .prcm = { |
737 | .omap4 = { | |
d0f0631d | 738 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 739 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
740 | }, |
741 | }, | |
3a23aafc TV |
742 | .opt_clks = dss_hdmi_opt_clks, |
743 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
744 | }; |
745 | ||
746 | /* | |
747 | * 'rfbi' class | |
748 | * remote frame buffer interface | |
749 | */ | |
750 | ||
751 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
752 | .rev_offs = 0x0000, | |
753 | .sysc_offs = 0x0010, | |
754 | .syss_offs = 0x0014, | |
755 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
756 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
757 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
758 | .sysc_fields = &omap_hwmod_sysc_type1, | |
759 | }; | |
760 | ||
761 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
762 | .name = "rfbi", | |
763 | .sysc = &omap44xx_rfbi_sysc, | |
764 | }; | |
765 | ||
766 | /* dss_rfbi */ | |
d63bd74f BC |
767 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
768 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 769 | { .dma_req = -1 } |
d63bd74f BC |
770 | }; |
771 | ||
3a23aafc TV |
772 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
773 | { .role = "ick", .clk = "dss_fck" }, | |
774 | }; | |
775 | ||
d63bd74f BC |
776 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
777 | .name = "dss_rfbi", | |
778 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 779 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 780 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 781 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
782 | .prcm = { |
783 | .omap4 = { | |
d0f0631d | 784 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 785 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
786 | }, |
787 | }, | |
3a23aafc TV |
788 | .opt_clks = dss_rfbi_opt_clks, |
789 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
790 | }; |
791 | ||
792 | /* | |
793 | * 'venc' class | |
794 | * video encoder | |
795 | */ | |
796 | ||
797 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
798 | .name = "venc", | |
799 | }; | |
800 | ||
801 | /* dss_venc */ | |
d63bd74f BC |
802 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
803 | .name = "dss_venc", | |
804 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 805 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 806 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
807 | .prcm = { |
808 | .omap4 = { | |
d0f0631d | 809 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 810 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
811 | }, |
812 | }, | |
d63bd74f BC |
813 | }; |
814 | ||
b050f688 ML |
815 | /* |
816 | * 'fdif' class | |
817 | * face detection hw accelerator module | |
818 | */ | |
819 | ||
820 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
821 | .rev_offs = 0x0000, | |
822 | .sysc_offs = 0x0010, | |
823 | /* | |
824 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
825 | * accessing sysconfig again. | |
826 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
827 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
828 | * | |
829 | * TODO: Indicate errata when available. | |
830 | */ | |
831 | .srst_udelay = 2, | |
832 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
833 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
834 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
835 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
836 | .sysc_fields = &omap_hwmod_sysc_type2, | |
837 | }; | |
838 | ||
839 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
840 | .name = "fdif", | |
841 | .sysc = &omap44xx_fdif_sysc, | |
842 | }; | |
843 | ||
844 | /* fdif */ | |
845 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
846 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
847 | { .irq = -1 } | |
848 | }; | |
849 | ||
850 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
851 | .name = "fdif", | |
852 | .class = &omap44xx_fdif_hwmod_class, | |
853 | .clkdm_name = "iss_clkdm", | |
854 | .mpu_irqs = omap44xx_fdif_irqs, | |
855 | .main_clk = "fdif_fck", | |
856 | .prcm = { | |
857 | .omap4 = { | |
858 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
859 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
860 | .modulemode = MODULEMODE_SWCTRL, | |
861 | }, | |
862 | }, | |
863 | }; | |
864 | ||
3b54baad BC |
865 | /* |
866 | * 'gpio' class | |
867 | * general purpose io module | |
868 | */ | |
869 | ||
870 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
871 | .rev_offs = 0x0000, | |
f776471f | 872 | .sysc_offs = 0x0010, |
3b54baad | 873 | .syss_offs = 0x0114, |
0cfe8751 BC |
874 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
875 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
876 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
877 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
878 | SIDLE_SMART_WKUP), | |
f776471f BC |
879 | .sysc_fields = &omap_hwmod_sysc_type1, |
880 | }; | |
881 | ||
3b54baad | 882 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
883 | .name = "gpio", |
884 | .sysc = &omap44xx_gpio_sysc, | |
885 | .rev = 2, | |
f776471f BC |
886 | }; |
887 | ||
3b54baad BC |
888 | /* gpio dev_attr */ |
889 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
890 | .bank_width = 32, |
891 | .dbck_flag = true, | |
f776471f BC |
892 | }; |
893 | ||
3b54baad | 894 | /* gpio1 */ |
3b54baad BC |
895 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
896 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 897 | { .irq = -1 } |
f776471f BC |
898 | }; |
899 | ||
3b54baad | 900 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 901 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
902 | }; |
903 | ||
904 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
905 | .name = "gpio1", | |
906 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 907 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 908 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 909 | .main_clk = "gpio1_ick", |
f776471f BC |
910 | .prcm = { |
911 | .omap4 = { | |
d0f0631d | 912 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 913 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 914 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
915 | }, |
916 | }, | |
3b54baad BC |
917 | .opt_clks = gpio1_opt_clks, |
918 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
919 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
920 | }; |
921 | ||
3b54baad | 922 | /* gpio2 */ |
3b54baad BC |
923 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
924 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 925 | { .irq = -1 } |
f776471f BC |
926 | }; |
927 | ||
3b54baad | 928 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 929 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
930 | }; |
931 | ||
932 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
933 | .name = "gpio2", | |
934 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 935 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 936 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 937 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 938 | .main_clk = "gpio2_ick", |
f776471f BC |
939 | .prcm = { |
940 | .omap4 = { | |
d0f0631d | 941 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 942 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 943 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
944 | }, |
945 | }, | |
3b54baad BC |
946 | .opt_clks = gpio2_opt_clks, |
947 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
948 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
949 | }; |
950 | ||
3b54baad | 951 | /* gpio3 */ |
3b54baad BC |
952 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
953 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 954 | { .irq = -1 } |
f776471f BC |
955 | }; |
956 | ||
3b54baad | 957 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 958 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
959 | }; |
960 | ||
961 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
962 | .name = "gpio3", | |
963 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 964 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 965 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 966 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 967 | .main_clk = "gpio3_ick", |
f776471f BC |
968 | .prcm = { |
969 | .omap4 = { | |
d0f0631d | 970 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 971 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 972 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
973 | }, |
974 | }, | |
3b54baad BC |
975 | .opt_clks = gpio3_opt_clks, |
976 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
977 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
978 | }; |
979 | ||
3b54baad | 980 | /* gpio4 */ |
3b54baad BC |
981 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
982 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 983 | { .irq = -1 } |
f776471f BC |
984 | }; |
985 | ||
3b54baad | 986 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 987 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
988 | }; |
989 | ||
990 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
991 | .name = "gpio4", | |
992 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 993 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 994 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 995 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 996 | .main_clk = "gpio4_ick", |
f776471f BC |
997 | .prcm = { |
998 | .omap4 = { | |
d0f0631d | 999 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1000 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1001 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1002 | }, |
1003 | }, | |
3b54baad BC |
1004 | .opt_clks = gpio4_opt_clks, |
1005 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1006 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1007 | }; |
1008 | ||
3b54baad | 1009 | /* gpio5 */ |
3b54baad BC |
1010 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1011 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1012 | { .irq = -1 } |
55d2cb08 BC |
1013 | }; |
1014 | ||
844a3b63 PW |
1015 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1016 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1017 | }; |
1018 | ||
3b54baad BC |
1019 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1020 | .name = "gpio5", | |
1021 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1022 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1023 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1024 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 1025 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
1026 | .prcm = { |
1027 | .omap4 = { | |
d0f0631d | 1028 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1029 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1030 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1031 | }, |
1032 | }, | |
3b54baad BC |
1033 | .opt_clks = gpio5_opt_clks, |
1034 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1035 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1036 | }; |
1037 | ||
3b54baad | 1038 | /* gpio6 */ |
3b54baad BC |
1039 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1040 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1041 | { .irq = -1 } |
92b18d1c BC |
1042 | }; |
1043 | ||
3b54baad | 1044 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1045 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1046 | }; |
1047 | ||
3b54baad BC |
1048 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1049 | .name = "gpio6", | |
1050 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1051 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1052 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1053 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
1054 | .main_clk = "gpio6_ick", |
1055 | .prcm = { | |
1056 | .omap4 = { | |
d0f0631d | 1057 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1058 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1059 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1060 | }, |
db12ba53 | 1061 | }, |
3b54baad BC |
1062 | .opt_clks = gpio6_opt_clks, |
1063 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1064 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1065 | }; |
1066 | ||
eb42b5d3 BC |
1067 | /* |
1068 | * 'gpmc' class | |
1069 | * general purpose memory controller | |
1070 | */ | |
1071 | ||
1072 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1073 | .rev_offs = 0x0000, | |
1074 | .sysc_offs = 0x0010, | |
1075 | .syss_offs = 0x0014, | |
1076 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1077 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1078 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1079 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1080 | }; | |
1081 | ||
1082 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1083 | .name = "gpmc", | |
1084 | .sysc = &omap44xx_gpmc_sysc, | |
1085 | }; | |
1086 | ||
1087 | /* gpmc */ | |
1088 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1089 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1090 | { .irq = -1 } | |
1091 | }; | |
1092 | ||
1093 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1094 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1095 | { .dma_req = -1 } | |
1096 | }; | |
1097 | ||
1098 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1099 | .name = "gpmc", | |
1100 | .class = &omap44xx_gpmc_hwmod_class, | |
1101 | .clkdm_name = "l3_2_clkdm", | |
1102 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1103 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1104 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1105 | .prcm = { | |
1106 | .omap4 = { | |
1107 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1108 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1109 | .modulemode = MODULEMODE_HWCTRL, | |
1110 | }, | |
1111 | }, | |
1112 | }; | |
1113 | ||
a091c08e PW |
1114 | /* |
1115 | * 'hdq1w' class | |
1116 | * hdq / 1-wire serial interface controller | |
1117 | */ | |
1118 | ||
1119 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1120 | .rev_offs = 0x0000, | |
1121 | .sysc_offs = 0x0014, | |
1122 | .syss_offs = 0x0018, | |
1123 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1124 | SYSS_HAS_RESET_STATUS), | |
1125 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1126 | }; | |
1127 | ||
1128 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1129 | .name = "hdq1w", | |
1130 | .sysc = &omap44xx_hdq1w_sysc, | |
1131 | }; | |
1132 | ||
1133 | /* hdq1w */ | |
1134 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1135 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1136 | { .irq = -1 } | |
1137 | }; | |
1138 | ||
1139 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1140 | .name = "hdq1w", | |
1141 | .class = &omap44xx_hdq1w_hwmod_class, | |
1142 | .clkdm_name = "l4_per_clkdm", | |
1143 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1144 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
1145 | .main_clk = "hdq1w_fck", | |
1146 | .prcm = { | |
1147 | .omap4 = { | |
1148 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1149 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1150 | .modulemode = MODULEMODE_SWCTRL, | |
1151 | }, | |
1152 | }, | |
1153 | }; | |
1154 | ||
407a6888 BC |
1155 | /* |
1156 | * 'hsi' class | |
1157 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1158 | * serial if) | |
1159 | */ | |
1160 | ||
1161 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1162 | .rev_offs = 0x0000, | |
1163 | .sysc_offs = 0x0010, | |
1164 | .syss_offs = 0x0014, | |
1165 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1166 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1167 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1168 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1169 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1170 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1171 | .sysc_fields = &omap_hwmod_sysc_type1, |
1172 | }; | |
1173 | ||
1174 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1175 | .name = "hsi", | |
1176 | .sysc = &omap44xx_hsi_sysc, | |
1177 | }; | |
1178 | ||
1179 | /* hsi */ | |
1180 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1181 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1182 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1183 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1184 | { .irq = -1 } |
407a6888 BC |
1185 | }; |
1186 | ||
407a6888 BC |
1187 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1188 | .name = "hsi", | |
1189 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1190 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1191 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1192 | .main_clk = "hsi_fck", |
00fe610b | 1193 | .prcm = { |
407a6888 | 1194 | .omap4 = { |
d0f0631d | 1195 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1196 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1197 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1198 | }, |
1199 | }, | |
407a6888 BC |
1200 | }; |
1201 | ||
3b54baad BC |
1202 | /* |
1203 | * 'i2c' class | |
1204 | * multimaster high-speed i2c controller | |
1205 | */ | |
db12ba53 | 1206 | |
3b54baad BC |
1207 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1208 | .sysc_offs = 0x0010, | |
1209 | .syss_offs = 0x0090, | |
1210 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1211 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1212 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1213 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1214 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1215 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1216 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1217 | }; |
1218 | ||
3b54baad | 1219 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1220 | .name = "i2c", |
1221 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1222 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1223 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1224 | }; |
1225 | ||
4d4441a6 AG |
1226 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
1227 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
1228 | }; | |
1229 | ||
3b54baad | 1230 | /* i2c1 */ |
3b54baad BC |
1231 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1232 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1233 | { .irq = -1 } |
db12ba53 BC |
1234 | }; |
1235 | ||
3b54baad BC |
1236 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1237 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1238 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1239 | { .dma_req = -1 } |
db12ba53 BC |
1240 | }; |
1241 | ||
3b54baad BC |
1242 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1243 | .name = "i2c1", | |
1244 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1245 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1246 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1247 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1248 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 1249 | .main_clk = "i2c1_fck", |
92b18d1c BC |
1250 | .prcm = { |
1251 | .omap4 = { | |
d0f0631d | 1252 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1253 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1254 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1255 | }, |
1256 | }, | |
4d4441a6 | 1257 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1258 | }; |
1259 | ||
3b54baad | 1260 | /* i2c2 */ |
3b54baad BC |
1261 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1262 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1263 | { .irq = -1 } |
92b18d1c BC |
1264 | }; |
1265 | ||
3b54baad BC |
1266 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1267 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1268 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1269 | { .dma_req = -1 } |
3b54baad BC |
1270 | }; |
1271 | ||
3b54baad BC |
1272 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1273 | .name = "i2c2", | |
1274 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1275 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1276 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1277 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1278 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 1279 | .main_clk = "i2c2_fck", |
db12ba53 BC |
1280 | .prcm = { |
1281 | .omap4 = { | |
d0f0631d | 1282 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1283 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1284 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1285 | }, |
1286 | }, | |
4d4441a6 | 1287 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1288 | }; |
1289 | ||
3b54baad | 1290 | /* i2c3 */ |
3b54baad BC |
1291 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1292 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1293 | { .irq = -1 } |
db12ba53 BC |
1294 | }; |
1295 | ||
3b54baad BC |
1296 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1297 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1298 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1299 | { .dma_req = -1 } |
92b18d1c BC |
1300 | }; |
1301 | ||
3b54baad BC |
1302 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1303 | .name = "i2c3", | |
1304 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1305 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1306 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1307 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1308 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 1309 | .main_clk = "i2c3_fck", |
db12ba53 BC |
1310 | .prcm = { |
1311 | .omap4 = { | |
d0f0631d | 1312 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1313 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1314 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1315 | }, |
1316 | }, | |
4d4441a6 | 1317 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1318 | }; |
1319 | ||
3b54baad | 1320 | /* i2c4 */ |
3b54baad BC |
1321 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1322 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1323 | { .irq = -1 } |
db12ba53 BC |
1324 | }; |
1325 | ||
3b54baad BC |
1326 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1327 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1328 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1329 | { .dma_req = -1 } |
db12ba53 BC |
1330 | }; |
1331 | ||
3b54baad BC |
1332 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1333 | .name = "i2c4", | |
1334 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1335 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1336 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1337 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1338 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 1339 | .main_clk = "i2c4_fck", |
92b18d1c BC |
1340 | .prcm = { |
1341 | .omap4 = { | |
d0f0631d | 1342 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1343 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1344 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1345 | }, |
1346 | }, | |
4d4441a6 | 1347 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1348 | }; |
1349 | ||
407a6888 BC |
1350 | /* |
1351 | * 'ipu' class | |
1352 | * imaging processor unit | |
1353 | */ | |
1354 | ||
1355 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1356 | .name = "ipu", | |
1357 | }; | |
1358 | ||
1359 | /* ipu */ | |
1360 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1361 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1362 | { .irq = -1 } |
407a6888 BC |
1363 | }; |
1364 | ||
f2f5736c | 1365 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1366 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1367 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1368 | { .name = "mmu_cache", .rst_shift = 2 }, |
1369 | }; | |
1370 | ||
407a6888 BC |
1371 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1372 | .name = "ipu", | |
1373 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1374 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1375 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1376 | .rst_lines = omap44xx_ipu_resets, |
1377 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
1378 | .main_clk = "ipu_fck", | |
00fe610b | 1379 | .prcm = { |
407a6888 | 1380 | .omap4 = { |
d0f0631d | 1381 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1382 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1383 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1384 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1385 | }, |
1386 | }, | |
407a6888 BC |
1387 | }; |
1388 | ||
1389 | /* | |
1390 | * 'iss' class | |
1391 | * external images sensor pixel data processor | |
1392 | */ | |
1393 | ||
1394 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1395 | .rev_offs = 0x0000, | |
1396 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1397 | /* |
1398 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1399 | * accessing sysconfig again. | |
1400 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1401 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1402 | * | |
1403 | * TODO: Indicate errata when available. | |
1404 | */ | |
1405 | .srst_udelay = 2, | |
407a6888 BC |
1406 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1407 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1408 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1409 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1410 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1411 | .sysc_fields = &omap_hwmod_sysc_type2, |
1412 | }; | |
1413 | ||
1414 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1415 | .name = "iss", | |
1416 | .sysc = &omap44xx_iss_sysc, | |
1417 | }; | |
1418 | ||
1419 | /* iss */ | |
1420 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1421 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1422 | { .irq = -1 } |
407a6888 BC |
1423 | }; |
1424 | ||
1425 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1426 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1427 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1428 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1429 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1430 | { .dma_req = -1 } |
407a6888 BC |
1431 | }; |
1432 | ||
407a6888 BC |
1433 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1434 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1435 | }; | |
1436 | ||
1437 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1438 | .name = "iss", | |
1439 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1440 | .clkdm_name = "iss_clkdm", |
407a6888 | 1441 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1442 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 1443 | .main_clk = "iss_fck", |
00fe610b | 1444 | .prcm = { |
407a6888 | 1445 | .omap4 = { |
d0f0631d | 1446 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1447 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1448 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1449 | }, |
1450 | }, | |
1451 | .opt_clks = iss_opt_clks, | |
1452 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1453 | }; |
1454 | ||
8f25bdc5 BC |
1455 | /* |
1456 | * 'iva' class | |
1457 | * multi-standard video encoder/decoder hardware accelerator | |
1458 | */ | |
1459 | ||
1460 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1461 | .name = "iva", |
8f25bdc5 BC |
1462 | }; |
1463 | ||
1464 | /* iva */ | |
1465 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1466 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1467 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1468 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1469 | { .irq = -1 } |
8f25bdc5 BC |
1470 | }; |
1471 | ||
1472 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1473 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1474 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1475 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1476 | }; |
1477 | ||
8f25bdc5 BC |
1478 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1479 | .name = "iva", | |
1480 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1481 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1482 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1483 | .rst_lines = omap44xx_iva_resets, |
1484 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1485 | .main_clk = "iva_fck", | |
1486 | .prcm = { | |
1487 | .omap4 = { | |
d0f0631d | 1488 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1489 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1490 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1491 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1492 | }, |
1493 | }, | |
8f25bdc5 BC |
1494 | }; |
1495 | ||
407a6888 BC |
1496 | /* |
1497 | * 'kbd' class | |
1498 | * keyboard controller | |
1499 | */ | |
1500 | ||
1501 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1502 | .rev_offs = 0x0000, | |
1503 | .sysc_offs = 0x0010, | |
1504 | .syss_offs = 0x0014, | |
1505 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1506 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1507 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1508 | SYSS_HAS_RESET_STATUS), | |
1509 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1510 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1511 | }; | |
1512 | ||
1513 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1514 | .name = "kbd", | |
1515 | .sysc = &omap44xx_kbd_sysc, | |
1516 | }; | |
1517 | ||
1518 | /* kbd */ | |
407a6888 BC |
1519 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1520 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1521 | { .irq = -1 } |
407a6888 BC |
1522 | }; |
1523 | ||
407a6888 BC |
1524 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1525 | .name = "kbd", | |
1526 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1527 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1528 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 1529 | .main_clk = "kbd_fck", |
00fe610b | 1530 | .prcm = { |
407a6888 | 1531 | .omap4 = { |
d0f0631d | 1532 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1533 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1534 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1535 | }, |
1536 | }, | |
407a6888 BC |
1537 | }; |
1538 | ||
ec5df927 BC |
1539 | /* |
1540 | * 'mailbox' class | |
1541 | * mailbox module allowing communication between the on-chip processors using a | |
1542 | * queued mailbox-interrupt mechanism. | |
1543 | */ | |
1544 | ||
1545 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1546 | .rev_offs = 0x0000, | |
1547 | .sysc_offs = 0x0010, | |
1548 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1549 | SYSC_HAS_SOFTRESET), | |
1550 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1551 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1552 | }; | |
1553 | ||
1554 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1555 | .name = "mailbox", | |
1556 | .sysc = &omap44xx_mailbox_sysc, | |
1557 | }; | |
1558 | ||
1559 | /* mailbox */ | |
ec5df927 BC |
1560 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1561 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1562 | { .irq = -1 } |
ec5df927 BC |
1563 | }; |
1564 | ||
ec5df927 BC |
1565 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1566 | .name = "mailbox", | |
1567 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1568 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1569 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1570 | .prcm = { |
ec5df927 | 1571 | .omap4 = { |
d0f0631d | 1572 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1573 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1574 | }, |
1575 | }, | |
ec5df927 BC |
1576 | }; |
1577 | ||
4ddff493 BC |
1578 | /* |
1579 | * 'mcbsp' class | |
1580 | * multi channel buffered serial port controller | |
1581 | */ | |
1582 | ||
1583 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1584 | .sysc_offs = 0x008c, | |
1585 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1586 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1587 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1588 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1589 | }; | |
1590 | ||
1591 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1592 | .name = "mcbsp", | |
1593 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1594 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1595 | }; |
1596 | ||
1597 | /* mcbsp1 */ | |
4ddff493 BC |
1598 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
1599 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1600 | { .irq = -1 } |
4ddff493 BC |
1601 | }; |
1602 | ||
1603 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1604 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1605 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1606 | { .dma_req = -1 } |
4ddff493 BC |
1607 | }; |
1608 | ||
503d0ea2 PW |
1609 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1610 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1611 | { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, | |
1612 | }; | |
1613 | ||
4ddff493 BC |
1614 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1615 | .name = "mcbsp1", | |
1616 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1617 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1618 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1619 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
1620 | .main_clk = "mcbsp1_fck", |
1621 | .prcm = { | |
1622 | .omap4 = { | |
d0f0631d | 1623 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1624 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1625 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1626 | }, |
1627 | }, | |
503d0ea2 PW |
1628 | .opt_clks = mcbsp1_opt_clks, |
1629 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1630 | }; |
1631 | ||
1632 | /* mcbsp2 */ | |
4ddff493 BC |
1633 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
1634 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1635 | { .irq = -1 } |
4ddff493 BC |
1636 | }; |
1637 | ||
1638 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1639 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1640 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1641 | { .dma_req = -1 } |
4ddff493 BC |
1642 | }; |
1643 | ||
844a3b63 PW |
1644 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1645 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1646 | { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, | |
503d0ea2 PW |
1647 | }; |
1648 | ||
4ddff493 BC |
1649 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1650 | .name = "mcbsp2", | |
1651 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1652 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1653 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 1654 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
1655 | .main_clk = "mcbsp2_fck", |
1656 | .prcm = { | |
1657 | .omap4 = { | |
d0f0631d | 1658 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1659 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1660 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1661 | }, |
1662 | }, | |
503d0ea2 PW |
1663 | .opt_clks = mcbsp2_opt_clks, |
1664 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1665 | }; |
1666 | ||
1667 | /* mcbsp3 */ | |
4ddff493 BC |
1668 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
1669 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1670 | { .irq = -1 } |
4ddff493 BC |
1671 | }; |
1672 | ||
1673 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
1674 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
1675 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1676 | { .dma_req = -1 } |
4ddff493 BC |
1677 | }; |
1678 | ||
503d0ea2 PW |
1679 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1680 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1681 | { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, | |
1682 | }; | |
1683 | ||
4ddff493 BC |
1684 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1685 | .name = "mcbsp3", | |
1686 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1687 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1688 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 1689 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
1690 | .main_clk = "mcbsp3_fck", |
1691 | .prcm = { | |
1692 | .omap4 = { | |
d0f0631d | 1693 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1694 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1695 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1696 | }, |
1697 | }, | |
503d0ea2 PW |
1698 | .opt_clks = mcbsp3_opt_clks, |
1699 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1700 | }; |
1701 | ||
1702 | /* mcbsp4 */ | |
4ddff493 BC |
1703 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
1704 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1705 | { .irq = -1 } |
4ddff493 BC |
1706 | }; |
1707 | ||
1708 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
1709 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
1710 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1711 | { .dma_req = -1 } |
4ddff493 BC |
1712 | }; |
1713 | ||
503d0ea2 PW |
1714 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
1715 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
1716 | { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, | |
1717 | }; | |
1718 | ||
4ddff493 BC |
1719 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
1720 | .name = "mcbsp4", | |
1721 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1722 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 1723 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 1724 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
1725 | .main_clk = "mcbsp4_fck", |
1726 | .prcm = { | |
1727 | .omap4 = { | |
d0f0631d | 1728 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 1729 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 1730 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1731 | }, |
1732 | }, | |
503d0ea2 PW |
1733 | .opt_clks = mcbsp4_opt_clks, |
1734 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
1735 | }; |
1736 | ||
407a6888 BC |
1737 | /* |
1738 | * 'mcpdm' class | |
1739 | * multi channel pdm controller (proprietary interface with phoenix power | |
1740 | * ic) | |
1741 | */ | |
1742 | ||
1743 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
1744 | .rev_offs = 0x0000, | |
1745 | .sysc_offs = 0x0010, | |
1746 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1747 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1748 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1749 | SIDLE_SMART_WKUP), | |
1750 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1751 | }; | |
1752 | ||
1753 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
1754 | .name = "mcpdm", | |
1755 | .sysc = &omap44xx_mcpdm_sysc, | |
1756 | }; | |
1757 | ||
1758 | /* mcpdm */ | |
407a6888 BC |
1759 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
1760 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1761 | { .irq = -1 } |
407a6888 BC |
1762 | }; |
1763 | ||
1764 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
1765 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
1766 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1767 | { .dma_req = -1 } |
407a6888 BC |
1768 | }; |
1769 | ||
407a6888 BC |
1770 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
1771 | .name = "mcpdm", | |
1772 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 1773 | .clkdm_name = "abe_clkdm", |
407a6888 | 1774 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 1775 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 1776 | .main_clk = "mcpdm_fck", |
00fe610b | 1777 | .prcm = { |
407a6888 | 1778 | .omap4 = { |
d0f0631d | 1779 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 1780 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 1781 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1782 | }, |
1783 | }, | |
407a6888 BC |
1784 | }; |
1785 | ||
9bcbd7f0 BC |
1786 | /* |
1787 | * 'mcspi' class | |
1788 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1789 | * bus | |
1790 | */ | |
1791 | ||
1792 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
1793 | .rev_offs = 0x0000, | |
1794 | .sysc_offs = 0x0010, | |
1795 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1796 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1797 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1798 | SIDLE_SMART_WKUP), | |
1799 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1800 | }; | |
1801 | ||
1802 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
1803 | .name = "mcspi", | |
1804 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 1805 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
1806 | }; |
1807 | ||
1808 | /* mcspi1 */ | |
9bcbd7f0 BC |
1809 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
1810 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1811 | { .irq = -1 } |
9bcbd7f0 BC |
1812 | }; |
1813 | ||
1814 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
1815 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
1816 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
1817 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
1818 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
1819 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
1820 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
1821 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
1822 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1823 | { .dma_req = -1 } |
9bcbd7f0 BC |
1824 | }; |
1825 | ||
905a74d9 BC |
1826 | /* mcspi1 dev_attr */ |
1827 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
1828 | .num_chipselect = 4, | |
1829 | }; | |
1830 | ||
9bcbd7f0 BC |
1831 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
1832 | .name = "mcspi1", | |
1833 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1834 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1835 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 1836 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
1837 | .main_clk = "mcspi1_fck", |
1838 | .prcm = { | |
1839 | .omap4 = { | |
d0f0631d | 1840 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 1841 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 1842 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1843 | }, |
1844 | }, | |
905a74d9 | 1845 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
1846 | }; |
1847 | ||
1848 | /* mcspi2 */ | |
9bcbd7f0 BC |
1849 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
1850 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1851 | { .irq = -1 } |
9bcbd7f0 BC |
1852 | }; |
1853 | ||
1854 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
1855 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
1856 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
1857 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
1858 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1859 | { .dma_req = -1 } |
9bcbd7f0 BC |
1860 | }; |
1861 | ||
905a74d9 BC |
1862 | /* mcspi2 dev_attr */ |
1863 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
1864 | .num_chipselect = 2, | |
1865 | }; | |
1866 | ||
9bcbd7f0 BC |
1867 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
1868 | .name = "mcspi2", | |
1869 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1870 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1871 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 1872 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
1873 | .main_clk = "mcspi2_fck", |
1874 | .prcm = { | |
1875 | .omap4 = { | |
d0f0631d | 1876 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 1877 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 1878 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1879 | }, |
1880 | }, | |
905a74d9 | 1881 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
1882 | }; |
1883 | ||
1884 | /* mcspi3 */ | |
9bcbd7f0 BC |
1885 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
1886 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1887 | { .irq = -1 } |
9bcbd7f0 BC |
1888 | }; |
1889 | ||
1890 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
1891 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
1892 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
1893 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
1894 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1895 | { .dma_req = -1 } |
9bcbd7f0 BC |
1896 | }; |
1897 | ||
905a74d9 BC |
1898 | /* mcspi3 dev_attr */ |
1899 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
1900 | .num_chipselect = 2, | |
1901 | }; | |
1902 | ||
9bcbd7f0 BC |
1903 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
1904 | .name = "mcspi3", | |
1905 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1906 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1907 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 1908 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
1909 | .main_clk = "mcspi3_fck", |
1910 | .prcm = { | |
1911 | .omap4 = { | |
d0f0631d | 1912 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 1913 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 1914 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1915 | }, |
1916 | }, | |
905a74d9 | 1917 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
1918 | }; |
1919 | ||
1920 | /* mcspi4 */ | |
9bcbd7f0 BC |
1921 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
1922 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1923 | { .irq = -1 } |
9bcbd7f0 BC |
1924 | }; |
1925 | ||
1926 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
1927 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
1928 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1929 | { .dma_req = -1 } |
9bcbd7f0 BC |
1930 | }; |
1931 | ||
905a74d9 BC |
1932 | /* mcspi4 dev_attr */ |
1933 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
1934 | .num_chipselect = 1, | |
1935 | }; | |
1936 | ||
9bcbd7f0 BC |
1937 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
1938 | .name = "mcspi4", | |
1939 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1940 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1941 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 1942 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
1943 | .main_clk = "mcspi4_fck", |
1944 | .prcm = { | |
1945 | .omap4 = { | |
d0f0631d | 1946 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 1947 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 1948 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1949 | }, |
1950 | }, | |
905a74d9 | 1951 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
1952 | }; |
1953 | ||
407a6888 BC |
1954 | /* |
1955 | * 'mmc' class | |
1956 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
1957 | */ | |
1958 | ||
1959 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
1960 | .rev_offs = 0x0000, | |
1961 | .sysc_offs = 0x0010, | |
1962 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1963 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1964 | SYSC_HAS_SOFTRESET), | |
1965 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1966 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1967 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1968 | .sysc_fields = &omap_hwmod_sysc_type2, |
1969 | }; | |
1970 | ||
1971 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
1972 | .name = "mmc", | |
1973 | .sysc = &omap44xx_mmc_sysc, | |
1974 | }; | |
1975 | ||
1976 | /* mmc1 */ | |
1977 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
1978 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1979 | { .irq = -1 } |
407a6888 BC |
1980 | }; |
1981 | ||
1982 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
1983 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
1984 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1985 | { .dma_req = -1 } |
407a6888 BC |
1986 | }; |
1987 | ||
6ab8946f KK |
1988 | /* mmc1 dev_attr */ |
1989 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1990 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1991 | }; | |
1992 | ||
407a6888 BC |
1993 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
1994 | .name = "mmc1", | |
1995 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 1996 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1997 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 1998 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 1999 | .main_clk = "mmc1_fck", |
00fe610b | 2000 | .prcm = { |
407a6888 | 2001 | .omap4 = { |
d0f0631d | 2002 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2003 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2004 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2005 | }, |
2006 | }, | |
6ab8946f | 2007 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2008 | }; |
2009 | ||
2010 | /* mmc2 */ | |
2011 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2012 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2013 | { .irq = -1 } |
407a6888 BC |
2014 | }; |
2015 | ||
2016 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2017 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2018 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2019 | { .dma_req = -1 } |
407a6888 BC |
2020 | }; |
2021 | ||
407a6888 BC |
2022 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2023 | .name = "mmc2", | |
2024 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2025 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2026 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2027 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 2028 | .main_clk = "mmc2_fck", |
00fe610b | 2029 | .prcm = { |
407a6888 | 2030 | .omap4 = { |
d0f0631d | 2031 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2032 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2033 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2034 | }, |
2035 | }, | |
407a6888 BC |
2036 | }; |
2037 | ||
2038 | /* mmc3 */ | |
407a6888 BC |
2039 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2040 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2041 | { .irq = -1 } |
407a6888 BC |
2042 | }; |
2043 | ||
2044 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2045 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2046 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2047 | { .dma_req = -1 } |
407a6888 BC |
2048 | }; |
2049 | ||
407a6888 BC |
2050 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2051 | .name = "mmc3", | |
2052 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2053 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2054 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2055 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 2056 | .main_clk = "mmc3_fck", |
00fe610b | 2057 | .prcm = { |
407a6888 | 2058 | .omap4 = { |
d0f0631d | 2059 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2060 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2061 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2062 | }, |
2063 | }, | |
407a6888 BC |
2064 | }; |
2065 | ||
2066 | /* mmc4 */ | |
407a6888 BC |
2067 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2068 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2069 | { .irq = -1 } |
407a6888 BC |
2070 | }; |
2071 | ||
2072 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2073 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2074 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2075 | { .dma_req = -1 } |
407a6888 BC |
2076 | }; |
2077 | ||
407a6888 BC |
2078 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2079 | .name = "mmc4", | |
2080 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2081 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2082 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2083 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 2084 | .main_clk = "mmc4_fck", |
00fe610b | 2085 | .prcm = { |
407a6888 | 2086 | .omap4 = { |
d0f0631d | 2087 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2088 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2089 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2090 | }, |
2091 | }, | |
407a6888 BC |
2092 | }; |
2093 | ||
2094 | /* mmc5 */ | |
407a6888 BC |
2095 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2096 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2097 | { .irq = -1 } |
407a6888 BC |
2098 | }; |
2099 | ||
2100 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2101 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2102 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2103 | { .dma_req = -1 } |
407a6888 BC |
2104 | }; |
2105 | ||
407a6888 BC |
2106 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2107 | .name = "mmc5", | |
2108 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2109 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2110 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2111 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 2112 | .main_clk = "mmc5_fck", |
00fe610b | 2113 | .prcm = { |
407a6888 | 2114 | .omap4 = { |
d0f0631d | 2115 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2116 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2117 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2118 | }, |
2119 | }, | |
407a6888 BC |
2120 | }; |
2121 | ||
3b54baad BC |
2122 | /* |
2123 | * 'mpu' class | |
2124 | * mpu sub-system | |
2125 | */ | |
2126 | ||
2127 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2128 | .name = "mpu", |
db12ba53 BC |
2129 | }; |
2130 | ||
3b54baad BC |
2131 | /* mpu */ |
2132 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
2133 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
2134 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2135 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2136 | { .irq = -1 } |
db12ba53 BC |
2137 | }; |
2138 | ||
3b54baad BC |
2139 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2140 | .name = "mpu", | |
2141 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2142 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2143 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2144 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2145 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2146 | .prcm = { |
2147 | .omap4 = { | |
d0f0631d | 2148 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2149 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2150 | }, |
2151 | }, | |
db12ba53 BC |
2152 | }; |
2153 | ||
1f6a717f BC |
2154 | /* |
2155 | * 'smartreflex' class | |
2156 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2157 | * performance error) | |
2158 | */ | |
2159 | ||
2160 | /* The IP is not compliant to type1 / type2 scheme */ | |
2161 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2162 | .sidle_shift = 24, | |
2163 | .enwkup_shift = 26, | |
2164 | }; | |
2165 | ||
2166 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2167 | .sysc_offs = 0x0038, | |
2168 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2169 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2170 | SIDLE_SMART_WKUP), | |
2171 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2172 | }; | |
2173 | ||
2174 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2175 | .name = "smartreflex", |
2176 | .sysc = &omap44xx_smartreflex_sysc, | |
2177 | .rev = 2, | |
1f6a717f BC |
2178 | }; |
2179 | ||
2180 | /* smartreflex_core */ | |
cea6b942 SG |
2181 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2182 | .sensor_voltdm_name = "core", | |
2183 | }; | |
2184 | ||
1f6a717f BC |
2185 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2186 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2187 | { .irq = -1 } |
1f6a717f BC |
2188 | }; |
2189 | ||
1f6a717f BC |
2190 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2191 | .name = "smartreflex_core", | |
2192 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2193 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2194 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2195 | |
1f6a717f | 2196 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2197 | .prcm = { |
2198 | .omap4 = { | |
d0f0631d | 2199 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2200 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2201 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2202 | }, |
2203 | }, | |
cea6b942 | 2204 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2205 | }; |
2206 | ||
2207 | /* smartreflex_iva */ | |
cea6b942 SG |
2208 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2209 | .sensor_voltdm_name = "iva", | |
2210 | }; | |
2211 | ||
1f6a717f BC |
2212 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
2213 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2214 | { .irq = -1 } |
1f6a717f BC |
2215 | }; |
2216 | ||
1f6a717f BC |
2217 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2218 | .name = "smartreflex_iva", | |
2219 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2220 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2221 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 2222 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2223 | .prcm = { |
2224 | .omap4 = { | |
d0f0631d | 2225 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2226 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2227 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2228 | }, |
2229 | }, | |
cea6b942 | 2230 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2231 | }; |
2232 | ||
2233 | /* smartreflex_mpu */ | |
cea6b942 SG |
2234 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2235 | .sensor_voltdm_name = "mpu", | |
2236 | }; | |
2237 | ||
1f6a717f BC |
2238 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
2239 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2240 | { .irq = -1 } |
1f6a717f BC |
2241 | }; |
2242 | ||
1f6a717f BC |
2243 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2244 | .name = "smartreflex_mpu", | |
2245 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2246 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2247 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 2248 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2249 | .prcm = { |
2250 | .omap4 = { | |
d0f0631d | 2251 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2252 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2253 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2254 | }, |
2255 | }, | |
cea6b942 | 2256 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2257 | }; |
2258 | ||
d11c217f BC |
2259 | /* |
2260 | * 'spinlock' class | |
2261 | * spinlock provides hardware assistance for synchronizing the processes | |
2262 | * running on multiple processors | |
2263 | */ | |
2264 | ||
2265 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2266 | .rev_offs = 0x0000, | |
2267 | .sysc_offs = 0x0010, | |
2268 | .syss_offs = 0x0014, | |
2269 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2270 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2271 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2272 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2273 | SIDLE_SMART_WKUP), | |
2274 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2275 | }; | |
2276 | ||
2277 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2278 | .name = "spinlock", | |
2279 | .sysc = &omap44xx_spinlock_sysc, | |
2280 | }; | |
2281 | ||
2282 | /* spinlock */ | |
d11c217f BC |
2283 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2284 | .name = "spinlock", | |
2285 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2286 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2287 | .prcm = { |
2288 | .omap4 = { | |
d0f0631d | 2289 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2290 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2291 | }, |
2292 | }, | |
d11c217f BC |
2293 | }; |
2294 | ||
35d1a66a BC |
2295 | /* |
2296 | * 'timer' class | |
2297 | * general purpose timer module with accurate 1ms tick | |
2298 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2299 | */ | |
2300 | ||
2301 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2302 | .rev_offs = 0x0000, | |
2303 | .sysc_offs = 0x0010, | |
2304 | .syss_offs = 0x0014, | |
2305 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2306 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2307 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2308 | SYSS_HAS_RESET_STATUS), | |
2309 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2310 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2311 | }; | |
2312 | ||
2313 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2314 | .name = "timer", | |
2315 | .sysc = &omap44xx_timer_1ms_sysc, | |
2316 | }; | |
2317 | ||
2318 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2319 | .rev_offs = 0x0000, | |
2320 | .sysc_offs = 0x0010, | |
2321 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2322 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2323 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2324 | SIDLE_SMART_WKUP), | |
2325 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2326 | }; | |
2327 | ||
2328 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2329 | .name = "timer", | |
2330 | .sysc = &omap44xx_timer_sysc, | |
2331 | }; | |
2332 | ||
c345c8b0 TKD |
2333 | /* always-on timers dev attribute */ |
2334 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2335 | .timer_capability = OMAP_TIMER_ALWON, | |
2336 | }; | |
2337 | ||
2338 | /* pwm timers dev attribute */ | |
2339 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2340 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2341 | }; | |
2342 | ||
35d1a66a | 2343 | /* timer1 */ |
35d1a66a BC |
2344 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
2345 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2346 | { .irq = -1 } |
35d1a66a BC |
2347 | }; |
2348 | ||
35d1a66a BC |
2349 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2350 | .name = "timer1", | |
2351 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2352 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 2353 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
2354 | .main_clk = "timer1_fck", |
2355 | .prcm = { | |
2356 | .omap4 = { | |
d0f0631d | 2357 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2358 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2359 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2360 | }, |
2361 | }, | |
c345c8b0 | 2362 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2363 | }; |
2364 | ||
2365 | /* timer2 */ | |
35d1a66a BC |
2366 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
2367 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2368 | { .irq = -1 } |
35d1a66a BC |
2369 | }; |
2370 | ||
35d1a66a BC |
2371 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2372 | .name = "timer2", | |
2373 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2374 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2375 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
2376 | .main_clk = "timer2_fck", |
2377 | .prcm = { | |
2378 | .omap4 = { | |
d0f0631d | 2379 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2380 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2381 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2382 | }, |
2383 | }, | |
c345c8b0 | 2384 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2385 | }; |
2386 | ||
2387 | /* timer3 */ | |
35d1a66a BC |
2388 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
2389 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2390 | { .irq = -1 } |
35d1a66a BC |
2391 | }; |
2392 | ||
35d1a66a BC |
2393 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2394 | .name = "timer3", | |
2395 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2396 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2397 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
2398 | .main_clk = "timer3_fck", |
2399 | .prcm = { | |
2400 | .omap4 = { | |
d0f0631d | 2401 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2402 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2403 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2404 | }, |
2405 | }, | |
c345c8b0 | 2406 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2407 | }; |
2408 | ||
2409 | /* timer4 */ | |
35d1a66a BC |
2410 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
2411 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2412 | { .irq = -1 } |
35d1a66a BC |
2413 | }; |
2414 | ||
35d1a66a BC |
2415 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2416 | .name = "timer4", | |
2417 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2418 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2419 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
2420 | .main_clk = "timer4_fck", |
2421 | .prcm = { | |
2422 | .omap4 = { | |
d0f0631d | 2423 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2424 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2425 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2426 | }, |
2427 | }, | |
c345c8b0 | 2428 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2429 | }; |
2430 | ||
2431 | /* timer5 */ | |
35d1a66a BC |
2432 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
2433 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2434 | { .irq = -1 } |
35d1a66a BC |
2435 | }; |
2436 | ||
35d1a66a BC |
2437 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2438 | .name = "timer5", | |
2439 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2440 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2441 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
2442 | .main_clk = "timer5_fck", |
2443 | .prcm = { | |
2444 | .omap4 = { | |
d0f0631d | 2445 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2446 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2447 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2448 | }, |
2449 | }, | |
c345c8b0 | 2450 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2451 | }; |
2452 | ||
2453 | /* timer6 */ | |
35d1a66a BC |
2454 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
2455 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2456 | { .irq = -1 } |
35d1a66a BC |
2457 | }; |
2458 | ||
35d1a66a BC |
2459 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
2460 | .name = "timer6", | |
2461 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2462 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2463 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 2464 | |
35d1a66a BC |
2465 | .main_clk = "timer6_fck", |
2466 | .prcm = { | |
2467 | .omap4 = { | |
d0f0631d | 2468 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 2469 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 2470 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2471 | }, |
2472 | }, | |
c345c8b0 | 2473 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2474 | }; |
2475 | ||
2476 | /* timer7 */ | |
35d1a66a BC |
2477 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
2478 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2479 | { .irq = -1 } |
35d1a66a BC |
2480 | }; |
2481 | ||
35d1a66a BC |
2482 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
2483 | .name = "timer7", | |
2484 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2485 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2486 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
2487 | .main_clk = "timer7_fck", |
2488 | .prcm = { | |
2489 | .omap4 = { | |
d0f0631d | 2490 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 2491 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 2492 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2493 | }, |
2494 | }, | |
c345c8b0 | 2495 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2496 | }; |
2497 | ||
2498 | /* timer8 */ | |
35d1a66a BC |
2499 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
2500 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2501 | { .irq = -1 } |
35d1a66a BC |
2502 | }; |
2503 | ||
35d1a66a BC |
2504 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
2505 | .name = "timer8", | |
2506 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2507 | .clkdm_name = "abe_clkdm", |
35d1a66a | 2508 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
2509 | .main_clk = "timer8_fck", |
2510 | .prcm = { | |
2511 | .omap4 = { | |
d0f0631d | 2512 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 2513 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 2514 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2515 | }, |
2516 | }, | |
c345c8b0 | 2517 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2518 | }; |
2519 | ||
2520 | /* timer9 */ | |
35d1a66a BC |
2521 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
2522 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2523 | { .irq = -1 } |
35d1a66a BC |
2524 | }; |
2525 | ||
35d1a66a BC |
2526 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
2527 | .name = "timer9", | |
2528 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2529 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2530 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
2531 | .main_clk = "timer9_fck", |
2532 | .prcm = { | |
2533 | .omap4 = { | |
d0f0631d | 2534 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 2535 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 2536 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2537 | }, |
2538 | }, | |
c345c8b0 | 2539 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2540 | }; |
2541 | ||
2542 | /* timer10 */ | |
35d1a66a BC |
2543 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
2544 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2545 | { .irq = -1 } |
35d1a66a BC |
2546 | }; |
2547 | ||
35d1a66a BC |
2548 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
2549 | .name = "timer10", | |
2550 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2551 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2552 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
2553 | .main_clk = "timer10_fck", |
2554 | .prcm = { | |
2555 | .omap4 = { | |
d0f0631d | 2556 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 2557 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 2558 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2559 | }, |
2560 | }, | |
c345c8b0 | 2561 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2562 | }; |
2563 | ||
2564 | /* timer11 */ | |
35d1a66a BC |
2565 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
2566 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2567 | { .irq = -1 } |
35d1a66a BC |
2568 | }; |
2569 | ||
35d1a66a BC |
2570 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
2571 | .name = "timer11", | |
2572 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2573 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2574 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
2575 | .main_clk = "timer11_fck", |
2576 | .prcm = { | |
2577 | .omap4 = { | |
d0f0631d | 2578 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 2579 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 2580 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2581 | }, |
2582 | }, | |
c345c8b0 | 2583 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2584 | }; |
2585 | ||
9780a9cf | 2586 | /* |
3b54baad BC |
2587 | * 'uart' class |
2588 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
2589 | */ |
2590 | ||
3b54baad BC |
2591 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
2592 | .rev_offs = 0x0050, | |
2593 | .sysc_offs = 0x0054, | |
2594 | .syss_offs = 0x0058, | |
2595 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
2596 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
2597 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
2598 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2599 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
2600 | .sysc_fields = &omap_hwmod_sysc_type1, |
2601 | }; | |
2602 | ||
3b54baad | 2603 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
2604 | .name = "uart", |
2605 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
2606 | }; |
2607 | ||
3b54baad | 2608 | /* uart1 */ |
3b54baad BC |
2609 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
2610 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2611 | { .irq = -1 } |
9780a9cf BC |
2612 | }; |
2613 | ||
3b54baad BC |
2614 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
2615 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
2616 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2617 | { .dma_req = -1 } |
9780a9cf BC |
2618 | }; |
2619 | ||
3b54baad BC |
2620 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
2621 | .name = "uart1", | |
2622 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2623 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 2624 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 2625 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 2626 | .main_clk = "uart1_fck", |
9780a9cf BC |
2627 | .prcm = { |
2628 | .omap4 = { | |
d0f0631d | 2629 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 2630 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 2631 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2632 | }, |
2633 | }, | |
9780a9cf BC |
2634 | }; |
2635 | ||
3b54baad | 2636 | /* uart2 */ |
3b54baad BC |
2637 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
2638 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2639 | { .irq = -1 } |
9780a9cf BC |
2640 | }; |
2641 | ||
3b54baad BC |
2642 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
2643 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
2644 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2645 | { .dma_req = -1 } |
3b54baad BC |
2646 | }; |
2647 | ||
3b54baad BC |
2648 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
2649 | .name = "uart2", | |
2650 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2651 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 2652 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 2653 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 2654 | .main_clk = "uart2_fck", |
9780a9cf BC |
2655 | .prcm = { |
2656 | .omap4 = { | |
d0f0631d | 2657 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 2658 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 2659 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2660 | }, |
2661 | }, | |
9780a9cf BC |
2662 | }; |
2663 | ||
3b54baad | 2664 | /* uart3 */ |
3b54baad BC |
2665 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
2666 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2667 | { .irq = -1 } |
9780a9cf BC |
2668 | }; |
2669 | ||
3b54baad BC |
2670 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
2671 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
2672 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2673 | { .dma_req = -1 } |
3b54baad BC |
2674 | }; |
2675 | ||
3b54baad BC |
2676 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
2677 | .name = "uart3", | |
2678 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2679 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 2680 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2681 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 2682 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 2683 | .main_clk = "uart3_fck", |
9780a9cf BC |
2684 | .prcm = { |
2685 | .omap4 = { | |
d0f0631d | 2686 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 2687 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 2688 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2689 | }, |
2690 | }, | |
9780a9cf BC |
2691 | }; |
2692 | ||
3b54baad | 2693 | /* uart4 */ |
3b54baad BC |
2694 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
2695 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2696 | { .irq = -1 } |
9780a9cf BC |
2697 | }; |
2698 | ||
3b54baad BC |
2699 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
2700 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
2701 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2702 | { .dma_req = -1 } |
3b54baad BC |
2703 | }; |
2704 | ||
3b54baad BC |
2705 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
2706 | .name = "uart4", | |
2707 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2708 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 2709 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 2710 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 2711 | .main_clk = "uart4_fck", |
9780a9cf BC |
2712 | .prcm = { |
2713 | .omap4 = { | |
d0f0631d | 2714 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 2715 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 2716 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2717 | }, |
2718 | }, | |
9780a9cf BC |
2719 | }; |
2720 | ||
5844c4ea | 2721 | /* |
844a3b63 PW |
2722 | * 'usb_host_hs' class |
2723 | * high-speed multi-port usb host controller | |
5844c4ea BC |
2724 | */ |
2725 | ||
844a3b63 PW |
2726 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
2727 | .rev_offs = 0x0000, | |
2728 | .sysc_offs = 0x0010, | |
2729 | .syss_offs = 0x0014, | |
2730 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2731 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
2732 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2733 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
2734 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
2735 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
2736 | }; |
2737 | ||
844a3b63 PW |
2738 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
2739 | .name = "usb_host_hs", | |
2740 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
2741 | }; |
2742 | ||
844a3b63 PW |
2743 | /* usb_host_hs */ |
2744 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
2745 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
2746 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2747 | { .irq = -1 } |
5844c4ea BC |
2748 | }; |
2749 | ||
844a3b63 PW |
2750 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
2751 | .name = "usb_host_hs", | |
2752 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 2753 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 2754 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
2755 | .prcm = { |
2756 | .omap4 = { | |
844a3b63 PW |
2757 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
2758 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
2759 | .modulemode = MODULEMODE_SWCTRL, | |
2760 | }, | |
2761 | }, | |
2762 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
2763 | ||
2764 | /* | |
2765 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
2766 | * id: i660 | |
2767 | * | |
2768 | * Description: | |
2769 | * In the following configuration : | |
2770 | * - USBHOST module is set to smart-idle mode | |
2771 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
2772 | * happens when the system is going to a low power mode : all ports | |
2773 | * have been suspended, the master part of the USBHOST module has | |
2774 | * entered the standby state, and SW has cut the functional clocks) | |
2775 | * - an USBHOST interrupt occurs before the module is able to answer | |
2776 | * idle_ack, typically a remote wakeup IRQ. | |
2777 | * Then the USB HOST module will enter a deadlock situation where it | |
2778 | * is no more accessible nor functional. | |
2779 | * | |
2780 | * Workaround: | |
2781 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
2782 | */ | |
2783 | ||
2784 | /* | |
2785 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
2786 | * Id: i571 | |
2787 | * | |
2788 | * Description: | |
2789 | * When the USBHOST module is set to smart-standby mode, and when it is | |
2790 | * ready to enter the standby state (i.e. all ports are suspended and | |
2791 | * all attached devices are in suspend mode), then it can wrongly assert | |
2792 | * the Mstandby signal too early while there are still some residual OCP | |
2793 | * transactions ongoing. If this condition occurs, the internal state | |
2794 | * machine may go to an undefined state and the USB link may be stuck | |
2795 | * upon the next resume. | |
2796 | * | |
2797 | * Workaround: | |
2798 | * Don't use smart standby; use only force standby, | |
2799 | * hence HWMOD_SWSUP_MSTANDBY | |
2800 | */ | |
2801 | ||
2802 | /* | |
2803 | * During system boot; If the hwmod framework resets the module | |
2804 | * the module will have smart idle settings; which can lead to deadlock | |
2805 | * (above Errata Id:i660); so, dont reset the module during boot; | |
2806 | * Use HWMOD_INIT_NO_RESET. | |
2807 | */ | |
2808 | ||
2809 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
2810 | HWMOD_INIT_NO_RESET, | |
2811 | }; | |
2812 | ||
2813 | /* | |
2814 | * 'usb_otg_hs' class | |
2815 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
2816 | */ | |
2817 | ||
2818 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
2819 | .rev_offs = 0x0400, | |
2820 | .sysc_offs = 0x0404, | |
2821 | .syss_offs = 0x0408, | |
2822 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
2823 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2824 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2825 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2826 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
2827 | MSTANDBY_SMART), | |
2828 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2829 | }; | |
2830 | ||
2831 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
2832 | .name = "usb_otg_hs", | |
2833 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
2834 | }; | |
2835 | ||
2836 | /* usb_otg_hs */ | |
2837 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
2838 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
2839 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
2840 | { .irq = -1 } | |
2841 | }; | |
2842 | ||
2843 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
2844 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
2845 | }; | |
2846 | ||
2847 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
2848 | .name = "usb_otg_hs", | |
2849 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
2850 | .clkdm_name = "l3_init_clkdm", | |
2851 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
2852 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
2853 | .main_clk = "usb_otg_hs_ick", | |
2854 | .prcm = { | |
2855 | .omap4 = { | |
2856 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
2857 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
2858 | .modulemode = MODULEMODE_HWCTRL, | |
2859 | }, | |
2860 | }, | |
2861 | .opt_clks = usb_otg_hs_opt_clks, | |
2862 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
2863 | }; | |
2864 | ||
2865 | /* | |
2866 | * 'usb_tll_hs' class | |
2867 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
2868 | */ | |
2869 | ||
2870 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
2871 | .rev_offs = 0x0000, | |
2872 | .sysc_offs = 0x0010, | |
2873 | .syss_offs = 0x0014, | |
2874 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2875 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2876 | SYSC_HAS_AUTOIDLE), | |
2877 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2878 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2879 | }; | |
2880 | ||
2881 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
2882 | .name = "usb_tll_hs", | |
2883 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
2884 | }; | |
2885 | ||
2886 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
2887 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
2888 | { .irq = -1 } | |
2889 | }; | |
2890 | ||
2891 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
2892 | .name = "usb_tll_hs", | |
2893 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
2894 | .clkdm_name = "l3_init_clkdm", | |
2895 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
2896 | .main_clk = "usb_tll_hs_ick", | |
2897 | .prcm = { | |
2898 | .omap4 = { | |
2899 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
2900 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
2901 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
2902 | }, |
2903 | }, | |
5844c4ea BC |
2904 | }; |
2905 | ||
3b54baad BC |
2906 | /* |
2907 | * 'wd_timer' class | |
2908 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
2909 | * overflow condition | |
2910 | */ | |
2911 | ||
2912 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
2913 | .rev_offs = 0x0000, | |
2914 | .sysc_offs = 0x0010, | |
2915 | .syss_offs = 0x0014, | |
2916 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 2917 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
2918 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2919 | SIDLE_SMART_WKUP), | |
3b54baad | 2920 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
2921 | }; |
2922 | ||
3b54baad BC |
2923 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
2924 | .name = "wd_timer", | |
2925 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 2926 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
2927 | }; |
2928 | ||
2929 | /* wd_timer2 */ | |
3b54baad BC |
2930 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
2931 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2932 | { .irq = -1 } |
3b54baad BC |
2933 | }; |
2934 | ||
3b54baad BC |
2935 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
2936 | .name = "wd_timer2", | |
2937 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 2938 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 2939 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 2940 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
2941 | .prcm = { |
2942 | .omap4 = { | |
d0f0631d | 2943 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 2944 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 2945 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2946 | }, |
2947 | }, | |
9780a9cf BC |
2948 | }; |
2949 | ||
3b54baad | 2950 | /* wd_timer3 */ |
3b54baad BC |
2951 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
2952 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2953 | { .irq = -1 } |
9780a9cf BC |
2954 | }; |
2955 | ||
3b54baad BC |
2956 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
2957 | .name = "wd_timer3", | |
2958 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 2959 | .clkdm_name = "abe_clkdm", |
3b54baad | 2960 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 2961 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
2962 | .prcm = { |
2963 | .omap4 = { | |
d0f0631d | 2964 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 2965 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 2966 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2967 | }, |
2968 | }, | |
9780a9cf | 2969 | }; |
531ce0d5 | 2970 | |
844a3b63 | 2971 | |
af88fa9a | 2972 | /* |
844a3b63 | 2973 | * interfaces |
af88fa9a | 2974 | */ |
af88fa9a | 2975 | |
844a3b63 PW |
2976 | /* l3_main_1 -> dmm */ |
2977 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
2978 | .master = &omap44xx_l3_main_1_hwmod, | |
2979 | .slave = &omap44xx_dmm_hwmod, | |
2980 | .clk = "l3_div_ck", | |
2981 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
2982 | }; |
2983 | ||
844a3b63 | 2984 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 2985 | { |
844a3b63 PW |
2986 | .pa_start = 0x4e000000, |
2987 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
2988 | .flags = ADDR_TYPE_RT |
2989 | }, | |
844a3b63 | 2990 | { } |
af88fa9a BC |
2991 | }; |
2992 | ||
844a3b63 PW |
2993 | /* mpu -> dmm */ |
2994 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
2995 | .master = &omap44xx_mpu_hwmod, | |
2996 | .slave = &omap44xx_dmm_hwmod, | |
2997 | .clk = "l3_div_ck", | |
2998 | .addr = omap44xx_dmm_addrs, | |
2999 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3000 | }; |
3001 | ||
844a3b63 PW |
3002 | /* dmm -> emif_fw */ |
3003 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3004 | .master = &omap44xx_dmm_hwmod, | |
3005 | .slave = &omap44xx_emif_fw_hwmod, | |
3006 | .clk = "l3_div_ck", | |
3007 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3008 | }; | |
3009 | ||
3010 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3011 | { | |
3012 | .pa_start = 0x4a20c000, | |
3013 | .pa_end = 0x4a20c0ff, | |
3014 | .flags = ADDR_TYPE_RT | |
3015 | }, | |
3016 | { } | |
3017 | }; | |
3018 | ||
3019 | /* l4_cfg -> emif_fw */ | |
3020 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3021 | .master = &omap44xx_l4_cfg_hwmod, | |
3022 | .slave = &omap44xx_emif_fw_hwmod, | |
3023 | .clk = "l4_div_ck", | |
3024 | .addr = omap44xx_emif_fw_addrs, | |
3025 | .user = OCP_USER_MPU, | |
3026 | }; | |
3027 | ||
3028 | /* iva -> l3_instr */ | |
3029 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3030 | .master = &omap44xx_iva_hwmod, | |
3031 | .slave = &omap44xx_l3_instr_hwmod, | |
3032 | .clk = "l3_div_ck", | |
3033 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3034 | }; | |
3035 | ||
3036 | /* l3_main_3 -> l3_instr */ | |
3037 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3038 | .master = &omap44xx_l3_main_3_hwmod, | |
3039 | .slave = &omap44xx_l3_instr_hwmod, | |
3040 | .clk = "l3_div_ck", | |
3041 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3042 | }; | |
3043 | ||
3044 | /* dsp -> l3_main_1 */ | |
3045 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3046 | .master = &omap44xx_dsp_hwmod, | |
3047 | .slave = &omap44xx_l3_main_1_hwmod, | |
3048 | .clk = "l3_div_ck", | |
3049 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3050 | }; | |
3051 | ||
3052 | /* dss -> l3_main_1 */ | |
3053 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3054 | .master = &omap44xx_dss_hwmod, | |
3055 | .slave = &omap44xx_l3_main_1_hwmod, | |
3056 | .clk = "l3_div_ck", | |
3057 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3058 | }; | |
3059 | ||
3060 | /* l3_main_2 -> l3_main_1 */ | |
3061 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3062 | .master = &omap44xx_l3_main_2_hwmod, | |
3063 | .slave = &omap44xx_l3_main_1_hwmod, | |
3064 | .clk = "l3_div_ck", | |
3065 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3066 | }; | |
3067 | ||
3068 | /* l4_cfg -> l3_main_1 */ | |
3069 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3070 | .master = &omap44xx_l4_cfg_hwmod, | |
3071 | .slave = &omap44xx_l3_main_1_hwmod, | |
3072 | .clk = "l4_div_ck", | |
3073 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3074 | }; | |
3075 | ||
3076 | /* mmc1 -> l3_main_1 */ | |
3077 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3078 | .master = &omap44xx_mmc1_hwmod, | |
3079 | .slave = &omap44xx_l3_main_1_hwmod, | |
3080 | .clk = "l3_div_ck", | |
3081 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3082 | }; | |
3083 | ||
3084 | /* mmc2 -> l3_main_1 */ | |
3085 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3086 | .master = &omap44xx_mmc2_hwmod, | |
3087 | .slave = &omap44xx_l3_main_1_hwmod, | |
3088 | .clk = "l3_div_ck", | |
3089 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3090 | }; | |
3091 | ||
3092 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3093 | { | |
3094 | .pa_start = 0x44000000, | |
3095 | .pa_end = 0x44000fff, | |
3096 | .flags = ADDR_TYPE_RT | |
3097 | }, | |
3098 | { } | |
3099 | }; | |
3100 | ||
3101 | /* mpu -> l3_main_1 */ | |
3102 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3103 | .master = &omap44xx_mpu_hwmod, | |
3104 | .slave = &omap44xx_l3_main_1_hwmod, | |
3105 | .clk = "l3_div_ck", | |
3106 | .addr = omap44xx_l3_main_1_addrs, | |
3107 | .user = OCP_USER_MPU, | |
3108 | }; | |
3109 | ||
3110 | /* dma_system -> l3_main_2 */ | |
3111 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3112 | .master = &omap44xx_dma_system_hwmod, | |
3113 | .slave = &omap44xx_l3_main_2_hwmod, | |
3114 | .clk = "l3_div_ck", | |
3115 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3116 | }; | |
3117 | ||
b050f688 ML |
3118 | /* fdif -> l3_main_2 */ |
3119 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3120 | .master = &omap44xx_fdif_hwmod, | |
3121 | .slave = &omap44xx_l3_main_2_hwmod, | |
3122 | .clk = "l3_div_ck", | |
3123 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3124 | }; | |
3125 | ||
844a3b63 PW |
3126 | /* hsi -> l3_main_2 */ |
3127 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3128 | .master = &omap44xx_hsi_hwmod, | |
3129 | .slave = &omap44xx_l3_main_2_hwmod, | |
3130 | .clk = "l3_div_ck", | |
3131 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3132 | }; | |
3133 | ||
3134 | /* ipu -> l3_main_2 */ | |
3135 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3136 | .master = &omap44xx_ipu_hwmod, | |
3137 | .slave = &omap44xx_l3_main_2_hwmod, | |
3138 | .clk = "l3_div_ck", | |
3139 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3140 | }; | |
3141 | ||
3142 | /* iss -> l3_main_2 */ | |
3143 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3144 | .master = &omap44xx_iss_hwmod, | |
3145 | .slave = &omap44xx_l3_main_2_hwmod, | |
3146 | .clk = "l3_div_ck", | |
3147 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3148 | }; | |
3149 | ||
3150 | /* iva -> l3_main_2 */ | |
3151 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3152 | .master = &omap44xx_iva_hwmod, | |
3153 | .slave = &omap44xx_l3_main_2_hwmod, | |
3154 | .clk = "l3_div_ck", | |
3155 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3156 | }; | |
3157 | ||
3158 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
3159 | { | |
3160 | .pa_start = 0x44800000, | |
3161 | .pa_end = 0x44801fff, | |
3162 | .flags = ADDR_TYPE_RT | |
3163 | }, | |
3164 | { } | |
3165 | }; | |
3166 | ||
3167 | /* l3_main_1 -> l3_main_2 */ | |
3168 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3169 | .master = &omap44xx_l3_main_1_hwmod, | |
3170 | .slave = &omap44xx_l3_main_2_hwmod, | |
3171 | .clk = "l3_div_ck", | |
3172 | .addr = omap44xx_l3_main_2_addrs, | |
3173 | .user = OCP_USER_MPU, | |
3174 | }; | |
3175 | ||
3176 | /* l4_cfg -> l3_main_2 */ | |
3177 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3178 | .master = &omap44xx_l4_cfg_hwmod, | |
3179 | .slave = &omap44xx_l3_main_2_hwmod, | |
3180 | .clk = "l4_div_ck", | |
3181 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3182 | }; | |
3183 | ||
3184 | /* usb_host_hs -> l3_main_2 */ | |
3185 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3186 | .master = &omap44xx_usb_host_hs_hwmod, | |
3187 | .slave = &omap44xx_l3_main_2_hwmod, | |
3188 | .clk = "l3_div_ck", | |
3189 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3190 | }; | |
3191 | ||
3192 | /* usb_otg_hs -> l3_main_2 */ | |
3193 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3194 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3195 | .slave = &omap44xx_l3_main_2_hwmod, | |
3196 | .clk = "l3_div_ck", | |
3197 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3198 | }; | |
3199 | ||
3200 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
3201 | { | |
3202 | .pa_start = 0x45000000, | |
3203 | .pa_end = 0x45000fff, | |
3204 | .flags = ADDR_TYPE_RT | |
3205 | }, | |
3206 | { } | |
3207 | }; | |
3208 | ||
3209 | /* l3_main_1 -> l3_main_3 */ | |
3210 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3211 | .master = &omap44xx_l3_main_1_hwmod, | |
3212 | .slave = &omap44xx_l3_main_3_hwmod, | |
3213 | .clk = "l3_div_ck", | |
3214 | .addr = omap44xx_l3_main_3_addrs, | |
3215 | .user = OCP_USER_MPU, | |
3216 | }; | |
3217 | ||
3218 | /* l3_main_2 -> l3_main_3 */ | |
3219 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3220 | .master = &omap44xx_l3_main_2_hwmod, | |
3221 | .slave = &omap44xx_l3_main_3_hwmod, | |
3222 | .clk = "l3_div_ck", | |
3223 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3224 | }; | |
3225 | ||
3226 | /* l4_cfg -> l3_main_3 */ | |
3227 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3228 | .master = &omap44xx_l4_cfg_hwmod, | |
3229 | .slave = &omap44xx_l3_main_3_hwmod, | |
3230 | .clk = "l4_div_ck", | |
3231 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3232 | }; | |
3233 | ||
3234 | /* aess -> l4_abe */ | |
3235 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { | |
3236 | .master = &omap44xx_aess_hwmod, | |
3237 | .slave = &omap44xx_l4_abe_hwmod, | |
3238 | .clk = "ocp_abe_iclk", | |
3239 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3240 | }; | |
3241 | ||
3242 | /* dsp -> l4_abe */ | |
3243 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3244 | .master = &omap44xx_dsp_hwmod, | |
3245 | .slave = &omap44xx_l4_abe_hwmod, | |
3246 | .clk = "ocp_abe_iclk", | |
3247 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3248 | }; | |
3249 | ||
3250 | /* l3_main_1 -> l4_abe */ | |
3251 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3252 | .master = &omap44xx_l3_main_1_hwmod, | |
3253 | .slave = &omap44xx_l4_abe_hwmod, | |
3254 | .clk = "l3_div_ck", | |
3255 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3256 | }; | |
3257 | ||
3258 | /* mpu -> l4_abe */ | |
3259 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3260 | .master = &omap44xx_mpu_hwmod, | |
3261 | .slave = &omap44xx_l4_abe_hwmod, | |
3262 | .clk = "ocp_abe_iclk", | |
3263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3264 | }; | |
3265 | ||
3266 | /* l3_main_1 -> l4_cfg */ | |
3267 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3268 | .master = &omap44xx_l3_main_1_hwmod, | |
3269 | .slave = &omap44xx_l4_cfg_hwmod, | |
3270 | .clk = "l3_div_ck", | |
3271 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3272 | }; | |
3273 | ||
3274 | /* l3_main_2 -> l4_per */ | |
3275 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3276 | .master = &omap44xx_l3_main_2_hwmod, | |
3277 | .slave = &omap44xx_l4_per_hwmod, | |
3278 | .clk = "l3_div_ck", | |
3279 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3280 | }; | |
3281 | ||
3282 | /* l4_cfg -> l4_wkup */ | |
3283 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3284 | .master = &omap44xx_l4_cfg_hwmod, | |
3285 | .slave = &omap44xx_l4_wkup_hwmod, | |
3286 | .clk = "l4_div_ck", | |
3287 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3288 | }; | |
3289 | ||
3290 | /* mpu -> mpu_private */ | |
3291 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3292 | .master = &omap44xx_mpu_hwmod, | |
3293 | .slave = &omap44xx_mpu_private_hwmod, | |
3294 | .clk = "l3_div_ck", | |
3295 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3296 | }; | |
3297 | ||
3298 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { | |
3299 | { | |
3300 | .pa_start = 0x401f1000, | |
3301 | .pa_end = 0x401f13ff, | |
3302 | .flags = ADDR_TYPE_RT | |
3303 | }, | |
3304 | { } | |
3305 | }; | |
3306 | ||
3307 | /* l4_abe -> aess */ | |
3308 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { | |
3309 | .master = &omap44xx_l4_abe_hwmod, | |
3310 | .slave = &omap44xx_aess_hwmod, | |
3311 | .clk = "ocp_abe_iclk", | |
3312 | .addr = omap44xx_aess_addrs, | |
3313 | .user = OCP_USER_MPU, | |
3314 | }; | |
3315 | ||
3316 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
3317 | { | |
3318 | .pa_start = 0x490f1000, | |
3319 | .pa_end = 0x490f13ff, | |
3320 | .flags = ADDR_TYPE_RT | |
3321 | }, | |
3322 | { } | |
3323 | }; | |
3324 | ||
3325 | /* l4_abe -> aess (dma) */ | |
3326 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { | |
3327 | .master = &omap44xx_l4_abe_hwmod, | |
3328 | .slave = &omap44xx_aess_hwmod, | |
3329 | .clk = "ocp_abe_iclk", | |
3330 | .addr = omap44xx_aess_dma_addrs, | |
3331 | .user = OCP_USER_SDMA, | |
3332 | }; | |
3333 | ||
3334 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { | |
3335 | { | |
3336 | .pa_start = 0x4a304000, | |
3337 | .pa_end = 0x4a30401f, | |
3338 | .flags = ADDR_TYPE_RT | |
3339 | }, | |
3340 | { } | |
3341 | }; | |
3342 | ||
3343 | /* l4_wkup -> counter_32k */ | |
3344 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
3345 | .master = &omap44xx_l4_wkup_hwmod, | |
3346 | .slave = &omap44xx_counter_32k_hwmod, | |
3347 | .clk = "l4_wkup_clk_mux_ck", | |
3348 | .addr = omap44xx_counter_32k_addrs, | |
3349 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3350 | }; | |
3351 | ||
3352 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
3353 | { | |
3354 | .pa_start = 0x4a056000, | |
3355 | .pa_end = 0x4a056fff, | |
3356 | .flags = ADDR_TYPE_RT | |
3357 | }, | |
3358 | { } | |
3359 | }; | |
3360 | ||
3361 | /* l4_cfg -> dma_system */ | |
3362 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
3363 | .master = &omap44xx_l4_cfg_hwmod, | |
3364 | .slave = &omap44xx_dma_system_hwmod, | |
3365 | .clk = "l4_div_ck", | |
3366 | .addr = omap44xx_dma_system_addrs, | |
3367 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3368 | }; | |
3369 | ||
3370 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
3371 | { | |
3372 | .name = "mpu", | |
3373 | .pa_start = 0x4012e000, | |
3374 | .pa_end = 0x4012e07f, | |
3375 | .flags = ADDR_TYPE_RT | |
3376 | }, | |
3377 | { } | |
3378 | }; | |
3379 | ||
3380 | /* l4_abe -> dmic */ | |
3381 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
3382 | .master = &omap44xx_l4_abe_hwmod, | |
3383 | .slave = &omap44xx_dmic_hwmod, | |
3384 | .clk = "ocp_abe_iclk", | |
3385 | .addr = omap44xx_dmic_addrs, | |
3386 | .user = OCP_USER_MPU, | |
3387 | }; | |
3388 | ||
3389 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
3390 | { | |
3391 | .name = "dma", | |
3392 | .pa_start = 0x4902e000, | |
3393 | .pa_end = 0x4902e07f, | |
3394 | .flags = ADDR_TYPE_RT | |
3395 | }, | |
3396 | { } | |
3397 | }; | |
3398 | ||
3399 | /* l4_abe -> dmic (dma) */ | |
3400 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
3401 | .master = &omap44xx_l4_abe_hwmod, | |
3402 | .slave = &omap44xx_dmic_hwmod, | |
3403 | .clk = "ocp_abe_iclk", | |
3404 | .addr = omap44xx_dmic_dma_addrs, | |
3405 | .user = OCP_USER_SDMA, | |
3406 | }; | |
3407 | ||
3408 | /* dsp -> iva */ | |
3409 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
3410 | .master = &omap44xx_dsp_hwmod, | |
3411 | .slave = &omap44xx_iva_hwmod, | |
3412 | .clk = "dpll_iva_m5x2_ck", | |
3413 | .user = OCP_USER_DSP, | |
3414 | }; | |
3415 | ||
3416 | /* l4_cfg -> dsp */ | |
3417 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
3418 | .master = &omap44xx_l4_cfg_hwmod, | |
3419 | .slave = &omap44xx_dsp_hwmod, | |
3420 | .clk = "l4_div_ck", | |
3421 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3422 | }; | |
3423 | ||
3424 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
3425 | { | |
3426 | .pa_start = 0x58000000, | |
3427 | .pa_end = 0x5800007f, | |
3428 | .flags = ADDR_TYPE_RT | |
3429 | }, | |
3430 | { } | |
3431 | }; | |
3432 | ||
3433 | /* l3_main_2 -> dss */ | |
3434 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
3435 | .master = &omap44xx_l3_main_2_hwmod, | |
3436 | .slave = &omap44xx_dss_hwmod, | |
3437 | .clk = "dss_fck", | |
3438 | .addr = omap44xx_dss_dma_addrs, | |
3439 | .user = OCP_USER_SDMA, | |
3440 | }; | |
3441 | ||
3442 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
3443 | { | |
3444 | .pa_start = 0x48040000, | |
3445 | .pa_end = 0x4804007f, | |
3446 | .flags = ADDR_TYPE_RT | |
3447 | }, | |
3448 | { } | |
3449 | }; | |
3450 | ||
3451 | /* l4_per -> dss */ | |
3452 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
3453 | .master = &omap44xx_l4_per_hwmod, | |
3454 | .slave = &omap44xx_dss_hwmod, | |
3455 | .clk = "l4_div_ck", | |
3456 | .addr = omap44xx_dss_addrs, | |
3457 | .user = OCP_USER_MPU, | |
3458 | }; | |
3459 | ||
3460 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
3461 | { | |
3462 | .pa_start = 0x58001000, | |
3463 | .pa_end = 0x58001fff, | |
3464 | .flags = ADDR_TYPE_RT | |
3465 | }, | |
3466 | { } | |
3467 | }; | |
3468 | ||
3469 | /* l3_main_2 -> dss_dispc */ | |
3470 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
3471 | .master = &omap44xx_l3_main_2_hwmod, | |
3472 | .slave = &omap44xx_dss_dispc_hwmod, | |
3473 | .clk = "dss_fck", | |
3474 | .addr = omap44xx_dss_dispc_dma_addrs, | |
3475 | .user = OCP_USER_SDMA, | |
3476 | }; | |
3477 | ||
3478 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
3479 | { | |
3480 | .pa_start = 0x48041000, | |
3481 | .pa_end = 0x48041fff, | |
3482 | .flags = ADDR_TYPE_RT | |
3483 | }, | |
3484 | { } | |
3485 | }; | |
3486 | ||
3487 | /* l4_per -> dss_dispc */ | |
3488 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
3489 | .master = &omap44xx_l4_per_hwmod, | |
3490 | .slave = &omap44xx_dss_dispc_hwmod, | |
3491 | .clk = "l4_div_ck", | |
3492 | .addr = omap44xx_dss_dispc_addrs, | |
3493 | .user = OCP_USER_MPU, | |
3494 | }; | |
3495 | ||
3496 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
3497 | { | |
3498 | .pa_start = 0x58004000, | |
3499 | .pa_end = 0x580041ff, | |
3500 | .flags = ADDR_TYPE_RT | |
3501 | }, | |
3502 | { } | |
3503 | }; | |
3504 | ||
3505 | /* l3_main_2 -> dss_dsi1 */ | |
3506 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
3507 | .master = &omap44xx_l3_main_2_hwmod, | |
3508 | .slave = &omap44xx_dss_dsi1_hwmod, | |
3509 | .clk = "dss_fck", | |
3510 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
3511 | .user = OCP_USER_SDMA, | |
3512 | }; | |
3513 | ||
3514 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
3515 | { | |
3516 | .pa_start = 0x48044000, | |
3517 | .pa_end = 0x480441ff, | |
3518 | .flags = ADDR_TYPE_RT | |
3519 | }, | |
3520 | { } | |
3521 | }; | |
3522 | ||
3523 | /* l4_per -> dss_dsi1 */ | |
3524 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
3525 | .master = &omap44xx_l4_per_hwmod, | |
3526 | .slave = &omap44xx_dss_dsi1_hwmod, | |
3527 | .clk = "l4_div_ck", | |
3528 | .addr = omap44xx_dss_dsi1_addrs, | |
3529 | .user = OCP_USER_MPU, | |
3530 | }; | |
3531 | ||
3532 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
3533 | { | |
3534 | .pa_start = 0x58005000, | |
3535 | .pa_end = 0x580051ff, | |
3536 | .flags = ADDR_TYPE_RT | |
3537 | }, | |
3538 | { } | |
3539 | }; | |
3540 | ||
3541 | /* l3_main_2 -> dss_dsi2 */ | |
3542 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
3543 | .master = &omap44xx_l3_main_2_hwmod, | |
3544 | .slave = &omap44xx_dss_dsi2_hwmod, | |
3545 | .clk = "dss_fck", | |
3546 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
3547 | .user = OCP_USER_SDMA, | |
3548 | }; | |
3549 | ||
3550 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
3551 | { | |
3552 | .pa_start = 0x48045000, | |
3553 | .pa_end = 0x480451ff, | |
3554 | .flags = ADDR_TYPE_RT | |
3555 | }, | |
3556 | { } | |
3557 | }; | |
3558 | ||
3559 | /* l4_per -> dss_dsi2 */ | |
3560 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
3561 | .master = &omap44xx_l4_per_hwmod, | |
3562 | .slave = &omap44xx_dss_dsi2_hwmod, | |
3563 | .clk = "l4_div_ck", | |
3564 | .addr = omap44xx_dss_dsi2_addrs, | |
3565 | .user = OCP_USER_MPU, | |
3566 | }; | |
3567 | ||
3568 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
3569 | { | |
3570 | .pa_start = 0x58006000, | |
3571 | .pa_end = 0x58006fff, | |
3572 | .flags = ADDR_TYPE_RT | |
3573 | }, | |
3574 | { } | |
3575 | }; | |
3576 | ||
3577 | /* l3_main_2 -> dss_hdmi */ | |
3578 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
3579 | .master = &omap44xx_l3_main_2_hwmod, | |
3580 | .slave = &omap44xx_dss_hdmi_hwmod, | |
3581 | .clk = "dss_fck", | |
3582 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
3583 | .user = OCP_USER_SDMA, | |
3584 | }; | |
3585 | ||
3586 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
3587 | { | |
3588 | .pa_start = 0x48046000, | |
3589 | .pa_end = 0x48046fff, | |
3590 | .flags = ADDR_TYPE_RT | |
3591 | }, | |
3592 | { } | |
3593 | }; | |
3594 | ||
3595 | /* l4_per -> dss_hdmi */ | |
3596 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
3597 | .master = &omap44xx_l4_per_hwmod, | |
3598 | .slave = &omap44xx_dss_hdmi_hwmod, | |
3599 | .clk = "l4_div_ck", | |
3600 | .addr = omap44xx_dss_hdmi_addrs, | |
3601 | .user = OCP_USER_MPU, | |
3602 | }; | |
3603 | ||
3604 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
3605 | { | |
3606 | .pa_start = 0x58002000, | |
3607 | .pa_end = 0x580020ff, | |
3608 | .flags = ADDR_TYPE_RT | |
3609 | }, | |
3610 | { } | |
3611 | }; | |
3612 | ||
3613 | /* l3_main_2 -> dss_rfbi */ | |
3614 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
3615 | .master = &omap44xx_l3_main_2_hwmod, | |
3616 | .slave = &omap44xx_dss_rfbi_hwmod, | |
3617 | .clk = "dss_fck", | |
3618 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
3619 | .user = OCP_USER_SDMA, | |
3620 | }; | |
3621 | ||
3622 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
3623 | { | |
3624 | .pa_start = 0x48042000, | |
3625 | .pa_end = 0x480420ff, | |
3626 | .flags = ADDR_TYPE_RT | |
3627 | }, | |
3628 | { } | |
3629 | }; | |
3630 | ||
3631 | /* l4_per -> dss_rfbi */ | |
3632 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
3633 | .master = &omap44xx_l4_per_hwmod, | |
3634 | .slave = &omap44xx_dss_rfbi_hwmod, | |
3635 | .clk = "l4_div_ck", | |
3636 | .addr = omap44xx_dss_rfbi_addrs, | |
3637 | .user = OCP_USER_MPU, | |
3638 | }; | |
3639 | ||
3640 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
3641 | { | |
3642 | .pa_start = 0x58003000, | |
3643 | .pa_end = 0x580030ff, | |
3644 | .flags = ADDR_TYPE_RT | |
3645 | }, | |
3646 | { } | |
3647 | }; | |
3648 | ||
3649 | /* l3_main_2 -> dss_venc */ | |
3650 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
3651 | .master = &omap44xx_l3_main_2_hwmod, | |
3652 | .slave = &omap44xx_dss_venc_hwmod, | |
3653 | .clk = "dss_fck", | |
3654 | .addr = omap44xx_dss_venc_dma_addrs, | |
3655 | .user = OCP_USER_SDMA, | |
3656 | }; | |
3657 | ||
3658 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
3659 | { | |
3660 | .pa_start = 0x48043000, | |
3661 | .pa_end = 0x480430ff, | |
3662 | .flags = ADDR_TYPE_RT | |
3663 | }, | |
3664 | { } | |
3665 | }; | |
3666 | ||
3667 | /* l4_per -> dss_venc */ | |
3668 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
3669 | .master = &omap44xx_l4_per_hwmod, | |
3670 | .slave = &omap44xx_dss_venc_hwmod, | |
3671 | .clk = "l4_div_ck", | |
3672 | .addr = omap44xx_dss_venc_addrs, | |
3673 | .user = OCP_USER_MPU, | |
3674 | }; | |
3675 | ||
b050f688 ML |
3676 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
3677 | { | |
3678 | .pa_start = 0x4a10a000, | |
3679 | .pa_end = 0x4a10a1ff, | |
3680 | .flags = ADDR_TYPE_RT | |
3681 | }, | |
3682 | { } | |
3683 | }; | |
3684 | ||
3685 | /* l4_cfg -> fdif */ | |
3686 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
3687 | .master = &omap44xx_l4_cfg_hwmod, | |
3688 | .slave = &omap44xx_fdif_hwmod, | |
3689 | .clk = "l4_div_ck", | |
3690 | .addr = omap44xx_fdif_addrs, | |
3691 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3692 | }; | |
3693 | ||
844a3b63 PW |
3694 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
3695 | { | |
3696 | .pa_start = 0x4a310000, | |
3697 | .pa_end = 0x4a3101ff, | |
3698 | .flags = ADDR_TYPE_RT | |
3699 | }, | |
3700 | { } | |
3701 | }; | |
3702 | ||
3703 | /* l4_wkup -> gpio1 */ | |
3704 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
3705 | .master = &omap44xx_l4_wkup_hwmod, | |
3706 | .slave = &omap44xx_gpio1_hwmod, | |
3707 | .clk = "l4_wkup_clk_mux_ck", | |
3708 | .addr = omap44xx_gpio1_addrs, | |
3709 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3710 | }; | |
3711 | ||
3712 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
3713 | { | |
3714 | .pa_start = 0x48055000, | |
3715 | .pa_end = 0x480551ff, | |
3716 | .flags = ADDR_TYPE_RT | |
3717 | }, | |
3718 | { } | |
3719 | }; | |
3720 | ||
3721 | /* l4_per -> gpio2 */ | |
3722 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
3723 | .master = &omap44xx_l4_per_hwmod, | |
3724 | .slave = &omap44xx_gpio2_hwmod, | |
3725 | .clk = "l4_div_ck", | |
3726 | .addr = omap44xx_gpio2_addrs, | |
3727 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3728 | }; | |
3729 | ||
3730 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
3731 | { | |
3732 | .pa_start = 0x48057000, | |
3733 | .pa_end = 0x480571ff, | |
3734 | .flags = ADDR_TYPE_RT | |
3735 | }, | |
3736 | { } | |
3737 | }; | |
3738 | ||
3739 | /* l4_per -> gpio3 */ | |
3740 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
3741 | .master = &omap44xx_l4_per_hwmod, | |
3742 | .slave = &omap44xx_gpio3_hwmod, | |
3743 | .clk = "l4_div_ck", | |
3744 | .addr = omap44xx_gpio3_addrs, | |
3745 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3746 | }; | |
3747 | ||
3748 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
3749 | { | |
3750 | .pa_start = 0x48059000, | |
3751 | .pa_end = 0x480591ff, | |
3752 | .flags = ADDR_TYPE_RT | |
3753 | }, | |
3754 | { } | |
3755 | }; | |
3756 | ||
3757 | /* l4_per -> gpio4 */ | |
3758 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
3759 | .master = &omap44xx_l4_per_hwmod, | |
3760 | .slave = &omap44xx_gpio4_hwmod, | |
3761 | .clk = "l4_div_ck", | |
3762 | .addr = omap44xx_gpio4_addrs, | |
3763 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3764 | }; | |
3765 | ||
3766 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
3767 | { | |
3768 | .pa_start = 0x4805b000, | |
3769 | .pa_end = 0x4805b1ff, | |
3770 | .flags = ADDR_TYPE_RT | |
3771 | }, | |
3772 | { } | |
3773 | }; | |
3774 | ||
3775 | /* l4_per -> gpio5 */ | |
3776 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
3777 | .master = &omap44xx_l4_per_hwmod, | |
3778 | .slave = &omap44xx_gpio5_hwmod, | |
3779 | .clk = "l4_div_ck", | |
3780 | .addr = omap44xx_gpio5_addrs, | |
3781 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3782 | }; | |
3783 | ||
3784 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
3785 | { | |
3786 | .pa_start = 0x4805d000, | |
3787 | .pa_end = 0x4805d1ff, | |
3788 | .flags = ADDR_TYPE_RT | |
3789 | }, | |
3790 | { } | |
3791 | }; | |
3792 | ||
3793 | /* l4_per -> gpio6 */ | |
3794 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
3795 | .master = &omap44xx_l4_per_hwmod, | |
3796 | .slave = &omap44xx_gpio6_hwmod, | |
3797 | .clk = "l4_div_ck", | |
3798 | .addr = omap44xx_gpio6_addrs, | |
3799 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3800 | }; | |
3801 | ||
eb42b5d3 BC |
3802 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
3803 | { | |
3804 | .pa_start = 0x50000000, | |
3805 | .pa_end = 0x500003ff, | |
3806 | .flags = ADDR_TYPE_RT | |
3807 | }, | |
3808 | { } | |
3809 | }; | |
3810 | ||
3811 | /* l3_main_2 -> gpmc */ | |
3812 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
3813 | .master = &omap44xx_l3_main_2_hwmod, | |
3814 | .slave = &omap44xx_gpmc_hwmod, | |
3815 | .clk = "l3_div_ck", | |
3816 | .addr = omap44xx_gpmc_addrs, | |
3817 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3818 | }; | |
3819 | ||
a091c08e PW |
3820 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
3821 | { | |
3822 | .pa_start = 0x480b2000, | |
3823 | .pa_end = 0x480b201f, | |
3824 | .flags = ADDR_TYPE_RT | |
3825 | }, | |
3826 | { } | |
3827 | }; | |
3828 | ||
3829 | /* l4_per -> hdq1w */ | |
3830 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
3831 | .master = &omap44xx_l4_per_hwmod, | |
3832 | .slave = &omap44xx_hdq1w_hwmod, | |
3833 | .clk = "l4_div_ck", | |
3834 | .addr = omap44xx_hdq1w_addrs, | |
3835 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3836 | }; | |
3837 | ||
844a3b63 PW |
3838 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
3839 | { | |
3840 | .pa_start = 0x4a058000, | |
3841 | .pa_end = 0x4a05bfff, | |
3842 | .flags = ADDR_TYPE_RT | |
3843 | }, | |
3844 | { } | |
3845 | }; | |
3846 | ||
3847 | /* l4_cfg -> hsi */ | |
3848 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
3849 | .master = &omap44xx_l4_cfg_hwmod, | |
3850 | .slave = &omap44xx_hsi_hwmod, | |
3851 | .clk = "l4_div_ck", | |
3852 | .addr = omap44xx_hsi_addrs, | |
3853 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3854 | }; | |
3855 | ||
3856 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
3857 | { | |
3858 | .pa_start = 0x48070000, | |
3859 | .pa_end = 0x480700ff, | |
3860 | .flags = ADDR_TYPE_RT | |
3861 | }, | |
3862 | { } | |
3863 | }; | |
3864 | ||
3865 | /* l4_per -> i2c1 */ | |
3866 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
3867 | .master = &omap44xx_l4_per_hwmod, | |
3868 | .slave = &omap44xx_i2c1_hwmod, | |
3869 | .clk = "l4_div_ck", | |
3870 | .addr = omap44xx_i2c1_addrs, | |
3871 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3872 | }; | |
3873 | ||
3874 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
3875 | { | |
3876 | .pa_start = 0x48072000, | |
3877 | .pa_end = 0x480720ff, | |
3878 | .flags = ADDR_TYPE_RT | |
3879 | }, | |
3880 | { } | |
3881 | }; | |
3882 | ||
3883 | /* l4_per -> i2c2 */ | |
3884 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
3885 | .master = &omap44xx_l4_per_hwmod, | |
3886 | .slave = &omap44xx_i2c2_hwmod, | |
3887 | .clk = "l4_div_ck", | |
3888 | .addr = omap44xx_i2c2_addrs, | |
3889 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3890 | }; | |
3891 | ||
3892 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
3893 | { | |
3894 | .pa_start = 0x48060000, | |
3895 | .pa_end = 0x480600ff, | |
3896 | .flags = ADDR_TYPE_RT | |
3897 | }, | |
3898 | { } | |
3899 | }; | |
3900 | ||
3901 | /* l4_per -> i2c3 */ | |
3902 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
3903 | .master = &omap44xx_l4_per_hwmod, | |
3904 | .slave = &omap44xx_i2c3_hwmod, | |
3905 | .clk = "l4_div_ck", | |
3906 | .addr = omap44xx_i2c3_addrs, | |
3907 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3908 | }; | |
3909 | ||
3910 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
3911 | { | |
3912 | .pa_start = 0x48350000, | |
3913 | .pa_end = 0x483500ff, | |
3914 | .flags = ADDR_TYPE_RT | |
3915 | }, | |
3916 | { } | |
3917 | }; | |
3918 | ||
3919 | /* l4_per -> i2c4 */ | |
3920 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
3921 | .master = &omap44xx_l4_per_hwmod, | |
3922 | .slave = &omap44xx_i2c4_hwmod, | |
3923 | .clk = "l4_div_ck", | |
3924 | .addr = omap44xx_i2c4_addrs, | |
3925 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3926 | }; | |
3927 | ||
3928 | /* l3_main_2 -> ipu */ | |
3929 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
3930 | .master = &omap44xx_l3_main_2_hwmod, | |
3931 | .slave = &omap44xx_ipu_hwmod, | |
3932 | .clk = "l3_div_ck", | |
3933 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3934 | }; | |
3935 | ||
3936 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
3937 | { | |
3938 | .pa_start = 0x52000000, | |
3939 | .pa_end = 0x520000ff, | |
3940 | .flags = ADDR_TYPE_RT | |
3941 | }, | |
3942 | { } | |
3943 | }; | |
3944 | ||
3945 | /* l3_main_2 -> iss */ | |
3946 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
3947 | .master = &omap44xx_l3_main_2_hwmod, | |
3948 | .slave = &omap44xx_iss_hwmod, | |
3949 | .clk = "l3_div_ck", | |
3950 | .addr = omap44xx_iss_addrs, | |
3951 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3952 | }; | |
3953 | ||
3954 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { | |
3955 | { | |
3956 | .pa_start = 0x5a000000, | |
3957 | .pa_end = 0x5a07ffff, | |
3958 | .flags = ADDR_TYPE_RT | |
3959 | }, | |
3960 | { } | |
3961 | }; | |
3962 | ||
3963 | /* l3_main_2 -> iva */ | |
3964 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
3965 | .master = &omap44xx_l3_main_2_hwmod, | |
3966 | .slave = &omap44xx_iva_hwmod, | |
3967 | .clk = "l3_div_ck", | |
3968 | .addr = omap44xx_iva_addrs, | |
3969 | .user = OCP_USER_MPU, | |
3970 | }; | |
3971 | ||
3972 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
3973 | { | |
3974 | .pa_start = 0x4a31c000, | |
3975 | .pa_end = 0x4a31c07f, | |
3976 | .flags = ADDR_TYPE_RT | |
3977 | }, | |
3978 | { } | |
3979 | }; | |
3980 | ||
3981 | /* l4_wkup -> kbd */ | |
3982 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
3983 | .master = &omap44xx_l4_wkup_hwmod, | |
3984 | .slave = &omap44xx_kbd_hwmod, | |
3985 | .clk = "l4_wkup_clk_mux_ck", | |
3986 | .addr = omap44xx_kbd_addrs, | |
3987 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3988 | }; | |
3989 | ||
3990 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
3991 | { | |
3992 | .pa_start = 0x4a0f4000, | |
3993 | .pa_end = 0x4a0f41ff, | |
3994 | .flags = ADDR_TYPE_RT | |
3995 | }, | |
3996 | { } | |
3997 | }; | |
3998 | ||
3999 | /* l4_cfg -> mailbox */ | |
4000 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4001 | .master = &omap44xx_l4_cfg_hwmod, | |
4002 | .slave = &omap44xx_mailbox_hwmod, | |
4003 | .clk = "l4_div_ck", | |
4004 | .addr = omap44xx_mailbox_addrs, | |
4005 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4006 | }; | |
4007 | ||
4008 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { | |
4009 | { | |
4010 | .name = "mpu", | |
4011 | .pa_start = 0x40122000, | |
4012 | .pa_end = 0x401220ff, | |
4013 | .flags = ADDR_TYPE_RT | |
4014 | }, | |
4015 | { } | |
4016 | }; | |
4017 | ||
4018 | /* l4_abe -> mcbsp1 */ | |
4019 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4020 | .master = &omap44xx_l4_abe_hwmod, | |
4021 | .slave = &omap44xx_mcbsp1_hwmod, | |
4022 | .clk = "ocp_abe_iclk", | |
4023 | .addr = omap44xx_mcbsp1_addrs, | |
4024 | .user = OCP_USER_MPU, | |
4025 | }; | |
4026 | ||
4027 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
4028 | { | |
4029 | .name = "dma", | |
4030 | .pa_start = 0x49022000, | |
4031 | .pa_end = 0x490220ff, | |
4032 | .flags = ADDR_TYPE_RT | |
4033 | }, | |
4034 | { } | |
4035 | }; | |
4036 | ||
4037 | /* l4_abe -> mcbsp1 (dma) */ | |
4038 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
4039 | .master = &omap44xx_l4_abe_hwmod, | |
4040 | .slave = &omap44xx_mcbsp1_hwmod, | |
4041 | .clk = "ocp_abe_iclk", | |
4042 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4043 | .user = OCP_USER_SDMA, | |
4044 | }; | |
4045 | ||
4046 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
4047 | { | |
4048 | .name = "mpu", | |
4049 | .pa_start = 0x40124000, | |
4050 | .pa_end = 0x401240ff, | |
4051 | .flags = ADDR_TYPE_RT | |
4052 | }, | |
4053 | { } | |
4054 | }; | |
4055 | ||
4056 | /* l4_abe -> mcbsp2 */ | |
4057 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4058 | .master = &omap44xx_l4_abe_hwmod, | |
4059 | .slave = &omap44xx_mcbsp2_hwmod, | |
4060 | .clk = "ocp_abe_iclk", | |
4061 | .addr = omap44xx_mcbsp2_addrs, | |
4062 | .user = OCP_USER_MPU, | |
4063 | }; | |
4064 | ||
4065 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
4066 | { | |
4067 | .name = "dma", | |
4068 | .pa_start = 0x49024000, | |
4069 | .pa_end = 0x490240ff, | |
4070 | .flags = ADDR_TYPE_RT | |
4071 | }, | |
4072 | { } | |
4073 | }; | |
4074 | ||
4075 | /* l4_abe -> mcbsp2 (dma) */ | |
4076 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
4077 | .master = &omap44xx_l4_abe_hwmod, | |
4078 | .slave = &omap44xx_mcbsp2_hwmod, | |
4079 | .clk = "ocp_abe_iclk", | |
4080 | .addr = omap44xx_mcbsp2_dma_addrs, | |
4081 | .user = OCP_USER_SDMA, | |
4082 | }; | |
4083 | ||
4084 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
4085 | { | |
4086 | .name = "mpu", | |
4087 | .pa_start = 0x40126000, | |
4088 | .pa_end = 0x401260ff, | |
4089 | .flags = ADDR_TYPE_RT | |
4090 | }, | |
4091 | { } | |
4092 | }; | |
4093 | ||
4094 | /* l4_abe -> mcbsp3 */ | |
4095 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
4096 | .master = &omap44xx_l4_abe_hwmod, | |
4097 | .slave = &omap44xx_mcbsp3_hwmod, | |
4098 | .clk = "ocp_abe_iclk", | |
4099 | .addr = omap44xx_mcbsp3_addrs, | |
4100 | .user = OCP_USER_MPU, | |
4101 | }; | |
4102 | ||
4103 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
4104 | { | |
4105 | .name = "dma", | |
4106 | .pa_start = 0x49026000, | |
4107 | .pa_end = 0x490260ff, | |
4108 | .flags = ADDR_TYPE_RT | |
4109 | }, | |
4110 | { } | |
4111 | }; | |
4112 | ||
4113 | /* l4_abe -> mcbsp3 (dma) */ | |
4114 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
4115 | .master = &omap44xx_l4_abe_hwmod, | |
4116 | .slave = &omap44xx_mcbsp3_hwmod, | |
4117 | .clk = "ocp_abe_iclk", | |
4118 | .addr = omap44xx_mcbsp3_dma_addrs, | |
4119 | .user = OCP_USER_SDMA, | |
4120 | }; | |
4121 | ||
4122 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
4123 | { | |
4124 | .pa_start = 0x48096000, | |
4125 | .pa_end = 0x480960ff, | |
4126 | .flags = ADDR_TYPE_RT | |
4127 | }, | |
4128 | { } | |
4129 | }; | |
4130 | ||
4131 | /* l4_per -> mcbsp4 */ | |
4132 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
4133 | .master = &omap44xx_l4_per_hwmod, | |
4134 | .slave = &omap44xx_mcbsp4_hwmod, | |
4135 | .clk = "l4_div_ck", | |
4136 | .addr = omap44xx_mcbsp4_addrs, | |
4137 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4138 | }; | |
4139 | ||
4140 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
4141 | { | |
4142 | .pa_start = 0x40132000, | |
4143 | .pa_end = 0x4013207f, | |
4144 | .flags = ADDR_TYPE_RT | |
4145 | }, | |
4146 | { } | |
4147 | }; | |
4148 | ||
4149 | /* l4_abe -> mcpdm */ | |
4150 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
4151 | .master = &omap44xx_l4_abe_hwmod, | |
4152 | .slave = &omap44xx_mcpdm_hwmod, | |
4153 | .clk = "ocp_abe_iclk", | |
4154 | .addr = omap44xx_mcpdm_addrs, | |
4155 | .user = OCP_USER_MPU, | |
4156 | }; | |
4157 | ||
4158 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
4159 | { | |
4160 | .pa_start = 0x49032000, | |
4161 | .pa_end = 0x4903207f, | |
4162 | .flags = ADDR_TYPE_RT | |
4163 | }, | |
4164 | { } | |
4165 | }; | |
4166 | ||
4167 | /* l4_abe -> mcpdm (dma) */ | |
4168 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
4169 | .master = &omap44xx_l4_abe_hwmod, | |
4170 | .slave = &omap44xx_mcpdm_hwmod, | |
4171 | .clk = "ocp_abe_iclk", | |
4172 | .addr = omap44xx_mcpdm_dma_addrs, | |
4173 | .user = OCP_USER_SDMA, | |
4174 | }; | |
4175 | ||
4176 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
4177 | { | |
4178 | .pa_start = 0x48098000, | |
4179 | .pa_end = 0x480981ff, | |
4180 | .flags = ADDR_TYPE_RT | |
4181 | }, | |
4182 | { } | |
4183 | }; | |
4184 | ||
4185 | /* l4_per -> mcspi1 */ | |
4186 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
4187 | .master = &omap44xx_l4_per_hwmod, | |
4188 | .slave = &omap44xx_mcspi1_hwmod, | |
4189 | .clk = "l4_div_ck", | |
4190 | .addr = omap44xx_mcspi1_addrs, | |
4191 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4192 | }; | |
4193 | ||
4194 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
4195 | { | |
4196 | .pa_start = 0x4809a000, | |
4197 | .pa_end = 0x4809a1ff, | |
4198 | .flags = ADDR_TYPE_RT | |
4199 | }, | |
4200 | { } | |
4201 | }; | |
4202 | ||
4203 | /* l4_per -> mcspi2 */ | |
4204 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
4205 | .master = &omap44xx_l4_per_hwmod, | |
4206 | .slave = &omap44xx_mcspi2_hwmod, | |
4207 | .clk = "l4_div_ck", | |
4208 | .addr = omap44xx_mcspi2_addrs, | |
4209 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4210 | }; | |
4211 | ||
4212 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
4213 | { | |
4214 | .pa_start = 0x480b8000, | |
4215 | .pa_end = 0x480b81ff, | |
4216 | .flags = ADDR_TYPE_RT | |
4217 | }, | |
4218 | { } | |
4219 | }; | |
4220 | ||
4221 | /* l4_per -> mcspi3 */ | |
4222 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
4223 | .master = &omap44xx_l4_per_hwmod, | |
4224 | .slave = &omap44xx_mcspi3_hwmod, | |
4225 | .clk = "l4_div_ck", | |
4226 | .addr = omap44xx_mcspi3_addrs, | |
4227 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4228 | }; | |
4229 | ||
4230 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
4231 | { | |
4232 | .pa_start = 0x480ba000, | |
4233 | .pa_end = 0x480ba1ff, | |
4234 | .flags = ADDR_TYPE_RT | |
4235 | }, | |
4236 | { } | |
4237 | }; | |
4238 | ||
4239 | /* l4_per -> mcspi4 */ | |
4240 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
4241 | .master = &omap44xx_l4_per_hwmod, | |
4242 | .slave = &omap44xx_mcspi4_hwmod, | |
4243 | .clk = "l4_div_ck", | |
4244 | .addr = omap44xx_mcspi4_addrs, | |
4245 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4246 | }; | |
4247 | ||
4248 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
4249 | { | |
4250 | .pa_start = 0x4809c000, | |
4251 | .pa_end = 0x4809c3ff, | |
4252 | .flags = ADDR_TYPE_RT | |
4253 | }, | |
4254 | { } | |
4255 | }; | |
4256 | ||
4257 | /* l4_per -> mmc1 */ | |
4258 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
4259 | .master = &omap44xx_l4_per_hwmod, | |
4260 | .slave = &omap44xx_mmc1_hwmod, | |
4261 | .clk = "l4_div_ck", | |
4262 | .addr = omap44xx_mmc1_addrs, | |
4263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4264 | }; | |
4265 | ||
4266 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
4267 | { | |
4268 | .pa_start = 0x480b4000, | |
4269 | .pa_end = 0x480b43ff, | |
4270 | .flags = ADDR_TYPE_RT | |
4271 | }, | |
4272 | { } | |
4273 | }; | |
4274 | ||
4275 | /* l4_per -> mmc2 */ | |
4276 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
4277 | .master = &omap44xx_l4_per_hwmod, | |
4278 | .slave = &omap44xx_mmc2_hwmod, | |
4279 | .clk = "l4_div_ck", | |
4280 | .addr = omap44xx_mmc2_addrs, | |
4281 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4282 | }; | |
4283 | ||
4284 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
4285 | { | |
4286 | .pa_start = 0x480ad000, | |
4287 | .pa_end = 0x480ad3ff, | |
4288 | .flags = ADDR_TYPE_RT | |
4289 | }, | |
4290 | { } | |
4291 | }; | |
4292 | ||
4293 | /* l4_per -> mmc3 */ | |
4294 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
4295 | .master = &omap44xx_l4_per_hwmod, | |
4296 | .slave = &omap44xx_mmc3_hwmod, | |
4297 | .clk = "l4_div_ck", | |
4298 | .addr = omap44xx_mmc3_addrs, | |
4299 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4300 | }; | |
4301 | ||
4302 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
4303 | { | |
4304 | .pa_start = 0x480d1000, | |
4305 | .pa_end = 0x480d13ff, | |
4306 | .flags = ADDR_TYPE_RT | |
4307 | }, | |
4308 | { } | |
4309 | }; | |
4310 | ||
4311 | /* l4_per -> mmc4 */ | |
4312 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
4313 | .master = &omap44xx_l4_per_hwmod, | |
4314 | .slave = &omap44xx_mmc4_hwmod, | |
4315 | .clk = "l4_div_ck", | |
4316 | .addr = omap44xx_mmc4_addrs, | |
4317 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4318 | }; | |
4319 | ||
4320 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
4321 | { | |
4322 | .pa_start = 0x480d5000, | |
4323 | .pa_end = 0x480d53ff, | |
4324 | .flags = ADDR_TYPE_RT | |
4325 | }, | |
4326 | { } | |
4327 | }; | |
4328 | ||
4329 | /* l4_per -> mmc5 */ | |
4330 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
4331 | .master = &omap44xx_l4_per_hwmod, | |
4332 | .slave = &omap44xx_mmc5_hwmod, | |
4333 | .clk = "l4_div_ck", | |
4334 | .addr = omap44xx_mmc5_addrs, | |
4335 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4336 | }; | |
4337 | ||
4338 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { | |
4339 | { | |
4340 | .pa_start = 0x4a0dd000, | |
4341 | .pa_end = 0x4a0dd03f, | |
4342 | .flags = ADDR_TYPE_RT | |
4343 | }, | |
4344 | { } | |
4345 | }; | |
4346 | ||
4347 | /* l4_cfg -> smartreflex_core */ | |
4348 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
4349 | .master = &omap44xx_l4_cfg_hwmod, | |
4350 | .slave = &omap44xx_smartreflex_core_hwmod, | |
4351 | .clk = "l4_div_ck", | |
4352 | .addr = omap44xx_smartreflex_core_addrs, | |
4353 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4354 | }; | |
4355 | ||
4356 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
4357 | { | |
4358 | .pa_start = 0x4a0db000, | |
4359 | .pa_end = 0x4a0db03f, | |
4360 | .flags = ADDR_TYPE_RT | |
4361 | }, | |
4362 | { } | |
4363 | }; | |
4364 | ||
4365 | /* l4_cfg -> smartreflex_iva */ | |
4366 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
4367 | .master = &omap44xx_l4_cfg_hwmod, | |
4368 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
4369 | .clk = "l4_div_ck", | |
4370 | .addr = omap44xx_smartreflex_iva_addrs, | |
4371 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4372 | }; | |
4373 | ||
4374 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
4375 | { | |
4376 | .pa_start = 0x4a0d9000, | |
4377 | .pa_end = 0x4a0d903f, | |
4378 | .flags = ADDR_TYPE_RT | |
4379 | }, | |
4380 | { } | |
4381 | }; | |
4382 | ||
4383 | /* l4_cfg -> smartreflex_mpu */ | |
4384 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
4385 | .master = &omap44xx_l4_cfg_hwmod, | |
4386 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
4387 | .clk = "l4_div_ck", | |
4388 | .addr = omap44xx_smartreflex_mpu_addrs, | |
4389 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4390 | }; | |
4391 | ||
4392 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
4393 | { | |
4394 | .pa_start = 0x4a0f6000, | |
4395 | .pa_end = 0x4a0f6fff, | |
4396 | .flags = ADDR_TYPE_RT | |
4397 | }, | |
4398 | { } | |
4399 | }; | |
4400 | ||
4401 | /* l4_cfg -> spinlock */ | |
4402 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
4403 | .master = &omap44xx_l4_cfg_hwmod, | |
4404 | .slave = &omap44xx_spinlock_hwmod, | |
4405 | .clk = "l4_div_ck", | |
4406 | .addr = omap44xx_spinlock_addrs, | |
4407 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4408 | }; | |
4409 | ||
4410 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
4411 | { | |
4412 | .pa_start = 0x4a318000, | |
4413 | .pa_end = 0x4a31807f, | |
4414 | .flags = ADDR_TYPE_RT | |
4415 | }, | |
4416 | { } | |
4417 | }; | |
4418 | ||
4419 | /* l4_wkup -> timer1 */ | |
4420 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
4421 | .master = &omap44xx_l4_wkup_hwmod, | |
4422 | .slave = &omap44xx_timer1_hwmod, | |
4423 | .clk = "l4_wkup_clk_mux_ck", | |
4424 | .addr = omap44xx_timer1_addrs, | |
4425 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4426 | }; | |
4427 | ||
4428 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
4429 | { | |
4430 | .pa_start = 0x48032000, | |
4431 | .pa_end = 0x4803207f, | |
4432 | .flags = ADDR_TYPE_RT | |
4433 | }, | |
4434 | { } | |
4435 | }; | |
4436 | ||
4437 | /* l4_per -> timer2 */ | |
4438 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
4439 | .master = &omap44xx_l4_per_hwmod, | |
4440 | .slave = &omap44xx_timer2_hwmod, | |
4441 | .clk = "l4_div_ck", | |
4442 | .addr = omap44xx_timer2_addrs, | |
4443 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4444 | }; | |
4445 | ||
4446 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
4447 | { | |
4448 | .pa_start = 0x48034000, | |
4449 | .pa_end = 0x4803407f, | |
4450 | .flags = ADDR_TYPE_RT | |
4451 | }, | |
4452 | { } | |
4453 | }; | |
4454 | ||
4455 | /* l4_per -> timer3 */ | |
4456 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
4457 | .master = &omap44xx_l4_per_hwmod, | |
4458 | .slave = &omap44xx_timer3_hwmod, | |
4459 | .clk = "l4_div_ck", | |
4460 | .addr = omap44xx_timer3_addrs, | |
4461 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4462 | }; | |
4463 | ||
4464 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
4465 | { | |
4466 | .pa_start = 0x48036000, | |
4467 | .pa_end = 0x4803607f, | |
4468 | .flags = ADDR_TYPE_RT | |
4469 | }, | |
4470 | { } | |
4471 | }; | |
4472 | ||
4473 | /* l4_per -> timer4 */ | |
4474 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
4475 | .master = &omap44xx_l4_per_hwmod, | |
4476 | .slave = &omap44xx_timer4_hwmod, | |
4477 | .clk = "l4_div_ck", | |
4478 | .addr = omap44xx_timer4_addrs, | |
4479 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4480 | }; | |
4481 | ||
4482 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
4483 | { | |
4484 | .pa_start = 0x40138000, | |
4485 | .pa_end = 0x4013807f, | |
4486 | .flags = ADDR_TYPE_RT | |
4487 | }, | |
4488 | { } | |
4489 | }; | |
4490 | ||
4491 | /* l4_abe -> timer5 */ | |
4492 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
4493 | .master = &omap44xx_l4_abe_hwmod, | |
4494 | .slave = &omap44xx_timer5_hwmod, | |
4495 | .clk = "ocp_abe_iclk", | |
4496 | .addr = omap44xx_timer5_addrs, | |
4497 | .user = OCP_USER_MPU, | |
4498 | }; | |
4499 | ||
4500 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
4501 | { | |
4502 | .pa_start = 0x49038000, | |
4503 | .pa_end = 0x4903807f, | |
4504 | .flags = ADDR_TYPE_RT | |
4505 | }, | |
4506 | { } | |
4507 | }; | |
4508 | ||
4509 | /* l4_abe -> timer5 (dma) */ | |
4510 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
4511 | .master = &omap44xx_l4_abe_hwmod, | |
4512 | .slave = &omap44xx_timer5_hwmod, | |
4513 | .clk = "ocp_abe_iclk", | |
4514 | .addr = omap44xx_timer5_dma_addrs, | |
4515 | .user = OCP_USER_SDMA, | |
4516 | }; | |
4517 | ||
4518 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
4519 | { | |
4520 | .pa_start = 0x4013a000, | |
4521 | .pa_end = 0x4013a07f, | |
4522 | .flags = ADDR_TYPE_RT | |
4523 | }, | |
4524 | { } | |
4525 | }; | |
4526 | ||
4527 | /* l4_abe -> timer6 */ | |
4528 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
4529 | .master = &omap44xx_l4_abe_hwmod, | |
4530 | .slave = &omap44xx_timer6_hwmod, | |
4531 | .clk = "ocp_abe_iclk", | |
4532 | .addr = omap44xx_timer6_addrs, | |
4533 | .user = OCP_USER_MPU, | |
4534 | }; | |
4535 | ||
4536 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
4537 | { | |
4538 | .pa_start = 0x4903a000, | |
4539 | .pa_end = 0x4903a07f, | |
4540 | .flags = ADDR_TYPE_RT | |
4541 | }, | |
4542 | { } | |
4543 | }; | |
4544 | ||
4545 | /* l4_abe -> timer6 (dma) */ | |
4546 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
4547 | .master = &omap44xx_l4_abe_hwmod, | |
4548 | .slave = &omap44xx_timer6_hwmod, | |
4549 | .clk = "ocp_abe_iclk", | |
4550 | .addr = omap44xx_timer6_dma_addrs, | |
4551 | .user = OCP_USER_SDMA, | |
4552 | }; | |
4553 | ||
4554 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
4555 | { | |
4556 | .pa_start = 0x4013c000, | |
4557 | .pa_end = 0x4013c07f, | |
4558 | .flags = ADDR_TYPE_RT | |
4559 | }, | |
4560 | { } | |
4561 | }; | |
4562 | ||
4563 | /* l4_abe -> timer7 */ | |
4564 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
4565 | .master = &omap44xx_l4_abe_hwmod, | |
4566 | .slave = &omap44xx_timer7_hwmod, | |
4567 | .clk = "ocp_abe_iclk", | |
4568 | .addr = omap44xx_timer7_addrs, | |
4569 | .user = OCP_USER_MPU, | |
4570 | }; | |
4571 | ||
4572 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
4573 | { | |
4574 | .pa_start = 0x4903c000, | |
4575 | .pa_end = 0x4903c07f, | |
4576 | .flags = ADDR_TYPE_RT | |
4577 | }, | |
4578 | { } | |
4579 | }; | |
4580 | ||
4581 | /* l4_abe -> timer7 (dma) */ | |
4582 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
4583 | .master = &omap44xx_l4_abe_hwmod, | |
4584 | .slave = &omap44xx_timer7_hwmod, | |
4585 | .clk = "ocp_abe_iclk", | |
4586 | .addr = omap44xx_timer7_dma_addrs, | |
4587 | .user = OCP_USER_SDMA, | |
4588 | }; | |
4589 | ||
4590 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
4591 | { | |
4592 | .pa_start = 0x4013e000, | |
4593 | .pa_end = 0x4013e07f, | |
4594 | .flags = ADDR_TYPE_RT | |
4595 | }, | |
4596 | { } | |
4597 | }; | |
4598 | ||
4599 | /* l4_abe -> timer8 */ | |
4600 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
4601 | .master = &omap44xx_l4_abe_hwmod, | |
4602 | .slave = &omap44xx_timer8_hwmod, | |
4603 | .clk = "ocp_abe_iclk", | |
4604 | .addr = omap44xx_timer8_addrs, | |
4605 | .user = OCP_USER_MPU, | |
4606 | }; | |
4607 | ||
4608 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
4609 | { | |
4610 | .pa_start = 0x4903e000, | |
4611 | .pa_end = 0x4903e07f, | |
4612 | .flags = ADDR_TYPE_RT | |
4613 | }, | |
4614 | { } | |
4615 | }; | |
4616 | ||
4617 | /* l4_abe -> timer8 (dma) */ | |
4618 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
4619 | .master = &omap44xx_l4_abe_hwmod, | |
4620 | .slave = &omap44xx_timer8_hwmod, | |
4621 | .clk = "ocp_abe_iclk", | |
4622 | .addr = omap44xx_timer8_dma_addrs, | |
4623 | .user = OCP_USER_SDMA, | |
4624 | }; | |
4625 | ||
4626 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
4627 | { | |
4628 | .pa_start = 0x4803e000, | |
4629 | .pa_end = 0x4803e07f, | |
4630 | .flags = ADDR_TYPE_RT | |
4631 | }, | |
4632 | { } | |
4633 | }; | |
4634 | ||
4635 | /* l4_per -> timer9 */ | |
4636 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
4637 | .master = &omap44xx_l4_per_hwmod, | |
4638 | .slave = &omap44xx_timer9_hwmod, | |
4639 | .clk = "l4_div_ck", | |
4640 | .addr = omap44xx_timer9_addrs, | |
4641 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4642 | }; | |
4643 | ||
4644 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
4645 | { | |
4646 | .pa_start = 0x48086000, | |
4647 | .pa_end = 0x4808607f, | |
4648 | .flags = ADDR_TYPE_RT | |
4649 | }, | |
4650 | { } | |
4651 | }; | |
4652 | ||
4653 | /* l4_per -> timer10 */ | |
4654 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
4655 | .master = &omap44xx_l4_per_hwmod, | |
4656 | .slave = &omap44xx_timer10_hwmod, | |
4657 | .clk = "l4_div_ck", | |
4658 | .addr = omap44xx_timer10_addrs, | |
4659 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4660 | }; | |
4661 | ||
4662 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
4663 | { | |
4664 | .pa_start = 0x48088000, | |
4665 | .pa_end = 0x4808807f, | |
4666 | .flags = ADDR_TYPE_RT | |
4667 | }, | |
4668 | { } | |
4669 | }; | |
4670 | ||
4671 | /* l4_per -> timer11 */ | |
4672 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
4673 | .master = &omap44xx_l4_per_hwmod, | |
4674 | .slave = &omap44xx_timer11_hwmod, | |
4675 | .clk = "l4_div_ck", | |
4676 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
4677 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4678 | }; | |
4679 | ||
844a3b63 PW |
4680 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
4681 | { | |
4682 | .pa_start = 0x4806a000, | |
4683 | .pa_end = 0x4806a0ff, | |
4684 | .flags = ADDR_TYPE_RT | |
af88fa9a | 4685 | }, |
844a3b63 PW |
4686 | { } |
4687 | }; | |
af88fa9a | 4688 | |
844a3b63 PW |
4689 | /* l4_per -> uart1 */ |
4690 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
4691 | .master = &omap44xx_l4_per_hwmod, | |
4692 | .slave = &omap44xx_uart1_hwmod, | |
4693 | .clk = "l4_div_ck", | |
4694 | .addr = omap44xx_uart1_addrs, | |
4695 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4696 | }; | |
af88fa9a | 4697 | |
844a3b63 PW |
4698 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
4699 | { | |
4700 | .pa_start = 0x4806c000, | |
4701 | .pa_end = 0x4806c0ff, | |
4702 | .flags = ADDR_TYPE_RT | |
4703 | }, | |
4704 | { } | |
4705 | }; | |
af88fa9a | 4706 | |
844a3b63 PW |
4707 | /* l4_per -> uart2 */ |
4708 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
4709 | .master = &omap44xx_l4_per_hwmod, | |
4710 | .slave = &omap44xx_uart2_hwmod, | |
4711 | .clk = "l4_div_ck", | |
4712 | .addr = omap44xx_uart2_addrs, | |
4713 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4714 | }; | |
af88fa9a | 4715 | |
844a3b63 PW |
4716 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
4717 | { | |
4718 | .pa_start = 0x48020000, | |
4719 | .pa_end = 0x480200ff, | |
4720 | .flags = ADDR_TYPE_RT | |
4721 | }, | |
4722 | { } | |
af88fa9a BC |
4723 | }; |
4724 | ||
844a3b63 PW |
4725 | /* l4_per -> uart3 */ |
4726 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
4727 | .master = &omap44xx_l4_per_hwmod, | |
4728 | .slave = &omap44xx_uart3_hwmod, | |
4729 | .clk = "l4_div_ck", | |
4730 | .addr = omap44xx_uart3_addrs, | |
4731 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
4732 | }; |
4733 | ||
844a3b63 PW |
4734 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
4735 | { | |
4736 | .pa_start = 0x4806e000, | |
4737 | .pa_end = 0x4806e0ff, | |
4738 | .flags = ADDR_TYPE_RT | |
4739 | }, | |
4740 | { } | |
af88fa9a BC |
4741 | }; |
4742 | ||
844a3b63 PW |
4743 | /* l4_per -> uart4 */ |
4744 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
4745 | .master = &omap44xx_l4_per_hwmod, | |
4746 | .slave = &omap44xx_uart4_hwmod, | |
4747 | .clk = "l4_div_ck", | |
4748 | .addr = omap44xx_uart4_addrs, | |
4749 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4750 | }; | |
4751 | ||
4752 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { | |
4753 | { | |
4754 | .name = "uhh", | |
4755 | .pa_start = 0x4a064000, | |
4756 | .pa_end = 0x4a0647ff, | |
4757 | .flags = ADDR_TYPE_RT | |
4758 | }, | |
4759 | { | |
4760 | .name = "ohci", | |
4761 | .pa_start = 0x4a064800, | |
4762 | .pa_end = 0x4a064bff, | |
4763 | }, | |
4764 | { | |
4765 | .name = "ehci", | |
4766 | .pa_start = 0x4a064c00, | |
4767 | .pa_end = 0x4a064fff, | |
4768 | }, | |
4769 | {} | |
4770 | }; | |
4771 | ||
4772 | /* l4_cfg -> usb_host_hs */ | |
4773 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
4774 | .master = &omap44xx_l4_cfg_hwmod, | |
4775 | .slave = &omap44xx_usb_host_hs_hwmod, | |
4776 | .clk = "l4_div_ck", | |
4777 | .addr = omap44xx_usb_host_hs_addrs, | |
4778 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4779 | }; | |
4780 | ||
4781 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
4782 | { | |
4783 | .pa_start = 0x4a0ab000, | |
4784 | .pa_end = 0x4a0ab003, | |
4785 | .flags = ADDR_TYPE_RT | |
4786 | }, | |
4787 | { } | |
4788 | }; | |
4789 | ||
4790 | /* l4_cfg -> usb_otg_hs */ | |
4791 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
4792 | .master = &omap44xx_l4_cfg_hwmod, | |
4793 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
4794 | .clk = "l4_div_ck", | |
4795 | .addr = omap44xx_usb_otg_hs_addrs, | |
4796 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
4797 | }; |
4798 | ||
4799 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
4800 | { | |
4801 | .name = "tll", | |
4802 | .pa_start = 0x4a062000, | |
4803 | .pa_end = 0x4a063fff, | |
4804 | .flags = ADDR_TYPE_RT | |
4805 | }, | |
4806 | {} | |
4807 | }; | |
4808 | ||
844a3b63 | 4809 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
4810 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
4811 | .master = &omap44xx_l4_cfg_hwmod, | |
4812 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
4813 | .clk = "l4_div_ck", | |
4814 | .addr = omap44xx_usb_tll_hs_addrs, | |
4815 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4816 | }; | |
4817 | ||
844a3b63 PW |
4818 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
4819 | { | |
4820 | .pa_start = 0x4a314000, | |
4821 | .pa_end = 0x4a31407f, | |
4822 | .flags = ADDR_TYPE_RT | |
af88fa9a | 4823 | }, |
844a3b63 PW |
4824 | { } |
4825 | }; | |
4826 | ||
4827 | /* l4_wkup -> wd_timer2 */ | |
4828 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
4829 | .master = &omap44xx_l4_wkup_hwmod, | |
4830 | .slave = &omap44xx_wd_timer2_hwmod, | |
4831 | .clk = "l4_wkup_clk_mux_ck", | |
4832 | .addr = omap44xx_wd_timer2_addrs, | |
4833 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4834 | }; | |
4835 | ||
4836 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
4837 | { | |
4838 | .pa_start = 0x40130000, | |
4839 | .pa_end = 0x4013007f, | |
4840 | .flags = ADDR_TYPE_RT | |
4841 | }, | |
4842 | { } | |
4843 | }; | |
4844 | ||
4845 | /* l4_abe -> wd_timer3 */ | |
4846 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
4847 | .master = &omap44xx_l4_abe_hwmod, | |
4848 | .slave = &omap44xx_wd_timer3_hwmod, | |
4849 | .clk = "ocp_abe_iclk", | |
4850 | .addr = omap44xx_wd_timer3_addrs, | |
4851 | .user = OCP_USER_MPU, | |
4852 | }; | |
4853 | ||
4854 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
4855 | { | |
4856 | .pa_start = 0x49030000, | |
4857 | .pa_end = 0x4903007f, | |
4858 | .flags = ADDR_TYPE_RT | |
4859 | }, | |
4860 | { } | |
4861 | }; | |
4862 | ||
4863 | /* l4_abe -> wd_timer3 (dma) */ | |
4864 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
4865 | .master = &omap44xx_l4_abe_hwmod, | |
4866 | .slave = &omap44xx_wd_timer3_hwmod, | |
4867 | .clk = "ocp_abe_iclk", | |
4868 | .addr = omap44xx_wd_timer3_dma_addrs, | |
4869 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
4870 | }; |
4871 | ||
0a78c5c5 PW |
4872 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
4873 | &omap44xx_l3_main_1__dmm, | |
4874 | &omap44xx_mpu__dmm, | |
4875 | &omap44xx_dmm__emif_fw, | |
4876 | &omap44xx_l4_cfg__emif_fw, | |
4877 | &omap44xx_iva__l3_instr, | |
4878 | &omap44xx_l3_main_3__l3_instr, | |
4879 | &omap44xx_dsp__l3_main_1, | |
4880 | &omap44xx_dss__l3_main_1, | |
4881 | &omap44xx_l3_main_2__l3_main_1, | |
4882 | &omap44xx_l4_cfg__l3_main_1, | |
4883 | &omap44xx_mmc1__l3_main_1, | |
4884 | &omap44xx_mmc2__l3_main_1, | |
4885 | &omap44xx_mpu__l3_main_1, | |
4886 | &omap44xx_dma_system__l3_main_2, | |
b050f688 | 4887 | &omap44xx_fdif__l3_main_2, |
0a78c5c5 PW |
4888 | &omap44xx_hsi__l3_main_2, |
4889 | &omap44xx_ipu__l3_main_2, | |
4890 | &omap44xx_iss__l3_main_2, | |
4891 | &omap44xx_iva__l3_main_2, | |
4892 | &omap44xx_l3_main_1__l3_main_2, | |
4893 | &omap44xx_l4_cfg__l3_main_2, | |
4894 | &omap44xx_usb_host_hs__l3_main_2, | |
4895 | &omap44xx_usb_otg_hs__l3_main_2, | |
4896 | &omap44xx_l3_main_1__l3_main_3, | |
4897 | &omap44xx_l3_main_2__l3_main_3, | |
4898 | &omap44xx_l4_cfg__l3_main_3, | |
4899 | &omap44xx_aess__l4_abe, | |
4900 | &omap44xx_dsp__l4_abe, | |
4901 | &omap44xx_l3_main_1__l4_abe, | |
4902 | &omap44xx_mpu__l4_abe, | |
4903 | &omap44xx_l3_main_1__l4_cfg, | |
4904 | &omap44xx_l3_main_2__l4_per, | |
4905 | &omap44xx_l4_cfg__l4_wkup, | |
4906 | &omap44xx_mpu__mpu_private, | |
4907 | &omap44xx_l4_abe__aess, | |
4908 | &omap44xx_l4_abe__aess_dma, | |
4909 | &omap44xx_l4_wkup__counter_32k, | |
4910 | &omap44xx_l4_cfg__dma_system, | |
4911 | &omap44xx_l4_abe__dmic, | |
4912 | &omap44xx_l4_abe__dmic_dma, | |
4913 | &omap44xx_dsp__iva, | |
4914 | &omap44xx_l4_cfg__dsp, | |
4915 | &omap44xx_l3_main_2__dss, | |
4916 | &omap44xx_l4_per__dss, | |
4917 | &omap44xx_l3_main_2__dss_dispc, | |
4918 | &omap44xx_l4_per__dss_dispc, | |
4919 | &omap44xx_l3_main_2__dss_dsi1, | |
4920 | &omap44xx_l4_per__dss_dsi1, | |
4921 | &omap44xx_l3_main_2__dss_dsi2, | |
4922 | &omap44xx_l4_per__dss_dsi2, | |
4923 | &omap44xx_l3_main_2__dss_hdmi, | |
4924 | &omap44xx_l4_per__dss_hdmi, | |
4925 | &omap44xx_l3_main_2__dss_rfbi, | |
4926 | &omap44xx_l4_per__dss_rfbi, | |
4927 | &omap44xx_l3_main_2__dss_venc, | |
4928 | &omap44xx_l4_per__dss_venc, | |
b050f688 | 4929 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
4930 | &omap44xx_l4_wkup__gpio1, |
4931 | &omap44xx_l4_per__gpio2, | |
4932 | &omap44xx_l4_per__gpio3, | |
4933 | &omap44xx_l4_per__gpio4, | |
4934 | &omap44xx_l4_per__gpio5, | |
4935 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 4936 | &omap44xx_l3_main_2__gpmc, |
a091c08e | 4937 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
4938 | &omap44xx_l4_cfg__hsi, |
4939 | &omap44xx_l4_per__i2c1, | |
4940 | &omap44xx_l4_per__i2c2, | |
4941 | &omap44xx_l4_per__i2c3, | |
4942 | &omap44xx_l4_per__i2c4, | |
4943 | &omap44xx_l3_main_2__ipu, | |
4944 | &omap44xx_l3_main_2__iss, | |
4945 | &omap44xx_l3_main_2__iva, | |
4946 | &omap44xx_l4_wkup__kbd, | |
4947 | &omap44xx_l4_cfg__mailbox, | |
4948 | &omap44xx_l4_abe__mcbsp1, | |
4949 | &omap44xx_l4_abe__mcbsp1_dma, | |
4950 | &omap44xx_l4_abe__mcbsp2, | |
4951 | &omap44xx_l4_abe__mcbsp2_dma, | |
4952 | &omap44xx_l4_abe__mcbsp3, | |
4953 | &omap44xx_l4_abe__mcbsp3_dma, | |
4954 | &omap44xx_l4_per__mcbsp4, | |
4955 | &omap44xx_l4_abe__mcpdm, | |
4956 | &omap44xx_l4_abe__mcpdm_dma, | |
4957 | &omap44xx_l4_per__mcspi1, | |
4958 | &omap44xx_l4_per__mcspi2, | |
4959 | &omap44xx_l4_per__mcspi3, | |
4960 | &omap44xx_l4_per__mcspi4, | |
4961 | &omap44xx_l4_per__mmc1, | |
4962 | &omap44xx_l4_per__mmc2, | |
4963 | &omap44xx_l4_per__mmc3, | |
4964 | &omap44xx_l4_per__mmc4, | |
4965 | &omap44xx_l4_per__mmc5, | |
4966 | &omap44xx_l4_cfg__smartreflex_core, | |
4967 | &omap44xx_l4_cfg__smartreflex_iva, | |
4968 | &omap44xx_l4_cfg__smartreflex_mpu, | |
4969 | &omap44xx_l4_cfg__spinlock, | |
4970 | &omap44xx_l4_wkup__timer1, | |
4971 | &omap44xx_l4_per__timer2, | |
4972 | &omap44xx_l4_per__timer3, | |
4973 | &omap44xx_l4_per__timer4, | |
4974 | &omap44xx_l4_abe__timer5, | |
4975 | &omap44xx_l4_abe__timer5_dma, | |
4976 | &omap44xx_l4_abe__timer6, | |
4977 | &omap44xx_l4_abe__timer6_dma, | |
4978 | &omap44xx_l4_abe__timer7, | |
4979 | &omap44xx_l4_abe__timer7_dma, | |
4980 | &omap44xx_l4_abe__timer8, | |
4981 | &omap44xx_l4_abe__timer8_dma, | |
4982 | &omap44xx_l4_per__timer9, | |
4983 | &omap44xx_l4_per__timer10, | |
4984 | &omap44xx_l4_per__timer11, | |
4985 | &omap44xx_l4_per__uart1, | |
4986 | &omap44xx_l4_per__uart2, | |
4987 | &omap44xx_l4_per__uart3, | |
4988 | &omap44xx_l4_per__uart4, | |
4989 | &omap44xx_l4_cfg__usb_host_hs, | |
4990 | &omap44xx_l4_cfg__usb_otg_hs, | |
4991 | &omap44xx_l4_cfg__usb_tll_hs, | |
4992 | &omap44xx_l4_wkup__wd_timer2, | |
4993 | &omap44xx_l4_abe__wd_timer3, | |
4994 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
4995 | NULL, |
4996 | }; | |
4997 | ||
4998 | int __init omap44xx_hwmod_init(void) | |
4999 | { | |
0a78c5c5 | 5000 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
5001 | } |
5002 |