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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
3b9b1015 S |
15 | * Note that this file is currently not in sync with autogeneration scripts. |
16 | * The above note to be removed, once it is synced up. | |
55d2cb08 BC |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License version 2 as | |
20 | * published by the Free Software Foundation. | |
21 | */ | |
22 | ||
23 | #include <linux/io.h> | |
4b25408f | 24 | #include <linux/platform_data/gpio-omap.h> |
55143438 | 25 | #include <linux/platform_data/hsmmc-omap.h> |
b86aeafc | 26 | #include <linux/power/smartreflex.h> |
3a8761c0 | 27 | #include <linux/i2c-omap.h> |
55d2cb08 | 28 | |
45c3eb7d | 29 | #include <linux/omap-dma.h> |
2a296c8f | 30 | |
2203747c AB |
31 | #include <linux/platform_data/spi-omap2-mcspi.h> |
32 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
c345c8b0 | 33 | #include <plat/dmtimer.h> |
55d2cb08 | 34 | |
2a296c8f | 35 | #include "omap_hwmod.h" |
55d2cb08 | 36 | #include "omap_hwmod_common_data.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
3a8761c0 | 41 | #include "i2c.h" |
ff2516fb | 42 | #include "wd_timer.h" |
55d2cb08 BC |
43 | |
44 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
45 | #define OMAP44XX_IRQ_GIC_START 32 | |
46 | ||
47 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 48 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
49 | |
50 | /* | |
844a3b63 | 51 | * IP blocks |
55d2cb08 BC |
52 | */ |
53 | ||
54 | /* | |
55 | * 'dmm' class | |
56 | * instance(s): dmm | |
57 | */ | |
58 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 59 | .name = "dmm", |
55d2cb08 BC |
60 | }; |
61 | ||
7e69ed97 | 62 | /* dmm */ |
55d2cb08 BC |
63 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
64 | .name = "dmm", | |
65 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 66 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
67 | .prcm = { |
68 | .omap4 = { | |
69 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 70 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
71 | }, |
72 | }, | |
55d2cb08 BC |
73 | }; |
74 | ||
55d2cb08 BC |
75 | /* |
76 | * 'l3' class | |
77 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
78 | */ | |
79 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 80 | .name = "l3", |
55d2cb08 BC |
81 | }; |
82 | ||
7e69ed97 | 83 | /* l3_instr */ |
55d2cb08 BC |
84 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
85 | .name = "l3_instr", | |
86 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 87 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
88 | .prcm = { |
89 | .omap4 = { | |
90 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 91 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 92 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
93 | }, |
94 | }, | |
55d2cb08 BC |
95 | }; |
96 | ||
7e69ed97 | 97 | /* l3_main_1 */ |
55d2cb08 BC |
98 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
99 | .name = "l3_main_1", | |
100 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 101 | .clkdm_name = "l3_1_clkdm", |
d0f0631d BC |
102 | .prcm = { |
103 | .omap4 = { | |
104 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 105 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
106 | }, |
107 | }, | |
55d2cb08 BC |
108 | }; |
109 | ||
7e69ed97 | 110 | /* l3_main_2 */ |
55d2cb08 BC |
111 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
112 | .name = "l3_main_2", | |
113 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 114 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
115 | .prcm = { |
116 | .omap4 = { | |
117 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 118 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
119 | }, |
120 | }, | |
55d2cb08 BC |
121 | }; |
122 | ||
7e69ed97 | 123 | /* l3_main_3 */ |
55d2cb08 BC |
124 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
125 | .name = "l3_main_3", | |
126 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 127 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
128 | .prcm = { |
129 | .omap4 = { | |
130 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 131 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 132 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
133 | }, |
134 | }, | |
55d2cb08 BC |
135 | }; |
136 | ||
137 | /* | |
138 | * 'l4' class | |
139 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
140 | */ | |
141 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 142 | .name = "l4", |
55d2cb08 BC |
143 | }; |
144 | ||
7e69ed97 | 145 | /* l4_abe */ |
55d2cb08 BC |
146 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
147 | .name = "l4_abe", | |
148 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 149 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
150 | .prcm = { |
151 | .omap4 = { | |
152 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
ce80979a TK |
153 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
154 | .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, | |
46b3af27 | 155 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
d0f0631d BC |
156 | }, |
157 | }, | |
55d2cb08 BC |
158 | }; |
159 | ||
7e69ed97 | 160 | /* l4_cfg */ |
55d2cb08 BC |
161 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
162 | .name = "l4_cfg", | |
163 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 164 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
165 | .prcm = { |
166 | .omap4 = { | |
167 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 168 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
169 | }, |
170 | }, | |
55d2cb08 BC |
171 | }; |
172 | ||
7e69ed97 | 173 | /* l4_per */ |
55d2cb08 BC |
174 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
175 | .name = "l4_per", | |
176 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 177 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
178 | .prcm = { |
179 | .omap4 = { | |
180 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 181 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
182 | }, |
183 | }, | |
55d2cb08 BC |
184 | }; |
185 | ||
7e69ed97 | 186 | /* l4_wkup */ |
55d2cb08 BC |
187 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
188 | .name = "l4_wkup", | |
189 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 190 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
191 | .prcm = { |
192 | .omap4 = { | |
193 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 194 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
195 | }, |
196 | }, | |
55d2cb08 BC |
197 | }; |
198 | ||
f776471f | 199 | /* |
3b54baad BC |
200 | * 'mpu_bus' class |
201 | * instance(s): mpu_private | |
f776471f | 202 | */ |
3b54baad | 203 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 204 | .name = "mpu_bus", |
3b54baad | 205 | }; |
f776471f | 206 | |
7e69ed97 | 207 | /* mpu_private */ |
3b54baad BC |
208 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
209 | .name = "mpu_private", | |
210 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 211 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
212 | .prcm = { |
213 | .omap4 = { | |
214 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
215 | }, | |
216 | }, | |
3b54baad BC |
217 | }; |
218 | ||
9a817bc8 BC |
219 | /* |
220 | * 'ocp_wp_noc' class | |
221 | * instance(s): ocp_wp_noc | |
222 | */ | |
223 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
224 | .name = "ocp_wp_noc", | |
225 | }; | |
226 | ||
227 | /* ocp_wp_noc */ | |
228 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
229 | .name = "ocp_wp_noc", | |
230 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
231 | .clkdm_name = "l3_instr_clkdm", | |
232 | .prcm = { | |
233 | .omap4 = { | |
234 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
235 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
236 | .modulemode = MODULEMODE_HWCTRL, | |
237 | }, | |
238 | }, | |
239 | }; | |
240 | ||
3b54baad BC |
241 | /* |
242 | * Modules omap_hwmod structures | |
243 | * | |
244 | * The following IPs are excluded for the moment because: | |
245 | * - They do not need an explicit SW control using omap_hwmod API. | |
246 | * - They still need to be validated with the driver | |
247 | * properly adapted to omap_hwmod / omap_device | |
248 | * | |
96566043 | 249 | * usim |
3b54baad BC |
250 | */ |
251 | ||
407a6888 BC |
252 | /* |
253 | * 'aess' class | |
254 | * audio engine sub system | |
255 | */ | |
256 | ||
257 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
258 | .rev_offs = 0x0000, | |
259 | .sysc_offs = 0x0010, | |
260 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
261 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
262 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
263 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
264 | .sysc_fields = &omap_hwmod_sysc_type2, |
265 | }; | |
266 | ||
267 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
268 | .name = "aess", | |
269 | .sysc = &omap44xx_aess_sysc, | |
c02060d8 | 270 | .enable_preprogram = omap_hwmod_aess_preprogram, |
407a6888 BC |
271 | }; |
272 | ||
273 | /* aess */ | |
407a6888 BC |
274 | static struct omap_hwmod omap44xx_aess_hwmod = { |
275 | .name = "aess", | |
276 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 277 | .clkdm_name = "abe_clkdm", |
9f0c5996 | 278 | .main_clk = "aess_fclk", |
00fe610b | 279 | .prcm = { |
407a6888 | 280 | .omap4 = { |
d0f0631d | 281 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 282 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
ce80979a | 283 | .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, |
03fdefe5 | 284 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
285 | }, |
286 | }, | |
407a6888 BC |
287 | }; |
288 | ||
42b9e387 PW |
289 | /* |
290 | * 'c2c' class | |
291 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
292 | * soc | |
293 | */ | |
294 | ||
295 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
296 | .name = "c2c", | |
297 | }; | |
298 | ||
299 | /* c2c */ | |
42b9e387 PW |
300 | static struct omap_hwmod omap44xx_c2c_hwmod = { |
301 | .name = "c2c", | |
302 | .class = &omap44xx_c2c_hwmod_class, | |
303 | .clkdm_name = "d2d_clkdm", | |
42b9e387 PW |
304 | .prcm = { |
305 | .omap4 = { | |
306 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
307 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
308 | }, | |
309 | }, | |
310 | }; | |
311 | ||
407a6888 BC |
312 | /* |
313 | * 'counter' class | |
314 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
315 | */ | |
316 | ||
317 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
318 | .rev_offs = 0x0000, | |
319 | .sysc_offs = 0x0004, | |
320 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 321 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
322 | .sysc_fields = &omap_hwmod_sysc_type1, |
323 | }; | |
324 | ||
325 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
326 | .name = "counter", | |
327 | .sysc = &omap44xx_counter_sysc, | |
328 | }; | |
329 | ||
330 | /* counter_32k */ | |
407a6888 BC |
331 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
332 | .name = "counter_32k", | |
333 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 334 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
335 | .flags = HWMOD_SWSUP_SIDLE, |
336 | .main_clk = "sys_32k_ck", | |
00fe610b | 337 | .prcm = { |
407a6888 | 338 | .omap4 = { |
d0f0631d | 339 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 340 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
341 | }, |
342 | }, | |
407a6888 BC |
343 | }; |
344 | ||
a0b5d813 PW |
345 | /* |
346 | * 'ctrl_module' class | |
347 | * attila core control module + core pad control module + wkup pad control | |
348 | * module + attila wkup control module | |
349 | */ | |
350 | ||
351 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
352 | .rev_offs = 0x0000, | |
353 | .sysc_offs = 0x0010, | |
354 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
355 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
356 | SIDLE_SMART_WKUP), | |
357 | .sysc_fields = &omap_hwmod_sysc_type2, | |
358 | }; | |
359 | ||
360 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
361 | .name = "ctrl_module", | |
362 | .sysc = &omap44xx_ctrl_module_sysc, | |
363 | }; | |
364 | ||
365 | /* ctrl_module_core */ | |
a0b5d813 PW |
366 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { |
367 | .name = "ctrl_module_core", | |
368 | .class = &omap44xx_ctrl_module_hwmod_class, | |
369 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
370 | .prcm = { |
371 | .omap4 = { | |
372 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
373 | }, | |
374 | }, | |
a0b5d813 PW |
375 | }; |
376 | ||
377 | /* ctrl_module_pad_core */ | |
378 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
379 | .name = "ctrl_module_pad_core", | |
380 | .class = &omap44xx_ctrl_module_hwmod_class, | |
381 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
382 | .prcm = { |
383 | .omap4 = { | |
384 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
385 | }, | |
386 | }, | |
a0b5d813 PW |
387 | }; |
388 | ||
389 | /* ctrl_module_wkup */ | |
390 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
391 | .name = "ctrl_module_wkup", | |
392 | .class = &omap44xx_ctrl_module_hwmod_class, | |
393 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
394 | .prcm = { |
395 | .omap4 = { | |
396 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
397 | }, | |
398 | }, | |
a0b5d813 PW |
399 | }; |
400 | ||
401 | /* ctrl_module_pad_wkup */ | |
402 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
403 | .name = "ctrl_module_pad_wkup", | |
404 | .class = &omap44xx_ctrl_module_hwmod_class, | |
405 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
406 | .prcm = { |
407 | .omap4 = { | |
408 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
409 | }, | |
410 | }, | |
a0b5d813 PW |
411 | }; |
412 | ||
96566043 BC |
413 | /* |
414 | * 'debugss' class | |
415 | * debug and emulation sub system | |
416 | */ | |
417 | ||
418 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
419 | .name = "debugss", | |
420 | }; | |
421 | ||
422 | /* debugss */ | |
423 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
424 | .name = "debugss", | |
425 | .class = &omap44xx_debugss_hwmod_class, | |
426 | .clkdm_name = "emu_sys_clkdm", | |
427 | .main_clk = "trace_clk_div_ck", | |
428 | .prcm = { | |
429 | .omap4 = { | |
430 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
431 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
432 | }, | |
433 | }, | |
434 | }; | |
435 | ||
d7cf5f33 BC |
436 | /* |
437 | * 'dma' class | |
438 | * dma controller for data exchange between memory to memory (i.e. internal or | |
439 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
440 | */ | |
441 | ||
442 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
443 | .rev_offs = 0x0000, | |
444 | .sysc_offs = 0x002c, | |
445 | .syss_offs = 0x0028, | |
446 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
447 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
448 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
449 | SYSS_HAS_RESET_STATUS), | |
450 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
451 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
452 | .sysc_fields = &omap_hwmod_sysc_type1, | |
453 | }; | |
454 | ||
455 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
456 | .name = "dma", | |
457 | .sysc = &omap44xx_dma_sysc, | |
458 | }; | |
459 | ||
460 | /* dma dev_attr */ | |
461 | static struct omap_dma_dev_attr dma_dev_attr = { | |
462 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
463 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
464 | .lch_count = 32, | |
465 | }; | |
466 | ||
467 | /* dma_system */ | |
468 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
469 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
470 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
471 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
472 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 473 | { .irq = -1 } |
d7cf5f33 BC |
474 | }; |
475 | ||
d7cf5f33 BC |
476 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
477 | .name = "dma_system", | |
478 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 479 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 480 | .mpu_irqs = omap44xx_dma_system_irqs, |
0fb22a8f | 481 | .xlate_irq = omap4_xlate_irq, |
d7cf5f33 BC |
482 | .main_clk = "l3_div_ck", |
483 | .prcm = { | |
484 | .omap4 = { | |
d0f0631d | 485 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 486 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
487 | }, |
488 | }, | |
489 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
490 | }; |
491 | ||
8ca476da BC |
492 | /* |
493 | * 'dmic' class | |
494 | * digital microphone controller | |
495 | */ | |
496 | ||
497 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
498 | .rev_offs = 0x0000, | |
499 | .sysc_offs = 0x0010, | |
500 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
501 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
502 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
503 | SIDLE_SMART_WKUP), | |
504 | .sysc_fields = &omap_hwmod_sysc_type2, | |
505 | }; | |
506 | ||
507 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
508 | .name = "dmic", | |
509 | .sysc = &omap44xx_dmic_sysc, | |
510 | }; | |
511 | ||
512 | /* dmic */ | |
8ca476da BC |
513 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
514 | .name = "dmic", | |
515 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 516 | .clkdm_name = "abe_clkdm", |
ee877acd | 517 | .main_clk = "func_dmic_abe_gfclk", |
00fe610b | 518 | .prcm = { |
8ca476da | 519 | .omap4 = { |
d0f0631d | 520 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 521 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 522 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
523 | }, |
524 | }, | |
8ca476da BC |
525 | }; |
526 | ||
8f25bdc5 BC |
527 | /* |
528 | * 'dsp' class | |
529 | * dsp sub-system | |
530 | */ | |
531 | ||
532 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 533 | .name = "dsp", |
8f25bdc5 BC |
534 | }; |
535 | ||
536 | /* dsp */ | |
8f25bdc5 | 537 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { |
8f25bdc5 BC |
538 | { .name = "dsp", .rst_shift = 0 }, |
539 | }; | |
540 | ||
8f25bdc5 BC |
541 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
542 | .name = "dsp", | |
543 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 544 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 BC |
545 | .rst_lines = omap44xx_dsp_resets, |
546 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
298ea44f | 547 | .main_clk = "dpll_iva_m4x2_ck", |
8f25bdc5 BC |
548 | .prcm = { |
549 | .omap4 = { | |
d0f0631d | 550 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 551 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 552 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 553 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
554 | }, |
555 | }, | |
8f25bdc5 BC |
556 | }; |
557 | ||
d63bd74f BC |
558 | /* |
559 | * 'dss' class | |
560 | * display sub-system | |
561 | */ | |
562 | ||
563 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
564 | .rev_offs = 0x0000, | |
565 | .syss_offs = 0x0014, | |
566 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
567 | }; | |
568 | ||
569 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
570 | .name = "dss", | |
571 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 572 | .reset = omap_dss_reset, |
d63bd74f BC |
573 | }; |
574 | ||
575 | /* dss */ | |
d63bd74f BC |
576 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
577 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
578 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 579 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
580 | }; |
581 | ||
582 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
583 | .name = "dss_core", | |
37ad0855 | 584 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 585 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 586 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 587 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
588 | .prcm = { |
589 | .omap4 = { | |
d0f0631d | 590 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 591 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
7ede8561 | 592 | .modulemode = MODULEMODE_SWCTRL, |
d63bd74f BC |
593 | }, |
594 | }, | |
595 | .opt_clks = dss_opt_clks, | |
596 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
597 | }; |
598 | ||
599 | /* | |
600 | * 'dispc' class | |
601 | * display controller | |
602 | */ | |
603 | ||
604 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
605 | .rev_offs = 0x0000, | |
606 | .sysc_offs = 0x0010, | |
607 | .syss_offs = 0x0014, | |
608 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
609 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
610 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
611 | SYSS_HAS_RESET_STATUS), | |
612 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
613 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
614 | .sysc_fields = &omap_hwmod_sysc_type1, | |
615 | }; | |
616 | ||
617 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
618 | .name = "dispc", | |
619 | .sysc = &omap44xx_dispc_sysc, | |
620 | }; | |
621 | ||
622 | /* dss_dispc */ | |
b38911f3 TV |
623 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
624 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
625 | { .irq = -1 } | |
626 | }; | |
627 | ||
628 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
629 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
630 | { .dma_req = -1 } | |
631 | }; | |
632 | ||
b923d40d AT |
633 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
634 | .manager_count = 3, | |
635 | .has_framedonetv_irq = 1 | |
636 | }; | |
637 | ||
d63bd74f BC |
638 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
639 | .name = "dss_dispc", | |
640 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 641 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 642 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
0fb22a8f | 643 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 644 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 645 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
646 | .prcm = { |
647 | .omap4 = { | |
d0f0631d | 648 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 649 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
650 | }, |
651 | }, | |
543b2847 TV |
652 | .dev_attr = &omap44xx_dss_dispc_dev_attr, |
653 | .parent_hwmod = &omap44xx_dss_hwmod, | |
d63bd74f BC |
654 | }; |
655 | ||
656 | /* | |
657 | * 'dsi' class | |
658 | * display serial interface controller | |
659 | */ | |
660 | ||
661 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
662 | .rev_offs = 0x0000, | |
663 | .sysc_offs = 0x0010, | |
664 | .syss_offs = 0x0014, | |
665 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
666 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
667 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
668 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
669 | .sysc_fields = &omap_hwmod_sysc_type1, | |
670 | }; | |
671 | ||
672 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
673 | .name = "dsi", | |
674 | .sysc = &omap44xx_dsi_sysc, | |
675 | }; | |
676 | ||
677 | /* dss_dsi1 */ | |
b38911f3 TV |
678 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
679 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
680 | { .irq = -1 } | |
681 | }; | |
682 | ||
683 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
684 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
685 | { .dma_req = -1 } | |
686 | }; | |
687 | ||
3a23aafc TV |
688 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
689 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
690 | }; | |
691 | ||
d63bd74f BC |
692 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
693 | .name = "dss_dsi1", | |
694 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 695 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 696 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
0fb22a8f | 697 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 698 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 699 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
700 | .prcm = { |
701 | .omap4 = { | |
d0f0631d | 702 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 703 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
704 | }, |
705 | }, | |
3a23aafc TV |
706 | .opt_clks = dss_dsi1_opt_clks, |
707 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
543b2847 | 708 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
709 | }; |
710 | ||
711 | /* dss_dsi2 */ | |
b38911f3 TV |
712 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
713 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
714 | { .irq = -1 } | |
715 | }; | |
716 | ||
717 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
718 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
719 | { .dma_req = -1 } | |
720 | }; | |
721 | ||
3a23aafc TV |
722 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
723 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
724 | }; | |
725 | ||
d63bd74f BC |
726 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
727 | .name = "dss_dsi2", | |
728 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 729 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 730 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
0fb22a8f | 731 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 732 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 733 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
734 | .prcm = { |
735 | .omap4 = { | |
d0f0631d | 736 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 737 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
738 | }, |
739 | }, | |
3a23aafc TV |
740 | .opt_clks = dss_dsi2_opt_clks, |
741 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
543b2847 | 742 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
743 | }; |
744 | ||
745 | /* | |
746 | * 'hdmi' class | |
747 | * hdmi controller | |
748 | */ | |
749 | ||
750 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
751 | .rev_offs = 0x0000, | |
752 | .sysc_offs = 0x0010, | |
753 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
754 | SYSC_HAS_SOFTRESET), | |
755 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
756 | SIDLE_SMART_WKUP), | |
757 | .sysc_fields = &omap_hwmod_sysc_type2, | |
758 | }; | |
759 | ||
760 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
761 | .name = "hdmi", | |
762 | .sysc = &omap44xx_hdmi_sysc, | |
763 | }; | |
764 | ||
765 | /* dss_hdmi */ | |
b38911f3 TV |
766 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
767 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
768 | { .irq = -1 } | |
769 | }; | |
770 | ||
771 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
772 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
773 | { .dma_req = -1 } | |
774 | }; | |
775 | ||
3a23aafc TV |
776 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
777 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
24d8d498 | 778 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
3a23aafc TV |
779 | }; |
780 | ||
d63bd74f BC |
781 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
782 | .name = "dss_hdmi", | |
783 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 784 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
785 | /* |
786 | * HDMI audio requires to use no-idle mode. Hence, | |
787 | * set idle mode by software. | |
788 | */ | |
24d8d498 | 789 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED, |
b38911f3 | 790 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
0fb22a8f | 791 | .xlate_irq = omap4_xlate_irq, |
b38911f3 | 792 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 793 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
794 | .prcm = { |
795 | .omap4 = { | |
d0f0631d | 796 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 797 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
798 | }, |
799 | }, | |
3a23aafc TV |
800 | .opt_clks = dss_hdmi_opt_clks, |
801 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
543b2847 | 802 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
803 | }; |
804 | ||
805 | /* | |
806 | * 'rfbi' class | |
807 | * remote frame buffer interface | |
808 | */ | |
809 | ||
810 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
811 | .rev_offs = 0x0000, | |
812 | .sysc_offs = 0x0010, | |
813 | .syss_offs = 0x0014, | |
814 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
815 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
816 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
817 | .sysc_fields = &omap_hwmod_sysc_type1, | |
818 | }; | |
819 | ||
820 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
821 | .name = "rfbi", | |
822 | .sysc = &omap44xx_rfbi_sysc, | |
823 | }; | |
824 | ||
825 | /* dss_rfbi */ | |
b38911f3 TV |
826 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
827 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
828 | { .dma_req = -1 } | |
829 | }; | |
830 | ||
3a23aafc | 831 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
2cc84f46 | 832 | { .role = "ick", .clk = "l3_div_ck" }, |
3a23aafc TV |
833 | }; |
834 | ||
d63bd74f BC |
835 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
836 | .name = "dss_rfbi", | |
837 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 838 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 839 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 840 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
841 | .prcm = { |
842 | .omap4 = { | |
d0f0631d | 843 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 844 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
845 | }, |
846 | }, | |
3a23aafc TV |
847 | .opt_clks = dss_rfbi_opt_clks, |
848 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
543b2847 | 849 | .parent_hwmod = &omap44xx_dss_hwmod, |
d63bd74f BC |
850 | }; |
851 | ||
852 | /* | |
853 | * 'venc' class | |
854 | * video encoder | |
855 | */ | |
856 | ||
857 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
858 | .name = "venc", | |
859 | }; | |
860 | ||
861 | /* dss_venc */ | |
24d8d498 TK |
862 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
863 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
864 | }; | |
865 | ||
d63bd74f BC |
866 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
867 | .name = "dss_venc", | |
868 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 869 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 870 | .main_clk = "dss_tv_clk", |
24d8d498 | 871 | .flags = HWMOD_OPT_CLKS_NEEDED, |
d63bd74f BC |
872 | .prcm = { |
873 | .omap4 = { | |
d0f0631d | 874 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 875 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
876 | }, |
877 | }, | |
543b2847 | 878 | .parent_hwmod = &omap44xx_dss_hwmod, |
24d8d498 TK |
879 | .opt_clks = dss_venc_opt_clks, |
880 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
d63bd74f BC |
881 | }; |
882 | ||
42b9e387 PW |
883 | /* |
884 | * 'elm' class | |
885 | * bch error location module | |
886 | */ | |
887 | ||
888 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
889 | .rev_offs = 0x0000, | |
890 | .sysc_offs = 0x0010, | |
891 | .syss_offs = 0x0014, | |
892 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
893 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
894 | SYSS_HAS_RESET_STATUS), | |
895 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
896 | .sysc_fields = &omap_hwmod_sysc_type1, | |
897 | }; | |
898 | ||
899 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
900 | .name = "elm", | |
901 | .sysc = &omap44xx_elm_sysc, | |
902 | }; | |
903 | ||
904 | /* elm */ | |
42b9e387 PW |
905 | static struct omap_hwmod omap44xx_elm_hwmod = { |
906 | .name = "elm", | |
907 | .class = &omap44xx_elm_hwmod_class, | |
908 | .clkdm_name = "l4_per_clkdm", | |
42b9e387 PW |
909 | .prcm = { |
910 | .omap4 = { | |
911 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
912 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
913 | }, | |
914 | }, | |
915 | }; | |
916 | ||
bf30f950 PW |
917 | /* |
918 | * 'emif' class | |
919 | * external memory interface no1 | |
920 | */ | |
921 | ||
922 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
923 | .rev_offs = 0x0000, | |
924 | }; | |
925 | ||
926 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
927 | .name = "emif", | |
928 | .sysc = &omap44xx_emif_sysc, | |
929 | }; | |
930 | ||
931 | /* emif1 */ | |
bf30f950 PW |
932 | static struct omap_hwmod omap44xx_emif1_hwmod = { |
933 | .name = "emif1", | |
934 | .class = &omap44xx_emif_hwmod_class, | |
935 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 936 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
937 | .main_clk = "ddrphy_ck", |
938 | .prcm = { | |
939 | .omap4 = { | |
940 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
941 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
942 | .modulemode = MODULEMODE_HWCTRL, | |
943 | }, | |
944 | }, | |
945 | }; | |
946 | ||
947 | /* emif2 */ | |
bf30f950 PW |
948 | static struct omap_hwmod omap44xx_emif2_hwmod = { |
949 | .name = "emif2", | |
950 | .class = &omap44xx_emif_hwmod_class, | |
951 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 952 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
953 | .main_clk = "ddrphy_ck", |
954 | .prcm = { | |
955 | .omap4 = { | |
956 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
957 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
958 | .modulemode = MODULEMODE_HWCTRL, | |
959 | }, | |
960 | }, | |
961 | }; | |
962 | ||
9a9ded89 SR |
963 | /* |
964 | Crypto modules AES0/1 belong to: | |
965 | PD_L4_PER power domain | |
966 | CD_L4_SEC clock domain | |
967 | On the L3, the AES modules are mapped to | |
968 | L3_CLK2: Peripherals and multimedia sub clock domain | |
969 | */ | |
970 | static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = { | |
971 | .rev_offs = 0x80, | |
972 | .sysc_offs = 0x84, | |
973 | .syss_offs = 0x88, | |
974 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
975 | }; | |
976 | ||
977 | static struct omap_hwmod_class omap44xx_aes_hwmod_class = { | |
978 | .name = "aes", | |
979 | .sysc = &omap44xx_aes_sysc, | |
980 | }; | |
981 | ||
982 | static struct omap_hwmod omap44xx_aes1_hwmod = { | |
983 | .name = "aes1", | |
984 | .class = &omap44xx_aes_hwmod_class, | |
985 | .clkdm_name = "l4_secure_clkdm", | |
986 | .main_clk = "l3_div_ck", | |
987 | .prcm = { | |
988 | .omap4 = { | |
989 | .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET, | |
990 | .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET, | |
991 | .modulemode = MODULEMODE_SWCTRL, | |
992 | }, | |
993 | }, | |
994 | }; | |
995 | ||
996 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = { | |
997 | .master = &omap44xx_l4_per_hwmod, | |
998 | .slave = &omap44xx_aes1_hwmod, | |
999 | .clk = "l3_div_ck", | |
1000 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1001 | }; | |
1002 | ||
478523dd SR |
1003 | static struct omap_hwmod omap44xx_aes2_hwmod = { |
1004 | .name = "aes2", | |
1005 | .class = &omap44xx_aes_hwmod_class, | |
1006 | .clkdm_name = "l4_secure_clkdm", | |
1007 | .main_clk = "l3_div_ck", | |
1008 | .prcm = { | |
1009 | .omap4 = { | |
1010 | .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET, | |
1011 | .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET, | |
1012 | .modulemode = MODULEMODE_SWCTRL, | |
1013 | }, | |
1014 | }, | |
1015 | }; | |
1016 | ||
1017 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = { | |
1018 | .master = &omap44xx_l4_per_hwmod, | |
1019 | .slave = &omap44xx_aes2_hwmod, | |
1020 | .clk = "l3_div_ck", | |
1021 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1022 | }; | |
1023 | ||
ebea90df SR |
1024 | /* |
1025 | * 'des' class for DES3DES module | |
1026 | */ | |
1027 | static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = { | |
1028 | .rev_offs = 0x30, | |
1029 | .sysc_offs = 0x34, | |
1030 | .syss_offs = 0x38, | |
1031 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
1032 | }; | |
1033 | ||
1034 | static struct omap_hwmod_class omap44xx_des_hwmod_class = { | |
1035 | .name = "des", | |
1036 | .sysc = &omap44xx_des_sysc, | |
1037 | }; | |
1038 | ||
1039 | static struct omap_hwmod omap44xx_des_hwmod = { | |
1040 | .name = "des", | |
1041 | .class = &omap44xx_des_hwmod_class, | |
1042 | .clkdm_name = "l4_secure_clkdm", | |
1043 | .main_clk = "l3_div_ck", | |
1044 | .prcm = { | |
1045 | .omap4 = { | |
1046 | .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET, | |
1047 | .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET, | |
1048 | .modulemode = MODULEMODE_SWCTRL, | |
1049 | }, | |
1050 | }, | |
1051 | }; | |
1052 | ||
1053 | struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = { | |
1054 | .master = &omap44xx_l3_main_2_hwmod, | |
1055 | .slave = &omap44xx_des_hwmod, | |
1056 | .clk = "l3_div_ck", | |
1057 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1058 | }; | |
1059 | ||
b050f688 ML |
1060 | /* |
1061 | * 'fdif' class | |
1062 | * face detection hw accelerator module | |
1063 | */ | |
1064 | ||
1065 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
1066 | .rev_offs = 0x0000, | |
1067 | .sysc_offs = 0x0010, | |
1068 | /* | |
1069 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
1070 | * accessing sysconfig again. | |
1071 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1072 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1073 | * | |
1074 | * TODO: Indicate errata when available. | |
1075 | */ | |
1076 | .srst_udelay = 2, | |
1077 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
1078 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1079 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1080 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1081 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1082 | }; | |
1083 | ||
1084 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1085 | .name = "fdif", | |
1086 | .sysc = &omap44xx_fdif_sysc, | |
1087 | }; | |
1088 | ||
1089 | /* fdif */ | |
b050f688 ML |
1090 | static struct omap_hwmod omap44xx_fdif_hwmod = { |
1091 | .name = "fdif", | |
1092 | .class = &omap44xx_fdif_hwmod_class, | |
1093 | .clkdm_name = "iss_clkdm", | |
b050f688 ML |
1094 | .main_clk = "fdif_fck", |
1095 | .prcm = { | |
1096 | .omap4 = { | |
1097 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1098 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1099 | .modulemode = MODULEMODE_SWCTRL, | |
1100 | }, | |
1101 | }, | |
1102 | }; | |
1103 | ||
3b54baad BC |
1104 | /* |
1105 | * 'gpio' class | |
1106 | * general purpose io module | |
1107 | */ | |
1108 | ||
1109 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1110 | .rev_offs = 0x0000, | |
f776471f | 1111 | .sysc_offs = 0x0010, |
3b54baad | 1112 | .syss_offs = 0x0114, |
0cfe8751 BC |
1113 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1114 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1115 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1116 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1117 | SIDLE_SMART_WKUP), | |
f776471f BC |
1118 | .sysc_fields = &omap_hwmod_sysc_type1, |
1119 | }; | |
1120 | ||
3b54baad | 1121 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1122 | .name = "gpio", |
1123 | .sysc = &omap44xx_gpio_sysc, | |
1124 | .rev = 2, | |
f776471f BC |
1125 | }; |
1126 | ||
3b54baad BC |
1127 | /* gpio dev_attr */ |
1128 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1129 | .bank_width = 32, |
1130 | .dbck_flag = true, | |
f776471f BC |
1131 | }; |
1132 | ||
3b54baad | 1133 | /* gpio1 */ |
3b54baad | 1134 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1135 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1136 | }; |
1137 | ||
1138 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1139 | .name = "gpio1", | |
1140 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1141 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 1142 | .main_clk = "l4_wkup_clk_mux_ck", |
f776471f BC |
1143 | .prcm = { |
1144 | .omap4 = { | |
d0f0631d | 1145 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1146 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1147 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1148 | }, |
1149 | }, | |
3b54baad BC |
1150 | .opt_clks = gpio1_opt_clks, |
1151 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1152 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1153 | }; |
1154 | ||
3b54baad | 1155 | /* gpio2 */ |
3b54baad | 1156 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1157 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1158 | }; |
1159 | ||
1160 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1161 | .name = "gpio2", | |
1162 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1163 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1164 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1165 | .main_clk = "l4_div_ck", |
f776471f BC |
1166 | .prcm = { |
1167 | .omap4 = { | |
d0f0631d | 1168 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1169 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1170 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1171 | }, |
1172 | }, | |
3b54baad BC |
1173 | .opt_clks = gpio2_opt_clks, |
1174 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1175 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1176 | }; |
1177 | ||
3b54baad | 1178 | /* gpio3 */ |
3b54baad | 1179 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1180 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1181 | }; |
1182 | ||
1183 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1184 | .name = "gpio3", | |
1185 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1186 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1187 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1188 | .main_clk = "l4_div_ck", |
f776471f BC |
1189 | .prcm = { |
1190 | .omap4 = { | |
d0f0631d | 1191 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1192 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1193 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1194 | }, |
1195 | }, | |
3b54baad BC |
1196 | .opt_clks = gpio3_opt_clks, |
1197 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1198 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1199 | }; |
1200 | ||
3b54baad | 1201 | /* gpio4 */ |
3b54baad | 1202 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1203 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1204 | }; |
1205 | ||
1206 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1207 | .name = "gpio4", | |
1208 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1209 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1210 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1211 | .main_clk = "l4_div_ck", |
f776471f BC |
1212 | .prcm = { |
1213 | .omap4 = { | |
d0f0631d | 1214 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1215 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1216 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1217 | }, |
1218 | }, | |
3b54baad BC |
1219 | .opt_clks = gpio4_opt_clks, |
1220 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1221 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1222 | }; |
1223 | ||
3b54baad | 1224 | /* gpio5 */ |
844a3b63 PW |
1225 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1226 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1227 | }; |
1228 | ||
3b54baad BC |
1229 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1230 | .name = "gpio5", | |
1231 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1232 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1233 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1234 | .main_clk = "l4_div_ck", |
55d2cb08 BC |
1235 | .prcm = { |
1236 | .omap4 = { | |
d0f0631d | 1237 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1238 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1239 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1240 | }, |
1241 | }, | |
3b54baad BC |
1242 | .opt_clks = gpio5_opt_clks, |
1243 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1244 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1245 | }; |
1246 | ||
3b54baad | 1247 | /* gpio6 */ |
3b54baad | 1248 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1249 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1250 | }; |
1251 | ||
3b54baad BC |
1252 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1253 | .name = "gpio6", | |
1254 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1255 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1256 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1257 | .main_clk = "l4_div_ck", |
3b54baad BC |
1258 | .prcm = { |
1259 | .omap4 = { | |
d0f0631d | 1260 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1261 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1262 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1263 | }, |
db12ba53 | 1264 | }, |
3b54baad BC |
1265 | .opt_clks = gpio6_opt_clks, |
1266 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1267 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1268 | }; |
1269 | ||
eb42b5d3 BC |
1270 | /* |
1271 | * 'gpmc' class | |
1272 | * general purpose memory controller | |
1273 | */ | |
1274 | ||
1275 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1276 | .rev_offs = 0x0000, | |
1277 | .sysc_offs = 0x0010, | |
1278 | .syss_offs = 0x0014, | |
1279 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1280 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1281 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1282 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1283 | }; | |
1284 | ||
1285 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1286 | .name = "gpmc", | |
1287 | .sysc = &omap44xx_gpmc_sysc, | |
1288 | }; | |
1289 | ||
1290 | /* gpmc */ | |
eb42b5d3 BC |
1291 | static struct omap_hwmod omap44xx_gpmc_hwmod = { |
1292 | .name = "gpmc", | |
1293 | .class = &omap44xx_gpmc_hwmod_class, | |
1294 | .clkdm_name = "l3_2_clkdm", | |
63aa945b TL |
1295 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
1296 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
eb42b5d3 BC |
1297 | .prcm = { |
1298 | .omap4 = { | |
1299 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1300 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1301 | .modulemode = MODULEMODE_HWCTRL, | |
1302 | }, | |
1303 | }, | |
1304 | }; | |
1305 | ||
9def390e PW |
1306 | /* |
1307 | * 'gpu' class | |
1308 | * 2d/3d graphics accelerator | |
1309 | */ | |
1310 | ||
1311 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1312 | .rev_offs = 0x1fc00, | |
1313 | .sysc_offs = 0x1fc10, | |
1314 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1315 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1316 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1317 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1318 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1319 | }; | |
1320 | ||
1321 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1322 | .name = "gpu", | |
1323 | .sysc = &omap44xx_gpu_sysc, | |
1324 | }; | |
1325 | ||
1326 | /* gpu */ | |
9def390e PW |
1327 | static struct omap_hwmod omap44xx_gpu_hwmod = { |
1328 | .name = "gpu", | |
1329 | .class = &omap44xx_gpu_hwmod_class, | |
1330 | .clkdm_name = "l3_gfx_clkdm", | |
ee877acd | 1331 | .main_clk = "sgx_clk_mux", |
9def390e PW |
1332 | .prcm = { |
1333 | .omap4 = { | |
1334 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1335 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1336 | .modulemode = MODULEMODE_SWCTRL, | |
1337 | }, | |
1338 | }, | |
1339 | }; | |
1340 | ||
a091c08e PW |
1341 | /* |
1342 | * 'hdq1w' class | |
1343 | * hdq / 1-wire serial interface controller | |
1344 | */ | |
1345 | ||
1346 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1347 | .rev_offs = 0x0000, | |
1348 | .sysc_offs = 0x0014, | |
1349 | .syss_offs = 0x0018, | |
1350 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1351 | SYSS_HAS_RESET_STATUS), | |
1352 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1353 | }; | |
1354 | ||
1355 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1356 | .name = "hdq1w", | |
1357 | .sysc = &omap44xx_hdq1w_sysc, | |
1358 | }; | |
1359 | ||
1360 | /* hdq1w */ | |
a091c08e PW |
1361 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { |
1362 | .name = "hdq1w", | |
1363 | .class = &omap44xx_hdq1w_hwmod_class, | |
1364 | .clkdm_name = "l4_per_clkdm", | |
1365 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
17b7e7d3 | 1366 | .main_clk = "func_12m_fclk", |
a091c08e PW |
1367 | .prcm = { |
1368 | .omap4 = { | |
1369 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1370 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1371 | .modulemode = MODULEMODE_SWCTRL, | |
1372 | }, | |
1373 | }, | |
1374 | }; | |
1375 | ||
407a6888 BC |
1376 | /* |
1377 | * 'hsi' class | |
1378 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1379 | * serial if) | |
1380 | */ | |
1381 | ||
1382 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1383 | .rev_offs = 0x0000, | |
1384 | .sysc_offs = 0x0010, | |
1385 | .syss_offs = 0x0014, | |
1386 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1387 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1388 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1389 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1390 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1391 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1392 | .sysc_fields = &omap_hwmod_sysc_type1, |
1393 | }; | |
1394 | ||
1395 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1396 | .name = "hsi", | |
1397 | .sysc = &omap44xx_hsi_sysc, | |
1398 | }; | |
1399 | ||
1400 | /* hsi */ | |
407a6888 BC |
1401 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1402 | .name = "hsi", | |
1403 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1404 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1405 | .main_clk = "hsi_fck", |
00fe610b | 1406 | .prcm = { |
407a6888 | 1407 | .omap4 = { |
d0f0631d | 1408 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1409 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1410 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1411 | }, |
1412 | }, | |
407a6888 BC |
1413 | }; |
1414 | ||
3b54baad BC |
1415 | /* |
1416 | * 'i2c' class | |
1417 | * multimaster high-speed i2c controller | |
1418 | */ | |
db12ba53 | 1419 | |
3b54baad BC |
1420 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1421 | .sysc_offs = 0x0010, | |
1422 | .syss_offs = 0x0090, | |
1423 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1424 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1425 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1426 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1427 | SIDLE_SMART_WKUP), | |
3b54baad | 1428 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1429 | }; |
1430 | ||
3b54baad | 1431 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1432 | .name = "i2c", |
1433 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1434 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1435 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1436 | }; |
1437 | ||
4d4441a6 | 1438 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
972deb4f | 1439 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
4d4441a6 AG |
1440 | }; |
1441 | ||
3b54baad | 1442 | /* i2c1 */ |
3b54baad BC |
1443 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1444 | .name = "i2c1", | |
1445 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1446 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1447 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1448 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1449 | .prcm = { |
1450 | .omap4 = { | |
d0f0631d | 1451 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1452 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1453 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1454 | }, |
1455 | }, | |
4d4441a6 | 1456 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1457 | }; |
1458 | ||
3b54baad | 1459 | /* i2c2 */ |
3b54baad BC |
1460 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1461 | .name = "i2c2", | |
1462 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1463 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1464 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1465 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1466 | .prcm = { |
1467 | .omap4 = { | |
d0f0631d | 1468 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1469 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1470 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1471 | }, |
1472 | }, | |
4d4441a6 | 1473 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1474 | }; |
1475 | ||
3b54baad | 1476 | /* i2c3 */ |
3b54baad BC |
1477 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1478 | .name = "i2c3", | |
1479 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1480 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1481 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1482 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1483 | .prcm = { |
1484 | .omap4 = { | |
d0f0631d | 1485 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1486 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1487 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1488 | }, |
1489 | }, | |
4d4441a6 | 1490 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1491 | }; |
1492 | ||
3b54baad | 1493 | /* i2c4 */ |
3b54baad BC |
1494 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1495 | .name = "i2c4", | |
1496 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1497 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1498 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1499 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1500 | .prcm = { |
1501 | .omap4 = { | |
d0f0631d | 1502 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1503 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1504 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1505 | }, |
1506 | }, | |
4d4441a6 | 1507 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1508 | }; |
1509 | ||
407a6888 BC |
1510 | /* |
1511 | * 'ipu' class | |
1512 | * imaging processor unit | |
1513 | */ | |
1514 | ||
1515 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1516 | .name = "ipu", | |
1517 | }; | |
1518 | ||
1519 | /* ipu */ | |
f2f5736c | 1520 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1521 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1522 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1523 | }; |
1524 | ||
407a6888 BC |
1525 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1526 | .name = "ipu", | |
1527 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1528 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
1529 | .rst_lines = omap44xx_ipu_resets, |
1530 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
298ea44f | 1531 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1532 | .prcm = { |
407a6888 | 1533 | .omap4 = { |
d0f0631d | 1534 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1535 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1536 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1537 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1538 | }, |
1539 | }, | |
407a6888 BC |
1540 | }; |
1541 | ||
1542 | /* | |
1543 | * 'iss' class | |
1544 | * external images sensor pixel data processor | |
1545 | */ | |
1546 | ||
1547 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1548 | .rev_offs = 0x0000, | |
1549 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1550 | /* |
1551 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1552 | * accessing sysconfig again. | |
1553 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1554 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1555 | * | |
1556 | * TODO: Indicate errata when available. | |
1557 | */ | |
1558 | .srst_udelay = 2, | |
407a6888 BC |
1559 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1560 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1561 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1562 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1563 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1564 | .sysc_fields = &omap_hwmod_sysc_type2, |
1565 | }; | |
1566 | ||
1567 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1568 | .name = "iss", | |
1569 | .sysc = &omap44xx_iss_sysc, | |
1570 | }; | |
1571 | ||
1572 | /* iss */ | |
407a6888 BC |
1573 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1574 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1575 | }; | |
1576 | ||
1577 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1578 | .name = "iss", | |
1579 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1580 | .clkdm_name = "iss_clkdm", |
17b7e7d3 | 1581 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1582 | .prcm = { |
407a6888 | 1583 | .omap4 = { |
d0f0631d | 1584 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1585 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1586 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1587 | }, |
1588 | }, | |
1589 | .opt_clks = iss_opt_clks, | |
1590 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1591 | }; |
1592 | ||
8f25bdc5 BC |
1593 | /* |
1594 | * 'iva' class | |
1595 | * multi-standard video encoder/decoder hardware accelerator | |
1596 | */ | |
1597 | ||
1598 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1599 | .name = "iva", |
8f25bdc5 BC |
1600 | }; |
1601 | ||
1602 | /* iva */ | |
8f25bdc5 | 1603 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { |
8f25bdc5 | 1604 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1605 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1606 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1607 | }; |
1608 | ||
8f25bdc5 BC |
1609 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1610 | .name = "iva", | |
1611 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1612 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
1613 | .rst_lines = omap44xx_iva_resets, |
1614 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
17b7e7d3 | 1615 | .main_clk = "dpll_iva_m5x2_ck", |
8f25bdc5 BC |
1616 | .prcm = { |
1617 | .omap4 = { | |
d0f0631d | 1618 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1619 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1620 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1621 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1622 | }, |
1623 | }, | |
8f25bdc5 BC |
1624 | }; |
1625 | ||
407a6888 BC |
1626 | /* |
1627 | * 'kbd' class | |
1628 | * keyboard controller | |
1629 | */ | |
1630 | ||
1631 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1632 | .rev_offs = 0x0000, | |
1633 | .sysc_offs = 0x0010, | |
1634 | .syss_offs = 0x0014, | |
1635 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1636 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1637 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1638 | SYSS_HAS_RESET_STATUS), | |
1639 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1640 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1641 | }; | |
1642 | ||
1643 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1644 | .name = "kbd", | |
1645 | .sysc = &omap44xx_kbd_sysc, | |
1646 | }; | |
1647 | ||
1648 | /* kbd */ | |
407a6888 BC |
1649 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1650 | .name = "kbd", | |
1651 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1652 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 1653 | .main_clk = "sys_32k_ck", |
00fe610b | 1654 | .prcm = { |
407a6888 | 1655 | .omap4 = { |
d0f0631d | 1656 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1657 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1658 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1659 | }, |
1660 | }, | |
407a6888 BC |
1661 | }; |
1662 | ||
ec5df927 BC |
1663 | /* |
1664 | * 'mailbox' class | |
1665 | * mailbox module allowing communication between the on-chip processors using a | |
1666 | * queued mailbox-interrupt mechanism. | |
1667 | */ | |
1668 | ||
1669 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1670 | .rev_offs = 0x0000, | |
1671 | .sysc_offs = 0x0010, | |
1672 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1673 | SYSC_HAS_SOFTRESET), | |
1674 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1675 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1676 | }; | |
1677 | ||
1678 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1679 | .name = "mailbox", | |
1680 | .sysc = &omap44xx_mailbox_sysc, | |
1681 | }; | |
1682 | ||
1683 | /* mailbox */ | |
ec5df927 BC |
1684 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1685 | .name = "mailbox", | |
1686 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1687 | .clkdm_name = "l4_cfg_clkdm", |
00fe610b | 1688 | .prcm = { |
ec5df927 | 1689 | .omap4 = { |
d0f0631d | 1690 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1691 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1692 | }, |
1693 | }, | |
ec5df927 BC |
1694 | }; |
1695 | ||
896d4e98 BC |
1696 | /* |
1697 | * 'mcasp' class | |
1698 | * multi-channel audio serial port controller | |
1699 | */ | |
1700 | ||
1701 | /* The IP is not compliant to type1 / type2 scheme */ | |
1702 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1703 | .sidle_shift = 0, | |
1704 | }; | |
1705 | ||
1706 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1707 | .sysc_offs = 0x0004, | |
1708 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1709 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1710 | SIDLE_SMART_WKUP), | |
1711 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1712 | }; | |
1713 | ||
1714 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1715 | .name = "mcasp", | |
1716 | .sysc = &omap44xx_mcasp_sysc, | |
1717 | }; | |
1718 | ||
1719 | /* mcasp */ | |
896d4e98 BC |
1720 | static struct omap_hwmod omap44xx_mcasp_hwmod = { |
1721 | .name = "mcasp", | |
1722 | .class = &omap44xx_mcasp_hwmod_class, | |
1723 | .clkdm_name = "abe_clkdm", | |
ee877acd | 1724 | .main_clk = "func_mcasp_abe_gfclk", |
896d4e98 BC |
1725 | .prcm = { |
1726 | .omap4 = { | |
1727 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1728 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1729 | .modulemode = MODULEMODE_SWCTRL, | |
1730 | }, | |
1731 | }, | |
1732 | }; | |
1733 | ||
4ddff493 BC |
1734 | /* |
1735 | * 'mcbsp' class | |
1736 | * multi channel buffered serial port controller | |
1737 | */ | |
1738 | ||
1739 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1740 | .sysc_offs = 0x008c, | |
1741 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1742 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1743 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1744 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1745 | }; | |
1746 | ||
1747 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1748 | .name = "mcbsp", | |
1749 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1750 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1751 | }; |
1752 | ||
1753 | /* mcbsp1 */ | |
503d0ea2 PW |
1754 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1755 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1756 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1757 | }; |
1758 | ||
4ddff493 BC |
1759 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1760 | .name = "mcbsp1", | |
1761 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1762 | .clkdm_name = "abe_clkdm", |
ee877acd | 1763 | .main_clk = "func_mcbsp1_gfclk", |
4ddff493 BC |
1764 | .prcm = { |
1765 | .omap4 = { | |
d0f0631d | 1766 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1767 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1768 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1769 | }, |
1770 | }, | |
503d0ea2 PW |
1771 | .opt_clks = mcbsp1_opt_clks, |
1772 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1773 | }; |
1774 | ||
1775 | /* mcbsp2 */ | |
844a3b63 PW |
1776 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1777 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1778 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
1779 | }; |
1780 | ||
4ddff493 BC |
1781 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1782 | .name = "mcbsp2", | |
1783 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1784 | .clkdm_name = "abe_clkdm", |
ee877acd | 1785 | .main_clk = "func_mcbsp2_gfclk", |
4ddff493 BC |
1786 | .prcm = { |
1787 | .omap4 = { | |
d0f0631d | 1788 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1789 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1790 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1791 | }, |
1792 | }, | |
503d0ea2 PW |
1793 | .opt_clks = mcbsp2_opt_clks, |
1794 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1795 | }; |
1796 | ||
1797 | /* mcbsp3 */ | |
503d0ea2 PW |
1798 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1799 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1800 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
1801 | }; |
1802 | ||
4ddff493 BC |
1803 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1804 | .name = "mcbsp3", | |
1805 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1806 | .clkdm_name = "abe_clkdm", |
ee877acd | 1807 | .main_clk = "func_mcbsp3_gfclk", |
4ddff493 BC |
1808 | .prcm = { |
1809 | .omap4 = { | |
d0f0631d | 1810 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1811 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1812 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1813 | }, |
1814 | }, | |
503d0ea2 PW |
1815 | .opt_clks = mcbsp3_opt_clks, |
1816 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1817 | }; |
1818 | ||
1819 | /* mcbsp4 */ | |
503d0ea2 PW |
1820 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
1821 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1822 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
1823 | }; |
1824 | ||
4ddff493 BC |
1825 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
1826 | .name = "mcbsp4", | |
1827 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1828 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 1829 | .main_clk = "per_mcbsp4_gfclk", |
4ddff493 BC |
1830 | .prcm = { |
1831 | .omap4 = { | |
d0f0631d | 1832 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 1833 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 1834 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1835 | }, |
1836 | }, | |
503d0ea2 PW |
1837 | .opt_clks = mcbsp4_opt_clks, |
1838 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
1839 | }; |
1840 | ||
407a6888 BC |
1841 | /* |
1842 | * 'mcpdm' class | |
1843 | * multi channel pdm controller (proprietary interface with phoenix power | |
1844 | * ic) | |
1845 | */ | |
1846 | ||
1847 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
1848 | .rev_offs = 0x0000, | |
1849 | .sysc_offs = 0x0010, | |
1850 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1851 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1852 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1853 | SIDLE_SMART_WKUP), | |
1854 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1855 | }; | |
1856 | ||
1857 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
1858 | .name = "mcpdm", | |
1859 | .sysc = &omap44xx_mcpdm_sysc, | |
1860 | }; | |
1861 | ||
1862 | /* mcpdm */ | |
407a6888 BC |
1863 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
1864 | .name = "mcpdm", | |
1865 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 1866 | .clkdm_name = "abe_clkdm", |
bc05244e PW |
1867 | /* |
1868 | * It's suspected that the McPDM requires an off-chip main | |
1869 | * functional clock, controlled via I2C. This IP block is | |
1870 | * currently reset very early during boot, before I2C is | |
1871 | * available, so it doesn't seem that we have any choice in | |
1872 | * the kernel other than to avoid resetting it. | |
12d82e4b PU |
1873 | * |
1874 | * Also, McPDM needs to be configured to NO_IDLE mode when it | |
1875 | * is in used otherwise vital clocks will be gated which | |
1876 | * results 'slow motion' audio playback. | |
bc05244e | 1877 | */ |
12d82e4b | 1878 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, |
17b7e7d3 | 1879 | .main_clk = "pad_clks_ck", |
00fe610b | 1880 | .prcm = { |
407a6888 | 1881 | .omap4 = { |
d0f0631d | 1882 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 1883 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 1884 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1885 | }, |
1886 | }, | |
407a6888 BC |
1887 | }; |
1888 | ||
9bcbd7f0 BC |
1889 | /* |
1890 | * 'mcspi' class | |
1891 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1892 | * bus | |
1893 | */ | |
1894 | ||
1895 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
1896 | .rev_offs = 0x0000, | |
1897 | .sysc_offs = 0x0010, | |
1898 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1899 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1900 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1901 | SIDLE_SMART_WKUP), | |
1902 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1903 | }; | |
1904 | ||
1905 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
1906 | .name = "mcspi", | |
1907 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 1908 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
1909 | }; |
1910 | ||
1911 | /* mcspi1 */ | |
9bcbd7f0 BC |
1912 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { |
1913 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
1914 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
1915 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
1916 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
1917 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
1918 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
1919 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
1920 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1921 | { .dma_req = -1 } |
9bcbd7f0 BC |
1922 | }; |
1923 | ||
905a74d9 BC |
1924 | /* mcspi1 dev_attr */ |
1925 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
1926 | .num_chipselect = 4, | |
1927 | }; | |
1928 | ||
9bcbd7f0 BC |
1929 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
1930 | .name = "mcspi1", | |
1931 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1932 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1933 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
17b7e7d3 | 1934 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1935 | .prcm = { |
1936 | .omap4 = { | |
d0f0631d | 1937 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 1938 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 1939 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1940 | }, |
1941 | }, | |
905a74d9 | 1942 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
1943 | }; |
1944 | ||
1945 | /* mcspi2 */ | |
9bcbd7f0 BC |
1946 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { |
1947 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
1948 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
1949 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
1950 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1951 | { .dma_req = -1 } |
9bcbd7f0 BC |
1952 | }; |
1953 | ||
905a74d9 BC |
1954 | /* mcspi2 dev_attr */ |
1955 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
1956 | .num_chipselect = 2, | |
1957 | }; | |
1958 | ||
9bcbd7f0 BC |
1959 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
1960 | .name = "mcspi2", | |
1961 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1962 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1963 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
17b7e7d3 | 1964 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1965 | .prcm = { |
1966 | .omap4 = { | |
d0f0631d | 1967 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 1968 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 1969 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1970 | }, |
1971 | }, | |
905a74d9 | 1972 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
1973 | }; |
1974 | ||
1975 | /* mcspi3 */ | |
9bcbd7f0 BC |
1976 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { |
1977 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
1978 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
1979 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
1980 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1981 | { .dma_req = -1 } |
9bcbd7f0 BC |
1982 | }; |
1983 | ||
905a74d9 BC |
1984 | /* mcspi3 dev_attr */ |
1985 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
1986 | .num_chipselect = 2, | |
1987 | }; | |
1988 | ||
9bcbd7f0 BC |
1989 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
1990 | .name = "mcspi3", | |
1991 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1992 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1993 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
17b7e7d3 | 1994 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1995 | .prcm = { |
1996 | .omap4 = { | |
d0f0631d | 1997 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 1998 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 1999 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2000 | }, |
2001 | }, | |
905a74d9 | 2002 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2003 | }; |
2004 | ||
2005 | /* mcspi4 */ | |
9bcbd7f0 BC |
2006 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { |
2007 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2008 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2009 | { .dma_req = -1 } |
9bcbd7f0 BC |
2010 | }; |
2011 | ||
905a74d9 BC |
2012 | /* mcspi4 dev_attr */ |
2013 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2014 | .num_chipselect = 1, | |
2015 | }; | |
2016 | ||
9bcbd7f0 BC |
2017 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2018 | .name = "mcspi4", | |
2019 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2020 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2021 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
17b7e7d3 | 2022 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
2023 | .prcm = { |
2024 | .omap4 = { | |
d0f0631d | 2025 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2026 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2027 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2028 | }, |
2029 | }, | |
905a74d9 | 2030 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2031 | }; |
2032 | ||
407a6888 BC |
2033 | /* |
2034 | * 'mmc' class | |
2035 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2036 | */ | |
2037 | ||
2038 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2039 | .rev_offs = 0x0000, | |
2040 | .sysc_offs = 0x0010, | |
2041 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2042 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2043 | SYSC_HAS_SOFTRESET), | |
2044 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2045 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2046 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2047 | .sysc_fields = &omap_hwmod_sysc_type2, |
2048 | }; | |
2049 | ||
2050 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2051 | .name = "mmc", | |
2052 | .sysc = &omap44xx_mmc_sysc, | |
2053 | }; | |
2054 | ||
2055 | /* mmc1 */ | |
407a6888 BC |
2056 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { |
2057 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2058 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2059 | { .dma_req = -1 } |
407a6888 BC |
2060 | }; |
2061 | ||
6ab8946f | 2062 | /* mmc1 dev_attr */ |
55143438 | 2063 | static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
6ab8946f KK |
2064 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
2065 | }; | |
2066 | ||
407a6888 BC |
2067 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2068 | .name = "mmc1", | |
2069 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2070 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2071 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
ee877acd | 2072 | .main_clk = "hsmmc1_fclk", |
00fe610b | 2073 | .prcm = { |
407a6888 | 2074 | .omap4 = { |
d0f0631d | 2075 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2076 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2077 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2078 | }, |
2079 | }, | |
6ab8946f | 2080 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2081 | }; |
2082 | ||
2083 | /* mmc2 */ | |
407a6888 BC |
2084 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { |
2085 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2086 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2087 | { .dma_req = -1 } |
407a6888 BC |
2088 | }; |
2089 | ||
407a6888 BC |
2090 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2091 | .name = "mmc2", | |
2092 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2093 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2094 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
ee877acd | 2095 | .main_clk = "hsmmc2_fclk", |
00fe610b | 2096 | .prcm = { |
407a6888 | 2097 | .omap4 = { |
d0f0631d | 2098 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2099 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2100 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2101 | }, |
2102 | }, | |
407a6888 BC |
2103 | }; |
2104 | ||
2105 | /* mmc3 */ | |
407a6888 BC |
2106 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { |
2107 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2108 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2109 | { .dma_req = -1 } |
407a6888 BC |
2110 | }; |
2111 | ||
407a6888 BC |
2112 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2113 | .name = "mmc3", | |
2114 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2115 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2116 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
17b7e7d3 | 2117 | .main_clk = "func_48m_fclk", |
00fe610b | 2118 | .prcm = { |
407a6888 | 2119 | .omap4 = { |
d0f0631d | 2120 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2121 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2122 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2123 | }, |
2124 | }, | |
407a6888 BC |
2125 | }; |
2126 | ||
2127 | /* mmc4 */ | |
407a6888 BC |
2128 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { |
2129 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2130 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2131 | { .dma_req = -1 } |
407a6888 BC |
2132 | }; |
2133 | ||
407a6888 BC |
2134 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2135 | .name = "mmc4", | |
2136 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2137 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2138 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
17b7e7d3 | 2139 | .main_clk = "func_48m_fclk", |
00fe610b | 2140 | .prcm = { |
407a6888 | 2141 | .omap4 = { |
d0f0631d | 2142 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2143 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2144 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2145 | }, |
2146 | }, | |
407a6888 BC |
2147 | }; |
2148 | ||
2149 | /* mmc5 */ | |
407a6888 BC |
2150 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { |
2151 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2152 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2153 | { .dma_req = -1 } |
407a6888 BC |
2154 | }; |
2155 | ||
407a6888 BC |
2156 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2157 | .name = "mmc5", | |
2158 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2159 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2160 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
17b7e7d3 | 2161 | .main_clk = "func_48m_fclk", |
00fe610b | 2162 | .prcm = { |
407a6888 | 2163 | .omap4 = { |
d0f0631d | 2164 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2165 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2166 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2167 | }, |
2168 | }, | |
407a6888 BC |
2169 | }; |
2170 | ||
230844db ORL |
2171 | /* |
2172 | * 'mmu' class | |
2173 | * The memory management unit performs virtual to physical address translation | |
2174 | * for its requestors. | |
2175 | */ | |
2176 | ||
2177 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2178 | .rev_offs = 0x000, | |
2179 | .sysc_offs = 0x010, | |
2180 | .syss_offs = 0x014, | |
2181 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2182 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2183 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2184 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2185 | }; | |
2186 | ||
2187 | static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { | |
2188 | .name = "mmu", | |
2189 | .sysc = &mmu_sysc, | |
2190 | }; | |
2191 | ||
2192 | /* mmu ipu */ | |
2193 | ||
230844db | 2194 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; |
230844db ORL |
2195 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { |
2196 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2197 | }; | |
2198 | ||
230844db ORL |
2199 | /* l3_main_2 -> mmu_ipu */ |
2200 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { | |
2201 | .master = &omap44xx_l3_main_2_hwmod, | |
2202 | .slave = &omap44xx_mmu_ipu_hwmod, | |
2203 | .clk = "l3_div_ck", | |
230844db ORL |
2204 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2205 | }; | |
2206 | ||
2207 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |
2208 | .name = "mmu_ipu", | |
2209 | .class = &omap44xx_mmu_hwmod_class, | |
2210 | .clkdm_name = "ducati_clkdm", | |
230844db ORL |
2211 | .rst_lines = omap44xx_mmu_ipu_resets, |
2212 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | |
2213 | .main_clk = "ducati_clk_mux_ck", | |
2214 | .prcm = { | |
2215 | .omap4 = { | |
2216 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, | |
2217 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, | |
2218 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, | |
2219 | .modulemode = MODULEMODE_HWCTRL, | |
2220 | }, | |
2221 | }, | |
230844db ORL |
2222 | }; |
2223 | ||
2224 | /* mmu dsp */ | |
2225 | ||
230844db | 2226 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; |
230844db ORL |
2227 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { |
2228 | { .name = "mmu_cache", .rst_shift = 1 }, | |
2229 | }; | |
2230 | ||
230844db ORL |
2231 | /* l4_cfg -> dsp */ |
2232 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { | |
2233 | .master = &omap44xx_l4_cfg_hwmod, | |
2234 | .slave = &omap44xx_mmu_dsp_hwmod, | |
2235 | .clk = "l4_div_ck", | |
230844db ORL |
2236 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2237 | }; | |
2238 | ||
2239 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |
2240 | .name = "mmu_dsp", | |
2241 | .class = &omap44xx_mmu_hwmod_class, | |
2242 | .clkdm_name = "tesla_clkdm", | |
230844db ORL |
2243 | .rst_lines = omap44xx_mmu_dsp_resets, |
2244 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | |
2245 | .main_clk = "dpll_iva_m4x2_ck", | |
2246 | .prcm = { | |
2247 | .omap4 = { | |
2248 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, | |
2249 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, | |
2250 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, | |
2251 | .modulemode = MODULEMODE_HWCTRL, | |
2252 | }, | |
2253 | }, | |
230844db ORL |
2254 | }; |
2255 | ||
3b54baad BC |
2256 | /* |
2257 | * 'mpu' class | |
2258 | * mpu sub-system | |
2259 | */ | |
2260 | ||
2261 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2262 | .name = "mpu", |
db12ba53 BC |
2263 | }; |
2264 | ||
3b54baad | 2265 | /* mpu */ |
3b54baad BC |
2266 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2267 | .name = "mpu", | |
2268 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2269 | .clkdm_name = "mpuss_clkdm", |
b2eb0002 | 2270 | .flags = HWMOD_INIT_NO_IDLE, |
3b54baad | 2271 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2272 | .prcm = { |
2273 | .omap4 = { | |
d0f0631d | 2274 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2275 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2276 | }, |
2277 | }, | |
db12ba53 BC |
2278 | }; |
2279 | ||
e17f18c0 PW |
2280 | /* |
2281 | * 'ocmc_ram' class | |
2282 | * top-level core on-chip ram | |
2283 | */ | |
2284 | ||
2285 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2286 | .name = "ocmc_ram", | |
2287 | }; | |
2288 | ||
2289 | /* ocmc_ram */ | |
2290 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2291 | .name = "ocmc_ram", | |
2292 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2293 | .clkdm_name = "l3_2_clkdm", | |
2294 | .prcm = { | |
2295 | .omap4 = { | |
2296 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2297 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2298 | }, | |
2299 | }, | |
2300 | }; | |
2301 | ||
0c668875 BC |
2302 | /* |
2303 | * 'ocp2scp' class | |
2304 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2305 | * protocol | |
2306 | */ | |
2307 | ||
33c976ec BC |
2308 | static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { |
2309 | .rev_offs = 0x0000, | |
2310 | .sysc_offs = 0x0010, | |
2311 | .syss_offs = 0x0014, | |
2312 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2313 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2314 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2315 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2316 | }; | |
2317 | ||
0c668875 BC |
2318 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { |
2319 | .name = "ocp2scp", | |
33c976ec | 2320 | .sysc = &omap44xx_ocp2scp_sysc, |
0c668875 BC |
2321 | }; |
2322 | ||
2323 | /* ocp2scp_usb_phy */ | |
0c668875 BC |
2324 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
2325 | .name = "ocp2scp_usb_phy", | |
2326 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2327 | .clkdm_name = "l3_init_clkdm", | |
f4d7a536 KVA |
2328 | /* |
2329 | * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP | |
2330 | * block as an "optional clock," and normally should never be | |
2331 | * specified as the main_clk for an OMAP IP block. However it | |
2332 | * turns out that this clock is actually the main clock for | |
2333 | * the ocp2scp_usb_phy IP block: | |
2334 | * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html | |
2335 | * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems | |
2336 | * to be the best workaround. | |
2337 | */ | |
2338 | .main_clk = "ocp2scp_usb_phy_phy_48m", | |
0c668875 BC |
2339 | .prcm = { |
2340 | .omap4 = { | |
2341 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2342 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2343 | .modulemode = MODULEMODE_HWCTRL, | |
2344 | }, | |
2345 | }, | |
0c668875 BC |
2346 | }; |
2347 | ||
794b480a PW |
2348 | /* |
2349 | * 'prcm' class | |
2350 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2351 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2352 | */ | |
2353 | ||
2354 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2355 | .name = "prcm", | |
2356 | }; | |
2357 | ||
2358 | /* prcm_mpu */ | |
2359 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2360 | .name = "prcm_mpu", | |
2361 | .class = &omap44xx_prcm_hwmod_class, | |
2362 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 2363 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2364 | .prcm = { |
2365 | .omap4 = { | |
2366 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2367 | }, | |
2368 | }, | |
794b480a PW |
2369 | }; |
2370 | ||
2371 | /* cm_core_aon */ | |
2372 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2373 | .name = "cm_core_aon", | |
2374 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2375 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2376 | .prcm = { |
2377 | .omap4 = { | |
2378 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2379 | }, | |
2380 | }, | |
794b480a PW |
2381 | }; |
2382 | ||
2383 | /* cm_core */ | |
2384 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2385 | .name = "cm_core", | |
2386 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2387 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2388 | .prcm = { |
2389 | .omap4 = { | |
2390 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2391 | }, | |
2392 | }, | |
794b480a PW |
2393 | }; |
2394 | ||
2395 | /* prm */ | |
794b480a PW |
2396 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { |
2397 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2398 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2399 | }; | |
2400 | ||
2401 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2402 | .name = "prm", | |
2403 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2404 | .rst_lines = omap44xx_prm_resets, |
2405 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2406 | }; | |
2407 | ||
2408 | /* | |
2409 | * 'scrm' class | |
2410 | * system clock and reset manager | |
2411 | */ | |
2412 | ||
2413 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2414 | .name = "scrm", | |
2415 | }; | |
2416 | ||
2417 | /* scrm */ | |
2418 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2419 | .name = "scrm", | |
2420 | .class = &omap44xx_scrm_hwmod_class, | |
2421 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
2422 | .prcm = { |
2423 | .omap4 = { | |
2424 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2425 | }, | |
2426 | }, | |
794b480a PW |
2427 | }; |
2428 | ||
42b9e387 PW |
2429 | /* |
2430 | * 'sl2if' class | |
2431 | * shared level 2 memory interface | |
2432 | */ | |
2433 | ||
2434 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2435 | .name = "sl2if", | |
2436 | }; | |
2437 | ||
2438 | /* sl2if */ | |
2439 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2440 | .name = "sl2if", | |
2441 | .class = &omap44xx_sl2if_hwmod_class, | |
2442 | .clkdm_name = "ivahd_clkdm", | |
2443 | .prcm = { | |
2444 | .omap4 = { | |
2445 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2446 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2447 | .modulemode = MODULEMODE_HWCTRL, | |
2448 | }, | |
2449 | }, | |
2450 | }; | |
2451 | ||
1e3b5e59 BC |
2452 | /* |
2453 | * 'slimbus' class | |
2454 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2455 | * the device and external components | |
2456 | */ | |
2457 | ||
2458 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2459 | .rev_offs = 0x0000, | |
2460 | .sysc_offs = 0x0010, | |
2461 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2462 | SYSC_HAS_SOFTRESET), | |
2463 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2464 | SIDLE_SMART_WKUP), | |
2465 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2466 | }; | |
2467 | ||
2468 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2469 | .name = "slimbus", | |
2470 | .sysc = &omap44xx_slimbus_sysc, | |
2471 | }; | |
2472 | ||
2473 | /* slimbus1 */ | |
1e3b5e59 BC |
2474 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { |
2475 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2476 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2477 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2478 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2479 | }; | |
2480 | ||
2481 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2482 | .name = "slimbus1", | |
2483 | .class = &omap44xx_slimbus_hwmod_class, | |
2484 | .clkdm_name = "abe_clkdm", | |
1e3b5e59 BC |
2485 | .prcm = { |
2486 | .omap4 = { | |
2487 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2488 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2489 | .modulemode = MODULEMODE_SWCTRL, | |
2490 | }, | |
2491 | }, | |
2492 | .opt_clks = slimbus1_opt_clks, | |
2493 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2494 | }; | |
2495 | ||
2496 | /* slimbus2 */ | |
1e3b5e59 BC |
2497 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { |
2498 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2499 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2500 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2501 | }; | |
2502 | ||
2503 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2504 | .name = "slimbus2", | |
2505 | .class = &omap44xx_slimbus_hwmod_class, | |
2506 | .clkdm_name = "l4_per_clkdm", | |
1e3b5e59 BC |
2507 | .prcm = { |
2508 | .omap4 = { | |
2509 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2510 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2511 | .modulemode = MODULEMODE_SWCTRL, | |
2512 | }, | |
2513 | }, | |
2514 | .opt_clks = slimbus2_opt_clks, | |
2515 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2516 | }; | |
2517 | ||
1f6a717f BC |
2518 | /* |
2519 | * 'smartreflex' class | |
2520 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2521 | * performance error) | |
2522 | */ | |
2523 | ||
2524 | /* The IP is not compliant to type1 / type2 scheme */ | |
2525 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2526 | .sidle_shift = 24, | |
2527 | .enwkup_shift = 26, | |
2528 | }; | |
2529 | ||
2530 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2531 | .sysc_offs = 0x0038, | |
2532 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2533 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2534 | SIDLE_SMART_WKUP), | |
2535 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2536 | }; | |
2537 | ||
2538 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2539 | .name = "smartreflex", |
2540 | .sysc = &omap44xx_smartreflex_sysc, | |
2541 | .rev = 2, | |
1f6a717f BC |
2542 | }; |
2543 | ||
2544 | /* smartreflex_core */ | |
cea6b942 SG |
2545 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2546 | .sensor_voltdm_name = "core", | |
2547 | }; | |
2548 | ||
1f6a717f BC |
2549 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2550 | .name = "smartreflex_core", | |
2551 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2552 | .clkdm_name = "l4_ao_clkdm", |
212738a4 | 2553 | |
1f6a717f | 2554 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2555 | .prcm = { |
2556 | .omap4 = { | |
d0f0631d | 2557 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2558 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2559 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2560 | }, |
2561 | }, | |
cea6b942 | 2562 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2563 | }; |
2564 | ||
2565 | /* smartreflex_iva */ | |
cea6b942 SG |
2566 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2567 | .sensor_voltdm_name = "iva", | |
2568 | }; | |
2569 | ||
1f6a717f BC |
2570 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2571 | .name = "smartreflex_iva", | |
2572 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2573 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2574 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2575 | .prcm = { |
2576 | .omap4 = { | |
d0f0631d | 2577 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2578 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2579 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2580 | }, |
2581 | }, | |
cea6b942 | 2582 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2583 | }; |
2584 | ||
2585 | /* smartreflex_mpu */ | |
cea6b942 SG |
2586 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2587 | .sensor_voltdm_name = "mpu", | |
2588 | }; | |
2589 | ||
1f6a717f BC |
2590 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2591 | .name = "smartreflex_mpu", | |
2592 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2593 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2594 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2595 | .prcm = { |
2596 | .omap4 = { | |
d0f0631d | 2597 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2598 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2599 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2600 | }, |
2601 | }, | |
cea6b942 | 2602 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2603 | }; |
2604 | ||
d11c217f BC |
2605 | /* |
2606 | * 'spinlock' class | |
2607 | * spinlock provides hardware assistance for synchronizing the processes | |
2608 | * running on multiple processors | |
2609 | */ | |
2610 | ||
2611 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2612 | .rev_offs = 0x0000, | |
2613 | .sysc_offs = 0x0010, | |
2614 | .syss_offs = 0x0014, | |
2615 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2616 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2617 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
77319669 | 2618 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
d11c217f BC |
2619 | .sysc_fields = &omap_hwmod_sysc_type1, |
2620 | }; | |
2621 | ||
2622 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2623 | .name = "spinlock", | |
2624 | .sysc = &omap44xx_spinlock_sysc, | |
2625 | }; | |
2626 | ||
2627 | /* spinlock */ | |
d11c217f BC |
2628 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2629 | .name = "spinlock", | |
2630 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2631 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2632 | .prcm = { |
2633 | .omap4 = { | |
d0f0631d | 2634 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2635 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2636 | }, |
2637 | }, | |
d11c217f BC |
2638 | }; |
2639 | ||
35d1a66a BC |
2640 | /* |
2641 | * 'timer' class | |
2642 | * general purpose timer module with accurate 1ms tick | |
2643 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2644 | */ | |
2645 | ||
2646 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2647 | .rev_offs = 0x0000, | |
2648 | .sysc_offs = 0x0010, | |
2649 | .syss_offs = 0x0014, | |
2650 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2651 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2652 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2653 | SYSS_HAS_RESET_STATUS), | |
2654 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2655 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2656 | }; | |
2657 | ||
2658 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2659 | .name = "timer", | |
2660 | .sysc = &omap44xx_timer_1ms_sysc, | |
2661 | }; | |
2662 | ||
2663 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2664 | .rev_offs = 0x0000, | |
2665 | .sysc_offs = 0x0010, | |
2666 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2667 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2668 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2669 | SIDLE_SMART_WKUP), | |
2670 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2671 | }; | |
2672 | ||
2673 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2674 | .name = "timer", | |
2675 | .sysc = &omap44xx_timer_sysc, | |
2676 | }; | |
2677 | ||
c345c8b0 TKD |
2678 | /* always-on timers dev attribute */ |
2679 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2680 | .timer_capability = OMAP_TIMER_ALWON, | |
2681 | }; | |
2682 | ||
2683 | /* pwm timers dev attribute */ | |
2684 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2685 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2686 | }; | |
2687 | ||
5c3e4ec4 JH |
2688 | /* timers with DSP interrupt dev attribute */ |
2689 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
2690 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
2691 | }; | |
2692 | ||
2693 | /* pwm timers with DSP interrupt dev attribute */ | |
2694 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
2695 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
2696 | }; | |
2697 | ||
35d1a66a | 2698 | /* timer1 */ |
35d1a66a BC |
2699 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2700 | .name = "timer1", | |
2701 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2702 | .clkdm_name = "l4_wkup_clkdm", |
10759e82 | 2703 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2704 | .main_clk = "dmt1_clk_mux", |
35d1a66a BC |
2705 | .prcm = { |
2706 | .omap4 = { | |
d0f0631d | 2707 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2708 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2709 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2710 | }, |
2711 | }, | |
c345c8b0 | 2712 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2713 | }; |
2714 | ||
2715 | /* timer2 */ | |
35d1a66a BC |
2716 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2717 | .name = "timer2", | |
2718 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2719 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2720 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2721 | .main_clk = "cm2_dm2_mux", |
35d1a66a BC |
2722 | .prcm = { |
2723 | .omap4 = { | |
d0f0631d | 2724 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2725 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2726 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2727 | }, |
2728 | }, | |
35d1a66a BC |
2729 | }; |
2730 | ||
2731 | /* timer3 */ | |
35d1a66a BC |
2732 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2733 | .name = "timer3", | |
2734 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2735 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2736 | .main_clk = "cm2_dm3_mux", |
35d1a66a BC |
2737 | .prcm = { |
2738 | .omap4 = { | |
d0f0631d | 2739 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2740 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2741 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2742 | }, |
2743 | }, | |
35d1a66a BC |
2744 | }; |
2745 | ||
2746 | /* timer4 */ | |
35d1a66a BC |
2747 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2748 | .name = "timer4", | |
2749 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2750 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2751 | .main_clk = "cm2_dm4_mux", |
35d1a66a BC |
2752 | .prcm = { |
2753 | .omap4 = { | |
d0f0631d | 2754 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2755 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2756 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2757 | }, |
2758 | }, | |
35d1a66a BC |
2759 | }; |
2760 | ||
2761 | /* timer5 */ | |
35d1a66a BC |
2762 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2763 | .name = "timer5", | |
2764 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2765 | .clkdm_name = "abe_clkdm", |
ee877acd | 2766 | .main_clk = "timer5_sync_mux", |
35d1a66a BC |
2767 | .prcm = { |
2768 | .omap4 = { | |
d0f0631d | 2769 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2770 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2771 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2772 | }, |
2773 | }, | |
5c3e4ec4 | 2774 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2775 | }; |
2776 | ||
2777 | /* timer6 */ | |
35d1a66a BC |
2778 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
2779 | .name = "timer6", | |
2780 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2781 | .clkdm_name = "abe_clkdm", |
ee877acd | 2782 | .main_clk = "timer6_sync_mux", |
35d1a66a BC |
2783 | .prcm = { |
2784 | .omap4 = { | |
d0f0631d | 2785 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 2786 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 2787 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2788 | }, |
2789 | }, | |
5c3e4ec4 | 2790 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2791 | }; |
2792 | ||
2793 | /* timer7 */ | |
35d1a66a BC |
2794 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
2795 | .name = "timer7", | |
2796 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2797 | .clkdm_name = "abe_clkdm", |
ee877acd | 2798 | .main_clk = "timer7_sync_mux", |
35d1a66a BC |
2799 | .prcm = { |
2800 | .omap4 = { | |
d0f0631d | 2801 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 2802 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 2803 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2804 | }, |
2805 | }, | |
5c3e4ec4 | 2806 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2807 | }; |
2808 | ||
2809 | /* timer8 */ | |
35d1a66a BC |
2810 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
2811 | .name = "timer8", | |
2812 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2813 | .clkdm_name = "abe_clkdm", |
ee877acd | 2814 | .main_clk = "timer8_sync_mux", |
35d1a66a BC |
2815 | .prcm = { |
2816 | .omap4 = { | |
d0f0631d | 2817 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 2818 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 2819 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2820 | }, |
2821 | }, | |
5c3e4ec4 | 2822 | .dev_attr = &capability_dsp_pwm_dev_attr, |
35d1a66a BC |
2823 | }; |
2824 | ||
2825 | /* timer9 */ | |
35d1a66a BC |
2826 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
2827 | .name = "timer9", | |
2828 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2829 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2830 | .main_clk = "cm2_dm9_mux", |
35d1a66a BC |
2831 | .prcm = { |
2832 | .omap4 = { | |
d0f0631d | 2833 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 2834 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 2835 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2836 | }, |
2837 | }, | |
c345c8b0 | 2838 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2839 | }; |
2840 | ||
2841 | /* timer10 */ | |
35d1a66a BC |
2842 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
2843 | .name = "timer10", | |
2844 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2845 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2846 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2847 | .main_clk = "cm2_dm10_mux", |
35d1a66a BC |
2848 | .prcm = { |
2849 | .omap4 = { | |
d0f0631d | 2850 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 2851 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 2852 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2853 | }, |
2854 | }, | |
c345c8b0 | 2855 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2856 | }; |
2857 | ||
2858 | /* timer11 */ | |
35d1a66a BC |
2859 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
2860 | .name = "timer11", | |
2861 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2862 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2863 | .main_clk = "cm2_dm11_mux", |
35d1a66a BC |
2864 | .prcm = { |
2865 | .omap4 = { | |
d0f0631d | 2866 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 2867 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 2868 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2869 | }, |
2870 | }, | |
c345c8b0 | 2871 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2872 | }; |
2873 | ||
9780a9cf | 2874 | /* |
3b54baad BC |
2875 | * 'uart' class |
2876 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
2877 | */ |
2878 | ||
3b54baad BC |
2879 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
2880 | .rev_offs = 0x0050, | |
2881 | .sysc_offs = 0x0054, | |
2882 | .syss_offs = 0x0058, | |
2883 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
2884 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
2885 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
2886 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2887 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
2888 | .sysc_fields = &omap_hwmod_sysc_type1, |
2889 | }; | |
2890 | ||
3b54baad | 2891 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
2892 | .name = "uart", |
2893 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
2894 | }; |
2895 | ||
3b54baad | 2896 | /* uart1 */ |
3b54baad BC |
2897 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
2898 | .name = "uart1", | |
2899 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2900 | .clkdm_name = "l4_per_clkdm", |
66dde54e | 2901 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2902 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2903 | .prcm = { |
2904 | .omap4 = { | |
d0f0631d | 2905 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 2906 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 2907 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2908 | }, |
2909 | }, | |
9780a9cf BC |
2910 | }; |
2911 | ||
3b54baad | 2912 | /* uart2 */ |
3b54baad BC |
2913 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
2914 | .name = "uart2", | |
2915 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2916 | .clkdm_name = "l4_per_clkdm", |
66dde54e | 2917 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2918 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2919 | .prcm = { |
2920 | .omap4 = { | |
d0f0631d | 2921 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 2922 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 2923 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2924 | }, |
2925 | }, | |
9780a9cf BC |
2926 | }; |
2927 | ||
3b54baad | 2928 | /* uart3 */ |
3b54baad BC |
2929 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
2930 | .name = "uart3", | |
2931 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2932 | .clkdm_name = "l4_per_clkdm", |
7dedd346 | 2933 | .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2934 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2935 | .prcm = { |
2936 | .omap4 = { | |
d0f0631d | 2937 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 2938 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 2939 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2940 | }, |
2941 | }, | |
9780a9cf BC |
2942 | }; |
2943 | ||
3b54baad | 2944 | /* uart4 */ |
3b54baad BC |
2945 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
2946 | .name = "uart4", | |
2947 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2948 | .clkdm_name = "l4_per_clkdm", |
7dedd346 | 2949 | .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2950 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2951 | .prcm = { |
2952 | .omap4 = { | |
d0f0631d | 2953 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 2954 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 2955 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2956 | }, |
2957 | }, | |
9780a9cf BC |
2958 | }; |
2959 | ||
0c668875 BC |
2960 | /* |
2961 | * 'usb_host_fs' class | |
2962 | * full-speed usb host controller | |
2963 | */ | |
2964 | ||
2965 | /* The IP is not compliant to type1 / type2 scheme */ | |
2966 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
2967 | .midle_shift = 4, | |
2968 | .sidle_shift = 2, | |
2969 | .srst_shift = 1, | |
2970 | }; | |
2971 | ||
2972 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
2973 | .rev_offs = 0x0000, | |
2974 | .sysc_offs = 0x0210, | |
2975 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2976 | SYSC_HAS_SOFTRESET), | |
2977 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2978 | SIDLE_SMART_WKUP), | |
2979 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
2980 | }; | |
2981 | ||
2982 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
2983 | .name = "usb_host_fs", | |
2984 | .sysc = &omap44xx_usb_host_fs_sysc, | |
2985 | }; | |
2986 | ||
2987 | /* usb_host_fs */ | |
0c668875 BC |
2988 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { |
2989 | .name = "usb_host_fs", | |
2990 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
2991 | .clkdm_name = "l3_init_clkdm", | |
0c668875 BC |
2992 | .main_clk = "usb_host_fs_fck", |
2993 | .prcm = { | |
2994 | .omap4 = { | |
2995 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
2996 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
2997 | .modulemode = MODULEMODE_SWCTRL, | |
2998 | }, | |
2999 | }, | |
3000 | }; | |
3001 | ||
5844c4ea | 3002 | /* |
844a3b63 PW |
3003 | * 'usb_host_hs' class |
3004 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3005 | */ |
3006 | ||
844a3b63 PW |
3007 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3008 | .rev_offs = 0x0000, | |
3009 | .sysc_offs = 0x0010, | |
3010 | .syss_offs = 0x0014, | |
3011 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
b483a4a5 | 3012 | SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS), |
5844c4ea BC |
3013 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3014 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3015 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3016 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3017 | }; |
3018 | ||
844a3b63 PW |
3019 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3020 | .name = "usb_host_hs", | |
3021 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3022 | }; |
3023 | ||
844a3b63 | 3024 | /* usb_host_hs */ |
844a3b63 PW |
3025 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3026 | .name = "usb_host_hs", | |
3027 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3028 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3029 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3030 | .prcm = { |
3031 | .omap4 = { | |
844a3b63 PW |
3032 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3033 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3034 | .modulemode = MODULEMODE_SWCTRL, | |
3035 | }, | |
3036 | }, | |
844a3b63 PW |
3037 | |
3038 | /* | |
3039 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3040 | * id: i660 | |
3041 | * | |
3042 | * Description: | |
3043 | * In the following configuration : | |
3044 | * - USBHOST module is set to smart-idle mode | |
3045 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3046 | * happens when the system is going to a low power mode : all ports | |
3047 | * have been suspended, the master part of the USBHOST module has | |
3048 | * entered the standby state, and SW has cut the functional clocks) | |
3049 | * - an USBHOST interrupt occurs before the module is able to answer | |
3050 | * idle_ack, typically a remote wakeup IRQ. | |
3051 | * Then the USB HOST module will enter a deadlock situation where it | |
3052 | * is no more accessible nor functional. | |
3053 | * | |
3054 | * Workaround: | |
3055 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3056 | */ | |
3057 | ||
3058 | /* | |
3059 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3060 | * Id: i571 | |
3061 | * | |
3062 | * Description: | |
3063 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3064 | * ready to enter the standby state (i.e. all ports are suspended and | |
3065 | * all attached devices are in suspend mode), then it can wrongly assert | |
3066 | * the Mstandby signal too early while there are still some residual OCP | |
3067 | * transactions ongoing. If this condition occurs, the internal state | |
3068 | * machine may go to an undefined state and the USB link may be stuck | |
3069 | * upon the next resume. | |
3070 | * | |
3071 | * Workaround: | |
3072 | * Don't use smart standby; use only force standby, | |
3073 | * hence HWMOD_SWSUP_MSTANDBY | |
3074 | */ | |
3075 | ||
b483a4a5 | 3076 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
844a3b63 PW |
3077 | }; |
3078 | ||
3079 | /* | |
3080 | * 'usb_otg_hs' class | |
3081 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3082 | */ | |
3083 | ||
3084 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3085 | .rev_offs = 0x0400, | |
3086 | .sysc_offs = 0x0404, | |
3087 | .syss_offs = 0x0408, | |
3088 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3089 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3090 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3091 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3092 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3093 | MSTANDBY_SMART), | |
3094 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3095 | }; | |
3096 | ||
3097 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3098 | .name = "usb_otg_hs", | |
3099 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3100 | }; | |
3101 | ||
3102 | /* usb_otg_hs */ | |
844a3b63 PW |
3103 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { |
3104 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3105 | }; | |
3106 | ||
3107 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3108 | .name = "usb_otg_hs", | |
3109 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3110 | .clkdm_name = "l3_init_clkdm", | |
3111 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
844a3b63 PW |
3112 | .main_clk = "usb_otg_hs_ick", |
3113 | .prcm = { | |
3114 | .omap4 = { | |
3115 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3116 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3117 | .modulemode = MODULEMODE_HWCTRL, | |
3118 | }, | |
3119 | }, | |
3120 | .opt_clks = usb_otg_hs_opt_clks, | |
3121 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3122 | }; | |
3123 | ||
3124 | /* | |
3125 | * 'usb_tll_hs' class | |
3126 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3127 | */ | |
3128 | ||
3129 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3130 | .rev_offs = 0x0000, | |
3131 | .sysc_offs = 0x0010, | |
3132 | .syss_offs = 0x0014, | |
3133 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3134 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3135 | SYSC_HAS_AUTOIDLE), | |
3136 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3137 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3138 | }; | |
3139 | ||
3140 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3141 | .name = "usb_tll_hs", | |
3142 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3143 | }; | |
3144 | ||
844a3b63 PW |
3145 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { |
3146 | .name = "usb_tll_hs", | |
3147 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3148 | .clkdm_name = "l3_init_clkdm", | |
844a3b63 PW |
3149 | .main_clk = "usb_tll_hs_ick", |
3150 | .prcm = { | |
3151 | .omap4 = { | |
3152 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3153 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3154 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3155 | }, |
3156 | }, | |
5844c4ea BC |
3157 | }; |
3158 | ||
3b54baad BC |
3159 | /* |
3160 | * 'wd_timer' class | |
3161 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3162 | * overflow condition | |
3163 | */ | |
3164 | ||
3165 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3166 | .rev_offs = 0x0000, | |
3167 | .sysc_offs = 0x0010, | |
3168 | .syss_offs = 0x0014, | |
3169 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3170 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3171 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3172 | SIDLE_SMART_WKUP), | |
3b54baad | 3173 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3174 | }; |
3175 | ||
3b54baad BC |
3176 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3177 | .name = "wd_timer", | |
3178 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3179 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 3180 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
3181 | }; |
3182 | ||
3183 | /* wd_timer2 */ | |
3b54baad BC |
3184 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3185 | .name = "wd_timer2", | |
3186 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3187 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 3188 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3189 | .prcm = { |
3190 | .omap4 = { | |
d0f0631d | 3191 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3192 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3193 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3194 | }, |
3195 | }, | |
9780a9cf BC |
3196 | }; |
3197 | ||
3b54baad | 3198 | /* wd_timer3 */ |
3b54baad BC |
3199 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3200 | .name = "wd_timer3", | |
3201 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3202 | .clkdm_name = "abe_clkdm", |
17b7e7d3 | 3203 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3204 | .prcm = { |
3205 | .omap4 = { | |
d0f0631d | 3206 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3207 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3208 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3209 | }, |
3210 | }, | |
9780a9cf | 3211 | }; |
531ce0d5 | 3212 | |
844a3b63 | 3213 | |
af88fa9a | 3214 | /* |
844a3b63 | 3215 | * interfaces |
af88fa9a | 3216 | */ |
af88fa9a | 3217 | |
844a3b63 PW |
3218 | /* l3_main_1 -> dmm */ |
3219 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3220 | .master = &omap44xx_l3_main_1_hwmod, | |
3221 | .slave = &omap44xx_dmm_hwmod, | |
3222 | .clk = "l3_div_ck", | |
3223 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3224 | }; |
3225 | ||
844a3b63 PW |
3226 | /* mpu -> dmm */ |
3227 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3228 | .master = &omap44xx_mpu_hwmod, | |
3229 | .slave = &omap44xx_dmm_hwmod, | |
3230 | .clk = "l3_div_ck", | |
844a3b63 PW |
3231 | .user = OCP_USER_MPU, |
3232 | }; | |
3233 | ||
3234 | /* iva -> l3_instr */ | |
3235 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3236 | .master = &omap44xx_iva_hwmod, | |
3237 | .slave = &omap44xx_l3_instr_hwmod, | |
3238 | .clk = "l3_div_ck", | |
3239 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3240 | }; | |
3241 | ||
3242 | /* l3_main_3 -> l3_instr */ | |
3243 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3244 | .master = &omap44xx_l3_main_3_hwmod, | |
3245 | .slave = &omap44xx_l3_instr_hwmod, | |
3246 | .clk = "l3_div_ck", | |
3247 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3248 | }; | |
3249 | ||
9a817bc8 BC |
3250 | /* ocp_wp_noc -> l3_instr */ |
3251 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3252 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3253 | .slave = &omap44xx_l3_instr_hwmod, | |
3254 | .clk = "l3_div_ck", | |
3255 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3256 | }; | |
3257 | ||
844a3b63 PW |
3258 | /* dsp -> l3_main_1 */ |
3259 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3260 | .master = &omap44xx_dsp_hwmod, | |
3261 | .slave = &omap44xx_l3_main_1_hwmod, | |
3262 | .clk = "l3_div_ck", | |
3263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3264 | }; | |
3265 | ||
3266 | /* dss -> l3_main_1 */ | |
3267 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3268 | .master = &omap44xx_dss_hwmod, | |
3269 | .slave = &omap44xx_l3_main_1_hwmod, | |
3270 | .clk = "l3_div_ck", | |
3271 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3272 | }; | |
3273 | ||
3274 | /* l3_main_2 -> l3_main_1 */ | |
3275 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3276 | .master = &omap44xx_l3_main_2_hwmod, | |
3277 | .slave = &omap44xx_l3_main_1_hwmod, | |
3278 | .clk = "l3_div_ck", | |
3279 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3280 | }; | |
3281 | ||
3282 | /* l4_cfg -> l3_main_1 */ | |
3283 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3284 | .master = &omap44xx_l4_cfg_hwmod, | |
3285 | .slave = &omap44xx_l3_main_1_hwmod, | |
3286 | .clk = "l4_div_ck", | |
3287 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3288 | }; | |
3289 | ||
3290 | /* mmc1 -> l3_main_1 */ | |
3291 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3292 | .master = &omap44xx_mmc1_hwmod, | |
3293 | .slave = &omap44xx_l3_main_1_hwmod, | |
3294 | .clk = "l3_div_ck", | |
3295 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3296 | }; | |
3297 | ||
3298 | /* mmc2 -> l3_main_1 */ | |
3299 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3300 | .master = &omap44xx_mmc2_hwmod, | |
3301 | .slave = &omap44xx_l3_main_1_hwmod, | |
3302 | .clk = "l3_div_ck", | |
3303 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3304 | }; | |
3305 | ||
844a3b63 PW |
3306 | /* mpu -> l3_main_1 */ |
3307 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3308 | .master = &omap44xx_mpu_hwmod, | |
3309 | .slave = &omap44xx_l3_main_1_hwmod, | |
3310 | .clk = "l3_div_ck", | |
844a3b63 PW |
3311 | .user = OCP_USER_MPU, |
3312 | }; | |
3313 | ||
96566043 BC |
3314 | /* debugss -> l3_main_2 */ |
3315 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
3316 | .master = &omap44xx_debugss_hwmod, | |
3317 | .slave = &omap44xx_l3_main_2_hwmod, | |
3318 | .clk = "dbgclk_mux_ck", | |
3319 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3320 | }; | |
3321 | ||
844a3b63 PW |
3322 | /* dma_system -> l3_main_2 */ |
3323 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3324 | .master = &omap44xx_dma_system_hwmod, | |
3325 | .slave = &omap44xx_l3_main_2_hwmod, | |
3326 | .clk = "l3_div_ck", | |
3327 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3328 | }; | |
3329 | ||
b050f688 ML |
3330 | /* fdif -> l3_main_2 */ |
3331 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3332 | .master = &omap44xx_fdif_hwmod, | |
3333 | .slave = &omap44xx_l3_main_2_hwmod, | |
3334 | .clk = "l3_div_ck", | |
3335 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3336 | }; | |
3337 | ||
9def390e PW |
3338 | /* gpu -> l3_main_2 */ |
3339 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3340 | .master = &omap44xx_gpu_hwmod, | |
3341 | .slave = &omap44xx_l3_main_2_hwmod, | |
3342 | .clk = "l3_div_ck", | |
3343 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3344 | }; | |
3345 | ||
844a3b63 PW |
3346 | /* hsi -> l3_main_2 */ |
3347 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3348 | .master = &omap44xx_hsi_hwmod, | |
3349 | .slave = &omap44xx_l3_main_2_hwmod, | |
3350 | .clk = "l3_div_ck", | |
3351 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3352 | }; | |
3353 | ||
3354 | /* ipu -> l3_main_2 */ | |
3355 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3356 | .master = &omap44xx_ipu_hwmod, | |
3357 | .slave = &omap44xx_l3_main_2_hwmod, | |
3358 | .clk = "l3_div_ck", | |
3359 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3360 | }; | |
3361 | ||
3362 | /* iss -> l3_main_2 */ | |
3363 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3364 | .master = &omap44xx_iss_hwmod, | |
3365 | .slave = &omap44xx_l3_main_2_hwmod, | |
3366 | .clk = "l3_div_ck", | |
3367 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3368 | }; | |
3369 | ||
3370 | /* iva -> l3_main_2 */ | |
3371 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3372 | .master = &omap44xx_iva_hwmod, | |
3373 | .slave = &omap44xx_l3_main_2_hwmod, | |
3374 | .clk = "l3_div_ck", | |
3375 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3376 | }; | |
3377 | ||
844a3b63 PW |
3378 | /* l3_main_1 -> l3_main_2 */ |
3379 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3380 | .master = &omap44xx_l3_main_1_hwmod, | |
3381 | .slave = &omap44xx_l3_main_2_hwmod, | |
3382 | .clk = "l3_div_ck", | |
844a3b63 PW |
3383 | .user = OCP_USER_MPU, |
3384 | }; | |
3385 | ||
3386 | /* l4_cfg -> l3_main_2 */ | |
3387 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3388 | .master = &omap44xx_l4_cfg_hwmod, | |
3389 | .slave = &omap44xx_l3_main_2_hwmod, | |
3390 | .clk = "l4_div_ck", | |
3391 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3392 | }; | |
3393 | ||
0c668875 | 3394 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 3395 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
3396 | .master = &omap44xx_usb_host_fs_hwmod, |
3397 | .slave = &omap44xx_l3_main_2_hwmod, | |
3398 | .clk = "l3_div_ck", | |
3399 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3400 | }; | |
3401 | ||
844a3b63 PW |
3402 | /* usb_host_hs -> l3_main_2 */ |
3403 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3404 | .master = &omap44xx_usb_host_hs_hwmod, | |
3405 | .slave = &omap44xx_l3_main_2_hwmod, | |
3406 | .clk = "l3_div_ck", | |
3407 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3408 | }; | |
3409 | ||
3410 | /* usb_otg_hs -> l3_main_2 */ | |
3411 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3412 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3413 | .slave = &omap44xx_l3_main_2_hwmod, | |
3414 | .clk = "l3_div_ck", | |
3415 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3416 | }; | |
3417 | ||
844a3b63 PW |
3418 | /* l3_main_1 -> l3_main_3 */ |
3419 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3420 | .master = &omap44xx_l3_main_1_hwmod, | |
3421 | .slave = &omap44xx_l3_main_3_hwmod, | |
3422 | .clk = "l3_div_ck", | |
844a3b63 PW |
3423 | .user = OCP_USER_MPU, |
3424 | }; | |
3425 | ||
3426 | /* l3_main_2 -> l3_main_3 */ | |
3427 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3428 | .master = &omap44xx_l3_main_2_hwmod, | |
3429 | .slave = &omap44xx_l3_main_3_hwmod, | |
3430 | .clk = "l3_div_ck", | |
3431 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3432 | }; | |
3433 | ||
3434 | /* l4_cfg -> l3_main_3 */ | |
3435 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3436 | .master = &omap44xx_l4_cfg_hwmod, | |
3437 | .slave = &omap44xx_l3_main_3_hwmod, | |
3438 | .clk = "l4_div_ck", | |
3439 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3440 | }; | |
3441 | ||
3442 | /* aess -> l4_abe */ | |
b0a70cc8 | 3443 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
3444 | .master = &omap44xx_aess_hwmod, |
3445 | .slave = &omap44xx_l4_abe_hwmod, | |
3446 | .clk = "ocp_abe_iclk", | |
3447 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3448 | }; | |
3449 | ||
3450 | /* dsp -> l4_abe */ | |
3451 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3452 | .master = &omap44xx_dsp_hwmod, | |
3453 | .slave = &omap44xx_l4_abe_hwmod, | |
3454 | .clk = "ocp_abe_iclk", | |
3455 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3456 | }; | |
3457 | ||
3458 | /* l3_main_1 -> l4_abe */ | |
3459 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3460 | .master = &omap44xx_l3_main_1_hwmod, | |
3461 | .slave = &omap44xx_l4_abe_hwmod, | |
3462 | .clk = "l3_div_ck", | |
3463 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3464 | }; | |
3465 | ||
3466 | /* mpu -> l4_abe */ | |
3467 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3468 | .master = &omap44xx_mpu_hwmod, | |
3469 | .slave = &omap44xx_l4_abe_hwmod, | |
3470 | .clk = "ocp_abe_iclk", | |
3471 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3472 | }; | |
3473 | ||
3474 | /* l3_main_1 -> l4_cfg */ | |
3475 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3476 | .master = &omap44xx_l3_main_1_hwmod, | |
3477 | .slave = &omap44xx_l4_cfg_hwmod, | |
3478 | .clk = "l3_div_ck", | |
3479 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3480 | }; | |
3481 | ||
3482 | /* l3_main_2 -> l4_per */ | |
3483 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3484 | .master = &omap44xx_l3_main_2_hwmod, | |
3485 | .slave = &omap44xx_l4_per_hwmod, | |
3486 | .clk = "l3_div_ck", | |
3487 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3488 | }; | |
3489 | ||
3490 | /* l4_cfg -> l4_wkup */ | |
3491 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3492 | .master = &omap44xx_l4_cfg_hwmod, | |
3493 | .slave = &omap44xx_l4_wkup_hwmod, | |
3494 | .clk = "l4_div_ck", | |
3495 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3496 | }; | |
3497 | ||
3498 | /* mpu -> mpu_private */ | |
3499 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3500 | .master = &omap44xx_mpu_hwmod, | |
3501 | .slave = &omap44xx_mpu_private_hwmod, | |
3502 | .clk = "l3_div_ck", | |
3503 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3504 | }; | |
3505 | ||
9a817bc8 BC |
3506 | /* l4_cfg -> ocp_wp_noc */ |
3507 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
3508 | .master = &omap44xx_l4_cfg_hwmod, | |
3509 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
3510 | .clk = "l4_div_ck", | |
9a817bc8 BC |
3511 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3512 | }; | |
3513 | ||
844a3b63 PW |
3514 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
3515 | { | |
9f0c5996 SG |
3516 | .name = "dmem", |
3517 | .pa_start = 0x40180000, | |
3518 | .pa_end = 0x4018ffff | |
3519 | }, | |
3520 | { | |
3521 | .name = "cmem", | |
3522 | .pa_start = 0x401a0000, | |
3523 | .pa_end = 0x401a1fff | |
3524 | }, | |
3525 | { | |
3526 | .name = "smem", | |
3527 | .pa_start = 0x401c0000, | |
3528 | .pa_end = 0x401c5fff | |
3529 | }, | |
3530 | { | |
3531 | .name = "pmem", | |
3532 | .pa_start = 0x401e0000, | |
3533 | .pa_end = 0x401e1fff | |
3534 | }, | |
3535 | { | |
3536 | .name = "mpu", | |
844a3b63 PW |
3537 | .pa_start = 0x401f1000, |
3538 | .pa_end = 0x401f13ff, | |
3539 | .flags = ADDR_TYPE_RT | |
3540 | }, | |
3541 | { } | |
3542 | }; | |
3543 | ||
3544 | /* l4_abe -> aess */ | |
b0a70cc8 | 3545 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
3546 | .master = &omap44xx_l4_abe_hwmod, |
3547 | .slave = &omap44xx_aess_hwmod, | |
3548 | .clk = "ocp_abe_iclk", | |
3549 | .addr = omap44xx_aess_addrs, | |
3550 | .user = OCP_USER_MPU, | |
3551 | }; | |
3552 | ||
3553 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
3554 | { | |
9f0c5996 SG |
3555 | .name = "dmem_dma", |
3556 | .pa_start = 0x49080000, | |
3557 | .pa_end = 0x4908ffff | |
3558 | }, | |
3559 | { | |
3560 | .name = "cmem_dma", | |
3561 | .pa_start = 0x490a0000, | |
3562 | .pa_end = 0x490a1fff | |
3563 | }, | |
3564 | { | |
3565 | .name = "smem_dma", | |
3566 | .pa_start = 0x490c0000, | |
3567 | .pa_end = 0x490c5fff | |
3568 | }, | |
3569 | { | |
3570 | .name = "pmem_dma", | |
3571 | .pa_start = 0x490e0000, | |
3572 | .pa_end = 0x490e1fff | |
3573 | }, | |
3574 | { | |
3575 | .name = "dma", | |
844a3b63 PW |
3576 | .pa_start = 0x490f1000, |
3577 | .pa_end = 0x490f13ff, | |
3578 | .flags = ADDR_TYPE_RT | |
3579 | }, | |
3580 | { } | |
3581 | }; | |
3582 | ||
3583 | /* l4_abe -> aess (dma) */ | |
b0a70cc8 | 3584 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
3585 | .master = &omap44xx_l4_abe_hwmod, |
3586 | .slave = &omap44xx_aess_hwmod, | |
3587 | .clk = "ocp_abe_iclk", | |
3588 | .addr = omap44xx_aess_dma_addrs, | |
3589 | .user = OCP_USER_SDMA, | |
3590 | }; | |
3591 | ||
42b9e387 PW |
3592 | /* l3_main_2 -> c2c */ |
3593 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
3594 | .master = &omap44xx_l3_main_2_hwmod, | |
3595 | .slave = &omap44xx_c2c_hwmod, | |
3596 | .clk = "l3_div_ck", | |
3597 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3598 | }; | |
3599 | ||
844a3b63 PW |
3600 | /* l4_wkup -> counter_32k */ |
3601 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
3602 | .master = &omap44xx_l4_wkup_hwmod, | |
3603 | .slave = &omap44xx_counter_32k_hwmod, | |
3604 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3605 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3606 | }; | |
3607 | ||
a0b5d813 PW |
3608 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
3609 | { | |
3610 | .pa_start = 0x4a002000, | |
3611 | .pa_end = 0x4a0027ff, | |
3612 | .flags = ADDR_TYPE_RT | |
3613 | }, | |
3614 | { } | |
3615 | }; | |
3616 | ||
3617 | /* l4_cfg -> ctrl_module_core */ | |
3618 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
3619 | .master = &omap44xx_l4_cfg_hwmod, | |
3620 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
3621 | .clk = "l4_div_ck", | |
3622 | .addr = omap44xx_ctrl_module_core_addrs, | |
3623 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3624 | }; | |
3625 | ||
3626 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
3627 | { | |
3628 | .pa_start = 0x4a100000, | |
3629 | .pa_end = 0x4a1007ff, | |
3630 | .flags = ADDR_TYPE_RT | |
3631 | }, | |
3632 | { } | |
3633 | }; | |
3634 | ||
3635 | /* l4_cfg -> ctrl_module_pad_core */ | |
3636 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
3637 | .master = &omap44xx_l4_cfg_hwmod, | |
3638 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
3639 | .clk = "l4_div_ck", | |
3640 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
3641 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3642 | }; | |
3643 | ||
3644 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
3645 | { | |
3646 | .pa_start = 0x4a30c000, | |
3647 | .pa_end = 0x4a30c7ff, | |
3648 | .flags = ADDR_TYPE_RT | |
3649 | }, | |
3650 | { } | |
3651 | }; | |
3652 | ||
3653 | /* l4_wkup -> ctrl_module_wkup */ | |
3654 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
3655 | .master = &omap44xx_l4_wkup_hwmod, | |
3656 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
3657 | .clk = "l4_wkup_clk_mux_ck", | |
3658 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
3659 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3660 | }; | |
3661 | ||
3662 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
3663 | { | |
3664 | .pa_start = 0x4a31e000, | |
3665 | .pa_end = 0x4a31e7ff, | |
3666 | .flags = ADDR_TYPE_RT | |
3667 | }, | |
3668 | { } | |
3669 | }; | |
3670 | ||
3671 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
3672 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
3673 | .master = &omap44xx_l4_wkup_hwmod, | |
3674 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
3675 | .clk = "l4_wkup_clk_mux_ck", | |
3676 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
3677 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3678 | }; | |
3679 | ||
96566043 BC |
3680 | /* l3_instr -> debugss */ |
3681 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
3682 | .master = &omap44xx_l3_instr_hwmod, | |
3683 | .slave = &omap44xx_debugss_hwmod, | |
3684 | .clk = "l3_div_ck", | |
96566043 BC |
3685 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3686 | }; | |
3687 | ||
844a3b63 PW |
3688 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
3689 | { | |
3690 | .pa_start = 0x4a056000, | |
3691 | .pa_end = 0x4a056fff, | |
3692 | .flags = ADDR_TYPE_RT | |
3693 | }, | |
3694 | { } | |
3695 | }; | |
3696 | ||
3697 | /* l4_cfg -> dma_system */ | |
3698 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
3699 | .master = &omap44xx_l4_cfg_hwmod, | |
3700 | .slave = &omap44xx_dma_system_hwmod, | |
3701 | .clk = "l4_div_ck", | |
3702 | .addr = omap44xx_dma_system_addrs, | |
3703 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3704 | }; | |
3705 | ||
844a3b63 PW |
3706 | /* l4_abe -> dmic */ |
3707 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
3708 | .master = &omap44xx_l4_abe_hwmod, | |
3709 | .slave = &omap44xx_dmic_hwmod, | |
3710 | .clk = "ocp_abe_iclk", | |
e3491795 | 3711 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3712 | }; |
3713 | ||
3714 | /* dsp -> iva */ | |
3715 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
3716 | .master = &omap44xx_dsp_hwmod, | |
3717 | .slave = &omap44xx_iva_hwmod, | |
3718 | .clk = "dpll_iva_m5x2_ck", | |
3719 | .user = OCP_USER_DSP, | |
3720 | }; | |
3721 | ||
42b9e387 | 3722 | /* dsp -> sl2if */ |
b360124e | 3723 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
42b9e387 PW |
3724 | .master = &omap44xx_dsp_hwmod, |
3725 | .slave = &omap44xx_sl2if_hwmod, | |
3726 | .clk = "dpll_iva_m5x2_ck", | |
3727 | .user = OCP_USER_DSP, | |
3728 | }; | |
3729 | ||
844a3b63 PW |
3730 | /* l4_cfg -> dsp */ |
3731 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
3732 | .master = &omap44xx_l4_cfg_hwmod, | |
3733 | .slave = &omap44xx_dsp_hwmod, | |
3734 | .clk = "l4_div_ck", | |
3735 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3736 | }; | |
3737 | ||
3738 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
3739 | { | |
3740 | .pa_start = 0x58000000, | |
3741 | .pa_end = 0x5800007f, | |
3742 | .flags = ADDR_TYPE_RT | |
3743 | }, | |
3744 | { } | |
3745 | }; | |
3746 | ||
3747 | /* l3_main_2 -> dss */ | |
3748 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
3749 | .master = &omap44xx_l3_main_2_hwmod, | |
3750 | .slave = &omap44xx_dss_hwmod, | |
7ede8561 | 3751 | .clk = "l3_div_ck", |
844a3b63 PW |
3752 | .addr = omap44xx_dss_dma_addrs, |
3753 | .user = OCP_USER_SDMA, | |
3754 | }; | |
3755 | ||
3756 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
3757 | { | |
3758 | .pa_start = 0x48040000, | |
3759 | .pa_end = 0x4804007f, | |
3760 | .flags = ADDR_TYPE_RT | |
3761 | }, | |
3762 | { } | |
3763 | }; | |
3764 | ||
3765 | /* l4_per -> dss */ | |
3766 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
3767 | .master = &omap44xx_l4_per_hwmod, | |
3768 | .slave = &omap44xx_dss_hwmod, | |
3769 | .clk = "l4_div_ck", | |
3770 | .addr = omap44xx_dss_addrs, | |
3771 | .user = OCP_USER_MPU, | |
3772 | }; | |
3773 | ||
3774 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
3775 | { | |
3776 | .pa_start = 0x58001000, | |
3777 | .pa_end = 0x58001fff, | |
3778 | .flags = ADDR_TYPE_RT | |
3779 | }, | |
3780 | { } | |
3781 | }; | |
3782 | ||
3783 | /* l3_main_2 -> dss_dispc */ | |
3784 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
3785 | .master = &omap44xx_l3_main_2_hwmod, | |
3786 | .slave = &omap44xx_dss_dispc_hwmod, | |
7ede8561 | 3787 | .clk = "l3_div_ck", |
844a3b63 PW |
3788 | .addr = omap44xx_dss_dispc_dma_addrs, |
3789 | .user = OCP_USER_SDMA, | |
3790 | }; | |
3791 | ||
3792 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
3793 | { | |
3794 | .pa_start = 0x48041000, | |
3795 | .pa_end = 0x48041fff, | |
3796 | .flags = ADDR_TYPE_RT | |
3797 | }, | |
3798 | { } | |
3799 | }; | |
3800 | ||
3801 | /* l4_per -> dss_dispc */ | |
3802 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
3803 | .master = &omap44xx_l4_per_hwmod, | |
3804 | .slave = &omap44xx_dss_dispc_hwmod, | |
3805 | .clk = "l4_div_ck", | |
3806 | .addr = omap44xx_dss_dispc_addrs, | |
3807 | .user = OCP_USER_MPU, | |
3808 | }; | |
3809 | ||
3810 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
3811 | { | |
3812 | .pa_start = 0x58004000, | |
3813 | .pa_end = 0x580041ff, | |
3814 | .flags = ADDR_TYPE_RT | |
3815 | }, | |
3816 | { } | |
3817 | }; | |
3818 | ||
3819 | /* l3_main_2 -> dss_dsi1 */ | |
3820 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
3821 | .master = &omap44xx_l3_main_2_hwmod, | |
3822 | .slave = &omap44xx_dss_dsi1_hwmod, | |
7ede8561 | 3823 | .clk = "l3_div_ck", |
844a3b63 PW |
3824 | .addr = omap44xx_dss_dsi1_dma_addrs, |
3825 | .user = OCP_USER_SDMA, | |
3826 | }; | |
3827 | ||
3828 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
3829 | { | |
3830 | .pa_start = 0x48044000, | |
3831 | .pa_end = 0x480441ff, | |
3832 | .flags = ADDR_TYPE_RT | |
3833 | }, | |
3834 | { } | |
3835 | }; | |
3836 | ||
3837 | /* l4_per -> dss_dsi1 */ | |
3838 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
3839 | .master = &omap44xx_l4_per_hwmod, | |
3840 | .slave = &omap44xx_dss_dsi1_hwmod, | |
3841 | .clk = "l4_div_ck", | |
3842 | .addr = omap44xx_dss_dsi1_addrs, | |
3843 | .user = OCP_USER_MPU, | |
3844 | }; | |
3845 | ||
3846 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
3847 | { | |
3848 | .pa_start = 0x58005000, | |
3849 | .pa_end = 0x580051ff, | |
3850 | .flags = ADDR_TYPE_RT | |
3851 | }, | |
3852 | { } | |
3853 | }; | |
3854 | ||
3855 | /* l3_main_2 -> dss_dsi2 */ | |
3856 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
3857 | .master = &omap44xx_l3_main_2_hwmod, | |
3858 | .slave = &omap44xx_dss_dsi2_hwmod, | |
7ede8561 | 3859 | .clk = "l3_div_ck", |
844a3b63 PW |
3860 | .addr = omap44xx_dss_dsi2_dma_addrs, |
3861 | .user = OCP_USER_SDMA, | |
3862 | }; | |
3863 | ||
3864 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
3865 | { | |
3866 | .pa_start = 0x48045000, | |
3867 | .pa_end = 0x480451ff, | |
3868 | .flags = ADDR_TYPE_RT | |
3869 | }, | |
3870 | { } | |
3871 | }; | |
3872 | ||
3873 | /* l4_per -> dss_dsi2 */ | |
3874 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
3875 | .master = &omap44xx_l4_per_hwmod, | |
3876 | .slave = &omap44xx_dss_dsi2_hwmod, | |
3877 | .clk = "l4_div_ck", | |
3878 | .addr = omap44xx_dss_dsi2_addrs, | |
3879 | .user = OCP_USER_MPU, | |
3880 | }; | |
3881 | ||
3882 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
3883 | { | |
3884 | .pa_start = 0x58006000, | |
3885 | .pa_end = 0x58006fff, | |
3886 | .flags = ADDR_TYPE_RT | |
3887 | }, | |
3888 | { } | |
3889 | }; | |
3890 | ||
3891 | /* l3_main_2 -> dss_hdmi */ | |
3892 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
3893 | .master = &omap44xx_l3_main_2_hwmod, | |
3894 | .slave = &omap44xx_dss_hdmi_hwmod, | |
7ede8561 | 3895 | .clk = "l3_div_ck", |
844a3b63 PW |
3896 | .addr = omap44xx_dss_hdmi_dma_addrs, |
3897 | .user = OCP_USER_SDMA, | |
3898 | }; | |
3899 | ||
3900 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
3901 | { | |
3902 | .pa_start = 0x48046000, | |
3903 | .pa_end = 0x48046fff, | |
3904 | .flags = ADDR_TYPE_RT | |
3905 | }, | |
3906 | { } | |
3907 | }; | |
3908 | ||
3909 | /* l4_per -> dss_hdmi */ | |
3910 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
3911 | .master = &omap44xx_l4_per_hwmod, | |
3912 | .slave = &omap44xx_dss_hdmi_hwmod, | |
3913 | .clk = "l4_div_ck", | |
3914 | .addr = omap44xx_dss_hdmi_addrs, | |
3915 | .user = OCP_USER_MPU, | |
3916 | }; | |
3917 | ||
3918 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
3919 | { | |
3920 | .pa_start = 0x58002000, | |
3921 | .pa_end = 0x580020ff, | |
3922 | .flags = ADDR_TYPE_RT | |
3923 | }, | |
3924 | { } | |
3925 | }; | |
3926 | ||
3927 | /* l3_main_2 -> dss_rfbi */ | |
3928 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
3929 | .master = &omap44xx_l3_main_2_hwmod, | |
3930 | .slave = &omap44xx_dss_rfbi_hwmod, | |
7ede8561 | 3931 | .clk = "l3_div_ck", |
844a3b63 PW |
3932 | .addr = omap44xx_dss_rfbi_dma_addrs, |
3933 | .user = OCP_USER_SDMA, | |
3934 | }; | |
3935 | ||
3936 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
3937 | { | |
3938 | .pa_start = 0x48042000, | |
3939 | .pa_end = 0x480420ff, | |
3940 | .flags = ADDR_TYPE_RT | |
3941 | }, | |
3942 | { } | |
3943 | }; | |
3944 | ||
3945 | /* l4_per -> dss_rfbi */ | |
3946 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
3947 | .master = &omap44xx_l4_per_hwmod, | |
3948 | .slave = &omap44xx_dss_rfbi_hwmod, | |
3949 | .clk = "l4_div_ck", | |
3950 | .addr = omap44xx_dss_rfbi_addrs, | |
3951 | .user = OCP_USER_MPU, | |
3952 | }; | |
3953 | ||
3954 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
3955 | { | |
3956 | .pa_start = 0x58003000, | |
3957 | .pa_end = 0x580030ff, | |
3958 | .flags = ADDR_TYPE_RT | |
3959 | }, | |
3960 | { } | |
3961 | }; | |
3962 | ||
3963 | /* l3_main_2 -> dss_venc */ | |
3964 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
3965 | .master = &omap44xx_l3_main_2_hwmod, | |
3966 | .slave = &omap44xx_dss_venc_hwmod, | |
7ede8561 | 3967 | .clk = "l3_div_ck", |
844a3b63 PW |
3968 | .addr = omap44xx_dss_venc_dma_addrs, |
3969 | .user = OCP_USER_SDMA, | |
3970 | }; | |
3971 | ||
3972 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
3973 | { | |
3974 | .pa_start = 0x48043000, | |
3975 | .pa_end = 0x480430ff, | |
3976 | .flags = ADDR_TYPE_RT | |
3977 | }, | |
3978 | { } | |
3979 | }; | |
3980 | ||
3981 | /* l4_per -> dss_venc */ | |
3982 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
3983 | .master = &omap44xx_l4_per_hwmod, | |
3984 | .slave = &omap44xx_dss_venc_hwmod, | |
3985 | .clk = "l4_div_ck", | |
3986 | .addr = omap44xx_dss_venc_addrs, | |
3987 | .user = OCP_USER_MPU, | |
3988 | }; | |
3989 | ||
42b9e387 PW |
3990 | /* l4_per -> elm */ |
3991 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
3992 | .master = &omap44xx_l4_per_hwmod, | |
3993 | .slave = &omap44xx_elm_hwmod, | |
3994 | .clk = "l4_div_ck", | |
42b9e387 PW |
3995 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3996 | }; | |
3997 | ||
b050f688 ML |
3998 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
3999 | { | |
4000 | .pa_start = 0x4a10a000, | |
4001 | .pa_end = 0x4a10a1ff, | |
4002 | .flags = ADDR_TYPE_RT | |
4003 | }, | |
4004 | { } | |
4005 | }; | |
4006 | ||
4007 | /* l4_cfg -> fdif */ | |
4008 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4009 | .master = &omap44xx_l4_cfg_hwmod, | |
4010 | .slave = &omap44xx_fdif_hwmod, | |
4011 | .clk = "l4_div_ck", | |
4012 | .addr = omap44xx_fdif_addrs, | |
4013 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4014 | }; | |
4015 | ||
844a3b63 PW |
4016 | /* l4_wkup -> gpio1 */ |
4017 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4018 | .master = &omap44xx_l4_wkup_hwmod, | |
4019 | .slave = &omap44xx_gpio1_hwmod, | |
4020 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4021 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4022 | }; | |
4023 | ||
844a3b63 PW |
4024 | /* l4_per -> gpio2 */ |
4025 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4026 | .master = &omap44xx_l4_per_hwmod, | |
4027 | .slave = &omap44xx_gpio2_hwmod, | |
4028 | .clk = "l4_div_ck", | |
844a3b63 PW |
4029 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4030 | }; | |
4031 | ||
844a3b63 PW |
4032 | /* l4_per -> gpio3 */ |
4033 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4034 | .master = &omap44xx_l4_per_hwmod, | |
4035 | .slave = &omap44xx_gpio3_hwmod, | |
4036 | .clk = "l4_div_ck", | |
844a3b63 PW |
4037 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4038 | }; | |
4039 | ||
844a3b63 PW |
4040 | /* l4_per -> gpio4 */ |
4041 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4042 | .master = &omap44xx_l4_per_hwmod, | |
4043 | .slave = &omap44xx_gpio4_hwmod, | |
4044 | .clk = "l4_div_ck", | |
844a3b63 PW |
4045 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4046 | }; | |
4047 | ||
844a3b63 PW |
4048 | /* l4_per -> gpio5 */ |
4049 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4050 | .master = &omap44xx_l4_per_hwmod, | |
4051 | .slave = &omap44xx_gpio5_hwmod, | |
4052 | .clk = "l4_div_ck", | |
844a3b63 PW |
4053 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4054 | }; | |
4055 | ||
844a3b63 PW |
4056 | /* l4_per -> gpio6 */ |
4057 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4058 | .master = &omap44xx_l4_per_hwmod, | |
4059 | .slave = &omap44xx_gpio6_hwmod, | |
4060 | .clk = "l4_div_ck", | |
844a3b63 PW |
4061 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4062 | }; | |
4063 | ||
eb42b5d3 BC |
4064 | /* l3_main_2 -> gpmc */ |
4065 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4066 | .master = &omap44xx_l3_main_2_hwmod, | |
4067 | .slave = &omap44xx_gpmc_hwmod, | |
4068 | .clk = "l3_div_ck", | |
eb42b5d3 BC |
4069 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4070 | }; | |
4071 | ||
9def390e PW |
4072 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4073 | { | |
4074 | .pa_start = 0x56000000, | |
4075 | .pa_end = 0x5600ffff, | |
4076 | .flags = ADDR_TYPE_RT | |
4077 | }, | |
4078 | { } | |
4079 | }; | |
4080 | ||
4081 | /* l3_main_2 -> gpu */ | |
4082 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4083 | .master = &omap44xx_l3_main_2_hwmod, | |
4084 | .slave = &omap44xx_gpu_hwmod, | |
4085 | .clk = "l3_div_ck", | |
4086 | .addr = omap44xx_gpu_addrs, | |
4087 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4088 | }; | |
4089 | ||
a091c08e PW |
4090 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4091 | { | |
4092 | .pa_start = 0x480b2000, | |
4093 | .pa_end = 0x480b201f, | |
4094 | .flags = ADDR_TYPE_RT | |
4095 | }, | |
4096 | { } | |
4097 | }; | |
4098 | ||
4099 | /* l4_per -> hdq1w */ | |
4100 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4101 | .master = &omap44xx_l4_per_hwmod, | |
4102 | .slave = &omap44xx_hdq1w_hwmod, | |
4103 | .clk = "l4_div_ck", | |
4104 | .addr = omap44xx_hdq1w_addrs, | |
4105 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4106 | }; | |
4107 | ||
844a3b63 PW |
4108 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4109 | { | |
4110 | .pa_start = 0x4a058000, | |
4111 | .pa_end = 0x4a05bfff, | |
4112 | .flags = ADDR_TYPE_RT | |
4113 | }, | |
4114 | { } | |
4115 | }; | |
4116 | ||
4117 | /* l4_cfg -> hsi */ | |
4118 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4119 | .master = &omap44xx_l4_cfg_hwmod, | |
4120 | .slave = &omap44xx_hsi_hwmod, | |
4121 | .clk = "l4_div_ck", | |
4122 | .addr = omap44xx_hsi_addrs, | |
4123 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4124 | }; | |
4125 | ||
844a3b63 PW |
4126 | /* l4_per -> i2c1 */ |
4127 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4128 | .master = &omap44xx_l4_per_hwmod, | |
4129 | .slave = &omap44xx_i2c1_hwmod, | |
4130 | .clk = "l4_div_ck", | |
844a3b63 PW |
4131 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4132 | }; | |
4133 | ||
844a3b63 PW |
4134 | /* l4_per -> i2c2 */ |
4135 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4136 | .master = &omap44xx_l4_per_hwmod, | |
4137 | .slave = &omap44xx_i2c2_hwmod, | |
4138 | .clk = "l4_div_ck", | |
844a3b63 PW |
4139 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4140 | }; | |
4141 | ||
844a3b63 PW |
4142 | /* l4_per -> i2c3 */ |
4143 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4144 | .master = &omap44xx_l4_per_hwmod, | |
4145 | .slave = &omap44xx_i2c3_hwmod, | |
4146 | .clk = "l4_div_ck", | |
844a3b63 PW |
4147 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4148 | }; | |
4149 | ||
844a3b63 PW |
4150 | /* l4_per -> i2c4 */ |
4151 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4152 | .master = &omap44xx_l4_per_hwmod, | |
4153 | .slave = &omap44xx_i2c4_hwmod, | |
4154 | .clk = "l4_div_ck", | |
844a3b63 PW |
4155 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4156 | }; | |
4157 | ||
4158 | /* l3_main_2 -> ipu */ | |
4159 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4160 | .master = &omap44xx_l3_main_2_hwmod, | |
4161 | .slave = &omap44xx_ipu_hwmod, | |
4162 | .clk = "l3_div_ck", | |
4163 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4164 | }; | |
4165 | ||
4166 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
4167 | { | |
4168 | .pa_start = 0x52000000, | |
4169 | .pa_end = 0x520000ff, | |
4170 | .flags = ADDR_TYPE_RT | |
4171 | }, | |
4172 | { } | |
4173 | }; | |
4174 | ||
4175 | /* l3_main_2 -> iss */ | |
4176 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
4177 | .master = &omap44xx_l3_main_2_hwmod, | |
4178 | .slave = &omap44xx_iss_hwmod, | |
4179 | .clk = "l3_div_ck", | |
4180 | .addr = omap44xx_iss_addrs, | |
4181 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4182 | }; | |
4183 | ||
42b9e387 | 4184 | /* iva -> sl2if */ |
b360124e | 4185 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
42b9e387 PW |
4186 | .master = &omap44xx_iva_hwmod, |
4187 | .slave = &omap44xx_sl2if_hwmod, | |
4188 | .clk = "dpll_iva_m5x2_ck", | |
4189 | .user = OCP_USER_IVA, | |
4190 | }; | |
4191 | ||
844a3b63 PW |
4192 | /* l3_main_2 -> iva */ |
4193 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
4194 | .master = &omap44xx_l3_main_2_hwmod, | |
4195 | .slave = &omap44xx_iva_hwmod, | |
4196 | .clk = "l3_div_ck", | |
844a3b63 PW |
4197 | .user = OCP_USER_MPU, |
4198 | }; | |
4199 | ||
844a3b63 PW |
4200 | /* l4_wkup -> kbd */ |
4201 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
4202 | .master = &omap44xx_l4_wkup_hwmod, | |
4203 | .slave = &omap44xx_kbd_hwmod, | |
4204 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4205 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4206 | }; | |
4207 | ||
844a3b63 PW |
4208 | /* l4_cfg -> mailbox */ |
4209 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4210 | .master = &omap44xx_l4_cfg_hwmod, | |
4211 | .slave = &omap44xx_mailbox_hwmod, | |
4212 | .clk = "l4_div_ck", | |
844a3b63 PW |
4213 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4214 | }; | |
4215 | ||
896d4e98 BC |
4216 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
4217 | { | |
4218 | .pa_start = 0x40128000, | |
4219 | .pa_end = 0x401283ff, | |
4220 | .flags = ADDR_TYPE_RT | |
4221 | }, | |
4222 | { } | |
4223 | }; | |
4224 | ||
4225 | /* l4_abe -> mcasp */ | |
4226 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
4227 | .master = &omap44xx_l4_abe_hwmod, | |
4228 | .slave = &omap44xx_mcasp_hwmod, | |
4229 | .clk = "ocp_abe_iclk", | |
4230 | .addr = omap44xx_mcasp_addrs, | |
4231 | .user = OCP_USER_MPU, | |
4232 | }; | |
4233 | ||
4234 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
4235 | { | |
4236 | .pa_start = 0x49028000, | |
4237 | .pa_end = 0x490283ff, | |
4238 | .flags = ADDR_TYPE_RT | |
4239 | }, | |
4240 | { } | |
4241 | }; | |
4242 | ||
4243 | /* l4_abe -> mcasp (dma) */ | |
4244 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
4245 | .master = &omap44xx_l4_abe_hwmod, | |
4246 | .slave = &omap44xx_mcasp_hwmod, | |
4247 | .clk = "ocp_abe_iclk", | |
4248 | .addr = omap44xx_mcasp_dma_addrs, | |
4249 | .user = OCP_USER_SDMA, | |
4250 | }; | |
4251 | ||
844a3b63 PW |
4252 | /* l4_abe -> mcbsp1 */ |
4253 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4254 | .master = &omap44xx_l4_abe_hwmod, | |
4255 | .slave = &omap44xx_mcbsp1_hwmod, | |
4256 | .clk = "ocp_abe_iclk", | |
e3491795 | 4257 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4258 | }; |
4259 | ||
844a3b63 PW |
4260 | /* l4_abe -> mcbsp2 */ |
4261 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4262 | .master = &omap44xx_l4_abe_hwmod, | |
4263 | .slave = &omap44xx_mcbsp2_hwmod, | |
4264 | .clk = "ocp_abe_iclk", | |
e3491795 | 4265 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4266 | }; |
4267 | ||
844a3b63 PW |
4268 | /* l4_abe -> mcbsp3 */ |
4269 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
4270 | .master = &omap44xx_l4_abe_hwmod, | |
4271 | .slave = &omap44xx_mcbsp3_hwmod, | |
4272 | .clk = "ocp_abe_iclk", | |
e3491795 | 4273 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4274 | }; |
4275 | ||
844a3b63 PW |
4276 | /* l4_per -> mcbsp4 */ |
4277 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
4278 | .master = &omap44xx_l4_per_hwmod, | |
4279 | .slave = &omap44xx_mcbsp4_hwmod, | |
4280 | .clk = "l4_div_ck", | |
844a3b63 PW |
4281 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4282 | }; | |
4283 | ||
844a3b63 PW |
4284 | /* l4_abe -> mcpdm */ |
4285 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
4286 | .master = &omap44xx_l4_abe_hwmod, | |
4287 | .slave = &omap44xx_mcpdm_hwmod, | |
4288 | .clk = "ocp_abe_iclk", | |
e3491795 | 4289 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4290 | }; |
4291 | ||
844a3b63 PW |
4292 | /* l4_per -> mcspi1 */ |
4293 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
4294 | .master = &omap44xx_l4_per_hwmod, | |
4295 | .slave = &omap44xx_mcspi1_hwmod, | |
4296 | .clk = "l4_div_ck", | |
844a3b63 PW |
4297 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4298 | }; | |
4299 | ||
844a3b63 PW |
4300 | /* l4_per -> mcspi2 */ |
4301 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
4302 | .master = &omap44xx_l4_per_hwmod, | |
4303 | .slave = &omap44xx_mcspi2_hwmod, | |
4304 | .clk = "l4_div_ck", | |
844a3b63 PW |
4305 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4306 | }; | |
4307 | ||
844a3b63 PW |
4308 | /* l4_per -> mcspi3 */ |
4309 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
4310 | .master = &omap44xx_l4_per_hwmod, | |
4311 | .slave = &omap44xx_mcspi3_hwmod, | |
4312 | .clk = "l4_div_ck", | |
844a3b63 PW |
4313 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4314 | }; | |
4315 | ||
844a3b63 PW |
4316 | /* l4_per -> mcspi4 */ |
4317 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
4318 | .master = &omap44xx_l4_per_hwmod, | |
4319 | .slave = &omap44xx_mcspi4_hwmod, | |
4320 | .clk = "l4_div_ck", | |
844a3b63 PW |
4321 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4322 | }; | |
4323 | ||
844a3b63 PW |
4324 | /* l4_per -> mmc1 */ |
4325 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
4326 | .master = &omap44xx_l4_per_hwmod, | |
4327 | .slave = &omap44xx_mmc1_hwmod, | |
4328 | .clk = "l4_div_ck", | |
844a3b63 PW |
4329 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4330 | }; | |
4331 | ||
844a3b63 PW |
4332 | /* l4_per -> mmc2 */ |
4333 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
4334 | .master = &omap44xx_l4_per_hwmod, | |
4335 | .slave = &omap44xx_mmc2_hwmod, | |
4336 | .clk = "l4_div_ck", | |
844a3b63 PW |
4337 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4338 | }; | |
4339 | ||
844a3b63 PW |
4340 | /* l4_per -> mmc3 */ |
4341 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
4342 | .master = &omap44xx_l4_per_hwmod, | |
4343 | .slave = &omap44xx_mmc3_hwmod, | |
4344 | .clk = "l4_div_ck", | |
844a3b63 PW |
4345 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4346 | }; | |
4347 | ||
844a3b63 PW |
4348 | /* l4_per -> mmc4 */ |
4349 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
4350 | .master = &omap44xx_l4_per_hwmod, | |
4351 | .slave = &omap44xx_mmc4_hwmod, | |
4352 | .clk = "l4_div_ck", | |
844a3b63 PW |
4353 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4354 | }; | |
4355 | ||
844a3b63 PW |
4356 | /* l4_per -> mmc5 */ |
4357 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
4358 | .master = &omap44xx_l4_per_hwmod, | |
4359 | .slave = &omap44xx_mmc5_hwmod, | |
4360 | .clk = "l4_div_ck", | |
844a3b63 PW |
4361 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4362 | }; | |
4363 | ||
e17f18c0 PW |
4364 | /* l3_main_2 -> ocmc_ram */ |
4365 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
4366 | .master = &omap44xx_l3_main_2_hwmod, | |
4367 | .slave = &omap44xx_ocmc_ram_hwmod, | |
4368 | .clk = "l3_div_ck", | |
4369 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4370 | }; | |
4371 | ||
0c668875 BC |
4372 | /* l4_cfg -> ocp2scp_usb_phy */ |
4373 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
4374 | .master = &omap44xx_l4_cfg_hwmod, | |
4375 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
4376 | .clk = "l4_div_ck", | |
4377 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4378 | }; | |
4379 | ||
794b480a PW |
4380 | /* mpu_private -> prcm_mpu */ |
4381 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
4382 | .master = &omap44xx_mpu_private_hwmod, | |
4383 | .slave = &omap44xx_prcm_mpu_hwmod, | |
4384 | .clk = "l3_div_ck", | |
794b480a PW |
4385 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4386 | }; | |
4387 | ||
794b480a PW |
4388 | /* l4_wkup -> cm_core_aon */ |
4389 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
4390 | .master = &omap44xx_l4_wkup_hwmod, | |
4391 | .slave = &omap44xx_cm_core_aon_hwmod, | |
4392 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4393 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4394 | }; | |
4395 | ||
794b480a PW |
4396 | /* l4_cfg -> cm_core */ |
4397 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
4398 | .master = &omap44xx_l4_cfg_hwmod, | |
4399 | .slave = &omap44xx_cm_core_hwmod, | |
4400 | .clk = "l4_div_ck", | |
794b480a PW |
4401 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4402 | }; | |
4403 | ||
794b480a PW |
4404 | /* l4_wkup -> prm */ |
4405 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
4406 | .master = &omap44xx_l4_wkup_hwmod, | |
4407 | .slave = &omap44xx_prm_hwmod, | |
4408 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4409 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4410 | }; | |
4411 | ||
794b480a PW |
4412 | /* l4_wkup -> scrm */ |
4413 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
4414 | .master = &omap44xx_l4_wkup_hwmod, | |
4415 | .slave = &omap44xx_scrm_hwmod, | |
4416 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4417 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4418 | }; | |
4419 | ||
42b9e387 | 4420 | /* l3_main_2 -> sl2if */ |
b360124e | 4421 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
4422 | .master = &omap44xx_l3_main_2_hwmod, |
4423 | .slave = &omap44xx_sl2if_hwmod, | |
4424 | .clk = "l3_div_ck", | |
4425 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4426 | }; | |
4427 | ||
1e3b5e59 BC |
4428 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
4429 | { | |
4430 | .pa_start = 0x4012c000, | |
4431 | .pa_end = 0x4012c3ff, | |
4432 | .flags = ADDR_TYPE_RT | |
4433 | }, | |
4434 | { } | |
4435 | }; | |
4436 | ||
4437 | /* l4_abe -> slimbus1 */ | |
4438 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
4439 | .master = &omap44xx_l4_abe_hwmod, | |
4440 | .slave = &omap44xx_slimbus1_hwmod, | |
4441 | .clk = "ocp_abe_iclk", | |
4442 | .addr = omap44xx_slimbus1_addrs, | |
4443 | .user = OCP_USER_MPU, | |
4444 | }; | |
4445 | ||
4446 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
4447 | { | |
4448 | .pa_start = 0x4902c000, | |
4449 | .pa_end = 0x4902c3ff, | |
4450 | .flags = ADDR_TYPE_RT | |
4451 | }, | |
4452 | { } | |
4453 | }; | |
4454 | ||
4455 | /* l4_abe -> slimbus1 (dma) */ | |
4456 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
4457 | .master = &omap44xx_l4_abe_hwmod, | |
4458 | .slave = &omap44xx_slimbus1_hwmod, | |
4459 | .clk = "ocp_abe_iclk", | |
4460 | .addr = omap44xx_slimbus1_dma_addrs, | |
4461 | .user = OCP_USER_SDMA, | |
4462 | }; | |
4463 | ||
4464 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
4465 | { | |
4466 | .pa_start = 0x48076000, | |
4467 | .pa_end = 0x480763ff, | |
4468 | .flags = ADDR_TYPE_RT | |
4469 | }, | |
4470 | { } | |
4471 | }; | |
4472 | ||
4473 | /* l4_per -> slimbus2 */ | |
4474 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
4475 | .master = &omap44xx_l4_per_hwmod, | |
4476 | .slave = &omap44xx_slimbus2_hwmod, | |
4477 | .clk = "l4_div_ck", | |
4478 | .addr = omap44xx_slimbus2_addrs, | |
4479 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4480 | }; | |
4481 | ||
844a3b63 PW |
4482 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
4483 | { | |
4484 | .pa_start = 0x4a0dd000, | |
4485 | .pa_end = 0x4a0dd03f, | |
4486 | .flags = ADDR_TYPE_RT | |
4487 | }, | |
4488 | { } | |
4489 | }; | |
4490 | ||
4491 | /* l4_cfg -> smartreflex_core */ | |
4492 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
4493 | .master = &omap44xx_l4_cfg_hwmod, | |
4494 | .slave = &omap44xx_smartreflex_core_hwmod, | |
4495 | .clk = "l4_div_ck", | |
4496 | .addr = omap44xx_smartreflex_core_addrs, | |
4497 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4498 | }; | |
4499 | ||
4500 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
4501 | { | |
4502 | .pa_start = 0x4a0db000, | |
4503 | .pa_end = 0x4a0db03f, | |
4504 | .flags = ADDR_TYPE_RT | |
4505 | }, | |
4506 | { } | |
4507 | }; | |
4508 | ||
4509 | /* l4_cfg -> smartreflex_iva */ | |
4510 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
4511 | .master = &omap44xx_l4_cfg_hwmod, | |
4512 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
4513 | .clk = "l4_div_ck", | |
4514 | .addr = omap44xx_smartreflex_iva_addrs, | |
4515 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4516 | }; | |
4517 | ||
4518 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
4519 | { | |
4520 | .pa_start = 0x4a0d9000, | |
4521 | .pa_end = 0x4a0d903f, | |
4522 | .flags = ADDR_TYPE_RT | |
4523 | }, | |
4524 | { } | |
4525 | }; | |
4526 | ||
4527 | /* l4_cfg -> smartreflex_mpu */ | |
4528 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
4529 | .master = &omap44xx_l4_cfg_hwmod, | |
4530 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
4531 | .clk = "l4_div_ck", | |
4532 | .addr = omap44xx_smartreflex_mpu_addrs, | |
4533 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4534 | }; | |
4535 | ||
844a3b63 PW |
4536 | /* l4_cfg -> spinlock */ |
4537 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
4538 | .master = &omap44xx_l4_cfg_hwmod, | |
4539 | .slave = &omap44xx_spinlock_hwmod, | |
4540 | .clk = "l4_div_ck", | |
844a3b63 PW |
4541 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4542 | }; | |
4543 | ||
844a3b63 PW |
4544 | /* l4_wkup -> timer1 */ |
4545 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
4546 | .master = &omap44xx_l4_wkup_hwmod, | |
4547 | .slave = &omap44xx_timer1_hwmod, | |
4548 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4549 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4550 | }; | |
4551 | ||
844a3b63 PW |
4552 | /* l4_per -> timer2 */ |
4553 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
4554 | .master = &omap44xx_l4_per_hwmod, | |
4555 | .slave = &omap44xx_timer2_hwmod, | |
4556 | .clk = "l4_div_ck", | |
844a3b63 PW |
4557 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4558 | }; | |
4559 | ||
844a3b63 PW |
4560 | /* l4_per -> timer3 */ |
4561 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
4562 | .master = &omap44xx_l4_per_hwmod, | |
4563 | .slave = &omap44xx_timer3_hwmod, | |
4564 | .clk = "l4_div_ck", | |
844a3b63 PW |
4565 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4566 | }; | |
4567 | ||
844a3b63 PW |
4568 | /* l4_per -> timer4 */ |
4569 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
4570 | .master = &omap44xx_l4_per_hwmod, | |
4571 | .slave = &omap44xx_timer4_hwmod, | |
4572 | .clk = "l4_div_ck", | |
844a3b63 PW |
4573 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4574 | }; | |
4575 | ||
844a3b63 PW |
4576 | /* l4_abe -> timer5 */ |
4577 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
4578 | .master = &omap44xx_l4_abe_hwmod, | |
4579 | .slave = &omap44xx_timer5_hwmod, | |
4580 | .clk = "ocp_abe_iclk", | |
e3491795 | 4581 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4582 | }; |
4583 | ||
844a3b63 PW |
4584 | /* l4_abe -> timer6 */ |
4585 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
4586 | .master = &omap44xx_l4_abe_hwmod, | |
4587 | .slave = &omap44xx_timer6_hwmod, | |
4588 | .clk = "ocp_abe_iclk", | |
e3491795 | 4589 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4590 | }; |
4591 | ||
844a3b63 PW |
4592 | /* l4_abe -> timer7 */ |
4593 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
4594 | .master = &omap44xx_l4_abe_hwmod, | |
4595 | .slave = &omap44xx_timer7_hwmod, | |
4596 | .clk = "ocp_abe_iclk", | |
e3491795 | 4597 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4598 | }; |
4599 | ||
844a3b63 PW |
4600 | /* l4_abe -> timer8 */ |
4601 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
4602 | .master = &omap44xx_l4_abe_hwmod, | |
4603 | .slave = &omap44xx_timer8_hwmod, | |
4604 | .clk = "ocp_abe_iclk", | |
e3491795 | 4605 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4606 | }; |
4607 | ||
844a3b63 PW |
4608 | /* l4_per -> timer9 */ |
4609 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
4610 | .master = &omap44xx_l4_per_hwmod, | |
4611 | .slave = &omap44xx_timer9_hwmod, | |
4612 | .clk = "l4_div_ck", | |
844a3b63 PW |
4613 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4614 | }; | |
4615 | ||
844a3b63 PW |
4616 | /* l4_per -> timer10 */ |
4617 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
4618 | .master = &omap44xx_l4_per_hwmod, | |
4619 | .slave = &omap44xx_timer10_hwmod, | |
4620 | .clk = "l4_div_ck", | |
844a3b63 PW |
4621 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4622 | }; | |
4623 | ||
844a3b63 PW |
4624 | /* l4_per -> timer11 */ |
4625 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
4626 | .master = &omap44xx_l4_per_hwmod, | |
4627 | .slave = &omap44xx_timer11_hwmod, | |
4628 | .clk = "l4_div_ck", | |
af88fa9a BC |
4629 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4630 | }; | |
4631 | ||
844a3b63 PW |
4632 | /* l4_per -> uart1 */ |
4633 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
4634 | .master = &omap44xx_l4_per_hwmod, | |
4635 | .slave = &omap44xx_uart1_hwmod, | |
4636 | .clk = "l4_div_ck", | |
844a3b63 PW |
4637 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4638 | }; | |
af88fa9a | 4639 | |
844a3b63 PW |
4640 | /* l4_per -> uart2 */ |
4641 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
4642 | .master = &omap44xx_l4_per_hwmod, | |
4643 | .slave = &omap44xx_uart2_hwmod, | |
4644 | .clk = "l4_div_ck", | |
844a3b63 PW |
4645 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4646 | }; | |
af88fa9a | 4647 | |
844a3b63 PW |
4648 | /* l4_per -> uart3 */ |
4649 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
4650 | .master = &omap44xx_l4_per_hwmod, | |
4651 | .slave = &omap44xx_uart3_hwmod, | |
4652 | .clk = "l4_div_ck", | |
844a3b63 | 4653 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
af88fa9a BC |
4654 | }; |
4655 | ||
844a3b63 PW |
4656 | /* l4_per -> uart4 */ |
4657 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
4658 | .master = &omap44xx_l4_per_hwmod, | |
4659 | .slave = &omap44xx_uart4_hwmod, | |
4660 | .clk = "l4_div_ck", | |
844a3b63 PW |
4661 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4662 | }; | |
4663 | ||
0c668875 | 4664 | /* l4_cfg -> usb_host_fs */ |
b0a70cc8 | 4665 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
4666 | .master = &omap44xx_l4_cfg_hwmod, |
4667 | .slave = &omap44xx_usb_host_fs_hwmod, | |
4668 | .clk = "l4_div_ck", | |
0c668875 BC |
4669 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4670 | }; | |
4671 | ||
844a3b63 PW |
4672 | /* l4_cfg -> usb_host_hs */ |
4673 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
4674 | .master = &omap44xx_l4_cfg_hwmod, | |
4675 | .slave = &omap44xx_usb_host_hs_hwmod, | |
4676 | .clk = "l4_div_ck", | |
844a3b63 PW |
4677 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4678 | }; | |
4679 | ||
844a3b63 PW |
4680 | /* l4_cfg -> usb_otg_hs */ |
4681 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
4682 | .master = &omap44xx_l4_cfg_hwmod, | |
4683 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
4684 | .clk = "l4_div_ck", | |
844a3b63 | 4685 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
af88fa9a BC |
4686 | }; |
4687 | ||
844a3b63 | 4688 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
4689 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
4690 | .master = &omap44xx_l4_cfg_hwmod, | |
4691 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
4692 | .clk = "l4_div_ck", | |
af88fa9a BC |
4693 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4694 | }; | |
4695 | ||
844a3b63 PW |
4696 | /* l4_wkup -> wd_timer2 */ |
4697 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
4698 | .master = &omap44xx_l4_wkup_hwmod, | |
4699 | .slave = &omap44xx_wd_timer2_hwmod, | |
4700 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4701 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4702 | }; | |
4703 | ||
4704 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
4705 | { | |
4706 | .pa_start = 0x40130000, | |
4707 | .pa_end = 0x4013007f, | |
4708 | .flags = ADDR_TYPE_RT | |
4709 | }, | |
4710 | { } | |
4711 | }; | |
4712 | ||
4713 | /* l4_abe -> wd_timer3 */ | |
4714 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
4715 | .master = &omap44xx_l4_abe_hwmod, | |
4716 | .slave = &omap44xx_wd_timer3_hwmod, | |
4717 | .clk = "ocp_abe_iclk", | |
4718 | .addr = omap44xx_wd_timer3_addrs, | |
4719 | .user = OCP_USER_MPU, | |
4720 | }; | |
4721 | ||
4722 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
4723 | { | |
4724 | .pa_start = 0x49030000, | |
4725 | .pa_end = 0x4903007f, | |
4726 | .flags = ADDR_TYPE_RT | |
4727 | }, | |
4728 | { } | |
4729 | }; | |
4730 | ||
4731 | /* l4_abe -> wd_timer3 (dma) */ | |
4732 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
4733 | .master = &omap44xx_l4_abe_hwmod, | |
4734 | .slave = &omap44xx_wd_timer3_hwmod, | |
4735 | .clk = "ocp_abe_iclk", | |
4736 | .addr = omap44xx_wd_timer3_dma_addrs, | |
4737 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
4738 | }; |
4739 | ||
3b9b1015 S |
4740 | /* mpu -> emif1 */ |
4741 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { | |
4742 | .master = &omap44xx_mpu_hwmod, | |
4743 | .slave = &omap44xx_emif1_hwmod, | |
4744 | .clk = "l3_div_ck", | |
4745 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4746 | }; | |
4747 | ||
4748 | /* mpu -> emif2 */ | |
4749 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { | |
4750 | .master = &omap44xx_mpu_hwmod, | |
4751 | .slave = &omap44xx_emif2_hwmod, | |
4752 | .clk = "l3_div_ck", | |
4753 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4754 | }; | |
4755 | ||
0a78c5c5 PW |
4756 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
4757 | &omap44xx_l3_main_1__dmm, | |
4758 | &omap44xx_mpu__dmm, | |
0a78c5c5 PW |
4759 | &omap44xx_iva__l3_instr, |
4760 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 4761 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
4762 | &omap44xx_dsp__l3_main_1, |
4763 | &omap44xx_dss__l3_main_1, | |
4764 | &omap44xx_l3_main_2__l3_main_1, | |
4765 | &omap44xx_l4_cfg__l3_main_1, | |
4766 | &omap44xx_mmc1__l3_main_1, | |
4767 | &omap44xx_mmc2__l3_main_1, | |
4768 | &omap44xx_mpu__l3_main_1, | |
96566043 | 4769 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 4770 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 4771 | &omap44xx_fdif__l3_main_2, |
9def390e | 4772 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
4773 | &omap44xx_hsi__l3_main_2, |
4774 | &omap44xx_ipu__l3_main_2, | |
4775 | &omap44xx_iss__l3_main_2, | |
4776 | &omap44xx_iva__l3_main_2, | |
4777 | &omap44xx_l3_main_1__l3_main_2, | |
4778 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 4779 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
4780 | &omap44xx_usb_host_hs__l3_main_2, |
4781 | &omap44xx_usb_otg_hs__l3_main_2, | |
4782 | &omap44xx_l3_main_1__l3_main_3, | |
4783 | &omap44xx_l3_main_2__l3_main_3, | |
4784 | &omap44xx_l4_cfg__l3_main_3, | |
5cebb23c | 4785 | &omap44xx_aess__l4_abe, |
0a78c5c5 PW |
4786 | &omap44xx_dsp__l4_abe, |
4787 | &omap44xx_l3_main_1__l4_abe, | |
4788 | &omap44xx_mpu__l4_abe, | |
4789 | &omap44xx_l3_main_1__l4_cfg, | |
4790 | &omap44xx_l3_main_2__l4_per, | |
4791 | &omap44xx_l4_cfg__l4_wkup, | |
4792 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 4793 | &omap44xx_l4_cfg__ocp_wp_noc, |
5cebb23c SG |
4794 | &omap44xx_l4_abe__aess, |
4795 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 4796 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 4797 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
4798 | &omap44xx_l4_cfg__ctrl_module_core, |
4799 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
4800 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
4801 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 4802 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
4803 | &omap44xx_l4_cfg__dma_system, |
4804 | &omap44xx_l4_abe__dmic, | |
0a78c5c5 | 4805 | &omap44xx_dsp__iva, |
b360124e | 4806 | /* &omap44xx_dsp__sl2if, */ |
0a78c5c5 PW |
4807 | &omap44xx_l4_cfg__dsp, |
4808 | &omap44xx_l3_main_2__dss, | |
4809 | &omap44xx_l4_per__dss, | |
4810 | &omap44xx_l3_main_2__dss_dispc, | |
4811 | &omap44xx_l4_per__dss_dispc, | |
4812 | &omap44xx_l3_main_2__dss_dsi1, | |
4813 | &omap44xx_l4_per__dss_dsi1, | |
4814 | &omap44xx_l3_main_2__dss_dsi2, | |
4815 | &omap44xx_l4_per__dss_dsi2, | |
4816 | &omap44xx_l3_main_2__dss_hdmi, | |
4817 | &omap44xx_l4_per__dss_hdmi, | |
4818 | &omap44xx_l3_main_2__dss_rfbi, | |
4819 | &omap44xx_l4_per__dss_rfbi, | |
4820 | &omap44xx_l3_main_2__dss_venc, | |
4821 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 4822 | &omap44xx_l4_per__elm, |
b050f688 | 4823 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
4824 | &omap44xx_l4_wkup__gpio1, |
4825 | &omap44xx_l4_per__gpio2, | |
4826 | &omap44xx_l4_per__gpio3, | |
4827 | &omap44xx_l4_per__gpio4, | |
4828 | &omap44xx_l4_per__gpio5, | |
4829 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 4830 | &omap44xx_l3_main_2__gpmc, |
9def390e | 4831 | &omap44xx_l3_main_2__gpu, |
a091c08e | 4832 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
4833 | &omap44xx_l4_cfg__hsi, |
4834 | &omap44xx_l4_per__i2c1, | |
4835 | &omap44xx_l4_per__i2c2, | |
4836 | &omap44xx_l4_per__i2c3, | |
4837 | &omap44xx_l4_per__i2c4, | |
4838 | &omap44xx_l3_main_2__ipu, | |
4839 | &omap44xx_l3_main_2__iss, | |
b360124e | 4840 | /* &omap44xx_iva__sl2if, */ |
0a78c5c5 PW |
4841 | &omap44xx_l3_main_2__iva, |
4842 | &omap44xx_l4_wkup__kbd, | |
4843 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
4844 | &omap44xx_l4_abe__mcasp, |
4845 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 | 4846 | &omap44xx_l4_abe__mcbsp1, |
0a78c5c5 | 4847 | &omap44xx_l4_abe__mcbsp2, |
0a78c5c5 | 4848 | &omap44xx_l4_abe__mcbsp3, |
0a78c5c5 PW |
4849 | &omap44xx_l4_per__mcbsp4, |
4850 | &omap44xx_l4_abe__mcpdm, | |
0a78c5c5 PW |
4851 | &omap44xx_l4_per__mcspi1, |
4852 | &omap44xx_l4_per__mcspi2, | |
4853 | &omap44xx_l4_per__mcspi3, | |
4854 | &omap44xx_l4_per__mcspi4, | |
4855 | &omap44xx_l4_per__mmc1, | |
4856 | &omap44xx_l4_per__mmc2, | |
4857 | &omap44xx_l4_per__mmc3, | |
4858 | &omap44xx_l4_per__mmc4, | |
4859 | &omap44xx_l4_per__mmc5, | |
230844db ORL |
4860 | &omap44xx_l3_main_2__mmu_ipu, |
4861 | &omap44xx_l4_cfg__mmu_dsp, | |
e17f18c0 | 4862 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 4863 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
4864 | &omap44xx_mpu_private__prcm_mpu, |
4865 | &omap44xx_l4_wkup__cm_core_aon, | |
4866 | &omap44xx_l4_cfg__cm_core, | |
4867 | &omap44xx_l4_wkup__prm, | |
4868 | &omap44xx_l4_wkup__scrm, | |
b360124e | 4869 | /* &omap44xx_l3_main_2__sl2if, */ |
1e3b5e59 BC |
4870 | &omap44xx_l4_abe__slimbus1, |
4871 | &omap44xx_l4_abe__slimbus1_dma, | |
4872 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
4873 | &omap44xx_l4_cfg__smartreflex_core, |
4874 | &omap44xx_l4_cfg__smartreflex_iva, | |
4875 | &omap44xx_l4_cfg__smartreflex_mpu, | |
4876 | &omap44xx_l4_cfg__spinlock, | |
4877 | &omap44xx_l4_wkup__timer1, | |
4878 | &omap44xx_l4_per__timer2, | |
4879 | &omap44xx_l4_per__timer3, | |
4880 | &omap44xx_l4_per__timer4, | |
4881 | &omap44xx_l4_abe__timer5, | |
0a78c5c5 | 4882 | &omap44xx_l4_abe__timer6, |
0a78c5c5 | 4883 | &omap44xx_l4_abe__timer7, |
0a78c5c5 | 4884 | &omap44xx_l4_abe__timer8, |
0a78c5c5 PW |
4885 | &omap44xx_l4_per__timer9, |
4886 | &omap44xx_l4_per__timer10, | |
4887 | &omap44xx_l4_per__timer11, | |
4888 | &omap44xx_l4_per__uart1, | |
4889 | &omap44xx_l4_per__uart2, | |
4890 | &omap44xx_l4_per__uart3, | |
4891 | &omap44xx_l4_per__uart4, | |
b0a70cc8 | 4892 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
4893 | &omap44xx_l4_cfg__usb_host_hs, |
4894 | &omap44xx_l4_cfg__usb_otg_hs, | |
4895 | &omap44xx_l4_cfg__usb_tll_hs, | |
4896 | &omap44xx_l4_wkup__wd_timer2, | |
4897 | &omap44xx_l4_abe__wd_timer3, | |
4898 | &omap44xx_l4_abe__wd_timer3_dma, | |
3b9b1015 S |
4899 | &omap44xx_mpu__emif1, |
4900 | &omap44xx_mpu__emif2, | |
9a9ded89 | 4901 | &omap44xx_l3_main_2__aes1, |
478523dd | 4902 | &omap44xx_l3_main_2__aes2, |
ebea90df | 4903 | &omap44xx_l3_main_2__des, |
55d2cb08 BC |
4904 | NULL, |
4905 | }; | |
4906 | ||
4907 | int __init omap44xx_hwmod_init(void) | |
4908 | { | |
9ebfd285 | 4909 | omap_hwmod_init(); |
0a78c5c5 | 4910 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
4911 | } |
4912 |