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Commit | Line | Data |
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6f88e9bc KH |
1 | /* |
2 | * pm.c - Common OMAP2+ power management-related code | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/err.h> | |
e4db1c74 | 16 | #include <linux/pm_opp.h> |
dc28094b | 17 | #include <linux/export.h> |
1416408d | 18 | #include <linux/suspend.h> |
24d7b40a | 19 | #include <linux/cpu.h> |
6f88e9bc | 20 | |
335aece5 G |
21 | #include <asm/system_misc.h> |
22 | ||
1d5aef49 | 23 | #include "omap-pm.h" |
25c7d49e | 24 | #include "omap_device.h" |
4e65331c | 25 | #include "common.h" |
6f88e9bc | 26 | |
e4c060db | 27 | #include "soc.h" |
1416408d | 28 | #include "prcm-common.h" |
e1d6f472 | 29 | #include "voltage.h" |
72e06d08 | 30 | #include "powerdomain.h" |
1540f214 | 31 | #include "clockdomain.h" |
0c0a5d61 | 32 | #include "pm.h" |
46232a36 | 33 | #include "twl-common.h" |
eb6a2c75 | 34 | |
2e4b62dc | 35 | #ifdef CONFIG_SUSPEND |
1416408d PW |
36 | /* |
37 | * omap_pm_suspend: points to a function that does the SoC-specific | |
38 | * suspend work | |
39 | */ | |
2e4b62dc DG |
40 | static int (*omap_pm_suspend)(void); |
41 | #endif | |
1416408d | 42 | |
74d29168 | 43 | #ifdef CONFIG_PM |
908b75e8 TK |
44 | /** |
45 | * struct omap2_oscillator - Describe the board main oscillator latencies | |
46 | * @startup_time: oscillator startup latency | |
47 | * @shutdown_time: oscillator shutdown latency | |
48 | */ | |
49 | struct omap2_oscillator { | |
50 | u32 startup_time; | |
51 | u32 shutdown_time; | |
52 | }; | |
53 | ||
54 | static struct omap2_oscillator oscillator = { | |
55 | .startup_time = ULONG_MAX, | |
56 | .shutdown_time = ULONG_MAX, | |
57 | }; | |
58 | ||
59 | void omap_pm_setup_oscillator(u32 tstart, u32 tshut) | |
60 | { | |
61 | oscillator.startup_time = tstart; | |
62 | oscillator.shutdown_time = tshut; | |
63 | } | |
64 | ||
65 | void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) | |
66 | { | |
67 | if (!tstart || !tshut) | |
68 | return; | |
69 | ||
70 | *tstart = oscillator.startup_time; | |
71 | *tshut = oscillator.shutdown_time; | |
72 | } | |
74d29168 | 73 | #endif |
908b75e8 | 74 | |
9cf793f9 | 75 | static int __init _init_omap_device(char *name) |
6f88e9bc KH |
76 | { |
77 | struct omap_hwmod *oh; | |
3528c58e | 78 | struct platform_device *pdev; |
6f88e9bc KH |
79 | |
80 | oh = omap_hwmod_lookup(name); | |
81 | if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", | |
82 | __func__, name)) | |
83 | return -ENODEV; | |
84 | ||
c1d1cd59 | 85 | pdev = omap_device_build(oh->name, 0, oh, NULL, 0); |
3528c58e | 86 | if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", |
6f88e9bc KH |
87 | __func__, name)) |
88 | return -ENODEV; | |
89 | ||
6f88e9bc KH |
90 | return 0; |
91 | } | |
92 | ||
93 | /* | |
94 | * Build omap_devices for processors and bus. | |
95 | */ | |
1f3b372b | 96 | static void __init omap2_init_processor_devices(void) |
6f88e9bc | 97 | { |
766e7afc | 98 | _init_omap_device("mpu"); |
2de0baef | 99 | if (omap3_has_iva()) |
766e7afc | 100 | _init_omap_device("iva"); |
2de0baef | 101 | |
cbf27660 | 102 | if (cpu_is_omap44xx()) { |
766e7afc BC |
103 | _init_omap_device("l3_main_1"); |
104 | _init_omap_device("dsp"); | |
105 | _init_omap_device("iva"); | |
cbf27660 | 106 | } else { |
766e7afc | 107 | _init_omap_device("l3_main"); |
cbf27660 | 108 | } |
6f88e9bc KH |
109 | } |
110 | ||
92206fd2 PW |
111 | int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) |
112 | { | |
92493870 | 113 | /* XXX The usecount test is racy */ |
b71c7217 PW |
114 | if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && |
115 | !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) | |
92206fd2 PW |
116 | clkdm_allow_idle(clkdm); |
117 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
92493870 | 118 | clkdm->usecount == 0) |
92206fd2 PW |
119 | clkdm_sleep(clkdm); |
120 | return 0; | |
121 | } | |
122 | ||
1482d8be | 123 | /* |
1e2d2df3 | 124 | * This API is to be called during init to set the various voltage |
1482d8be TG |
125 | * domains to the voltage as per the opp table. Typically we boot up |
126 | * at the nominal voltage. So this function finds out the rate of | |
127 | * the clock associated with the voltage domain, finds out the correct | |
1e2d2df3 | 128 | * opp entry and sets the voltage domain to the voltage specified |
1482d8be TG |
129 | * in the opp entry |
130 | */ | |
131 | static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, | |
0f7aa005 | 132 | const char *oh_name) |
1482d8be TG |
133 | { |
134 | struct voltagedomain *voltdm; | |
135 | struct clk *clk; | |
47d43ba7 | 136 | struct dev_pm_opp *opp; |
1482d8be | 137 | unsigned long freq, bootup_volt; |
0f7aa005 | 138 | struct device *dev; |
1482d8be | 139 | |
0f7aa005 | 140 | if (!vdd_name || !clk_name || !oh_name) { |
e9a5190a | 141 | pr_err("%s: invalid parameters\n", __func__); |
1482d8be TG |
142 | goto exit; |
143 | } | |
144 | ||
24d7b40a KH |
145 | if (!strncmp(oh_name, "mpu", 3)) |
146 | /* | |
147 | * All current OMAPs share voltage rail and clock | |
148 | * source, so CPU0 is used to represent the MPU-SS. | |
149 | */ | |
150 | dev = get_cpu_device(0); | |
151 | else | |
152 | dev = omap_device_get_by_hwmod_name(oh_name); | |
153 | ||
0f7aa005 BC |
154 | if (IS_ERR(dev)) { |
155 | pr_err("%s: Unable to get dev pointer for hwmod %s\n", | |
156 | __func__, oh_name); | |
157 | goto exit; | |
158 | } | |
159 | ||
81a60482 | 160 | voltdm = voltdm_lookup(vdd_name); |
93b44bea | 161 | if (!voltdm) { |
e9a5190a | 162 | pr_err("%s: unable to get vdd pointer for vdd_%s\n", |
1482d8be TG |
163 | __func__, vdd_name); |
164 | goto exit; | |
165 | } | |
166 | ||
167 | clk = clk_get(NULL, clk_name); | |
168 | if (IS_ERR(clk)) { | |
e9a5190a | 169 | pr_err("%s: unable to get clk %s\n", __func__, clk_name); |
1482d8be TG |
170 | goto exit; |
171 | } | |
172 | ||
5dcc3b97 | 173 | freq = clk_get_rate(clk); |
1482d8be TG |
174 | clk_put(clk); |
175 | ||
6369fd41 | 176 | rcu_read_lock(); |
5d4879cd | 177 | opp = dev_pm_opp_find_freq_ceil(dev, &freq); |
1482d8be | 178 | if (IS_ERR(opp)) { |
6369fd41 | 179 | rcu_read_unlock(); |
e9a5190a | 180 | pr_err("%s: unable to find boot up OPP for vdd_%s\n", |
1482d8be TG |
181 | __func__, vdd_name); |
182 | goto exit; | |
183 | } | |
184 | ||
5d4879cd | 185 | bootup_volt = dev_pm_opp_get_voltage(opp); |
6369fd41 | 186 | rcu_read_unlock(); |
1482d8be | 187 | if (!bootup_volt) { |
7852ec05 PW |
188 | pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", |
189 | __func__, vdd_name); | |
1482d8be TG |
190 | goto exit; |
191 | } | |
192 | ||
5e5651be | 193 | voltdm_scale(voltdm, bootup_volt); |
1482d8be TG |
194 | return 0; |
195 | ||
196 | exit: | |
e9a5190a | 197 | pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); |
1482d8be TG |
198 | return -EINVAL; |
199 | } | |
200 | ||
1416408d PW |
201 | #ifdef CONFIG_SUSPEND |
202 | static int omap_pm_enter(suspend_state_t suspend_state) | |
203 | { | |
204 | int ret = 0; | |
205 | ||
206 | if (!omap_pm_suspend) | |
207 | return -ENOENT; /* XXX doublecheck */ | |
208 | ||
209 | switch (suspend_state) { | |
210 | case PM_SUSPEND_STANDBY: | |
211 | case PM_SUSPEND_MEM: | |
212 | ret = omap_pm_suspend(); | |
213 | break; | |
214 | default: | |
215 | ret = -EINVAL; | |
216 | } | |
217 | ||
218 | return ret; | |
219 | } | |
220 | ||
221 | static int omap_pm_begin(suspend_state_t state) | |
222 | { | |
f7b861b7 | 223 | cpu_idle_poll_ctrl(true); |
1416408d PW |
224 | if (cpu_is_omap34xx()) |
225 | omap_prcm_irq_prepare(); | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static void omap_pm_end(void) | |
230 | { | |
f7b861b7 | 231 | cpu_idle_poll_ctrl(false); |
1416408d PW |
232 | } |
233 | ||
234 | static void omap_pm_finish(void) | |
235 | { | |
236 | if (cpu_is_omap34xx()) | |
237 | omap_prcm_irq_complete(); | |
238 | } | |
239 | ||
240 | static const struct platform_suspend_ops omap_pm_ops = { | |
241 | .begin = omap_pm_begin, | |
242 | .end = omap_pm_end, | |
243 | .enter = omap_pm_enter, | |
244 | .finish = omap_pm_finish, | |
245 | .valid = suspend_valid_only_mem, | |
246 | }; | |
247 | ||
2e4b62dc DG |
248 | /** |
249 | * omap_common_suspend_init - Set common suspend routines for OMAP SoCs | |
250 | * @pm_suspend: function pointer to SoC specific suspend function | |
251 | */ | |
252 | void omap_common_suspend_init(void *pm_suspend) | |
253 | { | |
254 | omap_pm_suspend = pm_suspend; | |
255 | suspend_set_ops(&omap_pm_ops); | |
256 | } | |
1416408d PW |
257 | #endif /* CONFIG_SUSPEND */ |
258 | ||
1482d8be TG |
259 | static void __init omap3_init_voltages(void) |
260 | { | |
261 | if (!cpu_is_omap34xx()) | |
262 | return; | |
263 | ||
0f7aa005 BC |
264 | omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); |
265 | omap2_set_init_voltage("core", "l3_ick", "l3_main"); | |
1482d8be TG |
266 | } |
267 | ||
1376ee1d TG |
268 | static void __init omap4_init_voltages(void) |
269 | { | |
270 | if (!cpu_is_omap44xx()) | |
271 | return; | |
272 | ||
0f7aa005 BC |
273 | omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); |
274 | omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1"); | |
275 | omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); | |
1376ee1d TG |
276 | } |
277 | ||
49ded525 NM |
278 | static inline void omap_init_cpufreq(void) |
279 | { | |
60c5fc86 NM |
280 | struct platform_device_info devinfo = { }; |
281 | ||
282 | if (!of_have_populated_dt()) | |
283 | devinfo.name = "omap-cpufreq"; | |
284 | else | |
bbcf0719 | 285 | devinfo.name = "cpufreq-dt"; |
49ded525 NM |
286 | platform_device_register_full(&devinfo); |
287 | } | |
288 | ||
6f88e9bc KH |
289 | static int __init omap2_common_pm_init(void) |
290 | { | |
476b679a BC |
291 | if (!of_have_populated_dt()) |
292 | omap2_init_processor_devices(); | |
6f88e9bc KH |
293 | omap_pm_if_init(); |
294 | ||
295 | return 0; | |
296 | } | |
b76c8b19 | 297 | omap_postcore_initcall(omap2_common_pm_init); |
6f88e9bc | 298 | |
bbd707ac | 299 | int __init omap2_common_pm_late_init(void) |
2f34ce81 | 300 | { |
2ee5f528 TL |
301 | if (of_have_populated_dt()) { |
302 | omap3_twl_init(); | |
303 | omap4_twl_init(); | |
304 | } | |
1482d8be | 305 | |
2ee5f528 TL |
306 | /* Init the voltage layer */ |
307 | omap_pmic_late_init(); | |
308 | omap_voltage_late_init(); | |
1482d8be | 309 | |
2ee5f528 TL |
310 | /* Initialize the voltages */ |
311 | omap3_init_voltages(); | |
312 | omap4_init_voltages(); | |
49ded525 | 313 | |
2ee5f528 TL |
314 | /* Smartreflex device init */ |
315 | omap_devinit_smartreflex(); | |
2f34ce81 | 316 | |
60c5fc86 NM |
317 | /* cpufreq dummy device instantiation */ |
318 | omap_init_cpufreq(); | |
319 | ||
2f34ce81 TG |
320 | return 0; |
321 | } |