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Commit | Line | Data |
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6f88e9bc KH |
1 | /* |
2 | * pm.c - Common OMAP2+ power management-related code | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/err.h> | |
1482d8be | 16 | #include <linux/opp.h> |
dc28094b | 17 | #include <linux/export.h> |
1416408d | 18 | #include <linux/suspend.h> |
6f88e9bc KH |
19 | |
20 | #include <plat/omap-pm.h> | |
21 | #include <plat/omap_device.h> | |
4e65331c | 22 | #include "common.h" |
6f88e9bc | 23 | |
1416408d | 24 | #include "prcm-common.h" |
e1d6f472 | 25 | #include "voltage.h" |
72e06d08 | 26 | #include "powerdomain.h" |
1540f214 | 27 | #include "clockdomain.h" |
0c0a5d61 | 28 | #include "pm.h" |
46232a36 | 29 | #include "twl-common.h" |
eb6a2c75 | 30 | |
6f88e9bc KH |
31 | static struct omap_device_pm_latency *pm_lats; |
32 | ||
1416408d PW |
33 | /* |
34 | * omap_pm_suspend: points to a function that does the SoC-specific | |
35 | * suspend work | |
36 | */ | |
37 | int (*omap_pm_suspend)(void); | |
38 | ||
9cf793f9 | 39 | static int __init _init_omap_device(char *name) |
6f88e9bc KH |
40 | { |
41 | struct omap_hwmod *oh; | |
3528c58e | 42 | struct platform_device *pdev; |
6f88e9bc KH |
43 | |
44 | oh = omap_hwmod_lookup(name); | |
45 | if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", | |
46 | __func__, name)) | |
47 | return -ENODEV; | |
48 | ||
3528c58e KH |
49 | pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); |
50 | if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", | |
6f88e9bc KH |
51 | __func__, name)) |
52 | return -ENODEV; | |
53 | ||
6f88e9bc KH |
54 | return 0; |
55 | } | |
56 | ||
57 | /* | |
58 | * Build omap_devices for processors and bus. | |
59 | */ | |
1f3b372b | 60 | static void __init omap2_init_processor_devices(void) |
6f88e9bc | 61 | { |
766e7afc | 62 | _init_omap_device("mpu"); |
2de0baef | 63 | if (omap3_has_iva()) |
766e7afc | 64 | _init_omap_device("iva"); |
2de0baef | 65 | |
cbf27660 | 66 | if (cpu_is_omap44xx()) { |
766e7afc BC |
67 | _init_omap_device("l3_main_1"); |
68 | _init_omap_device("dsp"); | |
69 | _init_omap_device("iva"); | |
cbf27660 | 70 | } else { |
766e7afc | 71 | _init_omap_device("l3_main"); |
cbf27660 | 72 | } |
6f88e9bc KH |
73 | } |
74 | ||
71a488db RN |
75 | /* Types of sleep_switch used in omap_set_pwrdm_state */ |
76 | #define FORCEWAKEUP_SWITCH 0 | |
77 | #define LOWPOWERSTATE_SWITCH 1 | |
78 | ||
92206fd2 PW |
79 | int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) |
80 | { | |
81 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
82 | clkdm_allow_idle(clkdm); | |
83 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
84 | atomic_read(&clkdm->usecount) == 0) | |
85 | clkdm_sleep(clkdm); | |
86 | return 0; | |
87 | } | |
88 | ||
eb6a2c75 SS |
89 | /* |
90 | * This sets pwrdm state (other than mpu & core. Currently only ON & | |
33de32b3 | 91 | * RET are supported. |
eb6a2c75 | 92 | */ |
e68e8093 | 93 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst) |
eb6a2c75 | 94 | { |
e68e8093 PW |
95 | u8 curr_pwrst, next_pwrst; |
96 | int sleep_switch = -1, ret = 0, hwsup = 0; | |
eb6a2c75 | 97 | |
e68e8093 | 98 | if (!pwrdm || IS_ERR(pwrdm)) |
eb6a2c75 SS |
99 | return -EINVAL; |
100 | ||
e68e8093 PW |
101 | while (!(pwrdm->pwrsts & (1 << pwrst))) { |
102 | if (pwrst == PWRDM_POWER_OFF) | |
eb6a2c75 | 103 | return ret; |
e68e8093 | 104 | pwrst--; |
eb6a2c75 SS |
105 | } |
106 | ||
e68e8093 PW |
107 | next_pwrst = pwrdm_read_next_pwrst(pwrdm); |
108 | if (next_pwrst == pwrst) | |
eb6a2c75 SS |
109 | return ret; |
110 | ||
e68e8093 PW |
111 | curr_pwrst = pwrdm_read_pwrst(pwrdm); |
112 | if (curr_pwrst < PWRDM_POWER_ON) { | |
113 | if ((curr_pwrst > pwrst) && | |
71a488db RN |
114 | (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { |
115 | sleep_switch = LOWPOWERSTATE_SWITCH; | |
116 | } else { | |
b86cfb52 | 117 | hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]); |
68b921ad | 118 | clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
119 | sleep_switch = FORCEWAKEUP_SWITCH; |
120 | } | |
eb6a2c75 SS |
121 | } |
122 | ||
e68e8093 PW |
123 | ret = pwrdm_set_next_pwrst(pwrdm, pwrst); |
124 | if (ret) | |
125 | pr_err("%s: unable to set power state of powerdomain: %s\n", | |
e9a5190a | 126 | __func__, pwrdm->name); |
eb6a2c75 | 127 | |
71a488db RN |
128 | switch (sleep_switch) { |
129 | case FORCEWAKEUP_SWITCH: | |
b86cfb52 | 130 | if (hwsup) |
5cd1937b | 131 | clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); |
33de32b3 | 132 | else |
68b921ad | 133 | clkdm_sleep(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
134 | break; |
135 | case LOWPOWERSTATE_SWITCH: | |
136 | pwrdm_set_lowpwrstchange(pwrdm); | |
e68e8093 PW |
137 | pwrdm_wait_transition(pwrdm); |
138 | pwrdm_state_switch(pwrdm); | |
71a488db | 139 | break; |
eb6a2c75 SS |
140 | } |
141 | ||
eb6a2c75 SS |
142 | return ret; |
143 | } | |
144 | ||
1416408d PW |
145 | |
146 | ||
1482d8be | 147 | /* |
1e2d2df3 | 148 | * This API is to be called during init to set the various voltage |
1482d8be TG |
149 | * domains to the voltage as per the opp table. Typically we boot up |
150 | * at the nominal voltage. So this function finds out the rate of | |
151 | * the clock associated with the voltage domain, finds out the correct | |
1e2d2df3 | 152 | * opp entry and sets the voltage domain to the voltage specified |
1482d8be TG |
153 | * in the opp entry |
154 | */ | |
155 | static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, | |
0f7aa005 | 156 | const char *oh_name) |
1482d8be TG |
157 | { |
158 | struct voltagedomain *voltdm; | |
159 | struct clk *clk; | |
160 | struct opp *opp; | |
161 | unsigned long freq, bootup_volt; | |
0f7aa005 | 162 | struct device *dev; |
1482d8be | 163 | |
0f7aa005 | 164 | if (!vdd_name || !clk_name || !oh_name) { |
e9a5190a | 165 | pr_err("%s: invalid parameters\n", __func__); |
1482d8be TG |
166 | goto exit; |
167 | } | |
168 | ||
0f7aa005 BC |
169 | dev = omap_device_get_by_hwmod_name(oh_name); |
170 | if (IS_ERR(dev)) { | |
171 | pr_err("%s: Unable to get dev pointer for hwmod %s\n", | |
172 | __func__, oh_name); | |
173 | goto exit; | |
174 | } | |
175 | ||
81a60482 | 176 | voltdm = voltdm_lookup(vdd_name); |
1482d8be | 177 | if (IS_ERR(voltdm)) { |
e9a5190a | 178 | pr_err("%s: unable to get vdd pointer for vdd_%s\n", |
1482d8be TG |
179 | __func__, vdd_name); |
180 | goto exit; | |
181 | } | |
182 | ||
183 | clk = clk_get(NULL, clk_name); | |
184 | if (IS_ERR(clk)) { | |
e9a5190a | 185 | pr_err("%s: unable to get clk %s\n", __func__, clk_name); |
1482d8be TG |
186 | goto exit; |
187 | } | |
188 | ||
189 | freq = clk->rate; | |
190 | clk_put(clk); | |
191 | ||
6369fd41 | 192 | rcu_read_lock(); |
1482d8be TG |
193 | opp = opp_find_freq_ceil(dev, &freq); |
194 | if (IS_ERR(opp)) { | |
6369fd41 | 195 | rcu_read_unlock(); |
e9a5190a | 196 | pr_err("%s: unable to find boot up OPP for vdd_%s\n", |
1482d8be TG |
197 | __func__, vdd_name); |
198 | goto exit; | |
199 | } | |
200 | ||
201 | bootup_volt = opp_get_voltage(opp); | |
6369fd41 | 202 | rcu_read_unlock(); |
1482d8be | 203 | if (!bootup_volt) { |
e9a5190a | 204 | pr_err("%s: unable to find voltage corresponding " |
1482d8be TG |
205 | "to the bootup OPP for vdd_%s\n", __func__, vdd_name); |
206 | goto exit; | |
207 | } | |
208 | ||
5e5651be | 209 | voltdm_scale(voltdm, bootup_volt); |
1482d8be TG |
210 | return 0; |
211 | ||
212 | exit: | |
e9a5190a | 213 | pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); |
1482d8be TG |
214 | return -EINVAL; |
215 | } | |
216 | ||
1416408d PW |
217 | #ifdef CONFIG_SUSPEND |
218 | static int omap_pm_enter(suspend_state_t suspend_state) | |
219 | { | |
220 | int ret = 0; | |
221 | ||
222 | if (!omap_pm_suspend) | |
223 | return -ENOENT; /* XXX doublecheck */ | |
224 | ||
225 | switch (suspend_state) { | |
226 | case PM_SUSPEND_STANDBY: | |
227 | case PM_SUSPEND_MEM: | |
228 | ret = omap_pm_suspend(); | |
229 | break; | |
230 | default: | |
231 | ret = -EINVAL; | |
232 | } | |
233 | ||
234 | return ret; | |
235 | } | |
236 | ||
237 | static int omap_pm_begin(suspend_state_t state) | |
238 | { | |
239 | disable_hlt(); | |
240 | if (cpu_is_omap34xx()) | |
241 | omap_prcm_irq_prepare(); | |
242 | return 0; | |
243 | } | |
244 | ||
245 | static void omap_pm_end(void) | |
246 | { | |
247 | enable_hlt(); | |
248 | return; | |
249 | } | |
250 | ||
251 | static void omap_pm_finish(void) | |
252 | { | |
253 | if (cpu_is_omap34xx()) | |
254 | omap_prcm_irq_complete(); | |
255 | } | |
256 | ||
257 | static const struct platform_suspend_ops omap_pm_ops = { | |
258 | .begin = omap_pm_begin, | |
259 | .end = omap_pm_end, | |
260 | .enter = omap_pm_enter, | |
261 | .finish = omap_pm_finish, | |
262 | .valid = suspend_valid_only_mem, | |
263 | }; | |
264 | ||
265 | #endif /* CONFIG_SUSPEND */ | |
266 | ||
1482d8be TG |
267 | static void __init omap3_init_voltages(void) |
268 | { | |
269 | if (!cpu_is_omap34xx()) | |
270 | return; | |
271 | ||
0f7aa005 BC |
272 | omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); |
273 | omap2_set_init_voltage("core", "l3_ick", "l3_main"); | |
1482d8be TG |
274 | } |
275 | ||
1376ee1d TG |
276 | static void __init omap4_init_voltages(void) |
277 | { | |
278 | if (!cpu_is_omap44xx()) | |
279 | return; | |
280 | ||
0f7aa005 BC |
281 | omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); |
282 | omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1"); | |
283 | omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); | |
1376ee1d TG |
284 | } |
285 | ||
6f88e9bc KH |
286 | static int __init omap2_common_pm_init(void) |
287 | { | |
476b679a BC |
288 | if (!of_have_populated_dt()) |
289 | omap2_init_processor_devices(); | |
6f88e9bc KH |
290 | omap_pm_if_init(); |
291 | ||
292 | return 0; | |
293 | } | |
1cbbe37a | 294 | postcore_initcall(omap2_common_pm_init); |
6f88e9bc | 295 | |
2f34ce81 TG |
296 | static int __init omap2_common_pm_late_init(void) |
297 | { | |
506d81ef BC |
298 | /* |
299 | * In the case of DT, the PMIC and SR initialization will be done using | |
300 | * a completely different mechanism. | |
301 | * Disable this part if a DT blob is available. | |
302 | */ | |
303 | if (of_have_populated_dt()) | |
304 | return 0; | |
305 | ||
fbc319f6 | 306 | /* Init the voltage layer */ |
46232a36 | 307 | omap_pmic_late_init(); |
2f34ce81 | 308 | omap_voltage_late_init(); |
1482d8be TG |
309 | |
310 | /* Initialize the voltages */ | |
311 | omap3_init_voltages(); | |
1376ee1d | 312 | omap4_init_voltages(); |
1482d8be | 313 | |
fbc319f6 | 314 | /* Smartreflex device init */ |
0c0a5d61 | 315 | omap_devinit_smartreflex(); |
2f34ce81 | 316 | |
1416408d PW |
317 | #ifdef CONFIG_SUSPEND |
318 | suspend_set_ops(&omap_pm_ops); | |
319 | #endif | |
320 | ||
2f34ce81 TG |
321 | return 0; |
322 | } | |
323 | late_initcall(omap2_common_pm_late_init); |