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Commit | Line | Data |
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6f88e9bc KH |
1 | /* |
2 | * pm.c - Common OMAP2+ power management-related code | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/err.h> | |
1482d8be | 16 | #include <linux/opp.h> |
dc28094b | 17 | #include <linux/export.h> |
1416408d | 18 | #include <linux/suspend.h> |
24d7b40a | 19 | #include <linux/cpu.h> |
6f88e9bc | 20 | |
335aece5 G |
21 | #include <asm/system_misc.h> |
22 | ||
1d5aef49 | 23 | #include "omap-pm.h" |
25c7d49e | 24 | #include "omap_device.h" |
4e65331c | 25 | #include "common.h" |
6f88e9bc | 26 | |
e4c060db | 27 | #include "soc.h" |
1416408d | 28 | #include "prcm-common.h" |
e1d6f472 | 29 | #include "voltage.h" |
72e06d08 | 30 | #include "powerdomain.h" |
1540f214 | 31 | #include "clockdomain.h" |
0c0a5d61 | 32 | #include "pm.h" |
46232a36 | 33 | #include "twl-common.h" |
eb6a2c75 | 34 | |
1416408d PW |
35 | /* |
36 | * omap_pm_suspend: points to a function that does the SoC-specific | |
37 | * suspend work | |
38 | */ | |
39 | int (*omap_pm_suspend)(void); | |
40 | ||
74d29168 | 41 | #ifdef CONFIG_PM |
908b75e8 TK |
42 | /** |
43 | * struct omap2_oscillator - Describe the board main oscillator latencies | |
44 | * @startup_time: oscillator startup latency | |
45 | * @shutdown_time: oscillator shutdown latency | |
46 | */ | |
47 | struct omap2_oscillator { | |
48 | u32 startup_time; | |
49 | u32 shutdown_time; | |
50 | }; | |
51 | ||
52 | static struct omap2_oscillator oscillator = { | |
53 | .startup_time = ULONG_MAX, | |
54 | .shutdown_time = ULONG_MAX, | |
55 | }; | |
56 | ||
57 | void omap_pm_setup_oscillator(u32 tstart, u32 tshut) | |
58 | { | |
59 | oscillator.startup_time = tstart; | |
60 | oscillator.shutdown_time = tshut; | |
61 | } | |
62 | ||
63 | void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) | |
64 | { | |
65 | if (!tstart || !tshut) | |
66 | return; | |
67 | ||
68 | *tstart = oscillator.startup_time; | |
69 | *tshut = oscillator.shutdown_time; | |
70 | } | |
74d29168 | 71 | #endif |
908b75e8 | 72 | |
9cf793f9 | 73 | static int __init _init_omap_device(char *name) |
6f88e9bc KH |
74 | { |
75 | struct omap_hwmod *oh; | |
3528c58e | 76 | struct platform_device *pdev; |
6f88e9bc KH |
77 | |
78 | oh = omap_hwmod_lookup(name); | |
79 | if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", | |
80 | __func__, name)) | |
81 | return -ENODEV; | |
82 | ||
c1d1cd59 | 83 | pdev = omap_device_build(oh->name, 0, oh, NULL, 0); |
3528c58e | 84 | if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", |
6f88e9bc KH |
85 | __func__, name)) |
86 | return -ENODEV; | |
87 | ||
6f88e9bc KH |
88 | return 0; |
89 | } | |
90 | ||
91 | /* | |
92 | * Build omap_devices for processors and bus. | |
93 | */ | |
1f3b372b | 94 | static void __init omap2_init_processor_devices(void) |
6f88e9bc | 95 | { |
766e7afc | 96 | _init_omap_device("mpu"); |
2de0baef | 97 | if (omap3_has_iva()) |
766e7afc | 98 | _init_omap_device("iva"); |
2de0baef | 99 | |
cbf27660 | 100 | if (cpu_is_omap44xx()) { |
766e7afc BC |
101 | _init_omap_device("l3_main_1"); |
102 | _init_omap_device("dsp"); | |
103 | _init_omap_device("iva"); | |
cbf27660 | 104 | } else { |
766e7afc | 105 | _init_omap_device("l3_main"); |
cbf27660 | 106 | } |
6f88e9bc KH |
107 | } |
108 | ||
92206fd2 PW |
109 | int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) |
110 | { | |
92493870 | 111 | /* XXX The usecount test is racy */ |
b71c7217 PW |
112 | if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && |
113 | !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) | |
92206fd2 PW |
114 | clkdm_allow_idle(clkdm); |
115 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
92493870 | 116 | clkdm->usecount == 0) |
92206fd2 PW |
117 | clkdm_sleep(clkdm); |
118 | return 0; | |
119 | } | |
120 | ||
1482d8be | 121 | /* |
1e2d2df3 | 122 | * This API is to be called during init to set the various voltage |
1482d8be TG |
123 | * domains to the voltage as per the opp table. Typically we boot up |
124 | * at the nominal voltage. So this function finds out the rate of | |
125 | * the clock associated with the voltage domain, finds out the correct | |
1e2d2df3 | 126 | * opp entry and sets the voltage domain to the voltage specified |
1482d8be TG |
127 | * in the opp entry |
128 | */ | |
129 | static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, | |
0f7aa005 | 130 | const char *oh_name) |
1482d8be TG |
131 | { |
132 | struct voltagedomain *voltdm; | |
133 | struct clk *clk; | |
134 | struct opp *opp; | |
135 | unsigned long freq, bootup_volt; | |
0f7aa005 | 136 | struct device *dev; |
1482d8be | 137 | |
0f7aa005 | 138 | if (!vdd_name || !clk_name || !oh_name) { |
e9a5190a | 139 | pr_err("%s: invalid parameters\n", __func__); |
1482d8be TG |
140 | goto exit; |
141 | } | |
142 | ||
24d7b40a KH |
143 | if (!strncmp(oh_name, "mpu", 3)) |
144 | /* | |
145 | * All current OMAPs share voltage rail and clock | |
146 | * source, so CPU0 is used to represent the MPU-SS. | |
147 | */ | |
148 | dev = get_cpu_device(0); | |
149 | else | |
150 | dev = omap_device_get_by_hwmod_name(oh_name); | |
151 | ||
0f7aa005 BC |
152 | if (IS_ERR(dev)) { |
153 | pr_err("%s: Unable to get dev pointer for hwmod %s\n", | |
154 | __func__, oh_name); | |
155 | goto exit; | |
156 | } | |
157 | ||
81a60482 | 158 | voltdm = voltdm_lookup(vdd_name); |
93b44bea | 159 | if (!voltdm) { |
e9a5190a | 160 | pr_err("%s: unable to get vdd pointer for vdd_%s\n", |
1482d8be TG |
161 | __func__, vdd_name); |
162 | goto exit; | |
163 | } | |
164 | ||
165 | clk = clk_get(NULL, clk_name); | |
166 | if (IS_ERR(clk)) { | |
e9a5190a | 167 | pr_err("%s: unable to get clk %s\n", __func__, clk_name); |
1482d8be TG |
168 | goto exit; |
169 | } | |
170 | ||
5dcc3b97 | 171 | freq = clk_get_rate(clk); |
1482d8be TG |
172 | clk_put(clk); |
173 | ||
6369fd41 | 174 | rcu_read_lock(); |
5d4879cd | 175 | opp = dev_pm_opp_find_freq_ceil(dev, &freq); |
1482d8be | 176 | if (IS_ERR(opp)) { |
6369fd41 | 177 | rcu_read_unlock(); |
e9a5190a | 178 | pr_err("%s: unable to find boot up OPP for vdd_%s\n", |
1482d8be TG |
179 | __func__, vdd_name); |
180 | goto exit; | |
181 | } | |
182 | ||
5d4879cd | 183 | bootup_volt = dev_pm_opp_get_voltage(opp); |
6369fd41 | 184 | rcu_read_unlock(); |
1482d8be | 185 | if (!bootup_volt) { |
7852ec05 PW |
186 | pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", |
187 | __func__, vdd_name); | |
1482d8be TG |
188 | goto exit; |
189 | } | |
190 | ||
5e5651be | 191 | voltdm_scale(voltdm, bootup_volt); |
1482d8be TG |
192 | return 0; |
193 | ||
194 | exit: | |
e9a5190a | 195 | pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); |
1482d8be TG |
196 | return -EINVAL; |
197 | } | |
198 | ||
1416408d PW |
199 | #ifdef CONFIG_SUSPEND |
200 | static int omap_pm_enter(suspend_state_t suspend_state) | |
201 | { | |
202 | int ret = 0; | |
203 | ||
204 | if (!omap_pm_suspend) | |
205 | return -ENOENT; /* XXX doublecheck */ | |
206 | ||
207 | switch (suspend_state) { | |
208 | case PM_SUSPEND_STANDBY: | |
209 | case PM_SUSPEND_MEM: | |
210 | ret = omap_pm_suspend(); | |
211 | break; | |
212 | default: | |
213 | ret = -EINVAL; | |
214 | } | |
215 | ||
216 | return ret; | |
217 | } | |
218 | ||
219 | static int omap_pm_begin(suspend_state_t state) | |
220 | { | |
f7b861b7 | 221 | cpu_idle_poll_ctrl(true); |
1416408d PW |
222 | if (cpu_is_omap34xx()) |
223 | omap_prcm_irq_prepare(); | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static void omap_pm_end(void) | |
228 | { | |
f7b861b7 | 229 | cpu_idle_poll_ctrl(false); |
1416408d PW |
230 | } |
231 | ||
232 | static void omap_pm_finish(void) | |
233 | { | |
234 | if (cpu_is_omap34xx()) | |
235 | omap_prcm_irq_complete(); | |
236 | } | |
237 | ||
238 | static const struct platform_suspend_ops omap_pm_ops = { | |
239 | .begin = omap_pm_begin, | |
240 | .end = omap_pm_end, | |
241 | .enter = omap_pm_enter, | |
242 | .finish = omap_pm_finish, | |
243 | .valid = suspend_valid_only_mem, | |
244 | }; | |
245 | ||
246 | #endif /* CONFIG_SUSPEND */ | |
247 | ||
1482d8be TG |
248 | static void __init omap3_init_voltages(void) |
249 | { | |
250 | if (!cpu_is_omap34xx()) | |
251 | return; | |
252 | ||
0f7aa005 BC |
253 | omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); |
254 | omap2_set_init_voltage("core", "l3_ick", "l3_main"); | |
1482d8be TG |
255 | } |
256 | ||
1376ee1d TG |
257 | static void __init omap4_init_voltages(void) |
258 | { | |
259 | if (!cpu_is_omap44xx()) | |
260 | return; | |
261 | ||
0f7aa005 BC |
262 | omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); |
263 | omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1"); | |
264 | omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); | |
1376ee1d TG |
265 | } |
266 | ||
49ded525 NM |
267 | static inline void omap_init_cpufreq(void) |
268 | { | |
269 | struct platform_device_info devinfo = { .name = "omap-cpufreq", }; | |
270 | platform_device_register_full(&devinfo); | |
271 | } | |
272 | ||
6f88e9bc KH |
273 | static int __init omap2_common_pm_init(void) |
274 | { | |
476b679a BC |
275 | if (!of_have_populated_dt()) |
276 | omap2_init_processor_devices(); | |
6f88e9bc KH |
277 | omap_pm_if_init(); |
278 | ||
279 | return 0; | |
280 | } | |
b76c8b19 | 281 | omap_postcore_initcall(omap2_common_pm_init); |
6f88e9bc | 282 | |
bbd707ac | 283 | int __init omap2_common_pm_late_init(void) |
2f34ce81 | 284 | { |
506d81ef BC |
285 | /* |
286 | * In the case of DT, the PMIC and SR initialization will be done using | |
287 | * a completely different mechanism. | |
288 | * Disable this part if a DT blob is available. | |
289 | */ | |
cd19010c | 290 | if (!of_have_populated_dt()) { |
506d81ef | 291 | |
cd19010c SS |
292 | /* Init the voltage layer */ |
293 | omap_pmic_late_init(); | |
294 | omap_voltage_late_init(); | |
1482d8be | 295 | |
cd19010c SS |
296 | /* Initialize the voltages */ |
297 | omap3_init_voltages(); | |
298 | omap4_init_voltages(); | |
1482d8be | 299 | |
cd19010c SS |
300 | /* Smartreflex device init */ |
301 | omap_devinit_smartreflex(); | |
49ded525 NM |
302 | |
303 | /* cpufreq dummy device instantiation */ | |
304 | omap_init_cpufreq(); | |
cd19010c | 305 | } |
2f34ce81 | 306 | |
1416408d PW |
307 | #ifdef CONFIG_SUSPEND |
308 | suspend_set_ops(&omap_pm_ops); | |
309 | #endif | |
310 | ||
2f34ce81 TG |
311 | return 0; |
312 | } |