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1/*
2 * pm.c - Common OMAP2+ power management-related code
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/err.h>
1482d8be 16#include <linux/opp.h>
dc28094b 17#include <linux/export.h>
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18
19#include <plat/omap-pm.h>
20#include <plat/omap_device.h>
21#include <plat/common.h>
22
e1d6f472 23#include "voltage.h"
72e06d08 24#include "powerdomain.h"
1540f214 25#include "clockdomain.h"
0c0a5d61 26#include "pm.h"
eb6a2c75 27
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28static struct omap_device_pm_latency *pm_lats;
29
766e7afc 30static int _init_omap_device(char *name)
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31{
32 struct omap_hwmod *oh;
3528c58e 33 struct platform_device *pdev;
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34
35 oh = omap_hwmod_lookup(name);
36 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
37 __func__, name))
38 return -ENODEV;
39
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40 pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
41 if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
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42 __func__, name))
43 return -ENODEV;
44
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45 return 0;
46}
47
48/*
49 * Build omap_devices for processors and bus.
50 */
51static void omap2_init_processor_devices(void)
52{
766e7afc 53 _init_omap_device("mpu");
2de0baef 54 if (omap3_has_iva())
766e7afc 55 _init_omap_device("iva");
2de0baef 56
cbf27660 57 if (cpu_is_omap44xx()) {
766e7afc
BC
58 _init_omap_device("l3_main_1");
59 _init_omap_device("dsp");
60 _init_omap_device("iva");
cbf27660 61 } else {
766e7afc 62 _init_omap_device("l3_main");
cbf27660 63 }
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64}
65
71a488db
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66/* Types of sleep_switch used in omap_set_pwrdm_state */
67#define FORCEWAKEUP_SWITCH 0
68#define LOWPOWERSTATE_SWITCH 1
69
eb6a2c75
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70/*
71 * This sets pwrdm state (other than mpu & core. Currently only ON &
33de32b3 72 * RET are supported.
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73 */
74int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
75{
76 u32 cur_state;
6349b96b 77 int sleep_switch = -1;
eb6a2c75 78 int ret = 0;
b86cfb52 79 int hwsup = 0;
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80
81 if (pwrdm == NULL || IS_ERR(pwrdm))
82 return -EINVAL;
83
84 while (!(pwrdm->pwrsts & (1 << state))) {
85 if (state == PWRDM_POWER_OFF)
86 return ret;
87 state--;
88 }
89
90 cur_state = pwrdm_read_next_pwrst(pwrdm);
91 if (cur_state == state)
92 return ret;
93
94 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
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95 if ((pwrdm_read_pwrst(pwrdm) > state) &&
96 (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
97 sleep_switch = LOWPOWERSTATE_SWITCH;
98 } else {
b86cfb52 99 hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
68b921ad 100 clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
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101 sleep_switch = FORCEWAKEUP_SWITCH;
102 }
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103 }
104
105 ret = pwrdm_set_next_pwrst(pwrdm, state);
106 if (ret) {
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107 pr_err("%s: unable to set state of powerdomain: %s\n",
108 __func__, pwrdm->name);
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109 goto err;
110 }
111
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112 switch (sleep_switch) {
113 case FORCEWAKEUP_SWITCH:
b86cfb52 114 if (hwsup)
5cd1937b 115 clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
33de32b3 116 else
68b921ad 117 clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
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118 break;
119 case LOWPOWERSTATE_SWITCH:
120 pwrdm_set_lowpwrstchange(pwrdm);
121 break;
122 default:
123 return ret;
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124 }
125
71a488db 126 pwrdm_state_switch(pwrdm);
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127err:
128 return ret;
129}
130
1482d8be 131/*
1e2d2df3 132 * This API is to be called during init to set the various voltage
1482d8be
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133 * domains to the voltage as per the opp table. Typically we boot up
134 * at the nominal voltage. So this function finds out the rate of
135 * the clock associated with the voltage domain, finds out the correct
1e2d2df3 136 * opp entry and sets the voltage domain to the voltage specified
1482d8be
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137 * in the opp entry
138 */
139static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
0f7aa005 140 const char *oh_name)
1482d8be
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141{
142 struct voltagedomain *voltdm;
143 struct clk *clk;
144 struct opp *opp;
145 unsigned long freq, bootup_volt;
0f7aa005 146 struct device *dev;
1482d8be 147
0f7aa005 148 if (!vdd_name || !clk_name || !oh_name) {
e9a5190a 149 pr_err("%s: invalid parameters\n", __func__);
1482d8be
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150 goto exit;
151 }
152
0f7aa005
BC
153 dev = omap_device_get_by_hwmod_name(oh_name);
154 if (IS_ERR(dev)) {
155 pr_err("%s: Unable to get dev pointer for hwmod %s\n",
156 __func__, oh_name);
157 goto exit;
158 }
159
81a60482 160 voltdm = voltdm_lookup(vdd_name);
1482d8be 161 if (IS_ERR(voltdm)) {
e9a5190a 162 pr_err("%s: unable to get vdd pointer for vdd_%s\n",
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163 __func__, vdd_name);
164 goto exit;
165 }
166
167 clk = clk_get(NULL, clk_name);
168 if (IS_ERR(clk)) {
e9a5190a 169 pr_err("%s: unable to get clk %s\n", __func__, clk_name);
1482d8be
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170 goto exit;
171 }
172
173 freq = clk->rate;
174 clk_put(clk);
175
176 opp = opp_find_freq_ceil(dev, &freq);
177 if (IS_ERR(opp)) {
e9a5190a 178 pr_err("%s: unable to find boot up OPP for vdd_%s\n",
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179 __func__, vdd_name);
180 goto exit;
181 }
182
183 bootup_volt = opp_get_voltage(opp);
184 if (!bootup_volt) {
e9a5190a 185 pr_err("%s: unable to find voltage corresponding "
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186 "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
187 goto exit;
188 }
189
5e5651be 190 voltdm_scale(voltdm, bootup_volt);
1482d8be
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191 return 0;
192
193exit:
e9a5190a 194 pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
1482d8be
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195 return -EINVAL;
196}
197
198static void __init omap3_init_voltages(void)
199{
200 if (!cpu_is_omap34xx())
201 return;
202
0f7aa005
BC
203 omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
204 omap2_set_init_voltage("core", "l3_ick", "l3_main");
1482d8be
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205}
206
1376ee1d
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207static void __init omap4_init_voltages(void)
208{
209 if (!cpu_is_omap44xx())
210 return;
211
0f7aa005
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212 omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
213 omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
214 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
1376ee1d
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215}
216
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217static int __init omap2_common_pm_init(void)
218{
476b679a
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219 if (!of_have_populated_dt())
220 omap2_init_processor_devices();
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221 omap_pm_if_init();
222
223 return 0;
224}
1cbbe37a 225postcore_initcall(omap2_common_pm_init);
6f88e9bc 226
2f34ce81
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227static int __init omap2_common_pm_late_init(void)
228{
fbc319f6
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229 /* Init the OMAP TWL parameters */
230 omap3_twl_init();
7bc3ed9a 231 omap4_twl_init();
1482d8be 232
fbc319f6 233 /* Init the voltage layer */
2f34ce81 234 omap_voltage_late_init();
1482d8be
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235
236 /* Initialize the voltages */
237 omap3_init_voltages();
1376ee1d 238 omap4_init_voltages();
1482d8be 239
fbc319f6 240 /* Smartreflex device init */
0c0a5d61 241 omap_devinit_smartreflex();
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242
243 return 0;
244}
245late_initcall(omap2_common_pm_late_init);