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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8bd22949 KH |
2 | /* |
3 | * OMAP2 Power Management Routines | |
4 | * | |
5 | * Copyright (C) 2005 Texas Instruments, Inc. | |
6 | * Copyright (C) 2006-2008 Nokia Corporation | |
7 | * | |
8 | * Written by: | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Tony Lindgren | |
11 | * Juha Yrjola | |
12 | * Amit Kucheria <amit.kucheria@nokia.com> | |
13 | * Igor Stoppa <igor.stoppa@nokia.com> | |
14 | * | |
15 | * Based on pm.c for omap1 | |
8bd22949 KH |
16 | */ |
17 | ||
b764a586 | 18 | #include <linux/cpu_pm.h> |
8bd22949 KH |
19 | #include <linux/suspend.h> |
20 | #include <linux/sched.h> | |
21 | #include <linux/proc_fs.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/sysfs.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/delay.h> | |
f5b00f6f | 26 | #include <linux/clk.h> |
ed1ebc49 | 27 | #include <linux/clk-provider.h> |
8bd22949 KH |
28 | #include <linux/irq.h> |
29 | #include <linux/time.h> | |
8bd22949 | 30 | |
bf027ca1 TL |
31 | #include <asm/fncpy.h> |
32 | ||
8bd22949 KH |
33 | #include <asm/mach/time.h> |
34 | #include <asm/mach/irq.h> | |
35 | #include <asm/mach-types.h> | |
9f97da78 | 36 | #include <asm/system_misc.h> |
8bd22949 | 37 | |
45c3eb7d | 38 | #include <linux/omap-dma.h> |
8bd22949 | 39 | |
e4c060db | 40 | #include "soc.h" |
4e65331c | 41 | #include "common.h" |
a135eaae | 42 | #include "clock.h" |
139563ad | 43 | #include "prm2xxx.h" |
8bd22949 | 44 | #include "prm-regbits-24xx.h" |
ff4ae5d9 | 45 | #include "cm2xxx.h" |
8bd22949 KH |
46 | #include "cm-regbits-24xx.h" |
47 | #include "sdrc.h" | |
bf027ca1 | 48 | #include "sram.h" |
8bd22949 | 49 | #include "pm.h" |
4814ced5 | 50 | #include "control.h" |
72e06d08 | 51 | #include "powerdomain.h" |
1540f214 | 52 | #include "clockdomain.h" |
8bd22949 | 53 | |
8bd22949 KH |
54 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, |
55 | void __iomem *sdrc_power); | |
56 | ||
369d5614 PW |
57 | static struct powerdomain *mpu_pwrdm, *core_pwrdm; |
58 | static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; | |
8bd22949 KH |
59 | |
60 | static struct clk *osc_ck, *emul_ck; | |
61 | ||
1416408d | 62 | static int omap2_enter_full_retention(void) |
8bd22949 KH |
63 | { |
64 | u32 l; | |
8bd22949 KH |
65 | |
66 | /* There is 1 reference hold for all children of the oscillator | |
67 | * clock, the following will remove it. If no one else uses the | |
68 | * oscillator itself it will be disabled if/when we enter retention | |
69 | * mode. | |
70 | */ | |
71 | clk_disable(osc_ck); | |
72 | ||
73 | /* Clear old wake-up events */ | |
74 | /* REVISIT: These write to reserved bits? */ | |
9cb6d363 TK |
75 | omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); |
76 | omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); | |
77 | omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); | |
8bd22949 | 78 | |
f653b298 | 79 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); |
8bd22949 KH |
80 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
81 | ||
82 | /* Workaround to kill USB */ | |
83 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; | |
84 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); | |
85 | ||
b764a586 | 86 | cpu_cluster_pm_enter(); |
8bd22949 | 87 | |
8bd22949 KH |
88 | /* One last check for pending IRQs to avoid extra latency due |
89 | * to sleeping unnecessarily. */ | |
94434535 | 90 | if (omap_irq_pending()) |
8bd22949 KH |
91 | goto no_sleep; |
92 | ||
93 | /* Jump to SRAM suspend code */ | |
94 | omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), | |
95 | OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), | |
96 | OMAP_SDRC_REGADDR(SDRC_POWER)); | |
8bd22949 | 97 | |
4af4016c | 98 | no_sleep: |
b764a586 | 99 | cpu_cluster_pm_exit(); |
8bd22949 KH |
100 | |
101 | clk_enable(osc_ck); | |
102 | ||
103 | /* clear CORE wake-up events */ | |
9cb6d363 TK |
104 | omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); |
105 | omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); | |
8bd22949 KH |
106 | |
107 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ | |
9cb6d363 | 108 | omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1); |
8bd22949 KH |
109 | |
110 | /* MPU domain wake events */ | |
9cb6d363 | 111 | omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1); |
8bd22949 | 112 | |
9cb6d363 | 113 | omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20); |
1416408d | 114 | |
f653b298 PW |
115 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
116 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); | |
117 | ||
1416408d | 118 | return 0; |
8bd22949 KH |
119 | } |
120 | ||
8bd22949 KH |
121 | static int sti_console_enabled; |
122 | ||
123 | static int omap2_allow_mpu_retention(void) | |
124 | { | |
cd6e9db2 | 125 | if (!omap2xxx_cm_mpu_retention_allowed()) |
8bd22949 KH |
126 | return 0; |
127 | if (sti_console_enabled) | |
128 | return 0; | |
129 | ||
130 | return 1; | |
131 | } | |
132 | ||
133 | static void omap2_enter_mpu_retention(void) | |
134 | { | |
088e8806 PW |
135 | const int zero = 0; |
136 | ||
8bd22949 KH |
137 | /* The peripherals seem not to be able to wake up the MPU when |
138 | * it is in retention mode. */ | |
139 | if (omap2_allow_mpu_retention()) { | |
140 | /* REVISIT: These write to reserved bits? */ | |
9cb6d363 TK |
141 | omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); |
142 | omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); | |
143 | omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); | |
8bd22949 KH |
144 | |
145 | /* Try to enter MPU retention */ | |
f653b298 PW |
146 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
147 | ||
8bd22949 KH |
148 | } else { |
149 | /* Block MPU retention */ | |
f653b298 | 150 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
8bd22949 KH |
151 | } |
152 | ||
088e8806 PW |
153 | /* WFI */ |
154 | asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc"); | |
f653b298 PW |
155 | |
156 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
8bd22949 KH |
157 | } |
158 | ||
159 | static int omap2_can_sleep(void) | |
160 | { | |
cd6e9db2 | 161 | if (omap2xxx_cm_fclks_active()) |
8bd22949 | 162 | return 0; |
ed1ebc49 | 163 | if (__clk_is_enabled(osc_ck)) |
8bd22949 KH |
164 | return 0; |
165 | if (omap_dma_running()) | |
166 | return 0; | |
167 | ||
168 | return 1; | |
169 | } | |
170 | ||
171 | static void omap2_pm_idle(void) | |
172 | { | |
8bd22949 | 173 | if (!omap2_can_sleep()) { |
94434535 | 174 | if (omap_irq_pending()) |
6b85638b | 175 | return; |
8bd22949 | 176 | omap2_enter_mpu_retention(); |
6b85638b | 177 | return; |
8bd22949 KH |
178 | } |
179 | ||
94434535 | 180 | if (omap_irq_pending()) |
6b85638b | 181 | return; |
8bd22949 KH |
182 | |
183 | omap2_enter_full_retention(); | |
8bd22949 KH |
184 | } |
185 | ||
8bd22949 KH |
186 | static void __init prcm_setup_regs(void) |
187 | { | |
188 | int i, num_mem_banks; | |
189 | struct powerdomain *pwrdm; | |
190 | ||
4ef70c06 PW |
191 | /* |
192 | * Enable autoidle | |
193 | * XXX This should be handled by hwmod code or PRCM init code | |
194 | */ | |
c4d7e58f | 195 | omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, |
8bd22949 KH |
196 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
197 | ||
8bd22949 KH |
198 | /* |
199 | * Set CORE powerdomain memory banks to retain their contents | |
200 | * during RETENTION | |
201 | */ | |
202 | num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); | |
203 | for (i = 0; i < num_mem_banks; i++) | |
204 | pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); | |
205 | ||
f653b298 | 206 | pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET); |
8bd22949 | 207 | |
8bd22949 | 208 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); |
8bd22949 KH |
209 | |
210 | /* Force-power down DSP, GFX powerdomains */ | |
211 | ||
212 | pwrdm = clkdm_get_pwrdm(dsp_clkdm); | |
213 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
8bd22949 KH |
214 | |
215 | pwrdm = clkdm_get_pwrdm(gfx_clkdm); | |
216 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
8bd22949 | 217 | |
51d070af | 218 | /* Enable hardware-supervised idle for all clkdms */ |
92206fd2 | 219 | clkdm_for_each(omap_pm_clkdms_setup, NULL); |
369d5614 | 220 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); |
8bd22949 | 221 | |
2e4b62dc | 222 | omap_common_suspend_init(omap2_enter_full_retention); |
1416408d | 223 | |
8bd22949 KH |
224 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk |
225 | * stabilisation */ | |
c4d7e58f PW |
226 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
227 | OMAP2_PRCM_CLKSSETUP_OFFSET); | |
8bd22949 KH |
228 | |
229 | /* Configure automatic voltage transition */ | |
c4d7e58f PW |
230 | omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
231 | OMAP2_PRCM_VOLTSETUP_OFFSET); | |
232 | omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | | |
233 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | | |
234 | OMAP24XX_MEMRETCTRL_MASK | | |
235 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | | |
236 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), | |
237 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); | |
8bd22949 KH |
238 | |
239 | /* Enable wake-up events */ | |
c4d7e58f PW |
240 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
241 | WKUP_MOD, PM_WKEN); | |
944ee5dc TK |
242 | |
243 | /* Enable SYS_CLKEN control when all domains idle */ | |
244 | omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD, | |
245 | OMAP2_PRCM_CLKSRC_CTRL_OFFSET); | |
8bd22949 KH |
246 | } |
247 | ||
bbd707ac | 248 | int __init omap2_pm_init(void) |
8bd22949 KH |
249 | { |
250 | u32 l; | |
251 | ||
8bd22949 | 252 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); |
c4d7e58f | 253 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
8bd22949 KH |
254 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
255 | ||
369d5614 | 256 | /* Look up important powerdomains */ |
8bd22949 KH |
257 | |
258 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
259 | if (!mpu_pwrdm) | |
260 | pr_err("PM: mpu_pwrdm not found\n"); | |
261 | ||
262 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
263 | if (!core_pwrdm) | |
264 | pr_err("PM: core_pwrdm not found\n"); | |
265 | ||
369d5614 PW |
266 | /* Look up important clockdomains */ |
267 | ||
268 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
269 | if (!mpu_clkdm) | |
270 | pr_err("PM: mpu_clkdm not found\n"); | |
271 | ||
272 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
273 | if (!wkup_clkdm) | |
274 | pr_err("PM: wkup_clkdm not found\n"); | |
275 | ||
8bd22949 KH |
276 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); |
277 | if (!dsp_clkdm) | |
369d5614 | 278 | pr_err("PM: dsp_clkdm not found\n"); |
8bd22949 KH |
279 | |
280 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); | |
281 | if (!gfx_clkdm) | |
282 | pr_err("PM: gfx_clkdm not found\n"); | |
283 | ||
284 | ||
285 | osc_ck = clk_get(NULL, "osc_ck"); | |
286 | if (IS_ERR(osc_ck)) { | |
287 | printk(KERN_ERR "could not get osc_ck\n"); | |
288 | return -ENODEV; | |
289 | } | |
290 | ||
291 | if (cpu_is_omap242x()) { | |
292 | emul_ck = clk_get(NULL, "emul_ck"); | |
293 | if (IS_ERR(emul_ck)) { | |
294 | printk(KERN_ERR "could not get emul_ck\n"); | |
295 | clk_put(osc_ck); | |
296 | return -ENODEV; | |
297 | } | |
298 | } | |
299 | ||
300 | prcm_setup_regs(); | |
301 | ||
8bd22949 KH |
302 | /* |
303 | * We copy the assembler sleep/wakeup routines to SRAM. | |
304 | * These routines need to be in SRAM as that's the only | |
088e8806 PW |
305 | * memory the MPU can see when it wakes up after the entire |
306 | * chip enters idle. | |
8bd22949 | 307 | */ |
bbd707ac SG |
308 | omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, |
309 | omap24xx_cpu_suspend_sz); | |
8bd22949 | 310 | |
0bcd24b0 | 311 | arm_pm_idle = omap2_pm_idle; |
8bd22949 KH |
312 | |
313 | return 0; | |
314 | } |