[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>

#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/dma.h>
#include <plat/board.h>

#include <mach/irqs.h>

#include "common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"
#include "control.h"
#include "powerdomain.h"
#include "clockdomain.h"

#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
{
	return (suspend_state != PM_SUSPEND_ON);
}
#else
static inline bool is_suspending(void)
{
	return false;
}
#endif

static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_fclks_active(void)
{
	u32 f1, f2;

	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	return (f1 | f2) ? 1 : 0;
}

static void omap2_enter_full_retention(void)
{
	u32 l;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_idle(0);

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

no_sleep:
	omap2_gpio_resume_after_idle();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);

	/* MPU domain wake events */
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x01)
		omap2_prm_write_mod_reg(0x01, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x20)
		omap2_prm_write_mod_reg(0x20, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	/* Mask future PRCM-to-MPU interrupts */
	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
}

static int omap2_i2c_active(void)
{
	u32 l;

	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
		return 0;
	/* Check for UART3. */
	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3_MASK)
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	int only_idle = 0;

	/* Putting MPU into the WFI state while a transfer is active
	 * seems to cause the I2C block to timeout. Why? Good question. */
	if (omap2_i2c_active())
		return;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
		omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

		/* Try to enter MPU retention */
		omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
				  OMAP_LOGICRETSTATE_MASK,
				  MPU_MOD, OMAP2_PM_PWSTCTRL);
	} else {
		/* Block MPU retention */

		omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
						 OMAP2_PM_PWSTCTRL);
		only_idle = 1;
	}

	omap2_sram_idle();
}

static int omap2_can_sleep(void)
{
	if (omap2_fclks_active())
		return 0;
	if (osc_ck->usecount > 1)
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	local_fiq_disable();

	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			goto out;
		omap2_enter_mpu_retention();
		goto out;
	}

	if (omap_irq_pending())
		goto out;

	omap2_enter_full_retention();

out:
	local_fiq_enable();
}

#ifdef CONFIG_SUSPEND
static int omap2_pm_begin(suspend_state_t state)
{
	disable_hlt();
	suspend_state = state;
	return 0;
}

static int omap2_pm_enter(suspend_state_t state)
{
	int ret = 0;

	switch (state) {
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		omap2_enter_full_retention();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void omap2_pm_end(void)
{
	suspend_state = PM_SUSPEND_ON;
	enable_hlt();
}

static const struct platform_suspend_ops omap_pm_ops = {
	.begin		= omap2_pm_begin,
	.enter		= omap2_pm_enter,
	.end		= omap2_pm_end,
	.valid		= suspend_valid_only_mem,
};
#else
static const struct platform_suspend_ops __initdata omap_pm_ops;
#endif /* CONFIG_SUSPEND */

/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
		clkdm_allow_idle(clkdm);
	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
		 atomic_read(&clkdm->usecount) == 0)
		clkdm_sleep(clkdm);
	return 0;
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/*
	 * Enable autoidle
	 * XXX This should be handled by hwmod code or PRCM init code
	 */
	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	/* Set CORE powerdomain's next power state to RETENTION */
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	clkdm_sleep(dsp_clkdm);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	clkdm_sleep(gfx_clkdm);

	/* Enable hardware-supervised idle for all clkdms */
	clkdm_for_each(clkdms_setup, NULL);
	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_VOLTSETUP_OFFSET);
	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
				(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
				OMAP24XX_MEMRETCTRL_MASK |
				(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
				(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
				OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
				WKUP_MOD, PM_WKEN);
}

static int __init omap2_pm_init(void)
{
	u32 l;

	if (!cpu_is_omap24xx())
		return -ENODEV;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	/* Look up important clockdomains */

	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	if (!mpu_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	if (!wkup_clkdm)
		pr_err("PM: wkup_clkdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: dsp_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/* Hack to prevent MPU retention when STI console is enabled. */
	{
		const struct omap_sti_console_config *sti;

		sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
				      struct omap_sti_console_config);
		if (sti != NULL && sti->enable)
			sti_console_enabled = 1;
	}

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up.
	 */
	if (cpu_is_omap24xx()) {
		omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
						 omap24xx_idle_loop_suspend_sz);

		omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
						    omap24xx_cpu_suspend_sz);
	}

	suspend_set_ops(&omap_pm_ops);
	arm_pm_idle = omap2_pm_idle;

	return 0;
}

late_initcall(omap2_pm_init);
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
	28	#include <linux/clk.h>
8bd22949 KH	29	#include <linux/irq.h>
	30	#include <linux/time.h>
	31	#include <linux/gpio.h>
	32
	33	#include <asm/mach/time.h>
	34	#include <asm/mach/irq.h>
	35	#include <asm/mach-types.h>
	36
ce491cf8 TL	37	#include <plat/clock.h>
ce491cf8 TL	38	#include <plat/sram.h>
ce491cf8 TL	39	#include <plat/dma.h>
ce491cf8 TL	40	#include <plat/board.h>
8bd22949	41
ee0839c2 TL	42	#include <mach/irqs.h>
ee0839c2 TL	43
4e65331c	44	#include "common.h"
59fb659b	45	#include "prm2xxx_3xxx.h"
8bd22949	46	#include "prm-regbits-24xx.h"
59fb659b	47	#include "cm2xxx_3xxx.h"
8bd22949 KH	48	#include "cm-regbits-24xx.h"
	49	#include "sdrc.h"
	50	#include "pm.h"
4814ced5	51	#include "control.h"
72e06d08	52	#include "powerdomain.h"
1540f214	53	#include "clockdomain.h"
8bd22949	54
e83df17f KH	55	#ifdef CONFIG_SUSPEND
	56	static suspend_state_t suspend_state = PM_SUSPEND_ON;
	57	static inline bool is_suspending(void)
	58	{
	59	return (suspend_state != PM_SUSPEND_ON);
	60	}
	61	#else
	62	static inline bool is_suspending(void)
	63	{
	64	return false;
	65	}
	66	#endif
	67
8bd22949 KH	68	static void (*omap2_sram_idle)(void);
	69	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	70	void __iomem *sdrc_power);
	71
369d5614 PW	72	static struct powerdomain mpu_pwrdm, core_pwrdm;
369d5614 PW	73	static struct clockdomain dsp_clkdm, mpu_clkdm, wkup_clkdm, gfx_clkdm;
8bd22949 KH	74
	75	static struct clk osc_ck, emul_ck;
	76
	77	static int omap2_fclks_active(void)
	78	{
	79	u32 f1, f2;
	80
c4d7e58f PW	81	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
c4d7e58f PW	82	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
4af4016c	83
1e056ddd	84	return (f1 \| f2) ? 1 : 0;
8bd22949 KH	85	}
8bd22949 KH	86
8bd22949 KH	87	static void omap2_enter_full_retention(void)
	88	{
	89	u32 l;
8bd22949 KH	90
	91	/* There is 1 reference hold for all children of the oscillator
	92	* clock, the following will remove it. If no one else uses the
	93	* oscillator itself it will be disabled if/when we enter retention
	94	* mode.
	95	*/
	96	clk_disable(osc_ck);
	97
	98	/* Clear old wake-up events */
	99	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	100	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	101	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	102	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949 KH	103
	104	/*
	105	* Set MPU powerdomain's next power state to RETENTION;
	106	* preserve logic state during retention
	107	*/
	108	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	109	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	110
	111	/* Workaround to kill USB */
	112	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	113	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	114
72e06d08	115	omap2_gpio_prepare_for_idle(0);
8bd22949	116
8bd22949 KH	117	/* One last check for pending IRQs to avoid extra latency due
8bd22949 KH	118	* to sleeping unnecessarily. */
94434535	119	if (omap_irq_pending())
8bd22949 KH	120	goto no_sleep;
	121
	122	/* Jump to SRAM suspend code */
	123	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	124	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	125	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	126
4af4016c	127	no_sleep:
43ffcd9a	128	omap2_gpio_resume_after_idle();
8bd22949 KH	129
	130	clk_enable(osc_ck);
	131
	132	/* clear CORE wake-up events */
c4d7e58f PW	133	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
c4d7e58f PW	134	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
8bd22949 KH	135
8bd22949 KH	136	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
c4d7e58f	137	omap2_prm_clear_mod_reg_bits(0x4 \| 0x1, WKUP_MOD, PM_WKST);
8bd22949 KH	138
8bd22949 KH	139	/* MPU domain wake events */
c4d7e58f	140	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949	141	if (l & 0x01)
c4d7e58f	142	omap2_prm_write_mod_reg(0x01, OCP_MOD,
8bd22949 KH	143	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949 KH	144	if (l & 0x20)
c4d7e58f	145	omap2_prm_write_mod_reg(0x20, OCP_MOD,
8bd22949 KH	146	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	147
	148	/* Mask future PRCM-to-MPU interrupts */
c4d7e58f	149	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949 KH	150	}
	151
	152	static int omap2_i2c_active(void)
	153	{
	154	u32 l;
	155
c4d7e58f	156	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f38ca10a	157	return l & (OMAP2420_EN_I2C2_MASK \| OMAP2420_EN_I2C1_MASK);
8bd22949 KH	158	}
	159
	160	static int sti_console_enabled;
	161
	162	static int omap2_allow_mpu_retention(void)
	163	{
	164	u32 l;
	165
	166	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
c4d7e58f	167	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
2fd0f75c PW	168	if (l & (OMAP2420_EN_MMC_MASK \| OMAP24XX_EN_UART2_MASK \|
	169	OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_MCSPI2_MASK \|
	170	OMAP24XX_EN_MCSPI1_MASK \| OMAP24XX_EN_DSS1_MASK))
8bd22949 KH	171	return 0;
8bd22949 KH	172	/* Check for UART3. */
c4d7e58f	173	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
2fd0f75c	174	if (l & OMAP24XX_EN_UART3_MASK)
8bd22949 KH	175	return 0;
	176	if (sti_console_enabled)
	177	return 0;
	178
	179	return 1;
	180	}
	181
	182	static void omap2_enter_mpu_retention(void)
	183	{
	184	int only_idle = 0;
8bd22949 KH	185
	186	/* Putting MPU into the WFI state while a transfer is active
	187	* seems to cause the I2C block to timeout. Why? Good question. */
	188	if (omap2_i2c_active())
	189	return;
	190
	191	/* The peripherals seem not to be able to wake up the MPU when
	192	* it is in retention mode. */
	193	if (omap2_allow_mpu_retention()) {
	194	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	195	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	196	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	197	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949 KH	198
8bd22949 KH	199	/* Try to enter MPU retention */
c4d7e58f	200	omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) \|
2fd0f75c	201	OMAP_LOGICRETSTATE_MASK,
37903009	202	MPU_MOD, OMAP2_PM_PWSTCTRL);
8bd22949 KH	203	} else {
	204	/* Block MPU retention */
	205
c4d7e58f	206	omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
37903009	207	OMAP2_PM_PWSTCTRL);
8bd22949 KH	208	only_idle = 1;
	209	}
	210
8bd22949	211	omap2_sram_idle();
8bd22949 KH	212	}
	213
	214	static int omap2_can_sleep(void)
	215	{
	216	if (omap2_fclks_active())
	217	return 0;
	218	if (osc_ck->usecount > 1)
	219	return 0;
	220	if (omap_dma_running())
	221	return 0;
	222
	223	return 1;
	224	}
	225
	226	static void omap2_pm_idle(void)
	227	{
8bd22949 KH	228	local_fiq_disable();
	229
	230	if (!omap2_can_sleep()) {
94434535	231	if (omap_irq_pending())
8bd22949 KH	232	goto out;
	233	omap2_enter_mpu_retention();
	234	goto out;
	235	}
	236
94434535	237	if (omap_irq_pending())
8bd22949 KH	238	goto out;
	239
	240	omap2_enter_full_retention();
	241
	242	out:
	243	local_fiq_enable();
8bd22949 KH	244	}
8bd22949 KH	245
05fad3e7	246	#ifdef CONFIG_SUSPEND
e83df17f KH	247	static int omap2_pm_begin(suspend_state_t state)
e83df17f KH	248	{
8bd22949	249	disable_hlt();
c166381d	250	suspend_state = state;
8bd22949 KH	251	return 0;
	252	}
	253
8bd22949 KH	254	static int omap2_pm_enter(suspend_state_t state)
	255	{
	256	int ret = 0;
	257
	258	switch (state) {
	259	case PM_SUSPEND_STANDBY:
	260	case PM_SUSPEND_MEM:
645c56a7	261	omap2_enter_full_retention();
8bd22949 KH	262	break;
	263	default:
	264	ret = -EINVAL;
	265	}
	266
	267	return ret;
	268	}
	269
e83df17f KH	270	static void omap2_pm_end(void)
	271	{
	272	suspend_state = PM_SUSPEND_ON;
c166381d	273	enable_hlt();
e83df17f KH	274	}
e83df17f KH	275
2f55ac07	276	static const struct platform_suspend_ops omap_pm_ops = {
e83df17f	277	.begin = omap2_pm_begin,
8bd22949	278	.enter = omap2_pm_enter,
e83df17f	279	.end = omap2_pm_end,
8bd22949 KH	280	.valid = suspend_valid_only_mem,
8bd22949 KH	281	};
05fad3e7 KH	282	#else
	283	static const struct platform_suspend_ops __initdata omap_pm_ops;
	284	#endif /* CONFIG_SUSPEND */
8bd22949	285
369d5614 PW	286	/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
369d5614 PW	287	static int __init clkdms_setup(struct clockdomain clkdm, void unused)
8bd22949	288	{
369d5614	289	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
5cd1937b	290	clkdm_allow_idle(clkdm);
369d5614 PW	291	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
369d5614 PW	292	atomic_read(&clkdm->usecount) == 0)
68b921ad	293	clkdm_sleep(clkdm);
8bd22949 KH	294	return 0;
	295	}
	296
	297	static void __init prcm_setup_regs(void)
	298	{
	299	int i, num_mem_banks;
	300	struct powerdomain *pwrdm;
	301
4ef70c06 PW	302	/*
	303	* Enable autoidle
	304	* XXX This should be handled by hwmod code or PRCM init code
	305	*/
c4d7e58f	306	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
8bd22949 KH	307	OMAP2_PRCM_SYSCONFIG_OFFSET);
8bd22949 KH	308
8bd22949 KH	309	/*
	310	* Set CORE powerdomain memory banks to retain their contents
	311	* during RETENTION
	312	*/
	313	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	314	for (i = 0; i < num_mem_banks; i++)
	315	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	316
	317	/* Set CORE powerdomain's next power state to RETENTION */
	318	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	319
	320	/*
	321	* Set MPU powerdomain's next power state to RETENTION;
	322	* preserve logic state during retention
	323	*/
	324	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	325	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	326
	327	/* Force-power down DSP, GFX powerdomains */
	328
	329	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	330	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
68b921ad	331	clkdm_sleep(dsp_clkdm);
8bd22949 KH	332
	333	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	334	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
68b921ad	335	clkdm_sleep(gfx_clkdm);
8bd22949	336
51d070af	337	/* Enable hardware-supervised idle for all clkdms */
369d5614 PW	338	clkdm_for_each(clkdms_setup, NULL);
369d5614 PW	339	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
8bd22949	340
8bd22949 KH	341	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
8bd22949 KH	342	* stabilisation */
c4d7e58f PW	343	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
c4d7e58f PW	344	OMAP2_PRCM_CLKSSETUP_OFFSET);
8bd22949 KH	345
8bd22949 KH	346	/* Configure automatic voltage transition */
c4d7e58f PW	347	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	348	OMAP2_PRCM_VOLTSETUP_OFFSET);
	349	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK \|
	350	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
	351	OMAP24XX_MEMRETCTRL_MASK \|
	352	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
	353	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
	354	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
8bd22949 KH	355
8bd22949 KH	356	/* Enable wake-up events */
c4d7e58f PW	357	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK \| OMAP24XX_EN_GPT1_MASK,
c4d7e58f PW	358	WKUP_MOD, PM_WKEN);
8bd22949 KH	359	}
8bd22949 KH	360
7cc515f7	361	static int __init omap2_pm_init(void)
8bd22949 KH	362	{
	363	u32 l;
	364
	365	if (!cpu_is_omap24xx())
	366	return -ENODEV;
	367
	368	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
c4d7e58f	369	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
8bd22949 KH	370	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
8bd22949 KH	371
369d5614	372	/* Look up important powerdomains */
8bd22949 KH	373
	374	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	375	if (!mpu_pwrdm)
	376	pr_err("PM: mpu_pwrdm not found\n");
	377
	378	core_pwrdm = pwrdm_lookup("core_pwrdm");
	379	if (!core_pwrdm)
	380	pr_err("PM: core_pwrdm not found\n");
	381
369d5614 PW	382	/* Look up important clockdomains */
	383
	384	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	385	if (!mpu_clkdm)
	386	pr_err("PM: mpu_clkdm not found\n");
	387
	388	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	389	if (!wkup_clkdm)
	390	pr_err("PM: wkup_clkdm not found\n");
	391
8bd22949 KH	392	dsp_clkdm = clkdm_lookup("dsp_clkdm");
8bd22949 KH	393	if (!dsp_clkdm)
369d5614	394	pr_err("PM: dsp_clkdm not found\n");
8bd22949 KH	395
	396	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	397	if (!gfx_clkdm)
	398	pr_err("PM: gfx_clkdm not found\n");
	399
	400
	401	osc_ck = clk_get(NULL, "osc_ck");
	402	if (IS_ERR(osc_ck)) {
	403	printk(KERN_ERR "could not get osc_ck\n");
	404	return -ENODEV;
	405	}
	406
	407	if (cpu_is_omap242x()) {
	408	emul_ck = clk_get(NULL, "emul_ck");
	409	if (IS_ERR(emul_ck)) {
	410	printk(KERN_ERR "could not get emul_ck\n");
	411	clk_put(osc_ck);
	412	return -ENODEV;
	413	}
	414	}
	415
	416	prcm_setup_regs();
	417
	418	/* Hack to prevent MPU retention when STI console is enabled. */
	419	{
	420	const struct omap_sti_console_config *sti;
	421
	422	sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
	423	struct omap_sti_console_config);
	424	if (sti != NULL && sti->enable)
	425	sti_console_enabled = 1;
	426	}
	427
	428	/*
	429	* We copy the assembler sleep/wakeup routines to SRAM.
	430	* These routines need to be in SRAM as that's the only
	431	* memory the MPU can see when it wakes up.
	432	*/
	433	if (cpu_is_omap24xx()) {
	434	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
	435	omap24xx_idle_loop_suspend_sz);
	436
	437	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
	438	omap24xx_cpu_suspend_sz);
	439	}
	440
	441	suspend_set_ops(&omap_pm_ops);
0bcd24b0	442	arm_pm_idle = omap2_pm_idle;
8bd22949 KH	443
	444	return 0;
	445	}
	446
	447	late_initcall(omap2_pm_init);