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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8bd22949 KH |
2 | /* |
3 | * OMAP3 Power Management Routines | |
4 | * | |
5 | * Copyright (C) 2006-2008 Nokia Corporation | |
6 | * Tony Lindgren <tony@atomide.com> | |
7 | * Jouni Hogander | |
8 | * | |
2f5939c3 RN |
9 | * Copyright (C) 2007 Texas Instruments, Inc. |
10 | * Rajendra Nayak <rnayak@ti.com> | |
11 | * | |
8bd22949 KH |
12 | * Copyright (C) 2005 Texas Instruments, Inc. |
13 | * Richard Woodruff <r-woodruff2@ti.com> | |
14 | * | |
15 | * Based on pm.c for omap1 | |
8bd22949 KH |
16 | */ |
17 | ||
b764a586 | 18 | #include <linux/cpu_pm.h> |
8bd22949 KH |
19 | #include <linux/pm.h> |
20 | #include <linux/suspend.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/err.h> | |
c40552bc | 25 | #include <linux/clk.h> |
dccaad89 | 26 | #include <linux/delay.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
fb2c599f | 28 | #include <linux/of.h> |
e639cd5b | 29 | #include <linux/omap-gpmc.h> |
4b25408f | 30 | |
5e7c58dc | 31 | #include <trace/events/power.h> |
8bd22949 | 32 | |
bf027ca1 | 33 | #include <asm/fncpy.h> |
2c74a0ce | 34 | #include <asm/suspend.h> |
9f97da78 | 35 | #include <asm/system_misc.h> |
2c74a0ce | 36 | |
1540f214 | 37 | #include "clockdomain.h" |
72e06d08 | 38 | #include "powerdomain.h" |
e4c060db | 39 | #include "soc.h" |
4e65331c | 40 | #include "common.h" |
ff4ae5d9 | 41 | #include "cm3xxx.h" |
8bd22949 KH |
42 | #include "cm-regbits-34xx.h" |
43 | #include "prm-regbits-34xx.h" | |
139563ad | 44 | #include "prm3xxx.h" |
8bd22949 | 45 | #include "pm.h" |
13a6fe0f | 46 | #include "sdrc.h" |
d09220a8 | 47 | #include "omap-secure.h" |
bf027ca1 | 48 | #include "sram.h" |
4814ced5 | 49 | #include "control.h" |
3b8c4ebb | 50 | #include "vc.h" |
13a6fe0f | 51 | |
8cdfd834 NM |
52 | /* pm34xx errata defined in pm.h */ |
53 | u16 pm34xx_errata; | |
54 | ||
8bd22949 KH |
55 | struct power_state { |
56 | struct powerdomain *pwrdm; | |
57 | u32 next_state; | |
10f90ed2 | 58 | #ifdef CONFIG_SUSPEND |
8bd22949 | 59 | u32 saved_state; |
10f90ed2 | 60 | #endif |
8bd22949 KH |
61 | struct list_head node; |
62 | }; | |
63 | ||
64 | static LIST_HEAD(pwrst_list); | |
65 | ||
46e130d2 | 66 | void (*omap3_do_wfi_sram)(void); |
27d59a4a | 67 | |
fa3c2a4f RN |
68 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
69 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
3a7ec26b | 70 | |
2f5939c3 RN |
71 | static void omap3_core_save_context(void) |
72 | { | |
596efe47 | 73 | omap3_ctrl_save_padconf(); |
dccaad89 TK |
74 | |
75 | /* | |
76 | * Force write last pad into memory, as this can fail in some | |
83521291 | 77 | * cases according to errata 1.157, 1.185 |
dccaad89 TK |
78 | */ |
79 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | |
80 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | |
81 | ||
2f5939c3 RN |
82 | /* Save the Interrupt controller context */ |
83 | omap_intc_save_context(); | |
84 | /* Save the GPMC context */ | |
85 | omap3_gpmc_save_context(); | |
86 | /* Save the system control module context, padconf already save above*/ | |
87 | omap3_control_save_context(); | |
88 | } | |
89 | ||
90 | static void omap3_core_restore_context(void) | |
91 | { | |
92 | /* Restore the control module context, padconf restored by h/w */ | |
93 | omap3_control_restore_context(); | |
94 | /* Restore the GPMC context */ | |
95 | omap3_gpmc_restore_context(); | |
96 | /* Restore the interrupt controller context */ | |
97 | omap_intc_restore_context(); | |
98 | } | |
99 | ||
9d97140b TK |
100 | /* |
101 | * FIXME: This function should be called before entering off-mode after | |
102 | * OMAP3 secure services have been accessed. Currently it is only called | |
103 | * once during boot sequence, but this works as we are not using secure | |
104 | * services. | |
105 | */ | |
617fcc98 | 106 | static void omap3_save_secure_ram_context(void) |
27d59a4a TK |
107 | { |
108 | u32 ret; | |
617fcc98 | 109 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
27d59a4a TK |
110 | |
111 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
112 | /* |
113 | * MPU next state must be set to POWER_ON temporarily, | |
114 | * otherwise the WFI executed inside the ROM code | |
115 | * will hang the system. | |
116 | */ | |
117 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
d09220a8 TL |
118 | ret = omap3_save_secure_ram(omap3_secure_ram_storage, |
119 | OMAP3_SAVE_SECURE_RAM_SZ); | |
617fcc98 | 120 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
27d59a4a TK |
121 | /* Following is for error tracking, it should not happen */ |
122 | if (ret) { | |
98179856 | 123 | pr_err("save_secure_sram() returns %08x\n", ret); |
27d59a4a TK |
124 | while (1) |
125 | ; | |
126 | } | |
127 | } | |
128 | } | |
129 | ||
22f51371 | 130 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
8cb0ac99 PW |
131 | { |
132 | int c; | |
133 | ||
9cb6d363 TK |
134 | c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK | |
135 | OMAP3430_ST_IO_CHAIN_MASK); | |
8cb0ac99 | 136 | |
22f51371 | 137 | return c ? IRQ_HANDLED : IRQ_NONE; |
77da2d91 | 138 | } |
8bd22949 | 139 | |
22f51371 | 140 | static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) |
77da2d91 | 141 | { |
22f51371 | 142 | int c; |
d6290a3e | 143 | |
22f51371 TK |
144 | /* |
145 | * Clear all except ST_IO and ST_IO_CHAIN for wkup module, | |
146 | * these are handled in a separate handler to avoid acking | |
147 | * IO events before parsing in mux code | |
148 | */ | |
9cb6d363 TK |
149 | c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK | |
150 | OMAP3430_ST_IO_CHAIN_MASK)); | |
151 | c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); | |
152 | c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0); | |
22f51371 | 153 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
9cb6d363 TK |
154 | c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); |
155 | c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0); | |
22f51371 | 156 | } |
8bd22949 | 157 | |
22f51371 | 158 | return c ? IRQ_HANDLED : IRQ_NONE; |
8bd22949 KH |
159 | } |
160 | ||
cbe26349 RK |
161 | static void omap34xx_save_context(u32 *save) |
162 | { | |
163 | u32 val; | |
164 | ||
165 | /* Read Auxiliary Control Register */ | |
166 | asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); | |
167 | *save++ = 1; | |
168 | *save++ = val; | |
169 | ||
170 | /* Read L2 AUX ctrl register */ | |
171 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); | |
172 | *save++ = 1; | |
173 | *save++ = val; | |
174 | } | |
175 | ||
29cb3cd2 | 176 | static int omap34xx_do_sram_idle(unsigned long save_state) |
57f277b0 | 177 | { |
cbe26349 | 178 | omap34xx_cpu_suspend(save_state); |
29cb3cd2 | 179 | return 0; |
57f277b0 RN |
180 | } |
181 | ||
99e6a4d2 | 182 | void omap_sram_idle(void) |
8bd22949 KH |
183 | { |
184 | /* Variable to tell what needs to be saved and restored | |
185 | * in omap_sram_idle*/ | |
186 | /* save_state = 0 => Nothing to save and restored */ | |
187 | /* save_state = 1 => Only L1 and logic lost */ | |
188 | /* save_state = 2 => Only L2 lost */ | |
189 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
190 | int save_state = 0; |
191 | int mpu_next_state = PWRDM_POWER_ON; | |
192 | int per_next_state = PWRDM_POWER_ON; | |
193 | int core_next_state = PWRDM_POWER_ON; | |
13a6fe0f | 194 | u32 sdrc_pwr = 0; |
55be2f50 | 195 | int error; |
8bd22949 | 196 | |
8bd22949 KH |
197 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
198 | switch (mpu_next_state) { | |
fa3c2a4f | 199 | case PWRDM_POWER_ON: |
8bd22949 KH |
200 | case PWRDM_POWER_RET: |
201 | /* No need to save context */ | |
202 | save_state = 0; | |
203 | break; | |
61255ab9 RN |
204 | case PWRDM_POWER_OFF: |
205 | save_state = 3; | |
206 | break; | |
8bd22949 KH |
207 | default: |
208 | /* Invalid state */ | |
98179856 | 209 | pr_err("Invalid mpu state in sram_idle\n"); |
8bd22949 KH |
210 | return; |
211 | } | |
fe617af7 | 212 | |
fa3c2a4f RN |
213 | /* NEON control */ |
214 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 215 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 216 | |
40742fa8 | 217 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
658ce97e | 218 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
ecf157d0 | 219 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
40742fa8 | 220 | |
e0e29fd7 | 221 | pwrdm_pre_transition(NULL); |
ff2f8e5f | 222 | |
40742fa8 | 223 | /* PER */ |
55be2f50 TL |
224 | if (per_next_state == PWRDM_POWER_OFF) { |
225 | error = cpu_cluster_pm_enter(); | |
226 | if (error) | |
227 | return; | |
228 | } | |
658ce97e KH |
229 | |
230 | /* CORE */ | |
fa3c2a4f | 231 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
232 | if (core_next_state == PWRDM_POWER_OFF) { |
233 | omap3_core_save_context(); | |
f0611a5c | 234 | omap3_cm_save_context(); |
2f5939c3 | 235 | } |
fa3c2a4f | 236 | } |
40742fa8 | 237 | |
3b8c4ebb TL |
238 | /* Configure PMIC signaling for I2C4 or sys_off_mode */ |
239 | omap3_vc_set_pmic_signaling(core_next_state); | |
240 | ||
f18cc2ff | 241 | omap3_intc_prepare_idle(); |
8bd22949 | 242 | |
13a6fe0f | 243 | /* |
30474544 PW |
244 | * On EMU/HS devices ROM code restores a SRDC value |
245 | * from scratchpad which has automatic self refresh on timeout | |
246 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. | |
247 | * Hence store/restore the SDRC_POWER register here. | |
248 | */ | |
249 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && | |
250 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
251 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
f265dc4c | 252 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 253 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 254 | |
61255ab9 | 255 | /* |
076f2cc4 RK |
256 | * omap3_arm_context is the location where some ARM context |
257 | * get saved. The rest is placed on the stack, and restored | |
258 | * from there before resuming. | |
61255ab9 | 259 | */ |
cbe26349 RK |
260 | if (save_state) |
261 | omap34xx_save_context(omap3_arm_context); | |
076f2cc4 | 262 | if (save_state == 1 || save_state == 3) |
2c74a0ce | 263 | cpu_suspend(save_state, omap34xx_do_sram_idle); |
076f2cc4 RK |
264 | else |
265 | omap34xx_do_sram_idle(save_state); | |
8bd22949 | 266 | |
f265dc4c | 267 | /* Restore normal SDRC POWER settings */ |
30474544 PW |
268 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
269 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
270 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
13a6fe0f TK |
271 | core_next_state == PWRDM_POWER_OFF) |
272 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
273 | ||
658ce97e | 274 | /* CORE */ |
1560d158 DG |
275 | if (core_next_state < PWRDM_POWER_ON && |
276 | pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) { | |
277 | omap3_core_restore_context(); | |
278 | omap3_cm_restore_context(); | |
279 | omap3_sram_restore_context(); | |
280 | omap2_sms_restore_context(); | |
281 | } else { | |
282 | /* | |
283 | * In off-mode resume path above, omap3_core_restore_context | |
284 | * also handles the INTC autoidle restore done here so limit | |
285 | * this to non-off mode resume paths so we don't do it twice. | |
286 | */ | |
287 | omap3_intc_resume_idle(); | |
658ce97e KH |
288 | } |
289 | ||
e0e29fd7 KH |
290 | pwrdm_post_transition(NULL); |
291 | ||
658ce97e | 292 | /* PER */ |
b764a586 TL |
293 | if (per_next_state == PWRDM_POWER_OFF) |
294 | cpu_cluster_pm_exit(); | |
8bd22949 KH |
295 | } |
296 | ||
8bd22949 KH |
297 | static void omap3_pm_idle(void) |
298 | { | |
0bcd24b0 | 299 | if (omap_irq_pending()) |
6b85638b | 300 | return; |
8bd22949 KH |
301 | |
302 | omap_sram_idle(); | |
8bd22949 KH |
303 | } |
304 | ||
10f90ed2 | 305 | #ifdef CONFIG_SUSPEND |
8bd22949 KH |
306 | static int omap3_pm_suspend(void) |
307 | { | |
308 | struct power_state *pwrst; | |
309 | int state, ret = 0; | |
310 | ||
311 | /* Read current next_pwrsts */ | |
312 | list_for_each_entry(pwrst, &pwrst_list, node) | |
313 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
314 | /* Set ones wanted by suspend */ | |
315 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
eb6a2c75 | 316 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
8bd22949 KH |
317 | goto restore; |
318 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
319 | goto restore; | |
320 | } | |
321 | ||
2bbe3af3 TK |
322 | omap3_intc_suspend(); |
323 | ||
8bd22949 KH |
324 | omap_sram_idle(); |
325 | ||
326 | restore: | |
327 | /* Restore next_pwrsts */ | |
328 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
329 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
330 | if (state > pwrst->next_state) { | |
7852ec05 PW |
331 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
332 | pwrst->pwrdm->name, pwrst->next_state); | |
8bd22949 KH |
333 | ret = -1; |
334 | } | |
eb6a2c75 | 335 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
336 | } |
337 | if (ret) | |
98179856 | 338 | pr_err("Could not enter target state in pm_suspend\n"); |
8bd22949 | 339 | else |
98179856 | 340 | pr_info("Successfully put all powerdomains to target state\n"); |
8bd22949 KH |
341 | |
342 | return ret; | |
343 | } | |
2e4b62dc DG |
344 | #else |
345 | #define omap3_pm_suspend NULL | |
10f90ed2 | 346 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 347 | |
8111b221 KH |
348 | static void __init prcm_setup_regs(void) |
349 | { | |
ba12c242 | 350 | omap3_ctrl_init(); |
b296c811 | 351 | |
c5180a2b | 352 | omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); |
8bd22949 KH |
353 | } |
354 | ||
c40552bc KH |
355 | void omap3_pm_off_mode_enable(int enable) |
356 | { | |
357 | struct power_state *pwrst; | |
358 | u32 state; | |
359 | ||
360 | if (enable) | |
361 | state = PWRDM_POWER_OFF; | |
362 | else | |
363 | state = PWRDM_POWER_RET; | |
364 | ||
365 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
cc1b6028 EV |
366 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
367 | pwrst->pwrdm == core_pwrdm && | |
368 | state == PWRDM_POWER_OFF) { | |
369 | pwrst->next_state = PWRDM_POWER_RET; | |
e16b41bf | 370 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
cc1b6028 EV |
371 | __func__); |
372 | } else { | |
373 | pwrst->next_state = state; | |
374 | } | |
375 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
c40552bc KH |
376 | } |
377 | } | |
378 | ||
68d4778c TK |
379 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
380 | { | |
381 | struct power_state *pwrst; | |
382 | ||
383 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
384 | if (pwrst->pwrdm == pwrdm) | |
385 | return pwrst->next_state; | |
386 | } | |
387 | return -EINVAL; | |
388 | } | |
389 | ||
390 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
391 | { | |
392 | struct power_state *pwrst; | |
393 | ||
394 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
395 | if (pwrst->pwrdm == pwrdm) { | |
396 | pwrst->next_state = state; | |
397 | return 0; | |
398 | } | |
399 | } | |
400 | return -EINVAL; | |
401 | } | |
402 | ||
a23456e9 | 403 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
404 | { |
405 | struct power_state *pwrst; | |
406 | ||
407 | if (!pwrdm->pwrsts) | |
408 | return 0; | |
409 | ||
d3d381c6 | 410 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
411 | if (!pwrst) |
412 | return -ENOMEM; | |
413 | pwrst->pwrdm = pwrdm; | |
fb2c599f AK |
414 | |
415 | if (enable_off_mode) | |
416 | pwrst->next_state = PWRDM_POWER_OFF; | |
417 | else | |
418 | pwrst->next_state = PWRDM_POWER_RET; | |
419 | ||
8bd22949 KH |
420 | list_add(&pwrst->node, &pwrst_list); |
421 | ||
422 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
423 | pwrdm_enable_hdwr_sar(pwrdm); | |
424 | ||
eb6a2c75 | 425 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
8bd22949 KH |
426 | } |
427 | ||
46e130d2 JP |
428 | /* |
429 | * Push functions to SRAM | |
430 | * | |
431 | * The minimum set of functions is pushed to SRAM for execution: | |
432 | * - omap3_do_wfi for erratum i581 WA, | |
46e130d2 | 433 | */ |
3231fc88 RN |
434 | void omap_push_sram_idle(void) |
435 | { | |
46e130d2 | 436 | omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
3231fc88 RN |
437 | } |
438 | ||
8cdfd834 NM |
439 | static void __init pm_errata_configure(void) |
440 | { | |
c4236d2e | 441 | if (cpu_is_omap3630()) { |
458e999e | 442 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
c4236d2e PDS |
443 | /* Enable the l2 cache toggling in sleep logic */ |
444 | enable_omap3630_toggle_l2_on_restore(); | |
cc1b6028 | 445 | if (omap_rev() < OMAP3630_REV_ES1_2) |
856c3c5b PW |
446 | pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | |
447 | PM_PER_MEMORIES_ERRATUM_i582); | |
448 | } else if (cpu_is_omap34xx()) { | |
449 | pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; | |
c4236d2e | 450 | } |
8cdfd834 NM |
451 | } |
452 | ||
fb2c599f AK |
453 | static void __init omap3_pm_check_pmic(void) |
454 | { | |
455 | struct device_node *np; | |
456 | ||
457 | np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle"); | |
458 | if (!np) | |
459 | np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off"); | |
460 | ||
461 | if (np) { | |
462 | of_node_put(np); | |
463 | enable_off_mode = 1; | |
464 | } else { | |
465 | enable_off_mode = 0; | |
466 | } | |
467 | } | |
468 | ||
bbd707ac | 469 | int __init omap3_pm_init(void) |
8bd22949 KH |
470 | { |
471 | struct power_state *pwrst, *tmp; | |
856c3c5b | 472 | struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; |
8bd22949 KH |
473 | int ret; |
474 | ||
b02b9172 | 475 | if (!omap3_has_io_chain_ctrl()) |
3d0cb73e | 476 | pr_warn("PM: no software I/O chain control; some wakeups may be lost\n"); |
b02b9172 | 477 | |
8cdfd834 NM |
478 | pm_errata_configure(); |
479 | ||
8bd22949 KH |
480 | /* XXX prcm_setup_regs needs to be before enabling hw |
481 | * supervised mode for powerdomains */ | |
482 | prcm_setup_regs(); | |
483 | ||
22f51371 TK |
484 | ret = request_irq(omap_prcm_event_to_irq("wkup"), |
485 | _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); | |
486 | ||
487 | if (ret) { | |
488 | pr_err("pm: Failed to request pm_wkup irq\n"); | |
489 | goto err1; | |
490 | } | |
491 | ||
492 | /* IO interrupt is shared with mux code */ | |
493 | ret = request_irq(omap_prcm_event_to_irq("io"), | |
494 | _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", | |
495 | omap3_pm_init); | |
496 | ||
8bd22949 | 497 | if (ret) { |
22f51371 | 498 | pr_err("pm: Failed to request pm_io irq\n"); |
ce229c5d | 499 | goto err2; |
8bd22949 KH |
500 | } |
501 | ||
fb2c599f AK |
502 | omap3_pm_check_pmic(); |
503 | ||
a23456e9 | 504 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 | 505 | if (ret) { |
98179856 | 506 | pr_err("Failed to setup powerdomains\n"); |
ce229c5d | 507 | goto err3; |
8bd22949 KH |
508 | } |
509 | ||
92206fd2 | 510 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
8bd22949 KH |
511 | |
512 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
513 | if (mpu_pwrdm == NULL) { | |
98179856 | 514 | pr_err("Failed to get mpu_pwrdm\n"); |
ce229c5d MG |
515 | ret = -EINVAL; |
516 | goto err3; | |
8bd22949 KH |
517 | } |
518 | ||
fa3c2a4f RN |
519 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
520 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
521 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
522 | ||
55ed9694 PW |
523 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
524 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
856c3c5b PW |
525 | per_clkdm = clkdm_lookup("per_clkdm"); |
526 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
55ed9694 | 527 | |
2e4b62dc | 528 | omap_common_suspend_init(omap3_pm_suspend); |
8bd22949 | 529 | |
0bcd24b0 | 530 | arm_pm_idle = omap3_pm_idle; |
0343371e | 531 | omap3_idle_init(); |
8bd22949 | 532 | |
458e999e NM |
533 | /* |
534 | * RTA is disabled during initialization as per erratum i608 | |
535 | * it is safer to disable RTA by the bootloader, but we would like | |
536 | * to be doubly sure here and prevent any mishaps. | |
537 | */ | |
538 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | |
539 | omap3630_ctrl_disable_rta(); | |
540 | ||
856c3c5b PW |
541 | /* |
542 | * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are | |
543 | * not correctly reset when the PER powerdomain comes back | |
544 | * from OFF or OSWR when the CORE powerdomain is kept active. | |
545 | * See OMAP36xx Erratum i582 "PER Domain reset issue after | |
546 | * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a | |
547 | * complete workaround. The kernel must also prevent the PER | |
548 | * powerdomain from going to OSWR/OFF while the CORE | |
549 | * powerdomain is not going to OSWR/OFF. And if PER last | |
550 | * power state was off while CORE last power state was ON, the | |
551 | * UART3/4 and McBSP2/3 SIDETONE devices need to run a | |
552 | * self-test using their loopback tests; if that fails, those | |
553 | * devices are unusable until the PER/CORE can complete a transition | |
554 | * from ON to OSWR/OFF and then back to ON. | |
555 | * | |
556 | * XXX Technically this workaround is only needed if off-mode | |
557 | * or OSWR is enabled. | |
558 | */ | |
559 | if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) | |
560 | clkdm_add_wkdep(per_clkdm, wkup_clkdm); | |
561 | ||
55ed9694 | 562 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
27d59a4a TK |
563 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
564 | omap3_secure_ram_storage = | |
d09220a8 | 565 | kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL); |
27d59a4a | 566 | if (!omap3_secure_ram_storage) |
7852ec05 | 567 | pr_err("Memory allocation failed when allocating for secure sram context\n"); |
9d97140b TK |
568 | |
569 | local_irq_disable(); | |
9d97140b | 570 | |
617fcc98 | 571 | omap3_save_secure_ram_context(); |
9d97140b TK |
572 | |
573 | local_irq_enable(); | |
27d59a4a | 574 | } |
27d59a4a | 575 | |
9d97140b | 576 | omap3_save_scratchpad_contents(); |
8bd22949 | 577 | return ret; |
ce229c5d MG |
578 | |
579 | err3: | |
8bd22949 KH |
580 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
581 | list_del(&pwrst->node); | |
582 | kfree(pwrst); | |
583 | } | |
ce229c5d MG |
584 | free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); |
585 | err2: | |
586 | free_irq(omap_prcm_event_to_irq("wkup"), NULL); | |
587 | err1: | |
8bd22949 KH |
588 | return ret; |
589 | } |