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Commit | Line | Data |
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8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
dccaad89 | 29 | #include <linux/delay.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
5e7c58dc | 31 | #include <trace/events/power.h> |
8bd22949 | 32 | |
2c74a0ce RK |
33 | #include <asm/suspend.h> |
34 | ||
ce491cf8 | 35 | #include <plat/sram.h> |
1540f214 | 36 | #include "clockdomain.h" |
72e06d08 | 37 | #include "powerdomain.h" |
61255ab9 | 38 | #include <plat/sdrc.h> |
2f5939c3 RN |
39 | #include <plat/prcm.h> |
40 | #include <plat/gpmc.h> | |
f2d11858 | 41 | #include <plat/dma.h> |
8bd22949 | 42 | |
4e65331c | 43 | #include "common.h" |
59fb659b | 44 | #include "cm2xxx_3xxx.h" |
8bd22949 KH |
45 | #include "cm-regbits-34xx.h" |
46 | #include "prm-regbits-34xx.h" | |
47 | ||
59fb659b | 48 | #include "prm2xxx_3xxx.h" |
8bd22949 | 49 | #include "pm.h" |
13a6fe0f | 50 | #include "sdrc.h" |
4814ced5 | 51 | #include "control.h" |
13a6fe0f | 52 | |
e83df17f KH |
53 | #ifdef CONFIG_SUSPEND |
54 | static suspend_state_t suspend_state = PM_SUSPEND_ON; | |
e83df17f KH |
55 | #endif |
56 | ||
8cdfd834 NM |
57 | /* pm34xx errata defined in pm.h */ |
58 | u16 pm34xx_errata; | |
59 | ||
8bd22949 KH |
60 | struct power_state { |
61 | struct powerdomain *pwrdm; | |
62 | u32 next_state; | |
10f90ed2 | 63 | #ifdef CONFIG_SUSPEND |
8bd22949 | 64 | u32 saved_state; |
10f90ed2 | 65 | #endif |
8bd22949 KH |
66 | struct list_head node; |
67 | }; | |
68 | ||
69 | static LIST_HEAD(pwrst_list); | |
70 | ||
27d59a4a | 71 | static int (*_omap_save_secure_sram)(u32 *addr); |
46e130d2 | 72 | void (*omap3_do_wfi_sram)(void); |
27d59a4a | 73 | |
fa3c2a4f RN |
74 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
75 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
c16c3f67 | 76 | static struct powerdomain *cam_pwrdm; |
fa3c2a4f | 77 | |
2f5939c3 RN |
78 | static inline void omap3_per_save_context(void) |
79 | { | |
80 | omap_gpio_save_context(); | |
81 | } | |
82 | ||
83 | static inline void omap3_per_restore_context(void) | |
84 | { | |
85 | omap_gpio_restore_context(); | |
86 | } | |
87 | ||
3a7ec26b KJ |
88 | static void omap3_enable_io_chain(void) |
89 | { | |
90 | int timeout = 0; | |
91 | ||
b02b9172 PW |
92 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
93 | PM_WKEN); | |
94 | /* Do a readback to assure write has been done */ | |
95 | omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); | |
96 | ||
97 | while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & | |
98 | OMAP3430_ST_IO_CHAIN_MASK)) { | |
99 | timeout++; | |
100 | if (timeout > 1000) { | |
101 | pr_err("Wake up daisy chain activation failed.\n"); | |
102 | return; | |
3a7ec26b | 103 | } |
b02b9172 PW |
104 | omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, |
105 | WKUP_MOD, PM_WKEN); | |
3a7ec26b KJ |
106 | } |
107 | } | |
108 | ||
109 | static void omap3_disable_io_chain(void) | |
110 | { | |
b02b9172 PW |
111 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
112 | PM_WKEN); | |
3a7ec26b KJ |
113 | } |
114 | ||
2f5939c3 RN |
115 | static void omap3_core_save_context(void) |
116 | { | |
596efe47 | 117 | omap3_ctrl_save_padconf(); |
dccaad89 TK |
118 | |
119 | /* | |
120 | * Force write last pad into memory, as this can fail in some | |
83521291 | 121 | * cases according to errata 1.157, 1.185 |
dccaad89 TK |
122 | */ |
123 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | |
124 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | |
125 | ||
2f5939c3 RN |
126 | /* Save the Interrupt controller context */ |
127 | omap_intc_save_context(); | |
128 | /* Save the GPMC context */ | |
129 | omap3_gpmc_save_context(); | |
130 | /* Save the system control module context, padconf already save above*/ | |
131 | omap3_control_save_context(); | |
f2d11858 | 132 | omap_dma_global_context_save(); |
2f5939c3 RN |
133 | } |
134 | ||
135 | static void omap3_core_restore_context(void) | |
136 | { | |
137 | /* Restore the control module context, padconf restored by h/w */ | |
138 | omap3_control_restore_context(); | |
139 | /* Restore the GPMC context */ | |
140 | omap3_gpmc_restore_context(); | |
141 | /* Restore the interrupt controller context */ | |
142 | omap_intc_restore_context(); | |
f2d11858 | 143 | omap_dma_global_context_restore(); |
2f5939c3 RN |
144 | } |
145 | ||
9d97140b TK |
146 | /* |
147 | * FIXME: This function should be called before entering off-mode after | |
148 | * OMAP3 secure services have been accessed. Currently it is only called | |
149 | * once during boot sequence, but this works as we are not using secure | |
150 | * services. | |
151 | */ | |
617fcc98 | 152 | static void omap3_save_secure_ram_context(void) |
27d59a4a TK |
153 | { |
154 | u32 ret; | |
617fcc98 | 155 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
27d59a4a TK |
156 | |
157 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
158 | /* |
159 | * MPU next state must be set to POWER_ON temporarily, | |
160 | * otherwise the WFI executed inside the ROM code | |
161 | * will hang the system. | |
162 | */ | |
163 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
164 | ret = _omap_save_secure_sram((u32 *) | |
165 | __pa(omap3_secure_ram_storage)); | |
617fcc98 | 166 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
27d59a4a TK |
167 | /* Following is for error tracking, it should not happen */ |
168 | if (ret) { | |
98179856 | 169 | pr_err("save_secure_sram() returns %08x\n", ret); |
27d59a4a TK |
170 | while (1) |
171 | ; | |
172 | } | |
173 | } | |
174 | } | |
175 | ||
77da2d91 JH |
176 | /* |
177 | * PRCM Interrupt Handler Helper Function | |
178 | * | |
179 | * The purpose of this function is to clear any wake-up events latched | |
180 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | |
181 | * may occur whilst attempting to clear a PM_WKST_x register and thus | |
182 | * set another bit in this register. A while loop is used to ensure | |
183 | * that any peripheral wake-up events occurring while attempting to | |
184 | * clear the PM_WKST_x are detected and cleared. | |
185 | */ | |
22f51371 | 186 | static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) |
8bd22949 | 187 | { |
71a80775 | 188 | u32 wkst, fclk, iclk, clken; |
77da2d91 JH |
189 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
190 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | |
191 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | |
5d805978 PW |
192 | u16 grpsel_off = (regs == 3) ? |
193 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | |
8cb0ac99 | 194 | int c = 0; |
8bd22949 | 195 | |
c4d7e58f PW |
196 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
197 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); | |
22f51371 | 198 | wkst &= ~ignore_bits; |
8bd22949 | 199 | if (wkst) { |
c4d7e58f PW |
200 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
201 | fclk = omap2_cm_read_mod_reg(module, fclk_off); | |
77da2d91 | 202 | while (wkst) { |
71a80775 | 203 | clken = wkst; |
c4d7e58f | 204 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
71a80775 VP |
205 | /* |
206 | * For USBHOST, we don't know whether HOST1 or | |
207 | * HOST2 woke us up, so enable both f-clocks | |
208 | */ | |
209 | if (module == OMAP3430ES2_USBHOST_MOD) | |
210 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | |
c4d7e58f PW |
211 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
212 | omap2_prm_write_mod_reg(wkst, module, wkst_off); | |
213 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | |
22f51371 | 214 | wkst &= ~ignore_bits; |
8cb0ac99 | 215 | c++; |
77da2d91 | 216 | } |
c4d7e58f PW |
217 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
218 | omap2_cm_write_mod_reg(fclk, module, fclk_off); | |
8bd22949 | 219 | } |
8cb0ac99 PW |
220 | |
221 | return c; | |
222 | } | |
223 | ||
22f51371 | 224 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
8cb0ac99 PW |
225 | { |
226 | int c; | |
227 | ||
22f51371 TK |
228 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, |
229 | ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); | |
8cb0ac99 | 230 | |
22f51371 | 231 | return c ? IRQ_HANDLED : IRQ_NONE; |
77da2d91 | 232 | } |
8bd22949 | 233 | |
22f51371 | 234 | static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) |
77da2d91 | 235 | { |
22f51371 | 236 | int c; |
d6290a3e | 237 | |
22f51371 TK |
238 | /* |
239 | * Clear all except ST_IO and ST_IO_CHAIN for wkup module, | |
240 | * these are handled in a separate handler to avoid acking | |
241 | * IO events before parsing in mux code | |
242 | */ | |
243 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, | |
244 | OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); | |
245 | c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); | |
246 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); | |
247 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
248 | c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); | |
249 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); | |
250 | } | |
8bd22949 | 251 | |
22f51371 | 252 | return c ? IRQ_HANDLED : IRQ_NONE; |
8bd22949 KH |
253 | } |
254 | ||
cbe26349 RK |
255 | static void omap34xx_save_context(u32 *save) |
256 | { | |
257 | u32 val; | |
258 | ||
259 | /* Read Auxiliary Control Register */ | |
260 | asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); | |
261 | *save++ = 1; | |
262 | *save++ = val; | |
263 | ||
264 | /* Read L2 AUX ctrl register */ | |
265 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); | |
266 | *save++ = 1; | |
267 | *save++ = val; | |
268 | } | |
269 | ||
29cb3cd2 | 270 | static int omap34xx_do_sram_idle(unsigned long save_state) |
57f277b0 | 271 | { |
cbe26349 | 272 | omap34xx_cpu_suspend(save_state); |
29cb3cd2 | 273 | return 0; |
57f277b0 RN |
274 | } |
275 | ||
99e6a4d2 | 276 | void omap_sram_idle(void) |
8bd22949 KH |
277 | { |
278 | /* Variable to tell what needs to be saved and restored | |
279 | * in omap_sram_idle*/ | |
280 | /* save_state = 0 => Nothing to save and restored */ | |
281 | /* save_state = 1 => Only L1 and logic lost */ | |
282 | /* save_state = 2 => Only L2 lost */ | |
283 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
284 | int save_state = 0; |
285 | int mpu_next_state = PWRDM_POWER_ON; | |
286 | int per_next_state = PWRDM_POWER_ON; | |
287 | int core_next_state = PWRDM_POWER_ON; | |
72e06d08 | 288 | int per_going_off; |
2f5939c3 | 289 | int core_prev_state, per_prev_state; |
13a6fe0f | 290 | u32 sdrc_pwr = 0; |
8bd22949 | 291 | |
fa3c2a4f RN |
292 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
293 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); | |
294 | pwrdm_clear_all_prev_pwrst(core_pwrdm); | |
295 | pwrdm_clear_all_prev_pwrst(per_pwrdm); | |
296 | ||
8bd22949 KH |
297 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
298 | switch (mpu_next_state) { | |
fa3c2a4f | 299 | case PWRDM_POWER_ON: |
8bd22949 KH |
300 | case PWRDM_POWER_RET: |
301 | /* No need to save context */ | |
302 | save_state = 0; | |
303 | break; | |
61255ab9 RN |
304 | case PWRDM_POWER_OFF: |
305 | save_state = 3; | |
306 | break; | |
8bd22949 KH |
307 | default: |
308 | /* Invalid state */ | |
98179856 | 309 | pr_err("Invalid mpu state in sram_idle\n"); |
8bd22949 KH |
310 | return; |
311 | } | |
fe617af7 | 312 | |
fa3c2a4f RN |
313 | /* NEON control */ |
314 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 315 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 316 | |
40742fa8 | 317 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
658ce97e | 318 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
ecf157d0 | 319 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
d5c47d7e KH |
320 | if (omap3_has_io_wakeup() && |
321 | (per_next_state < PWRDM_POWER_ON || | |
322 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f | 323 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
b02b9172 PW |
324 | if (omap3_has_io_chain_ctrl()) |
325 | omap3_enable_io_chain(); | |
40742fa8 MC |
326 | } |
327 | ||
ff2f8e5f C |
328 | pwrdm_pre_transition(); |
329 | ||
40742fa8 | 330 | /* PER */ |
658ce97e | 331 | if (per_next_state < PWRDM_POWER_ON) { |
72e06d08 | 332 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
72e06d08 | 333 | omap2_gpio_prepare_for_idle(per_going_off); |
e7410cf7 | 334 | if (per_next_state == PWRDM_POWER_OFF) |
ecf157d0 | 335 | omap3_per_save_context(); |
658ce97e KH |
336 | } |
337 | ||
338 | /* CORE */ | |
fa3c2a4f | 339 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
340 | if (core_next_state == PWRDM_POWER_OFF) { |
341 | omap3_core_save_context(); | |
f0611a5c | 342 | omap3_cm_save_context(); |
2f5939c3 | 343 | } |
fa3c2a4f | 344 | } |
40742fa8 | 345 | |
f18cc2ff | 346 | omap3_intc_prepare_idle(); |
8bd22949 | 347 | |
13a6fe0f | 348 | /* |
30474544 PW |
349 | * On EMU/HS devices ROM code restores a SRDC value |
350 | * from scratchpad which has automatic self refresh on timeout | |
351 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. | |
352 | * Hence store/restore the SDRC_POWER register here. | |
353 | */ | |
354 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && | |
355 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
356 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
f265dc4c | 357 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 358 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 359 | |
61255ab9 | 360 | /* |
076f2cc4 RK |
361 | * omap3_arm_context is the location where some ARM context |
362 | * get saved. The rest is placed on the stack, and restored | |
363 | * from there before resuming. | |
61255ab9 | 364 | */ |
cbe26349 RK |
365 | if (save_state) |
366 | omap34xx_save_context(omap3_arm_context); | |
076f2cc4 | 367 | if (save_state == 1 || save_state == 3) |
2c74a0ce | 368 | cpu_suspend(save_state, omap34xx_do_sram_idle); |
076f2cc4 RK |
369 | else |
370 | omap34xx_do_sram_idle(save_state); | |
8bd22949 | 371 | |
f265dc4c | 372 | /* Restore normal SDRC POWER settings */ |
30474544 PW |
373 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
374 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
375 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
13a6fe0f TK |
376 | core_next_state == PWRDM_POWER_OFF) |
377 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
378 | ||
658ce97e | 379 | /* CORE */ |
fa3c2a4f | 380 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
381 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
382 | if (core_prev_state == PWRDM_POWER_OFF) { | |
383 | omap3_core_restore_context(); | |
f0611a5c | 384 | omap3_cm_restore_context(); |
2f5939c3 | 385 | omap3_sram_restore_context(); |
8a917d2f | 386 | omap2_sms_restore_context(); |
2f5939c3 | 387 | } |
658ce97e | 388 | if (core_next_state == PWRDM_POWER_OFF) |
c4d7e58f | 389 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
658ce97e KH |
390 | OMAP3430_GR_MOD, |
391 | OMAP3_PRM_VOLTCTRL_OFFSET); | |
392 | } | |
f18cc2ff | 393 | omap3_intc_resume_idle(); |
658ce97e | 394 | |
ff2f8e5f C |
395 | pwrdm_post_transition(); |
396 | ||
658ce97e KH |
397 | /* PER */ |
398 | if (per_next_state < PWRDM_POWER_ON) { | |
399 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | |
43ffcd9a KH |
400 | omap2_gpio_resume_after_idle(); |
401 | if (per_prev_state == PWRDM_POWER_OFF) | |
658ce97e | 402 | omap3_per_restore_context(); |
fa3c2a4f | 403 | } |
fe617af7 | 404 | |
3a7ec26b | 405 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
58a5559e KH |
406 | if (omap3_has_io_wakeup() && |
407 | (per_next_state < PWRDM_POWER_ON || | |
408 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f PW |
409 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
410 | PM_WKEN); | |
b02b9172 PW |
411 | if (omap3_has_io_chain_ctrl()) |
412 | omap3_disable_io_chain(); | |
3a7ec26b | 413 | } |
658ce97e | 414 | |
5cd1937b | 415 | clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
8bd22949 KH |
416 | } |
417 | ||
8bd22949 KH |
418 | static void omap3_pm_idle(void) |
419 | { | |
420 | local_irq_disable(); | |
421 | local_fiq_disable(); | |
422 | ||
cf22854c | 423 | if (omap_irq_pending() || need_resched()) |
8bd22949 KH |
424 | goto out; |
425 | ||
5e7c58dc JP |
426 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
427 | trace_cpu_idle(1, smp_processor_id()); | |
428 | ||
8bd22949 KH |
429 | omap_sram_idle(); |
430 | ||
5e7c58dc JP |
431 | trace_power_end(smp_processor_id()); |
432 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
433 | ||
8bd22949 KH |
434 | out: |
435 | local_fiq_enable(); | |
436 | local_irq_enable(); | |
437 | } | |
438 | ||
10f90ed2 | 439 | #ifdef CONFIG_SUSPEND |
8bd22949 KH |
440 | static int omap3_pm_suspend(void) |
441 | { | |
442 | struct power_state *pwrst; | |
443 | int state, ret = 0; | |
444 | ||
445 | /* Read current next_pwrsts */ | |
446 | list_for_each_entry(pwrst, &pwrst_list, node) | |
447 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
448 | /* Set ones wanted by suspend */ | |
449 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
eb6a2c75 | 450 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
8bd22949 KH |
451 | goto restore; |
452 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
453 | goto restore; | |
454 | } | |
455 | ||
2bbe3af3 TK |
456 | omap3_intc_suspend(); |
457 | ||
8bd22949 KH |
458 | omap_sram_idle(); |
459 | ||
460 | restore: | |
461 | /* Restore next_pwrsts */ | |
462 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
463 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
464 | if (state > pwrst->next_state) { | |
98179856 MG |
465 | pr_info("Powerdomain (%s) didn't enter " |
466 | "target state %d\n", | |
8bd22949 KH |
467 | pwrst->pwrdm->name, pwrst->next_state); |
468 | ret = -1; | |
469 | } | |
eb6a2c75 | 470 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
471 | } |
472 | if (ret) | |
98179856 | 473 | pr_err("Could not enter target state in pm_suspend\n"); |
8bd22949 | 474 | else |
98179856 | 475 | pr_info("Successfully put all powerdomains to target state\n"); |
8bd22949 KH |
476 | |
477 | return ret; | |
478 | } | |
479 | ||
2466211e | 480 | static int omap3_pm_enter(suspend_state_t unused) |
8bd22949 KH |
481 | { |
482 | int ret = 0; | |
483 | ||
2466211e | 484 | switch (suspend_state) { |
8bd22949 KH |
485 | case PM_SUSPEND_STANDBY: |
486 | case PM_SUSPEND_MEM: | |
487 | ret = omap3_pm_suspend(); | |
488 | break; | |
489 | default: | |
490 | ret = -EINVAL; | |
491 | } | |
492 | ||
493 | return ret; | |
494 | } | |
495 | ||
2466211e TK |
496 | /* Hooks to enable / disable UART interrupts during suspend */ |
497 | static int omap3_pm_begin(suspend_state_t state) | |
498 | { | |
c166381d | 499 | disable_hlt(); |
2466211e | 500 | suspend_state = state; |
22f51371 | 501 | omap_prcm_irq_prepare(); |
2466211e TK |
502 | return 0; |
503 | } | |
504 | ||
505 | static void omap3_pm_end(void) | |
506 | { | |
507 | suspend_state = PM_SUSPEND_ON; | |
c166381d | 508 | enable_hlt(); |
2466211e TK |
509 | return; |
510 | } | |
511 | ||
22f51371 TK |
512 | static void omap3_pm_finish(void) |
513 | { | |
514 | omap_prcm_irq_complete(); | |
515 | } | |
516 | ||
2f55ac07 | 517 | static const struct platform_suspend_ops omap_pm_ops = { |
2466211e TK |
518 | .begin = omap3_pm_begin, |
519 | .end = omap3_pm_end, | |
8bd22949 | 520 | .enter = omap3_pm_enter, |
22f51371 | 521 | .finish = omap3_pm_finish, |
8bd22949 KH |
522 | .valid = suspend_valid_only_mem, |
523 | }; | |
10f90ed2 | 524 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 525 | |
1155e426 KH |
526 | |
527 | /** | |
528 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | |
529 | * retention | |
530 | * | |
531 | * In cases where IVA2 is activated by bootcode, it may prevent | |
532 | * full-chip retention or off-mode because it is not idle. This | |
533 | * function forces the IVA2 into idle state so it can go | |
534 | * into retention/off and thus allow full-chip retention/off. | |
535 | * | |
536 | **/ | |
537 | static void __init omap3_iva_idle(void) | |
538 | { | |
539 | /* ensure IVA2 clock is disabled */ | |
c4d7e58f | 540 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
541 | |
542 | /* if no clock activity, nothing else to do */ | |
c4d7e58f | 543 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
1155e426 KH |
544 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
545 | return; | |
546 | ||
547 | /* Reset IVA2 */ | |
c4d7e58f | 548 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
549 | OMAP3430_RST2_IVA2_MASK | |
550 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 551 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
552 | |
553 | /* Enable IVA2 clock */ | |
c4d7e58f | 554 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
1155e426 KH |
555 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
556 | ||
557 | /* Set IVA2 boot mode to 'idle' */ | |
558 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
559 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
560 | ||
561 | /* Un-reset IVA2 */ | |
c4d7e58f | 562 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
563 | |
564 | /* Disable IVA2 clock */ | |
c4d7e58f | 565 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
566 | |
567 | /* Reset IVA2 */ | |
c4d7e58f | 568 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
569 | OMAP3430_RST2_IVA2_MASK | |
570 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 571 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
572 | } |
573 | ||
8111b221 | 574 | static void __init omap3_d2d_idle(void) |
8bd22949 | 575 | { |
8111b221 KH |
576 | u16 mask, padconf; |
577 | ||
578 | /* In a stand alone OMAP3430 where there is not a stacked | |
579 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | |
580 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | |
581 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | |
582 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | |
583 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | |
584 | padconf |= mask; | |
585 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | |
586 | ||
587 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | |
588 | padconf |= mask; | |
589 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | |
590 | ||
8bd22949 | 591 | /* reset modem */ |
c4d7e58f | 592 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
2bc4ef71 | 593 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
37903009 | 594 | CORE_MOD, OMAP2_RM_RSTCTRL); |
c4d7e58f | 595 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
8111b221 | 596 | } |
8bd22949 | 597 | |
8111b221 KH |
598 | static void __init prcm_setup_regs(void) |
599 | { | |
e5863689 G |
600 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
601 | OMAP3630_EN_UART4_MASK : 0; | |
602 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? | |
603 | OMAP3630_GRPSEL_UART4_MASK : 0; | |
604 | ||
4ef70c06 | 605 | /* XXX This should be handled by hwmod code or SCM init code */ |
2fd0f75c | 606 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
b296c811 | 607 | |
8bd22949 KH |
608 | /* |
609 | * Enable control of expternal oscillator through | |
610 | * sys_clkreq. In the long run clock framework should | |
611 | * take care of this. | |
612 | */ | |
c4d7e58f | 613 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
8bd22949 KH |
614 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
615 | OMAP3430_GR_MOD, | |
616 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
617 | ||
618 | /* setup wakup source */ | |
c4d7e58f | 619 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
2fd0f75c | 620 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
8bd22949 KH |
621 | WKUP_MOD, PM_WKEN); |
622 | /* No need to write EN_IO, that is always enabled */ | |
c4d7e58f | 623 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
275f675c PW |
624 | OMAP3430_GRPSEL_GPT1_MASK | |
625 | OMAP3430_GRPSEL_GPT12_MASK, | |
8bd22949 | 626 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
1155e426 | 627 | |
b92c5721 | 628 | /* Enable PM_WKEN to support DSS LPR */ |
c4d7e58f | 629 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
b92c5721 SV |
630 | OMAP3430_DSS_MOD, PM_WKEN); |
631 | ||
b427f92f | 632 | /* Enable wakeups in PER */ |
c4d7e58f | 633 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | |
e5863689 | 634 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
2fd0f75c PW |
635 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
636 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | | |
637 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | | |
638 | OMAP3430_EN_MCBSP4_MASK, | |
b427f92f | 639 | OMAP3430_PER_MOD, PM_WKEN); |
eb350f74 | 640 | /* and allow them to wake up MPU */ |
c4d7e58f | 641 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
e5863689 | 642 | OMAP3430_GRPSEL_GPIO2_MASK | |
275f675c PW |
643 | OMAP3430_GRPSEL_GPIO3_MASK | |
644 | OMAP3430_GRPSEL_GPIO4_MASK | | |
645 | OMAP3430_GRPSEL_GPIO5_MASK | | |
646 | OMAP3430_GRPSEL_GPIO6_MASK | | |
647 | OMAP3430_GRPSEL_UART3_MASK | | |
648 | OMAP3430_GRPSEL_MCBSP2_MASK | | |
649 | OMAP3430_GRPSEL_MCBSP3_MASK | | |
650 | OMAP3430_GRPSEL_MCBSP4_MASK, | |
eb350f74 KH |
651 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
652 | ||
d3fd3290 | 653 | /* Don't attach IVA interrupts */ |
c4d7e58f PW |
654 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
655 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
656 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
657 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | |
d3fd3290 | 658 | |
b1340d17 | 659 | /* Clear any pending 'reset' flags */ |
c4d7e58f PW |
660 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
661 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | |
662 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | |
663 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | |
664 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | |
665 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | |
666 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); | |
b1340d17 | 667 | |
014c46db | 668 | /* Clear any pending PRCM interrupts */ |
c4d7e58f | 669 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
014c46db | 670 | |
1155e426 | 671 | omap3_iva_idle(); |
8111b221 | 672 | omap3_d2d_idle(); |
8bd22949 KH |
673 | } |
674 | ||
c40552bc KH |
675 | void omap3_pm_off_mode_enable(int enable) |
676 | { | |
677 | struct power_state *pwrst; | |
678 | u32 state; | |
679 | ||
680 | if (enable) | |
681 | state = PWRDM_POWER_OFF; | |
682 | else | |
683 | state = PWRDM_POWER_RET; | |
684 | ||
685 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
cc1b6028 EV |
686 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
687 | pwrst->pwrdm == core_pwrdm && | |
688 | state == PWRDM_POWER_OFF) { | |
689 | pwrst->next_state = PWRDM_POWER_RET; | |
e16b41bf | 690 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
cc1b6028 EV |
691 | __func__); |
692 | } else { | |
693 | pwrst->next_state = state; | |
694 | } | |
695 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
c40552bc KH |
696 | } |
697 | } | |
698 | ||
68d4778c TK |
699 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
700 | { | |
701 | struct power_state *pwrst; | |
702 | ||
703 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
704 | if (pwrst->pwrdm == pwrdm) | |
705 | return pwrst->next_state; | |
706 | } | |
707 | return -EINVAL; | |
708 | } | |
709 | ||
710 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
711 | { | |
712 | struct power_state *pwrst; | |
713 | ||
714 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
715 | if (pwrst->pwrdm == pwrdm) { | |
716 | pwrst->next_state = state; | |
717 | return 0; | |
718 | } | |
719 | } | |
720 | return -EINVAL; | |
721 | } | |
722 | ||
a23456e9 | 723 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
724 | { |
725 | struct power_state *pwrst; | |
726 | ||
727 | if (!pwrdm->pwrsts) | |
728 | return 0; | |
729 | ||
d3d381c6 | 730 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
731 | if (!pwrst) |
732 | return -ENOMEM; | |
733 | pwrst->pwrdm = pwrdm; | |
734 | pwrst->next_state = PWRDM_POWER_RET; | |
735 | list_add(&pwrst->node, &pwrst_list); | |
736 | ||
737 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
738 | pwrdm_enable_hdwr_sar(pwrdm); | |
739 | ||
eb6a2c75 | 740 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
8bd22949 KH |
741 | } |
742 | ||
743 | /* | |
744 | * Enable hw supervised mode for all clockdomains if it's | |
745 | * supported. Initiate sleep transition for other clockdomains, if | |
746 | * they are not used | |
747 | */ | |
a23456e9 | 748 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
8bd22949 KH |
749 | { |
750 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
5cd1937b | 751 | clkdm_allow_idle(clkdm); |
8bd22949 KH |
752 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
753 | atomic_read(&clkdm->usecount) == 0) | |
68b921ad | 754 | clkdm_sleep(clkdm); |
8bd22949 KH |
755 | return 0; |
756 | } | |
757 | ||
46e130d2 JP |
758 | /* |
759 | * Push functions to SRAM | |
760 | * | |
761 | * The minimum set of functions is pushed to SRAM for execution: | |
762 | * - omap3_do_wfi for erratum i581 WA, | |
763 | * - save_secure_ram_context for security extensions. | |
764 | */ | |
3231fc88 RN |
765 | void omap_push_sram_idle(void) |
766 | { | |
46e130d2 JP |
767 | omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
768 | ||
27d59a4a TK |
769 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
770 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
771 | save_secure_ram_context_sz); | |
3231fc88 RN |
772 | } |
773 | ||
8cdfd834 NM |
774 | static void __init pm_errata_configure(void) |
775 | { | |
c4236d2e | 776 | if (cpu_is_omap3630()) { |
458e999e | 777 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
c4236d2e PDS |
778 | /* Enable the l2 cache toggling in sleep logic */ |
779 | enable_omap3630_toggle_l2_on_restore(); | |
cc1b6028 EV |
780 | if (omap_rev() < OMAP3630_REV_ES1_2) |
781 | pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; | |
c4236d2e | 782 | } |
8cdfd834 NM |
783 | } |
784 | ||
7cc515f7 | 785 | static int __init omap3_pm_init(void) |
8bd22949 KH |
786 | { |
787 | struct power_state *pwrst, *tmp; | |
55ed9694 | 788 | struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; |
8bd22949 KH |
789 | int ret; |
790 | ||
791 | if (!cpu_is_omap34xx()) | |
792 | return -ENODEV; | |
793 | ||
b02b9172 PW |
794 | if (!omap3_has_io_chain_ctrl()) |
795 | pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); | |
796 | ||
8cdfd834 NM |
797 | pm_errata_configure(); |
798 | ||
8bd22949 KH |
799 | /* XXX prcm_setup_regs needs to be before enabling hw |
800 | * supervised mode for powerdomains */ | |
801 | prcm_setup_regs(); | |
802 | ||
22f51371 TK |
803 | ret = request_irq(omap_prcm_event_to_irq("wkup"), |
804 | _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); | |
805 | ||
806 | if (ret) { | |
807 | pr_err("pm: Failed to request pm_wkup irq\n"); | |
808 | goto err1; | |
809 | } | |
810 | ||
811 | /* IO interrupt is shared with mux code */ | |
812 | ret = request_irq(omap_prcm_event_to_irq("io"), | |
813 | _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", | |
814 | omap3_pm_init); | |
815 | ||
8bd22949 | 816 | if (ret) { |
22f51371 | 817 | pr_err("pm: Failed to request pm_io irq\n"); |
ce229c5d | 818 | goto err2; |
8bd22949 KH |
819 | } |
820 | ||
a23456e9 | 821 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 | 822 | if (ret) { |
98179856 | 823 | pr_err("Failed to setup powerdomains\n"); |
ce229c5d | 824 | goto err3; |
8bd22949 KH |
825 | } |
826 | ||
a23456e9 | 827 | (void) clkdm_for_each(clkdms_setup, NULL); |
8bd22949 KH |
828 | |
829 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
830 | if (mpu_pwrdm == NULL) { | |
98179856 | 831 | pr_err("Failed to get mpu_pwrdm\n"); |
ce229c5d MG |
832 | ret = -EINVAL; |
833 | goto err3; | |
8bd22949 KH |
834 | } |
835 | ||
fa3c2a4f RN |
836 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
837 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
838 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
c16c3f67 | 839 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
fa3c2a4f | 840 | |
55ed9694 PW |
841 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
842 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
843 | per_clkdm = clkdm_lookup("per_clkdm"); | |
844 | core_clkdm = clkdm_lookup("core_clkdm"); | |
845 | ||
10f90ed2 | 846 | #ifdef CONFIG_SUSPEND |
8bd22949 | 847 | suspend_set_ops(&omap_pm_ops); |
10f90ed2 | 848 | #endif /* CONFIG_SUSPEND */ |
8bd22949 KH |
849 | |
850 | pm_idle = omap3_pm_idle; | |
0343371e | 851 | omap3_idle_init(); |
8bd22949 | 852 | |
458e999e NM |
853 | /* |
854 | * RTA is disabled during initialization as per erratum i608 | |
855 | * it is safer to disable RTA by the bootloader, but we would like | |
856 | * to be doubly sure here and prevent any mishaps. | |
857 | */ | |
858 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | |
859 | omap3630_ctrl_disable_rta(); | |
860 | ||
55ed9694 | 861 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
27d59a4a TK |
862 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
863 | omap3_secure_ram_storage = | |
864 | kmalloc(0x803F, GFP_KERNEL); | |
865 | if (!omap3_secure_ram_storage) | |
98179856 MG |
866 | pr_err("Memory allocation failed when " |
867 | "allocating for secure sram context\n"); | |
9d97140b TK |
868 | |
869 | local_irq_disable(); | |
870 | local_fiq_disable(); | |
871 | ||
872 | omap_dma_global_context_save(); | |
617fcc98 | 873 | omap3_save_secure_ram_context(); |
9d97140b TK |
874 | omap_dma_global_context_restore(); |
875 | ||
876 | local_irq_enable(); | |
877 | local_fiq_enable(); | |
27d59a4a | 878 | } |
27d59a4a | 879 | |
9d97140b | 880 | omap3_save_scratchpad_contents(); |
8bd22949 | 881 | return ret; |
ce229c5d MG |
882 | |
883 | err3: | |
8bd22949 KH |
884 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
885 | list_del(&pwrst->node); | |
886 | kfree(pwrst); | |
887 | } | |
ce229c5d MG |
888 | free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); |
889 | err2: | |
890 | free_irq(omap_prcm_event_to_irq("wkup"), NULL); | |
891 | err1: | |
8bd22949 KH |
892 | return ret; |
893 | } | |
894 | ||
895 | late_initcall(omap3_pm_init); |