[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-omap2 / pm44xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP4+ Power Management Routines
 *
 * Copyright (C) 2010-2013 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <asm/system_misc.h>

#include "soc.h"
#include "common.h"
#include "clockdomain.h"
#include "powerdomain.h"
#include "pm.h"

u16 pm44xx_errata;

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
	u32 next_logic_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
	u32 saved_logic_state;
#endif
	struct list_head node;
};

/**
 * struct static_dep_map - Static dependency map
 * @from:	from clockdomain
 * @to:		to clockdomain
  */
struct static_dep_map {
	const char *from;
	const char *to;
};

static u32 cpu_suspend_state = PWRDM_POWER_OFF;

static LIST_HEAD(pwrst_list);

#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;
	u32 cpu_id = smp_processor_id();

	/* Save current powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
	}

	/* Set targeted power domain states by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
	}

	/*
	 * For MPUSS to hit power domain retention(CSWR or OSWR),
	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	 * since CPU power domain CSWR is not supported by hardware
	 * Only master CPU follows suspend path. All other CPUs follow
	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
	 * domain CSWR is not supported by hardware.
	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
	 */
	omap4_enter_lowpower(cpu_id, cpu_suspend_state);

	/* Restore next powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter target state %d\n",
				pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
	}
	if (ret) {
		pr_crit("Could not enter target state in pm_suspend\n");
		/*
		 * OMAP4 chip PM currently works only with certain (newer)
		 * versions of bootloaders. This is due to missing code in the
		 * kernel to properly reset and initialize some devices.
		 * Warn the user about the bootloader version being one of the
		 * possible causes.
		 * http://www.spinics.net/lists/arm-kernel/msg218641.html
		 */
		pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	} else {
		pr_info("Successfully put all powerdomains to target state\n");
	}

	return 0;
}
#else
#define omap4_pm_suspend NULL
#endif /* CONFIG_SUSPEND */

static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	/*
	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
	 * through hotplug path and CPU0 explicitly programmed
	 * further down in the code path
	 */
	if (!strncmp(pwrdm->name, "cpu", 3)) {
		if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
			cpu_suspend_state = PWRDM_POWER_RET;
		return 0;
	}

	/*
	 * Bootloader or kexec boot may have LOGICRETSTATE cleared
	 * for some domains. This is the case when kexec booting from
	 * Android kernels that support off mode for example.
	 * Make sure it's set at least for core and per, otherwise
	 * we currently will see lost GPIO interrupts for wlcore and
	 * smsc911x at least if per hits retention during idle.
	 */
	if (!strncmp(pwrdm->name, "core", 4) ||
	    !strncmp(pwrdm->name, "l4per", 5) ||
	    !strncmp(pwrdm->name, "wkup", 4))
		pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET);

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;

	pwrst->pwrdm = pwrdm;
	pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
						     PWRDM_POWER_RET);
	pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
							   PWRDM_POWER_OFF);

	list_add(&pwrst->node, &pwrst_list);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/**
 * omap_default_idle - OMAP4 default ilde routine.'
 *
 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
 * by secondary CPU with CONFIG_CPU_IDLE.
 */
static void omap_default_idle(void)
{
	omap_do_wfi();
}

/*
 * The dynamic dependency between MPUSS -> MEMIF and
 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
 * expected. The hardware recommendation is to enable static
 * dependencies for these to avoid system lock ups or random crashes.
 * The L4 wakeup depedency is added to workaround the OCP sync hardware
 * BUG with 32K synctimer which lead to incorrect timer value read
 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
 * are part of L4 wakeup clockdomain.
 */
static const struct static_dep_map omap4_static_dep_map[] = {
	{.from = "mpuss_clkdm", .to = "l3_emif_clkdm"},
	{.from = "mpuss_clkdm", .to = "l3_1_clkdm"},
	{.from = "mpuss_clkdm", .to = "l3_2_clkdm"},
	{.from = "ducati_clkdm", .to = "l3_1_clkdm"},
	{.from = "ducati_clkdm", .to = "l3_2_clkdm"},
	{.from  = NULL} /* TERMINATION */
};

static const struct static_dep_map omap5_dra7_static_dep_map[] = {
	{.from = "mpu_clkdm", .to = "emif_clkdm"},
	{.from  = NULL} /* TERMINATION */
};

/**
 * omap4plus_init_static_deps() - Initialize a static dependency map
 * @map:	Mapping of clock domains
 */
static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
{
	int ret;
	struct clockdomain *from, *to;

	if (!map)
		return 0;

	while (map->from) {
		from = clkdm_lookup(map->from);
		to = clkdm_lookup(map->to);
		if (!from || !to) {
			pr_err("Failed lookup %s or %s for wakeup dependency\n",
			       map->from, map->to);
			return -EINVAL;
		}
		ret = clkdm_add_wkdep(from, to);
		if (ret) {
			pr_err("Failed to add %s -> %s wakeup dependency(%d)\n",
			       map->from, map->to, ret);
			return ret;
		}

		map++;
	}

	return 0;
}

/**
 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
 *
 * Initializes basic stuff for power management functionality.
 */
int __init omap4_pm_init_early(void)
{
	if (cpu_is_omap446x())
		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	if (soc_is_omap54xx() || soc_is_dra7xx())
		pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;

	return 0;
}

/**
 * omap4_pm_init - Init routine for OMAP4+ devices
 *
 * Initializes all powerdomain and clockdomain target states
 * and all PRCM settings.
 * Return: Returns the error code returned by called functions.
 */
int __init omap4_pm_init(void)
{
	int ret = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	pr_info("Power Management for TI OMAP4+ devices.\n");

	/*
	 * OMAP4 chip PM currently works only with certain (newer)
	 * versions of bootloaders. This is due to missing code in the
	 * kernel to properly reset and initialize some devices.
	 * http://www.spinics.net/lists/arm-kernel/msg218641.html
	 */
	if (cpu_is_omap44xx())
		pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains.\n");
		goto err2;
	}

	if (cpu_is_omap44xx())
		ret = omap4plus_init_static_deps(omap4_static_dep_map);
	else if (soc_is_omap54xx() || soc_is_dra7xx())
		ret = omap4plus_init_static_deps(omap5_dra7_static_dep_map);

	if (ret) {
		pr_err("Failed to initialise static dependencies.\n");
		goto err2;
	}

	ret = omap4_mpuss_init();
	if (ret) {
		pr_err("Failed to initialise OMAP4 MPUSS\n");
		goto err2;
	}

	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);

	omap_common_suspend_init(omap4_pm_suspend);

	/* Overwrite the default cpu_do_idle() */
	arm_pm_idle = omap_default_idle;

	if (cpu_is_omap44xx() || soc_is_omap54xx())
		omap4_idle_init();

err2:
	return ret;
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
5643aebb	2	/*
705814b5	3	* OMAP4+ Power Management Routines
5643aebb	4	*
705814b5	5	* Copyright (C) 2010-2013 Texas Instruments, Inc.
5643aebb	6	* Rajendra Nayak <rnayak@ti.com>
e44f9a77	7	* Santosh Shilimkar <santosh.shilimkar@ti.com>
5643aebb RN	8	*/
	9
	10	#include <linux/pm.h>
	11	#include <linux/suspend.h>
	12	#include <linux/module.h>
	13	#include <linux/list.h>
	14	#include <linux/err.h>
	15	#include <linux/slab.h>
9f97da78	16	#include <asm/system_misc.h>
5643aebb	17
e4c060db	18	#include "soc.h"
4e65331c	19	#include "common.h"
3c50729b	20	#include "clockdomain.h"
72e06d08	21	#include "powerdomain.h"
e44f9a77	22	#include "pm.h"
5643aebb	23
de70af49 NM	24	u16 pm44xx_errata;
de70af49 NM	25
5643aebb RN	26	struct power_state {
	27	struct powerdomain *pwrdm;
	28	u32 next_state;
46ba5526	29	u32 next_logic_state;
5643aebb RN	30	#ifdef CONFIG_SUSPEND
5643aebb RN	31	u32 saved_state;
3ba2a739	32	u32 saved_logic_state;
5643aebb RN	33	#endif
	34	struct list_head node;
	35	};
	36
b9f5fe64 NM	37	/**
	38	* struct static_dep_map - Static dependency map
	39	* @from: from clockdomain
	40	* @to: to clockdomain
	41	*/
	42	struct static_dep_map {
	43	const char *from;
	44	const char *to;
	45	};
	46
6099dd37 RN	47	static u32 cpu_suspend_state = PWRDM_POWER_OFF;
6099dd37 RN	48
5643aebb RN	49	static LIST_HEAD(pwrst_list);
	50
	51	#ifdef CONFIG_SUSPEND
5643aebb RN	52	static int omap4_pm_suspend(void)
5643aebb RN	53	{
e44f9a77 SS	54	struct power_state *pwrst;
	55	int state, ret = 0;
	56	u32 cpu_id = smp_processor_id();
	57
	58	/* Save current powerdomain state */
	59	list_for_each_entry(pwrst, &pwrst_list, node) {
	60	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
3ba2a739	61	pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
e44f9a77 SS	62	}
	63
	64	/* Set targeted power domain states by suspend */
	65	list_for_each_entry(pwrst, &pwrst_list, node) {
	66	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
46ba5526	67	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
e44f9a77 SS	68	}
	69
	70	/*
	71	* For MPUSS to hit power domain retention(CSWR or OSWR),
	72	* CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	73	* since CPU power domain CSWR is not supported by hardware
	74	* Only master CPU follows suspend path. All other CPUs follow
	75	* CPU hotplug path in system wide suspend. On OMAP4, CPU power
	76	* domain CSWR is not supported by hardware.
	77	* More details can be found in OMAP4430 TRM section 4.3.4.2.
	78	*/
6099dd37	79	omap4_enter_lowpower(cpu_id, cpu_suspend_state);
e44f9a77 SS	80
	81	/* Restore next powerdomain state */
	82	list_for_each_entry(pwrst, &pwrst_list, node) {
	83	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
	84	if (state > pwrst->next_state) {
7852ec05 PW	85	pr_info("Powerdomain (%s) didn't enter target state %d\n",
7852ec05 PW	86	pwrst->pwrdm->name, pwrst->next_state);
e44f9a77 SS	87	ret = -1;
	88	}
	89	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
3ba2a739	90	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
e44f9a77	91	}
60480098	92	if (ret) {
e44f9a77	93	pr_crit("Could not enter target state in pm_suspend\n");
60480098 RN	94	/*
	95	* OMAP4 chip PM currently works only with certain (newer)
	96	* versions of bootloaders. This is due to missing code in the
	97	* kernel to properly reset and initialize some devices.
	98	* Warn the user about the bootloader version being one of the
	99	* possible causes.
	100	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	101	*/
	102	pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	103	} else {
e44f9a77	104	pr_info("Successfully put all powerdomains to target state\n");
60480098	105	}
e44f9a77	106
5643aebb RN	107	return 0;
5643aebb RN	108	}
2e4b62dc DG	109	#else
2e4b62dc DG	110	#define omap4_pm_suspend NULL
5643aebb RN	111	#endif /* CONFIG_SUSPEND */
	112
	113	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
	114	{
	115	struct power_state *pwrst;
	116
	117	if (!pwrdm->pwrsts)
	118	return 0;
	119
e44f9a77 SS	120	/*
	121	* Skip CPU0 and CPU1 power domains. CPU1 is programmed
	122	* through hotplug path and CPU0 explicitly programmed
	123	* further down in the code path
	124	*/
6099dd37 RN	125	if (!strncmp(pwrdm->name, "cpu", 3)) {
	126	if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
	127	cpu_suspend_state = PWRDM_POWER_RET;
e44f9a77	128	return 0;
6099dd37	129	}
e44f9a77	130
f74297dd TL	131	/*
	132	* Bootloader or kexec boot may have LOGICRETSTATE cleared
	133	* for some domains. This is the case when kexec booting from
	134	* Android kernels that support off mode for example.
	135	* Make sure it's set at least for core and per, otherwise
	136	* we currently will see lost GPIO interrupts for wlcore and
	137	* smsc911x at least if per hits retention during idle.
	138	*/
	139	if (!strncmp(pwrdm->name, "core", 4) \|\|
	140	!strncmp(pwrdm->name, "l4per", 5) \|\|
	141	!strncmp(pwrdm->name, "wkup", 4))
	142	pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET);
	143
5643aebb RN	144	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	145	if (!pwrst)
	146	return -ENOMEM;
e44f9a77	147
5643aebb	148	pwrst->pwrdm = pwrdm;
bd7593c6 NM	149	pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
	150	PWRDM_POWER_RET);
	151	pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
	152	PWRDM_POWER_OFF);
46ba5526	153
5643aebb RN	154	list_add(&pwrst->node, &pwrst_list);
5643aebb RN	155
e44f9a77	156	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
5643aebb RN	157	}
5643aebb RN	158
72826b9f SS	159	/**
	160	* omap_default_idle - OMAP4 default ilde routine.'
	161	*
	162	* Implements OMAP4 memory, IO ordering requirements which can't be addressed
62006324 PB	163	* with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
62006324 PB	164	* by secondary CPU with CONFIG_CPU_IDLE.
72826b9f SS	165	*/
	166	static void omap_default_idle(void)
	167	{
72826b9f	168	omap_do_wfi();
72826b9f SS	169	}
72826b9f SS	170
b9f5fe64 NM	171	/*
	172	* The dynamic dependency between MPUSS -> MEMIF and
	173	* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	174	* expected. The hardware recommendation is to enable static
	175	* dependencies for these to avoid system lock ups or random crashes.
	176	* The L4 wakeup depedency is added to workaround the OCP sync hardware
	177	* BUG with 32K synctimer which lead to incorrect timer value read
	178	* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	179	* are part of L4 wakeup clockdomain.
5643aebb	180	*/
b9f5fe64 NM	181	static const struct static_dep_map omap4_static_dep_map[] = {
	182	{.from = "mpuss_clkdm", .to = "l3_emif_clkdm"},
	183	{.from = "mpuss_clkdm", .to = "l3_1_clkdm"},
	184	{.from = "mpuss_clkdm", .to = "l3_2_clkdm"},
	185	{.from = "ducati_clkdm", .to = "l3_1_clkdm"},
	186	{.from = "ducati_clkdm", .to = "l3_2_clkdm"},
	187	{.from = NULL} /* TERMINATION */
	188	};
705814b5	189
b9f5fe64 NM	190	static const struct static_dep_map omap5_dra7_static_dep_map[] = {
	191	{.from = "mpu_clkdm", .to = "emif_clkdm"},
	192	{.from = NULL} /* TERMINATION */
	193	};
de70af49	194
d2136bce	195	/**
b9f5fe64 NM	196	* omap4plus_init_static_deps() - Initialize a static dependency map
b9f5fe64 NM	197	* @map: Mapping of clock domains
d2136bce	198	*/
b9f5fe64	199	static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
d2136bce	200	{
d2136bce	201	int ret;
b9f5fe64	202	struct clockdomain from, to;
d2136bce	203
b9f5fe64 NM	204	if (!map)
	205	return 0;
	206
	207	while (map->from) {
	208	from = clkdm_lookup(map->from);
	209	to = clkdm_lookup(map->to);
	210	if (!from \|\| !to) {
	211	pr_err("Failed lookup %s or %s for wakeup dependency\n",
	212	map->from, map->to);
	213	return -EINVAL;
	214	}
	215	ret = clkdm_add_wkdep(from, to);
	216	if (ret) {
	217	pr_err("Failed to add %s -> %s wakeup dependency(%d)\n",
	218	map->from, map->to, ret);
	219	return ret;
	220	}
d2136bce	221
b9f5fe64	222	map++;
ae428a72	223	}
d2136bce	224
b9f5fe64	225	return 0;
d2136bce SS	226	}
d2136bce SS	227
de70af49 NM	228	/**
	229	* omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
	230	*
	231	* Initializes basic stuff for power management functionality.
	232	*/
	233	int __init omap4_pm_init_early(void)
	234	{
	235	if (cpu_is_omap446x())
	236	pm44xx_errata \|= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	237
6099dd37 RN	238	if (soc_is_omap54xx() \|\| soc_is_dra7xx())
	239	pm44xx_errata \|= PM_OMAP4_CPU_OSWR_DISABLE;
	240
de70af49	241	return 0;
705814b5 SS	242	}
	243
	244	/**
	245	* omap4_pm_init - Init routine for OMAP4+ devices
	246	*
	247	* Initializes all powerdomain and clockdomain target states
	248	* and all PRCM settings.
	249	* Return: Returns the error code returned by called functions.
	250	*/
	251	int __init omap4_pm_init(void)
	252	{
	253	int ret = 0;
	254
	255	if (omap_rev() == OMAP4430_REV_ES1_0) {
	256	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	257	return -ENODEV;
	258	}
	259
	260	pr_info("Power Management for TI OMAP4+ devices.\n");
	261
9008d83f NM	262	/*
	263	* OMAP4 chip PM currently works only with certain (newer)
	264	* versions of bootloaders. This is due to missing code in the
	265	* kernel to properly reset and initialize some devices.
	266	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	267	*/
	268	if (cpu_is_omap44xx())
	269	pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
	270
705814b5 SS	271	ret = pwrdm_for_each(pwrdms_setup, NULL);
	272	if (ret) {
	273	pr_err("Failed to setup powerdomains.\n");
12f27826 SS	274	goto err2;
	275	}
	276
d2136bce	277	if (cpu_is_omap44xx())
b9f5fe64	278	ret = omap4plus_init_static_deps(omap4_static_dep_map);
d2136bce	279	else if (soc_is_omap54xx() \|\| soc_is_dra7xx())
b9f5fe64	280	ret = omap4plus_init_static_deps(omap5_dra7_static_dep_map);
d2136bce SS	281
	282	if (ret) {
	283	pr_err("Failed to initialise static dependencies.\n");
	284	goto err2;
705814b5 SS	285	}
705814b5 SS	286
b2b9762f SS	287	ret = omap4_mpuss_init();
	288	if (ret) {
	289	pr_err("Failed to initialise OMAP4 MPUSS\n");
	290	goto err2;
	291	}
	292
92206fd2	293	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
3c50729b	294
2e4b62dc	295	omap_common_suspend_init(omap4_pm_suspend);
5643aebb	296
ae940913	297	/* Overwrite the default cpu_do_idle() */
0bcd24b0	298	arm_pm_idle = omap_default_idle;
72826b9f	299
7abdb0e2	300	if (cpu_is_omap44xx() \|\| soc_is_omap54xx())
705814b5	301	omap4_idle_init();
98272660	302
5643aebb RN	303	err2:
	304	return ret;
	305	}