[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / powerdomains34xx.h

/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 *
 * Written by Paul Walmsley
 * Debugging and integration fixes by Jouni Högander
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX

/*
 * N.B. If powerdomains are added or removed from this file, update
 * the array in mach-omap2/powerdomains.h.
 */

#include <plat/powerdomain.h>

#include "prcm-common.h"
#include "prm.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

#ifdef CONFIG_ARCH_OMAP3

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,
		[1] = PWRDM_POWER_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRDM_POWER_ON,
	},
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
};

static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
					   CHIP_IS_OMAP3430ES2 |
					   CHIP_IS_OMAP3430ES3_0),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};


#endif    /* CONFIG_ARCH_OMAP3 */


#endif
Commit	Line	Data
ecb24aa1	1	/*
98fa3d8a	2	* OMAP3 powerdomain definitions
ecb24aa1 PW	3	*
ecb24aa1 PW	4	* Copyright (C) 2007-2008 Texas Instruments, Inc.
98fa3d8a	5	* Copyright (C) 2007-2010 Nokia Corporation
ecb24aa1 PW	6	*
	7	* Written by Paul Walmsley
	8	* Debugging and integration fixes by Jouni Högander
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
	16	#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
	17
	18	/*
	19	* N.B. If powerdomains are added or removed from this file, update
	20	* the array in mach-omap2/powerdomains.h.
	21	*/
	22
ce491cf8	23	#include <plat/powerdomain.h>
ecb24aa1 PW	24
	25	#include "prcm-common.h"
	26	#include "prm.h"
	27	#include "prm-regbits-34xx.h"
	28	#include "cm.h"
	29	#include "cm-regbits-34xx.h"
	30
	31	/*
	32	* 34XX-specific powerdomains, dependencies
	33	*/
	34
98fa3d8a	35	#ifdef CONFIG_ARCH_OMAP3
ecb24aa1	36
ecb24aa1 PW	37	/*
	38	* Powerdomains
	39	*/
	40
	41	static struct powerdomain iva2_pwrdm = {
	42	.name = "iva2_pwrdm",
	43	.prcm_offs = OMAP3430_IVA2_MOD,
	44	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	45	.pwrsts = PWRSTS_OFF_RET_ON,
	46	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	47	.banks = 4,
	48	.pwrsts_mem_ret = {
	49	[0] = PWRSTS_OFF_RET,
	50	[1] = PWRSTS_OFF_RET,
	51	[2] = PWRSTS_OFF_RET,
	52	[3] = PWRSTS_OFF_RET,
	53	},
	54	.pwrsts_mem_on = {
	55	[0] = PWRDM_POWER_ON,
	56	[1] = PWRDM_POWER_ON,
	57	[2] = PWRSTS_OFF_ON,
	58	[3] = PWRDM_POWER_ON,
	59	},
	60	};
	61
98fa3d8a	62	static struct powerdomain mpu_3xxx_pwrdm = {
ecb24aa1 PW	63	.name = "mpu_pwrdm",
	64	.prcm_offs = MPU_MOD,
	65	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	66	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	67	.pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b	68	.flags = PWRDM_HAS_MPU_QUIRK,
ecb24aa1 PW	69	.banks = 1,
	70	.pwrsts_mem_ret = {
	71	[0] = PWRSTS_OFF_RET,
	72	},
	73	.pwrsts_mem_on = {
	74	[0] = PWRSTS_OFF_ON,
	75	},
	76	};
	77
98fa3d8a	78	static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
ecb24aa1 PW	79	.name = "core_pwrdm",
ecb24aa1 PW	80	.prcm_offs = CORE_MOD,
7eb1afc9 PW	81	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 \|
	82	CHIP_IS_OMAP3430ES2 \|
	83	CHIP_IS_OMAP3430ES3_0),
	84	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	85	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9 PW	86	.banks = 2,
	87	.pwrsts_mem_ret = {
	88	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	89	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	90	},
	91	.pwrsts_mem_on = {
	92	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	93	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	94	},
	95	};
	96
98fa3d8a	97	static struct powerdomain core_3xxx_es3_1_pwrdm = {
7eb1afc9 PW	98	.name = "core_pwrdm",
	99	.prcm_offs = CORE_MOD,
	100	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
ecb24aa1	101	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	102	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9	103	.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
ecb24aa1 PW	104	.banks = 2,
	105	.pwrsts_mem_ret = {
	106	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	107	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	108	},
	109	.pwrsts_mem_on = {
	110	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	111	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	112	},
	113	};
	114
ecb24aa1 PW	115	static struct powerdomain dss_pwrdm = {
	116	.name = "dss_pwrdm",
	117	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	118	.prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1 PW	119	.pwrsts = PWRSTS_OFF_RET_ON,
	120	.pwrsts_logic_ret = PWRDM_POWER_RET,
	121	.banks = 1,
	122	.pwrsts_mem_ret = {
	123	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	124	},
	125	.pwrsts_mem_on = {
	126	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	127	},
	128	};
	129
be48ea74 PW	130	/*
	131	* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
	132	* possible SGX powerstate, the SGX device itself does not support
	133	* retention.
	134	*/
ecb24aa1 PW	135	static struct powerdomain sgx_pwrdm = {
	136	.name = "sgx_pwrdm",
	137	.prcm_offs = OMAP3430ES2_SGX_MOD,
d41ad520	138	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
ecb24aa1	139	/* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74	140	.pwrsts = PWRSTS_OFF_ON,
ecb24aa1 PW	141	.pwrsts_logic_ret = PWRDM_POWER_RET,
	142	.banks = 1,
	143	.pwrsts_mem_ret = {
	144	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	145	},
	146	.pwrsts_mem_on = {
	147	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	148	},
	149	};
	150
	151	static struct powerdomain cam_pwrdm = {
	152	.name = "cam_pwrdm",
	153	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	154	.prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1 PW	155	.pwrsts = PWRSTS_OFF_RET_ON,
	156	.pwrsts_logic_ret = PWRDM_POWER_RET,
	157	.banks = 1,
	158	.pwrsts_mem_ret = {
	159	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	160	},
	161	.pwrsts_mem_on = {
	162	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	163	},
	164	};
	165
	166	static struct powerdomain per_pwrdm = {
	167	.name = "per_pwrdm",
	168	.prcm_offs = OMAP3430_PER_MOD,
	169	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	170	.pwrsts = PWRSTS_OFF_RET_ON,
	171	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	172	.banks = 1,
	173	.pwrsts_mem_ret = {
	174	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	175	},
	176	.pwrsts_mem_on = {
	177	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	178	},
	179	};
	180
	181	static struct powerdomain emu_pwrdm = {
	182	.name = "emu_pwrdm",
	183	.prcm_offs = OMAP3430_EMU_MOD,
	184	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	185	};
	186
	187	static struct powerdomain neon_pwrdm = {
	188	.name = "neon_pwrdm",
	189	.prcm_offs = OMAP3430_NEON_MOD,
	190	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	191	.pwrsts = PWRSTS_OFF_RET_ON,
	192	.pwrsts_logic_ret = PWRDM_POWER_RET,
	193	};
	194
	195	static struct powerdomain usbhost_pwrdm = {
	196	.name = "usbhost_pwrdm",
	197	.prcm_offs = OMAP3430ES2_USBHOST_MOD,
d41ad520	198	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
ecb24aa1 PW	199	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	200	.pwrsts_logic_ret = PWRDM_POWER_RET,
867d320b KJ	201	/*
	202	* REVISIT: Enabling usb host save and restore mechanism seems to
	203	* leave the usb host domain permanently in ACTIVE mode after
	204	* changing the usb host power domain state from OFF to active once.
	205	* Disabling for now.
	206	*/
	207	/.flags = PWRDM_HAS_HDWR_SAR,/ /* for USBHOST ctrlr only */
ecb24aa1 PW	208	.banks = 1,
	209	.pwrsts_mem_ret = {
	210	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	211	},
	212	.pwrsts_mem_on = {
	213	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	214	},
	215	};
	216
46e0ccf8 PW	217	static struct powerdomain dpll1_pwrdm = {
	218	.name = "dpll1_pwrdm",
	219	.prcm_offs = MPU_MOD,
	220	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	221	};
	222
	223	static struct powerdomain dpll2_pwrdm = {
	224	.name = "dpll2_pwrdm",
	225	.prcm_offs = OMAP3430_IVA2_MOD,
	226	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	227	};
	228
	229	static struct powerdomain dpll3_pwrdm = {
	230	.name = "dpll3_pwrdm",
	231	.prcm_offs = PLL_MOD,
	232	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	233	};
	234
	235	static struct powerdomain dpll4_pwrdm = {
	236	.name = "dpll4_pwrdm",
	237	.prcm_offs = PLL_MOD,
	238	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	239	};
	240
	241	static struct powerdomain dpll5_pwrdm = {
	242	.name = "dpll5_pwrdm",
	243	.prcm_offs = PLL_MOD,
d41ad520	244	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
46e0ccf8 PW	245	};
	246
	247
98fa3d8a	248	#endif /* CONFIG_ARCH_OMAP3 */
ecb24aa1 PW	249
	250
	251	#endif