[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / powerdomains3xxx_data.c

/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>

#include "soc.h"
#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
		[1] = PWRSTS_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_am35x_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

/*
 * The USBTLL Save-and-Restore mechanism is broken on
 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
 * needs to be disabled on these chips.
 * Refer: 3430 errata ID i459 and 3630 errata ID i579
 *
 * Note: setting the SAR flag could help for errata ID i478
 *  which applies to 3430 <= ES3.1, but since the SAR feature
 *  is broken, do not use it.
 */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	/*
	 * Setting the SAR flag for errata ID i478 which applies
	 *  to 3430 <= ES3.1
	 */
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_am35x_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,	 /* MEM1RETSTATE */
		[1] = PWRSTS_ON,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_am35x_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain sgx_am35x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_am35x_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain neon_am35x_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain alwon_81xx_pwrdm = {
	.name		  = "alwon_pwrdm",
	.prcm_offs	  = TI81XX_PRM_ALWON_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain device_81xx_pwrdm = {
	.name		  = "device_pwrdm",
	.prcm_offs	  = TI81XX_PRM_DEVICE_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain gem_814x_pwrdm = {
	.name		= "gem_pwrdm",
	.prcm_offs	= TI814X_PRM_DSP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "dsp" },
};

static struct powerdomain ivahd_814x_pwrdm = {
	.name		= "ivahd_pwrdm",
	.prcm_offs	= TI814X_PRM_HDVICP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "iva" },
};

static struct powerdomain hdvpss_814x_pwrdm = {
	.name		= "hdvpss_pwrdm",
	.prcm_offs	= TI814X_PRM_HDVPSS_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "dsp" },
};

static struct powerdomain sgx_814x_pwrdm = {
	.name		= "sgx_pwrdm",
	.prcm_offs	= TI814X_PRM_GFX_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "core" },
};

static struct powerdomain isp_814x_pwrdm = {
	.name		= "isp_pwrdm",
	.prcm_offs	= TI814X_PRM_ISP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "core" },
};

static struct powerdomain active_81xx_pwrdm = {
	.name		  = "active_pwrdm",
	.prcm_offs	  = TI816X_PRM_ACTIVE_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain default_81xx_pwrdm = {
	.name		  = "default_pwrdm",
	.prcm_offs	  = TI81XX_PRM_DEFAULT_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain ivahd0_816x_pwrdm = {
	.name		  = "ivahd0_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD0_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain ivahd1_816x_pwrdm = {
	.name		  = "ivahd1_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD1_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain ivahd2_816x_pwrdm = {
	.name		  = "ivahd2_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD2_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain sgx_816x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = TI816X_PRM_SGX_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
	&wkup_omap2_pwrdm,
	&iva2_pwrdm,
	&mpu_3xxx_pwrdm,
	&neon_pwrdm,
	&cam_pwrdm,
	&dss_pwrdm,
	&per_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll2_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	&gfx_omap2_pwrdm,
	&core_3xxx_pre_es3_1_pwrdm,
	NULL
};

/* also includes 3630ES1.0 */
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	&core_3xxx_pre_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

/* also includes 3630ES1.1+ */
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	&core_3xxx_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_am35x[] __initdata = {
	&wkup_omap2_pwrdm,
	&mpu_am35x_pwrdm,
	&neon_am35x_pwrdm,
	&core_am35x_pwrdm,
	&sgx_am35x_pwrdm,
	&dss_am35x_pwrdm,
	&per_am35x_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_ti814x[] __initdata = {
	&alwon_81xx_pwrdm,
	&device_81xx_pwrdm,
	&active_81xx_pwrdm,
	&default_81xx_pwrdm,
	&gem_814x_pwrdm,
	&ivahd_814x_pwrdm,
	&hdvpss_814x_pwrdm,
	&sgx_814x_pwrdm,
	&isp_814x_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_ti816x[] __initdata = {
	&alwon_81xx_pwrdm,
	&device_81xx_pwrdm,
	&active_81xx_pwrdm,
	&default_81xx_pwrdm,
	&ivahd0_816x_pwrdm,
	&ivahd1_816x_pwrdm,
	&ivahd2_816x_pwrdm,
	&sgx_816x_pwrdm,
	NULL
};

/* TI81XX specific ops */
#define TI81XX_PM_PWSTCTRL				0x0000
#define TI81XX_RM_RSTCTRL				0x0010
#define TI81XX_PM_PWSTST				0x0004

static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
				   (pwrst << OMAP_POWERSTATE_SHIFT),
				   pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
	return 0;
}

static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
					     TI81XX_PM_PWSTCTRL,
					     OMAP_POWERSTATE_MASK);
}

static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
					     TI81XX_PM_PWSTST,
					     OMAP_POWERSTATEST_MASK);
}

static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
					     TI81XX_PM_PWSTST,
					     OMAP3430_LOGICSTATEST_MASK);
}

static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
{
	u32 c = 0;

	while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
				       TI81XX_PM_PWSTST) &
		OMAP_INTRANSITION_MASK) &&
		(c++ < PWRDM_TRANSITION_BAILOUT))
			udelay(1);

	if (c > PWRDM_TRANSITION_BAILOUT) {
		pr_err("powerdomain: %s timeout waiting for transition\n",
		       pwrdm->name);
		return -EAGAIN;
	}

	pr_debug("powerdomain: completed transition in %d loops\n", c);

	return 0;
}

/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
static struct pwrdm_ops ti81xx_pwrdm_operations = {
	.pwrdm_set_next_pwrst	= ti81xx_pwrdm_set_next_pwrst,
	.pwrdm_read_next_pwrst	= ti81xx_pwrdm_read_next_pwrst,
	.pwrdm_read_pwrst	= ti81xx_pwrdm_read_pwrst,
	.pwrdm_read_logic_pwrst	= ti81xx_pwrdm_read_logic_pwrst,
	.pwrdm_wait_transition	= ti81xx_pwrdm_wait_transition,
};

void __init omap3xxx_powerdomains_init(void)
{
	unsigned int rev;

	if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
		return;

	/* Only 81xx needs custom pwrdm_operations */
	if (!cpu_is_ti81xx())
		pwrdm_register_platform_funcs(&omap3_pwrdm_operations);

	rev = omap_rev();

	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
		pwrdm_register_pwrdms(powerdomains_am35x);
	} else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 ||
		   rev == TI8148_REV_ES2_1) {
		pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
		pwrdm_register_pwrdms(powerdomains_ti814x);
	} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
			|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
		pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
		pwrdm_register_pwrdms(powerdomains_ti816x);
	} else {
		pwrdm_register_pwrdms(powerdomains_omap3430_common);

		switch (rev) {
		case OMAP3430_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es1);
			break;
		case OMAP3430_REV_ES2_0:
		case OMAP3430_REV_ES2_1:
		case OMAP3430_REV_ES3_0:
		case OMAP3630_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
			break;
		case OMAP3430_REV_ES3_1:
		case OMAP3430_REV_ES3_1_2:
		case OMAP3630_REV_ES1_1:
		case OMAP3630_REV_ES1_2:
			pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
			break;
		default:
			WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
		}
	}

	pwrdm_complete_init();
}
Commit	Line	Data
ecb24aa1	1	/*
98fa3d8a	2	* OMAP3 powerdomain definitions
ecb24aa1	3	*
8179488a	4	* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
4cb49fec	5	* Copyright (C) 2007-2011 Nokia Corporation
ecb24aa1	6	*
6e01478a	7	* Paul Walmsley, Jouni Högander
ecb24aa1 PW	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
6e01478a PW	14	#include <linux/kernel.h>
6e01478a PW	15	#include <linux/init.h>
d9a5f4dd	16	#include <linux/bug.h>
ecb24aa1	17
dbc04161	18	#include "soc.h"
72e06d08	19	#include "powerdomain.h"
6e01478a	20	#include "powerdomains2xxx_3xxx_data.h"
ecb24aa1	21	#include "prcm-common.h"
59fb659b	22	#include "prm2xxx_3xxx.h"
ecb24aa1	23	#include "prm-regbits-34xx.h"
59fb659b	24	#include "cm2xxx_3xxx.h"
ecb24aa1 PW	25	#include "cm-regbits-34xx.h"
	26
	27	/*
	28	* 34XX-specific powerdomains, dependencies
	29	*/
	30
ecb24aa1 PW	31	/*
	32	* Powerdomains
	33	*/
	34
	35	static struct powerdomain iva2_pwrdm = {
	36	.name = "iva2_pwrdm",
	37	.prcm_offs = OMAP3430_IVA2_MOD,
ecb24aa1 PW	38	.pwrsts = PWRSTS_OFF_RET_ON,
	39	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	40	.banks = 4,
	41	.pwrsts_mem_ret = {
	42	[0] = PWRSTS_OFF_RET,
	43	[1] = PWRSTS_OFF_RET,
	44	[2] = PWRSTS_OFF_RET,
	45	[3] = PWRSTS_OFF_RET,
	46	},
	47	.pwrsts_mem_on = {
4cb49fec PW	48	[0] = PWRSTS_ON,
4cb49fec PW	49	[1] = PWRSTS_ON,
ecb24aa1	50	[2] = PWRSTS_OFF_ON,
4cb49fec	51	[3] = PWRSTS_ON,
ecb24aa1	52	},
562e54d1	53	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	54	};
ecb24aa1 PW	55
98fa3d8a	56	static struct powerdomain mpu_3xxx_pwrdm = {
ecb24aa1 PW	57	.name = "mpu_pwrdm",
ecb24aa1 PW	58	.prcm_offs = MPU_MOD,
ecb24aa1 PW	59	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	60	.pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b	61	.flags = PWRDM_HAS_MPU_QUIRK,
ecb24aa1 PW	62	.banks = 1,
	63	.pwrsts_mem_ret = {
	64	[0] = PWRSTS_OFF_RET,
	65	},
	66	.pwrsts_mem_on = {
	67	[0] = PWRSTS_OFF_ON,
	68	},
562e54d1	69	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	70	};
ecb24aa1 PW	71
ff7ad7e4 MG	72	static struct powerdomain mpu_am35x_pwrdm = {
	73	.name = "mpu_pwrdm",
	74	.prcm_offs = MPU_MOD,
	75	.pwrsts = PWRSTS_ON,
	76	.pwrsts_logic_ret = PWRSTS_ON,
	77	.flags = PWRDM_HAS_MPU_QUIRK,
	78	.banks = 1,
	79	.pwrsts_mem_ret = {
	80	[0] = PWRSTS_ON,
	81	},
	82	.pwrsts_mem_on = {
	83	[0] = PWRSTS_ON,
	84	},
562e54d1	85	.voltdm = { .name = "mpu_iva" },
ff7ad7e4 MG	86	};
ff7ad7e4 MG	87
58dcfb3a AG	88	/*
58dcfb3a AG	89	* The USBTLL Save-and-Restore mechanism is broken on
25985edc	90	* 3430s up to ES3.0 and 3630ES1.0. Hence this feature
58dcfb3a AG	91	* needs to be disabled on these chips.
58dcfb3a AG	92	* Refer: 3430 errata ID i459 and 3630 errata ID i579
447b8da5 JP	93	*
	94	* Note: setting the SAR flag could help for errata ID i478
	95	* which applies to 3430 <= ES3.1, but since the SAR feature
	96	* is broken, do not use it.
58dcfb3a	97	*/
98fa3d8a	98	static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
ecb24aa1 PW	99	.name = "core_pwrdm",
ecb24aa1 PW	100	.prcm_offs = CORE_MOD,
7eb1afc9	101	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	102	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9 PW	103	.banks = 2,
	104	.pwrsts_mem_ret = {
	105	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	106	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	107	},
	108	.pwrsts_mem_on = {
	109	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	110	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	111	},
562e54d1	112	.voltdm = { .name = "core" },
7eb1afc9 PW	113	};
7eb1afc9 PW	114
98fa3d8a	115	static struct powerdomain core_3xxx_es3_1_pwrdm = {
7eb1afc9 PW	116	.name = "core_pwrdm",
7eb1afc9 PW	117	.prcm_offs = CORE_MOD,
ecb24aa1	118	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	119	.pwrsts_logic_ret = PWRSTS_OFF_RET,
447b8da5 JP	120	/*
	121	* Setting the SAR flag for errata ID i478 which applies
	122	* to 3430 <= ES3.1
	123	*/
7eb1afc9	124	.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
ecb24aa1 PW	125	.banks = 2,
	126	.pwrsts_mem_ret = {
	127	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	128	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	129	},
	130	.pwrsts_mem_on = {
	131	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	132	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	133	},
562e54d1	134	.voltdm = { .name = "core" },
ecb24aa1 PW	135	};
ecb24aa1 PW	136
ff7ad7e4 MG	137	static struct powerdomain core_am35x_pwrdm = {
	138	.name = "core_pwrdm",
	139	.prcm_offs = CORE_MOD,
	140	.pwrsts = PWRSTS_ON,
	141	.pwrsts_logic_ret = PWRSTS_ON,
	142	.banks = 2,
	143	.pwrsts_mem_ret = {
	144	[0] = PWRSTS_ON, /* MEM1RETSTATE */
	145	[1] = PWRSTS_ON, /* MEM2RETSTATE */
	146	},
	147	.pwrsts_mem_on = {
	148	[0] = PWRSTS_ON, /* MEM1ONSTATE */
	149	[1] = PWRSTS_ON, /* MEM2ONSTATE */
	150	},
562e54d1	151	.voltdm = { .name = "core" },
ff7ad7e4 MG	152	};
ff7ad7e4 MG	153
ecb24aa1 PW	154	static struct powerdomain dss_pwrdm = {
ecb24aa1 PW	155	.name = "dss_pwrdm",
ecb24aa1	156	.prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1	157	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	158	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	159	.banks = 1,
ecb24aa1 PW	160	.pwrsts_mem_ret = {
4cb49fec	161	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	162	},
ecb24aa1 PW	163	.pwrsts_mem_on = {
4cb49fec	164	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	165	},
562e54d1	166	.voltdm = { .name = "core" },
ecb24aa1 PW	167	};
ecb24aa1 PW	168
ff7ad7e4 MG	169	static struct powerdomain dss_am35x_pwrdm = {
	170	.name = "dss_pwrdm",
	171	.prcm_offs = OMAP3430_DSS_MOD,
	172	.pwrsts = PWRSTS_ON,
	173	.pwrsts_logic_ret = PWRSTS_ON,
	174	.banks = 1,
	175	.pwrsts_mem_ret = {
	176	[0] = PWRSTS_ON, /* MEMRETSTATE */
	177	},
	178	.pwrsts_mem_on = {
	179	[0] = PWRSTS_ON, /* MEMONSTATE */
	180	},
562e54d1	181	.voltdm = { .name = "core" },
ff7ad7e4 MG	182	};
ff7ad7e4 MG	183
be48ea74 PW	184	/*
	185	* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
	186	* possible SGX powerstate, the SGX device itself does not support
	187	* retention.
	188	*/
ecb24aa1 PW	189	static struct powerdomain sgx_pwrdm = {
	190	.name = "sgx_pwrdm",
	191	.prcm_offs = OMAP3430ES2_SGX_MOD,
ecb24aa1	192	/* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74	193	.pwrsts = PWRSTS_OFF_ON,
4cb49fec	194	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	195	.banks = 1,
ecb24aa1 PW	196	.pwrsts_mem_ret = {
4cb49fec	197	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	198	},
ecb24aa1 PW	199	.pwrsts_mem_on = {
4cb49fec	200	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	201	},
562e54d1	202	.voltdm = { .name = "core" },
ecb24aa1 PW	203	};
ecb24aa1 PW	204
ff7ad7e4 MG	205	static struct powerdomain sgx_am35x_pwrdm = {
	206	.name = "sgx_pwrdm",
	207	.prcm_offs = OMAP3430ES2_SGX_MOD,
	208	.pwrsts = PWRSTS_ON,
	209	.pwrsts_logic_ret = PWRSTS_ON,
	210	.banks = 1,
	211	.pwrsts_mem_ret = {
	212	[0] = PWRSTS_ON, /* MEMRETSTATE */
	213	},
	214	.pwrsts_mem_on = {
	215	[0] = PWRSTS_ON, /* MEMONSTATE */
	216	},
562e54d1	217	.voltdm = { .name = "core" },
ff7ad7e4 MG	218	};
ff7ad7e4 MG	219
ecb24aa1 PW	220	static struct powerdomain cam_pwrdm = {
ecb24aa1 PW	221	.name = "cam_pwrdm",
ecb24aa1	222	.prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1	223	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	224	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	225	.banks = 1,
ecb24aa1 PW	226	.pwrsts_mem_ret = {
4cb49fec	227	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	228	},
ecb24aa1 PW	229	.pwrsts_mem_on = {
4cb49fec	230	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	231	},
562e54d1	232	.voltdm = { .name = "core" },
ecb24aa1 PW	233	};
	234
	235	static struct powerdomain per_pwrdm = {
	236	.name = "per_pwrdm",
	237	.prcm_offs = OMAP3430_PER_MOD,
ecb24aa1 PW	238	.pwrsts = PWRSTS_OFF_RET_ON,
	239	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	240	.banks = 1,
	241	.pwrsts_mem_ret = {
4cb49fec	242	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	243	},
ecb24aa1 PW	244	.pwrsts_mem_on = {
4cb49fec	245	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	246	},
562e54d1	247	.voltdm = { .name = "core" },
ecb24aa1 PW	248	};
ecb24aa1 PW	249
ff7ad7e4 MG	250	static struct powerdomain per_am35x_pwrdm = {
	251	.name = "per_pwrdm",
	252	.prcm_offs = OMAP3430_PER_MOD,
	253	.pwrsts = PWRSTS_ON,
	254	.pwrsts_logic_ret = PWRSTS_ON,
	255	.banks = 1,
	256	.pwrsts_mem_ret = {
	257	[0] = PWRSTS_ON, /* MEMRETSTATE */
	258	},
	259	.pwrsts_mem_on = {
	260	[0] = PWRSTS_ON, /* MEMONSTATE */
	261	},
562e54d1	262	.voltdm = { .name = "core" },
ff7ad7e4 MG	263	};
ff7ad7e4 MG	264
ecb24aa1 PW	265	static struct powerdomain emu_pwrdm = {
	266	.name = "emu_pwrdm",
	267	.prcm_offs = OMAP3430_EMU_MOD,
562e54d1	268	.voltdm = { .name = "core" },
ecb24aa1 PW	269	};
	270
	271	static struct powerdomain neon_pwrdm = {
	272	.name = "neon_pwrdm",
	273	.prcm_offs = OMAP3430_NEON_MOD,
ecb24aa1	274	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	275	.pwrsts_logic_ret = PWRSTS_RET,
562e54d1	276	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	277	};
ecb24aa1 PW	278
ff7ad7e4 MG	279	static struct powerdomain neon_am35x_pwrdm = {
	280	.name = "neon_pwrdm",
	281	.prcm_offs = OMAP3430_NEON_MOD,
	282	.pwrsts = PWRSTS_ON,
	283	.pwrsts_logic_ret = PWRSTS_ON,
562e54d1	284	.voltdm = { .name = "mpu_iva" },
ff7ad7e4 MG	285	};
ff7ad7e4 MG	286
ecb24aa1 PW	287	static struct powerdomain usbhost_pwrdm = {
	288	.name = "usbhost_pwrdm",
	289	.prcm_offs = OMAP3430ES2_USBHOST_MOD,
ecb24aa1	290	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	291	.pwrsts_logic_ret = PWRSTS_RET,
867d320b KJ	292	/*
	293	* REVISIT: Enabling usb host save and restore mechanism seems to
	294	* leave the usb host domain permanently in ACTIVE mode after
	295	* changing the usb host power domain state from OFF to active once.
	296	* Disabling for now.
	297	*/
	298	/.flags = PWRDM_HAS_HDWR_SAR,/ /* for USBHOST ctrlr only */
ecb24aa1 PW	299	.banks = 1,
ecb24aa1 PW	300	.pwrsts_mem_ret = {
4cb49fec	301	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	302	},
ecb24aa1 PW	303	.pwrsts_mem_on = {
4cb49fec	304	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	305	},
562e54d1	306	.voltdm = { .name = "core" },
ecb24aa1 PW	307	};
ecb24aa1 PW	308
46e0ccf8 PW	309	static struct powerdomain dpll1_pwrdm = {
	310	.name = "dpll1_pwrdm",
	311	.prcm_offs = MPU_MOD,
562e54d1	312	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	313	};
	314
	315	static struct powerdomain dpll2_pwrdm = {
	316	.name = "dpll2_pwrdm",
	317	.prcm_offs = OMAP3430_IVA2_MOD,
562e54d1	318	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	319	};
	320
	321	static struct powerdomain dpll3_pwrdm = {
	322	.name = "dpll3_pwrdm",
	323	.prcm_offs = PLL_MOD,
562e54d1	324	.voltdm = { .name = "core" },
46e0ccf8 PW	325	};
	326
	327	static struct powerdomain dpll4_pwrdm = {
	328	.name = "dpll4_pwrdm",
	329	.prcm_offs = PLL_MOD,
562e54d1	330	.voltdm = { .name = "core" },
46e0ccf8 PW	331	};
	332
	333	static struct powerdomain dpll5_pwrdm = {
	334	.name = "dpll5_pwrdm",
	335	.prcm_offs = PLL_MOD,
562e54d1	336	.voltdm = { .name = "core" },
46e0ccf8 PW	337	};
46e0ccf8 PW	338
0f0dd089 AM	339	static struct powerdomain alwon_81xx_pwrdm = {
	340	.name = "alwon_pwrdm",
	341	.prcm_offs = TI81XX_PRM_ALWON_MOD,
	342	.pwrsts = PWRSTS_OFF_ON,
	343	.voltdm = { .name = "core" },
	344	};
	345
c3ed359c AM	346	static struct powerdomain device_81xx_pwrdm = {
	347	.name = "device_pwrdm",
	348	.prcm_offs = TI81XX_PRM_DEVICE_MOD,
	349	.voltdm = { .name = "core" },
	350	};
	351
7c80a3f8 TL	352	static struct powerdomain gem_814x_pwrdm = {
	353	.name = "gem_pwrdm",
	354	.prcm_offs = TI814X_PRM_DSP_MOD,
	355	.pwrsts = PWRSTS_OFF_ON,
	356	.voltdm = { .name = "dsp" },
	357	};
	358
	359	static struct powerdomain ivahd_814x_pwrdm = {
	360	.name = "ivahd_pwrdm",
	361	.prcm_offs = TI814X_PRM_HDVICP_MOD,
	362	.pwrsts = PWRSTS_OFF_ON,
	363	.voltdm = { .name = "iva" },
	364	};
	365
	366	static struct powerdomain hdvpss_814x_pwrdm = {
	367	.name = "hdvpss_pwrdm",
	368	.prcm_offs = TI814X_PRM_HDVPSS_MOD,
	369	.pwrsts = PWRSTS_OFF_ON,
	370	.voltdm = { .name = "dsp" },
	371	};
	372
	373	static struct powerdomain sgx_814x_pwrdm = {
	374	.name = "sgx_pwrdm",
	375	.prcm_offs = TI814X_PRM_GFX_MOD,
	376	.pwrsts = PWRSTS_OFF_ON,
	377	.voltdm = { .name = "core" },
	378	};
	379
	380	static struct powerdomain isp_814x_pwrdm = {
	381	.name = "isp_pwrdm",
	382	.prcm_offs = TI814X_PRM_ISP_MOD,
	383	.pwrsts = PWRSTS_OFF_ON,
	384	.voltdm = { .name = "core" },
	385	};
	386
418d4ebc	387	static struct powerdomain active_81xx_pwrdm = {
c3ed359c AM	388	.name = "active_pwrdm",
	389	.prcm_offs = TI816X_PRM_ACTIVE_MOD,
	390	.pwrsts = PWRSTS_OFF_ON,
	391	.voltdm = { .name = "core" },
	392	};
	393
418d4ebc	394	static struct powerdomain default_81xx_pwrdm = {
c3ed359c AM	395	.name = "default_pwrdm",
	396	.prcm_offs = TI81XX_PRM_DEFAULT_MOD,
	397	.pwrsts = PWRSTS_OFF_ON,
	398	.voltdm = { .name = "core" },
	399	};
	400
	401	static struct powerdomain ivahd0_816x_pwrdm = {
	402	.name = "ivahd0_pwrdm",
	403	.prcm_offs = TI816X_PRM_IVAHD0_MOD,
	404	.pwrsts = PWRSTS_OFF_ON,
	405	.voltdm = { .name = "mpu_iva" },
	406	};
	407
	408	static struct powerdomain ivahd1_816x_pwrdm = {
	409	.name = "ivahd1_pwrdm",
	410	.prcm_offs = TI816X_PRM_IVAHD1_MOD,
	411	.pwrsts = PWRSTS_OFF_ON,
	412	.voltdm = { .name = "mpu_iva" },
	413	};
	414
	415	static struct powerdomain ivahd2_816x_pwrdm = {
	416	.name = "ivahd2_pwrdm",
	417	.prcm_offs = TI816X_PRM_IVAHD2_MOD,
	418	.pwrsts = PWRSTS_OFF_ON,
	419	.voltdm = { .name = "mpu_iva" },
	420	};
	421
	422	static struct powerdomain sgx_816x_pwrdm = {
	423	.name = "sgx_pwrdm",
	424	.prcm_offs = TI816X_PRM_SGX_MOD,
	425	.pwrsts = PWRSTS_OFF_ON,
	426	.voltdm = { .name = "core" },
	427	};
	428
6e01478a	429	/* As powerdomains are added or removed above, this list must also be changed */
8179488a	430	static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
6e01478a	431	&wkup_omap2_pwrdm,
6e01478a PW	432	&iva2_pwrdm,
	433	&mpu_3xxx_pwrdm,
	434	&neon_pwrdm,
6e01478a PW	435	&cam_pwrdm,
	436	&dss_pwrdm,
	437	&per_pwrdm,
	438	&emu_pwrdm,
6e01478a PW	439	&dpll1_pwrdm,
	440	&dpll2_pwrdm,
	441	&dpll3_pwrdm,
	442	&dpll4_pwrdm,
8179488a PW	443	NULL
	444	};
	445
	446	static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	447	&gfx_omap2_pwrdm,
	448	&core_3xxx_pre_es3_1_pwrdm,
	449	NULL
	450	};
	451
	452	/* also includes 3630ES1.0 */
	453	static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	454	&core_3xxx_pre_es3_1_pwrdm,
	455	&sgx_pwrdm,
	456	&usbhost_pwrdm,
6e01478a	457	&dpll5_pwrdm,
6e01478a PW	458	NULL
6e01478a PW	459	};
ecb24aa1	460
8179488a PW	461	/* also includes 3630ES1.1+ */
	462	static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	463	&core_3xxx_es3_1_pwrdm,
	464	&sgx_pwrdm,
	465	&usbhost_pwrdm,
	466	&dpll5_pwrdm,
	467	NULL
	468	};
ecb24aa1	469
ff7ad7e4 MG	470	static struct powerdomain *powerdomains_am35x[] __initdata = {
	471	&wkup_omap2_pwrdm,
	472	&mpu_am35x_pwrdm,
	473	&neon_am35x_pwrdm,
	474	&core_am35x_pwrdm,
	475	&sgx_am35x_pwrdm,
	476	&dss_am35x_pwrdm,
	477	&per_am35x_pwrdm,
	478	&emu_pwrdm,
	479	&dpll1_pwrdm,
	480	&dpll3_pwrdm,
	481	&dpll4_pwrdm,
	482	&dpll5_pwrdm,
	483	NULL
	484	};
	485
7c80a3f8 TL	486	static struct powerdomain *powerdomains_ti814x[] __initdata = {
	487	&alwon_81xx_pwrdm,
	488	&device_81xx_pwrdm,
418d4ebc TL	489	&active_81xx_pwrdm,
418d4ebc TL	490	&default_81xx_pwrdm,
7c80a3f8 TL	491	&gem_814x_pwrdm,
	492	&ivahd_814x_pwrdm,
	493	&hdvpss_814x_pwrdm,
	494	&sgx_814x_pwrdm,
	495	&isp_814x_pwrdm,
	496	NULL
	497	};
	498
	499	static struct powerdomain *powerdomains_ti816x[] __initdata = {
0f0dd089	500	&alwon_81xx_pwrdm,
c3ed359c	501	&device_81xx_pwrdm,
418d4ebc TL	502	&active_81xx_pwrdm,
418d4ebc TL	503	&default_81xx_pwrdm,
c3ed359c AM	504	&ivahd0_816x_pwrdm,
	505	&ivahd1_816x_pwrdm,
	506	&ivahd2_816x_pwrdm,
	507	&sgx_816x_pwrdm,
	508	NULL
	509	};
	510
7c80a3f8 TL	511	/* TI81XX specific ops */
	512	#define TI81XX_PM_PWSTCTRL 0x0000
	513	#define TI81XX_RM_RSTCTRL 0x0010
	514	#define TI81XX_PM_PWSTST 0x0004
	515
	516	static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
	517	{
	518	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
	519	(pwrst << OMAP_POWERSTATE_SHIFT),
	520	pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
	521	return 0;
	522	}
	523
	524	static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
	525	{
	526	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
	527	TI81XX_PM_PWSTCTRL,
	528	OMAP_POWERSTATE_MASK);
	529	}
	530
	531	static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
	532	{
	533	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
	534	(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
	535	TI81XX_PM_PWSTST,
	536	OMAP_POWERSTATEST_MASK);
	537	}
	538
	539	static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
	540	{
	541	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
	542	(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
	543	TI81XX_PM_PWSTST,
	544	OMAP3430_LOGICSTATEST_MASK);
	545	}
	546
	547	static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
	548	{
	549	u32 c = 0;
	550
	551	while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
	552	(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
	553	TI81XX_PM_PWSTST) &
	554	OMAP_INTRANSITION_MASK) &&
	555	(c++ < PWRDM_TRANSITION_BAILOUT))
	556	udelay(1);
	557
	558	if (c > PWRDM_TRANSITION_BAILOUT) {
	559	pr_err("powerdomain: %s timeout waiting for transition\n",
	560	pwrdm->name);
	561	return -EAGAIN;
	562	}
	563
	564	pr_debug("powerdomain: completed transition in %d loops\n", c);
	565
	566	return 0;
	567	}
	568
	569	/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
	570	static struct pwrdm_ops ti81xx_pwrdm_operations = {
	571	.pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
	572	.pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
	573	.pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
	574	.pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
575	.pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
576	};
577
6e01478a PW	578	void __init omap3xxx_powerdomains_init(void)
6e01478a PW	579	{
8179488a PW	580	unsigned int rev;
8179488a PW	581
c27964b5	582	if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
8179488a PW	583	return;
8179488a PW	584
9610c8ab TL	585	/* Only 81xx needs custom pwrdm_operations */
9610c8ab TL	586	if (!cpu_is_ti81xx())
ae428a72	587	pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
8179488a PW	588
	589	rev = omap_rev();
	590
ff7ad7e4 MG	591	if (rev == AM35XX_REV_ES1_0 \|\| rev == AM35XX_REV_ES1_1) {
ff7ad7e4 MG	592	pwrdm_register_pwrdms(powerdomains_am35x);
7c80a3f8 TL	593	} else if (rev == TI8148_REV_ES1_0 \|\| rev == TI8148_REV_ES2_0 \|\|
7c80a3f8 TL	594	rev == TI8148_REV_ES2_1) {
9610c8ab	595	pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
7c80a3f8	596	pwrdm_register_pwrdms(powerdomains_ti814x);
c3ed359c AM	597	} else if (rev == TI8168_REV_ES1_0 \|\| rev == TI8168_REV_ES1_1
c3ed359c AM	598	\|\| rev == TI8168_REV_ES2_0 \|\| rev == TI8168_REV_ES2_1) {
9610c8ab	599	pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
7c80a3f8	600	pwrdm_register_pwrdms(powerdomains_ti816x);
ff7ad7e4 MG	601	} else {
	602	pwrdm_register_pwrdms(powerdomains_omap3430_common);
	603
	604	switch (rev) {
	605	case OMAP3430_REV_ES1_0:
	606	pwrdm_register_pwrdms(powerdomains_omap3430es1);
	607	break;
	608	case OMAP3430_REV_ES2_0:
	609	case OMAP3430_REV_ES2_1:
	610	case OMAP3430_REV_ES3_0:
	611	case OMAP3630_REV_ES1_0:
	612	pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
	613	break;
	614	case OMAP3430_REV_ES3_1:
	615	case OMAP3430_REV_ES3_1_2:
	616	case OMAP3630_REV_ES1_1:
	617	case OMAP3630_REV_ES1_2:
	618	pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
	619	break;
	620	default:
	621	WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
	622	}
	623	}
8179488a	624
129c65ee	625	pwrdm_complete_init();
6e01478a	626	}