[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / powerdomains3xxx_data.c

/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include <plat/powerdomain.h>
#include "powerdomains2xxx_3xxx_data.h"
#include "powerdomains.h"

#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

#ifdef CONFIG_ARCH_OMAP3

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,
		[1] = PWRDM_POWER_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRDM_POWER_ON,
	},
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
};

/*
 * The USBTLL Save-and-Restore mechanism is broken on
 * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
 * needs to be disabled on these chips.
 * Refer: 3430 errata ID i459 and 3630 errata ID i579
 *
 * Note: setting the SAR flag could help for errata ID i478
 *  which applies to 3430 <= ES3.1, but since the SAR feature
 *  is broken, do not use it.
 */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
					   CHIP_IS_OMAP3430ES2 |
					   CHIP_IS_OMAP3430ES3_0 |
					   CHIP_IS_OMAP3630ES1),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
					  CHIP_GE_OMAP3630ES1_1),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	/*
	 * Setting the SAR flag for errata ID i478 which applies
	 *  to 3430 <= ES3.1
	 */
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap3xxx[] __initdata = {

	&wkup_omap2_pwrdm,
	&gfx_omap2_pwrdm,
	&iva2_pwrdm,
	&mpu_3xxx_pwrdm,
	&neon_pwrdm,
	&core_3xxx_pre_es3_1_pwrdm,
	&core_3xxx_es3_1_pwrdm,
	&cam_pwrdm,
	&dss_pwrdm,
	&per_pwrdm,
	&emu_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll1_pwrdm,
	&dpll2_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	&dpll5_pwrdm,
#endif
	NULL
};


void __init omap3xxx_powerdomains_init(void)
{
	pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
}
Commit	Line	Data
ecb24aa1	1	/*
98fa3d8a	2	* OMAP3 powerdomain definitions
ecb24aa1 PW	3	*
ecb24aa1 PW	4	* Copyright (C) 2007-2008 Texas Instruments, Inc.
98fa3d8a	5	* Copyright (C) 2007-2010 Nokia Corporation
ecb24aa1	6	*
6e01478a	7	* Paul Walmsley, Jouni Högander
ecb24aa1 PW	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
6e01478a PW	14	#include <linux/kernel.h>
6e01478a PW	15	#include <linux/init.h>
ecb24aa1	16
ce491cf8	17	#include <plat/powerdomain.h>
6e01478a PW	18	#include "powerdomains2xxx_3xxx_data.h"
6e01478a PW	19	#include "powerdomains.h"
ecb24aa1 PW	20
ecb24aa1 PW	21	#include "prcm-common.h"
59fb659b	22	#include "prm2xxx_3xxx.h"
ecb24aa1	23	#include "prm-regbits-34xx.h"
59fb659b	24	#include "cm2xxx_3xxx.h"
ecb24aa1 PW	25	#include "cm-regbits-34xx.h"
	26
	27	/*
	28	* 34XX-specific powerdomains, dependencies
	29	*/
	30
98fa3d8a	31	#ifdef CONFIG_ARCH_OMAP3
ecb24aa1	32
ecb24aa1 PW	33	/*
	34	* Powerdomains
	35	*/
	36
	37	static struct powerdomain iva2_pwrdm = {
	38	.name = "iva2_pwrdm",
	39	.prcm_offs = OMAP3430_IVA2_MOD,
	40	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	41	.pwrsts = PWRSTS_OFF_RET_ON,
	42	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	43	.banks = 4,
	44	.pwrsts_mem_ret = {
	45	[0] = PWRSTS_OFF_RET,
	46	[1] = PWRSTS_OFF_RET,
	47	[2] = PWRSTS_OFF_RET,
	48	[3] = PWRSTS_OFF_RET,
	49	},
	50	.pwrsts_mem_on = {
	51	[0] = PWRDM_POWER_ON,
	52	[1] = PWRDM_POWER_ON,
	53	[2] = PWRSTS_OFF_ON,
	54	[3] = PWRDM_POWER_ON,
	55	},
	56	};
	57
98fa3d8a	58	static struct powerdomain mpu_3xxx_pwrdm = {
ecb24aa1 PW	59	.name = "mpu_pwrdm",
	60	.prcm_offs = MPU_MOD,
	61	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	62	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	63	.pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b	64	.flags = PWRDM_HAS_MPU_QUIRK,
ecb24aa1 PW	65	.banks = 1,
	66	.pwrsts_mem_ret = {
	67	[0] = PWRSTS_OFF_RET,
	68	},
	69	.pwrsts_mem_on = {
	70	[0] = PWRSTS_OFF_ON,
	71	},
	72	};
	73
58dcfb3a AG	74	/*
	75	* The USBTLL Save-and-Restore mechanism is broken on
	76	* 3430s upto ES3.0 and 3630ES1.0. Hence this feature
	77	* needs to be disabled on these chips.
	78	* Refer: 3430 errata ID i459 and 3630 errata ID i579
447b8da5 JP	79	*
	80	* Note: setting the SAR flag could help for errata ID i478
	81	* which applies to 3430 <= ES3.1, but since the SAR feature
	82	* is broken, do not use it.
58dcfb3a	83	*/
98fa3d8a	84	static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
ecb24aa1 PW	85	.name = "core_pwrdm",
ecb24aa1 PW	86	.prcm_offs = CORE_MOD,
7eb1afc9 PW	87	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 \|
7eb1afc9 PW	88	CHIP_IS_OMAP3430ES2 \|
58dcfb3a AG	89	CHIP_IS_OMAP3430ES3_0 \|
58dcfb3a AG	90	CHIP_IS_OMAP3630ES1),
7eb1afc9	91	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	92	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9 PW	93	.banks = 2,
	94	.pwrsts_mem_ret = {
	95	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	96	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	97	},
	98	.pwrsts_mem_on = {
	99	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	100	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	101	},
	102	};
	103
98fa3d8a	104	static struct powerdomain core_3xxx_es3_1_pwrdm = {
7eb1afc9 PW	105	.name = "core_pwrdm",
7eb1afc9 PW	106	.prcm_offs = CORE_MOD,
58dcfb3a AG	107	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 \|
58dcfb3a AG	108	CHIP_GE_OMAP3630ES1_1),
ecb24aa1	109	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	110	.pwrsts_logic_ret = PWRSTS_OFF_RET,
447b8da5 JP	111	/*
	112	* Setting the SAR flag for errata ID i478 which applies
	113	* to 3430 <= ES3.1
	114	*/
7eb1afc9	115	.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
ecb24aa1 PW	116	.banks = 2,
	117	.pwrsts_mem_ret = {
	118	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	119	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	120	},
	121	.pwrsts_mem_on = {
	122	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	123	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	124	},
	125	};
	126
ecb24aa1 PW	127	static struct powerdomain dss_pwrdm = {
	128	.name = "dss_pwrdm",
	129	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	130	.prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1 PW	131	.pwrsts = PWRSTS_OFF_RET_ON,
	132	.pwrsts_logic_ret = PWRDM_POWER_RET,
	133	.banks = 1,
	134	.pwrsts_mem_ret = {
	135	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	136	},
	137	.pwrsts_mem_on = {
	138	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	139	},
	140	};
	141
be48ea74 PW	142	/*
	143	* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
	144	* possible SGX powerstate, the SGX device itself does not support
	145	* retention.
	146	*/
ecb24aa1 PW	147	static struct powerdomain sgx_pwrdm = {
	148	.name = "sgx_pwrdm",
	149	.prcm_offs = OMAP3430ES2_SGX_MOD,
d41ad520	150	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
ecb24aa1	151	/* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74	152	.pwrsts = PWRSTS_OFF_ON,
ecb24aa1 PW	153	.pwrsts_logic_ret = PWRDM_POWER_RET,
	154	.banks = 1,
	155	.pwrsts_mem_ret = {
	156	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	157	},
	158	.pwrsts_mem_on = {
	159	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	160	},
	161	};
	162
	163	static struct powerdomain cam_pwrdm = {
	164	.name = "cam_pwrdm",
	165	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	166	.prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1 PW	167	.pwrsts = PWRSTS_OFF_RET_ON,
	168	.pwrsts_logic_ret = PWRDM_POWER_RET,
	169	.banks = 1,
	170	.pwrsts_mem_ret = {
	171	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	172	},
	173	.pwrsts_mem_on = {
	174	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	175	},
	176	};
	177
	178	static struct powerdomain per_pwrdm = {
	179	.name = "per_pwrdm",
	180	.prcm_offs = OMAP3430_PER_MOD,
	181	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	182	.pwrsts = PWRSTS_OFF_RET_ON,
	183	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	184	.banks = 1,
	185	.pwrsts_mem_ret = {
	186	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	187	},
	188	.pwrsts_mem_on = {
	189	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	190	},
	191	};
	192
	193	static struct powerdomain emu_pwrdm = {
	194	.name = "emu_pwrdm",
	195	.prcm_offs = OMAP3430_EMU_MOD,
	196	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	197	};
	198
	199	static struct powerdomain neon_pwrdm = {
	200	.name = "neon_pwrdm",
	201	.prcm_offs = OMAP3430_NEON_MOD,
	202	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	203	.pwrsts = PWRSTS_OFF_RET_ON,
	204	.pwrsts_logic_ret = PWRDM_POWER_RET,
	205	};
	206
	207	static struct powerdomain usbhost_pwrdm = {
	208	.name = "usbhost_pwrdm",
	209	.prcm_offs = OMAP3430ES2_USBHOST_MOD,
d41ad520	210	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
ecb24aa1 PW	211	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	212	.pwrsts_logic_ret = PWRDM_POWER_RET,
867d320b KJ	213	/*
	214	* REVISIT: Enabling usb host save and restore mechanism seems to
	215	* leave the usb host domain permanently in ACTIVE mode after
	216	* changing the usb host power domain state from OFF to active once.
	217	* Disabling for now.
	218	*/
	219	/.flags = PWRDM_HAS_HDWR_SAR,/ /* for USBHOST ctrlr only */
ecb24aa1 PW	220	.banks = 1,
	221	.pwrsts_mem_ret = {
	222	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	223	},
	224	.pwrsts_mem_on = {
	225	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	226	},
	227	};
	228
46e0ccf8 PW	229	static struct powerdomain dpll1_pwrdm = {
	230	.name = "dpll1_pwrdm",
	231	.prcm_offs = MPU_MOD,
	232	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	233	};
	234
	235	static struct powerdomain dpll2_pwrdm = {
	236	.name = "dpll2_pwrdm",
	237	.prcm_offs = OMAP3430_IVA2_MOD,
	238	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	239	};
	240
	241	static struct powerdomain dpll3_pwrdm = {
	242	.name = "dpll3_pwrdm",
	243	.prcm_offs = PLL_MOD,
	244	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	245	};
	246
	247	static struct powerdomain dpll4_pwrdm = {
	248	.name = "dpll4_pwrdm",
	249	.prcm_offs = PLL_MOD,
	250	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	251	};
	252
	253	static struct powerdomain dpll5_pwrdm = {
	254	.name = "dpll5_pwrdm",
	255	.prcm_offs = PLL_MOD,
d41ad520	256	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
46e0ccf8 PW	257	};
46e0ccf8 PW	258
6e01478a PW	259	/* As powerdomains are added or removed above, this list must also be changed */
6e01478a PW	260	static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
46e0ccf8	261
6e01478a PW	262	&wkup_omap2_pwrdm,
	263	&gfx_omap2_pwrdm,
	264	&iva2_pwrdm,
	265	&mpu_3xxx_pwrdm,
	266	&neon_pwrdm,
	267	&core_3xxx_pre_es3_1_pwrdm,
	268	&core_3xxx_es3_1_pwrdm,
	269	&cam_pwrdm,
	270	&dss_pwrdm,
	271	&per_pwrdm,
	272	&emu_pwrdm,
	273	&sgx_pwrdm,
	274	&usbhost_pwrdm,
	275	&dpll1_pwrdm,
	276	&dpll2_pwrdm,
	277	&dpll3_pwrdm,
	278	&dpll4_pwrdm,
	279	&dpll5_pwrdm,
	280	#endif
	281	NULL
	282	};
ecb24aa1 PW	283
ecb24aa1 PW	284
6e01478a PW	285	void __init omap3xxx_powerdomains_init(void)
	286	{
	287	pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
	288	}