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[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / powerdomains3xxx_data.c
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ecb24aa1 1/*
98fa3d8a 2 * OMAP3 powerdomain definitions
ecb24aa1 3 *
8179488a 4 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
4cb49fec 5 * Copyright (C) 2007-2011 Nokia Corporation
ecb24aa1 6 *
6e01478a 7 * Paul Walmsley, Jouni Högander
ecb24aa1
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8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
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14#include <linux/kernel.h>
15#include <linux/init.h>
ecb24aa1 16
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17#include <plat/cpu.h>
18
72e06d08 19#include "powerdomain.h"
6e01478a 20#include "powerdomains2xxx_3xxx_data.h"
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21
22#include "prcm-common.h"
59fb659b 23#include "prm2xxx_3xxx.h"
ecb24aa1 24#include "prm-regbits-34xx.h"
59fb659b 25#include "cm2xxx_3xxx.h"
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26#include "cm-regbits-34xx.h"
27
28/*
29 * 34XX-specific powerdomains, dependencies
30 */
31
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32/*
33 * Powerdomains
34 */
35
36static struct powerdomain iva2_pwrdm = {
37 .name = "iva2_pwrdm",
38 .prcm_offs = OMAP3430_IVA2_MOD,
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39 .pwrsts = PWRSTS_OFF_RET_ON,
40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
41 .banks = 4,
42 .pwrsts_mem_ret = {
43 [0] = PWRSTS_OFF_RET,
44 [1] = PWRSTS_OFF_RET,
45 [2] = PWRSTS_OFF_RET,
46 [3] = PWRSTS_OFF_RET,
47 },
48 .pwrsts_mem_on = {
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49 [0] = PWRSTS_ON,
50 [1] = PWRSTS_ON,
ecb24aa1 51 [2] = PWRSTS_OFF_ON,
4cb49fec 52 [3] = PWRSTS_ON,
ecb24aa1 53 },
da03ce65 54 .voltdm = { .name = "mpu_iva" },
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55};
56
98fa3d8a 57static struct powerdomain mpu_3xxx_pwrdm = {
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58 .name = "mpu_pwrdm",
59 .prcm_offs = MPU_MOD,
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60 .pwrsts = PWRSTS_OFF_RET_ON,
61 .pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b 62 .flags = PWRDM_HAS_MPU_QUIRK,
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63 .banks = 1,
64 .pwrsts_mem_ret = {
65 [0] = PWRSTS_OFF_RET,
66 },
67 .pwrsts_mem_on = {
68 [0] = PWRSTS_OFF_ON,
69 },
da03ce65 70 .voltdm = { .name = "mpu_iva" },
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71};
72
58dcfb3a
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73/*
74 * The USBTLL Save-and-Restore mechanism is broken on
25985edc 75 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
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76 * needs to be disabled on these chips.
77 * Refer: 3430 errata ID i459 and 3630 errata ID i579
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78 *
79 * Note: setting the SAR flag could help for errata ID i478
80 * which applies to 3430 <= ES3.1, but since the SAR feature
81 * is broken, do not use it.
58dcfb3a 82 */
98fa3d8a 83static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
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84 .name = "core_pwrdm",
85 .prcm_offs = CORE_MOD,
7eb1afc9 86 .pwrsts = PWRSTS_OFF_RET_ON,
4133a44e 87 .pwrsts_logic_ret = PWRSTS_OFF_RET,
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88 .banks = 2,
89 .pwrsts_mem_ret = {
90 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
91 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
92 },
93 .pwrsts_mem_on = {
94 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
95 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
96 },
da03ce65 97 .voltdm = { .name = "core" },
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98};
99
98fa3d8a 100static struct powerdomain core_3xxx_es3_1_pwrdm = {
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101 .name = "core_pwrdm",
102 .prcm_offs = CORE_MOD,
ecb24aa1 103 .pwrsts = PWRSTS_OFF_RET_ON,
4133a44e 104 .pwrsts_logic_ret = PWRSTS_OFF_RET,
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105 /*
106 * Setting the SAR flag for errata ID i478 which applies
107 * to 3430 <= ES3.1
108 */
7eb1afc9 109 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
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110 .banks = 2,
111 .pwrsts_mem_ret = {
112 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
113 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
114 },
115 .pwrsts_mem_on = {
116 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
117 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
118 },
da03ce65 119 .voltdm = { .name = "core" },
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120};
121
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122static struct powerdomain dss_pwrdm = {
123 .name = "dss_pwrdm",
ecb24aa1 124 .prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1 125 .pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec 126 .pwrsts_logic_ret = PWRSTS_RET,
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127 .banks = 1,
128 .pwrsts_mem_ret = {
4cb49fec 129 [0] = PWRSTS_RET, /* MEMRETSTATE */
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130 },
131 .pwrsts_mem_on = {
4cb49fec 132 [0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1 133 },
da03ce65 134 .voltdm = { .name = "core" },
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135};
136
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137/*
138 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
139 * possible SGX powerstate, the SGX device itself does not support
140 * retention.
141 */
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142static struct powerdomain sgx_pwrdm = {
143 .name = "sgx_pwrdm",
144 .prcm_offs = OMAP3430ES2_SGX_MOD,
ecb24aa1 145 /* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74 146 .pwrsts = PWRSTS_OFF_ON,
4cb49fec 147 .pwrsts_logic_ret = PWRSTS_RET,
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148 .banks = 1,
149 .pwrsts_mem_ret = {
4cb49fec 150 [0] = PWRSTS_RET, /* MEMRETSTATE */
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151 },
152 .pwrsts_mem_on = {
4cb49fec 153 [0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1 154 },
da03ce65 155 .voltdm = { .name = "core" },
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156};
157
158static struct powerdomain cam_pwrdm = {
159 .name = "cam_pwrdm",
ecb24aa1 160 .prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1 161 .pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec 162 .pwrsts_logic_ret = PWRSTS_RET,
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163 .banks = 1,
164 .pwrsts_mem_ret = {
4cb49fec 165 [0] = PWRSTS_RET, /* MEMRETSTATE */
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166 },
167 .pwrsts_mem_on = {
4cb49fec 168 [0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1 169 },
da03ce65 170 .voltdm = { .name = "core" },
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171};
172
173static struct powerdomain per_pwrdm = {
174 .name = "per_pwrdm",
175 .prcm_offs = OMAP3430_PER_MOD,
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176 .pwrsts = PWRSTS_OFF_RET_ON,
177 .pwrsts_logic_ret = PWRSTS_OFF_RET,
178 .banks = 1,
179 .pwrsts_mem_ret = {
4cb49fec 180 [0] = PWRSTS_RET, /* MEMRETSTATE */
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181 },
182 .pwrsts_mem_on = {
4cb49fec 183 [0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1 184 },
da03ce65 185 .voltdm = { .name = "core" },
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186};
187
188static struct powerdomain emu_pwrdm = {
189 .name = "emu_pwrdm",
190 .prcm_offs = OMAP3430_EMU_MOD,
da03ce65 191 .voltdm = { .name = "core" },
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192};
193
194static struct powerdomain neon_pwrdm = {
195 .name = "neon_pwrdm",
196 .prcm_offs = OMAP3430_NEON_MOD,
ecb24aa1 197 .pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec 198 .pwrsts_logic_ret = PWRSTS_RET,
da03ce65 199 .voltdm = { .name = "mpu_iva" },
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200};
201
202static struct powerdomain usbhost_pwrdm = {
203 .name = "usbhost_pwrdm",
204 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
ecb24aa1 205 .pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec 206 .pwrsts_logic_ret = PWRSTS_RET,
867d320b
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207 /*
208 * REVISIT: Enabling usb host save and restore mechanism seems to
209 * leave the usb host domain permanently in ACTIVE mode after
210 * changing the usb host power domain state from OFF to active once.
211 * Disabling for now.
212 */
213 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
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214 .banks = 1,
215 .pwrsts_mem_ret = {
4cb49fec 216 [0] = PWRSTS_RET, /* MEMRETSTATE */
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217 },
218 .pwrsts_mem_on = {
4cb49fec 219 [0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1 220 },
da03ce65 221 .voltdm = { .name = "core" },
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222};
223
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224static struct powerdomain dpll1_pwrdm = {
225 .name = "dpll1_pwrdm",
226 .prcm_offs = MPU_MOD,
da03ce65 227 .voltdm = { .name = "mpu_iva" },
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228};
229
230static struct powerdomain dpll2_pwrdm = {
231 .name = "dpll2_pwrdm",
232 .prcm_offs = OMAP3430_IVA2_MOD,
da03ce65 233 .voltdm = { .name = "mpu_iva" },
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234};
235
236static struct powerdomain dpll3_pwrdm = {
237 .name = "dpll3_pwrdm",
238 .prcm_offs = PLL_MOD,
da03ce65 239 .voltdm = { .name = "core" },
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240};
241
242static struct powerdomain dpll4_pwrdm = {
243 .name = "dpll4_pwrdm",
244 .prcm_offs = PLL_MOD,
da03ce65 245 .voltdm = { .name = "core" },
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246};
247
248static struct powerdomain dpll5_pwrdm = {
249 .name = "dpll5_pwrdm",
250 .prcm_offs = PLL_MOD,
da03ce65 251 .voltdm = { .name = "core" },
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252};
253
6e01478a 254/* As powerdomains are added or removed above, this list must also be changed */
8179488a 255static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
6e01478a 256 &wkup_omap2_pwrdm,
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257 &iva2_pwrdm,
258 &mpu_3xxx_pwrdm,
259 &neon_pwrdm,
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260 &cam_pwrdm,
261 &dss_pwrdm,
262 &per_pwrdm,
263 &emu_pwrdm,
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264 &dpll1_pwrdm,
265 &dpll2_pwrdm,
266 &dpll3_pwrdm,
267 &dpll4_pwrdm,
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268 NULL
269};
270
271static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
272 &gfx_omap2_pwrdm,
273 &core_3xxx_pre_es3_1_pwrdm,
274 NULL
275};
276
277/* also includes 3630ES1.0 */
278static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
279 &core_3xxx_pre_es3_1_pwrdm,
280 &sgx_pwrdm,
281 &usbhost_pwrdm,
6e01478a 282 &dpll5_pwrdm,
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283 NULL
284};
ecb24aa1 285
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286/* also includes 3630ES1.1+ */
287static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
288 &core_3xxx_es3_1_pwrdm,
289 &sgx_pwrdm,
290 &usbhost_pwrdm,
291 &dpll5_pwrdm,
292 NULL
293};
ecb24aa1 294
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295void __init omap3xxx_powerdomains_init(void)
296{
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297 unsigned int rev;
298
299 if (!cpu_is_omap34xx())
300 return;
301
129c65ee 302 pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
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303 pwrdm_register_pwrdms(powerdomains_omap3430_common);
304
305 rev = omap_rev();
306
307 if (rev == OMAP3430_REV_ES1_0)
308 pwrdm_register_pwrdms(powerdomains_omap3430es1);
309 else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
310 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
311 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
312 else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
313 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
314 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
315 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
316 else
317 WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
318
129c65ee 319 pwrdm_complete_init();
6e01478a 320}