[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / powerdomains7xx_data.c

/*
 * DRA7xx Power domains framework
 *
 * Copyright (C) 2009-2013 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Generated by code originally written by:
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include "powerdomain.h"

#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm7xx.h"
#include "prcm_mpu7xx.h"
#include "soc.h"

/* iva_7xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_7xx_pwrdm = {
	.name		  = "iva_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_IVA_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 4,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* hwa_mem */
		[1] = PWRSTS_ON,	/* sl2_mem */
		[2] = PWRSTS_ON,	/* tcm1_mem */
		[3] = PWRSTS_ON,	/* tcm2_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* rtc_7xx_pwrdm:  */
static struct powerdomain rtc_7xx_pwrdm = {
	.name		  = "rtc_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_RTC_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_7xx_pwrdm = {
	.name		  = "custefuse_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CUSTEFUSE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_aon_7xx_pwrdm = {
	.name		  = "custefuse_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CUSTEFUSE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* ipu_7xx_pwrdm: Audio back end power domain */
static struct powerdomain ipu_7xx_pwrdm = {
	.name		  = "ipu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_IPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 2,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* aessmem */
		[1] = PWRSTS_ON,	/* periphmem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dss_7xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_7xx_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSS_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dss_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l4per_7xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_7xx_pwrdm = {
	.name		  = "l4per_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_L4PER_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* nonretained_bank */
		[1] = PWRSTS_ON,	/* retained_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* gpu_7xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_7xx_pwrdm = {
	.name		  = "gpu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_GPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gpu_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* wkupaon_7xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_7xx_pwrdm = {
	.name		  = "wkupaon_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_WKUPAON_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* wkup_bank */
	},
};

/* core_7xx_pwrdm: CORE power domain */
static struct powerdomain core_7xx_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CORE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 5,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* core_nret_bank */
		[1] = PWRSTS_ON,	/* core_ocmram */
		[2] = PWRSTS_ON,	/* core_other_bank */
		[3] = PWRSTS_ON,	/* ipu_l2ram */
		[4] = PWRSTS_ON,	/* ipu_unicache */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_7xx_pwrdm = {
	.name		  = "coreaon_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_COREAON_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_7xx_pwrdm = {
	.name		  = "cpu0_pwrdm",
	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C0_INST,
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu0_l1 */
	},
};

/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_7xx_pwrdm = {
	.name		  = "cpu1_pwrdm",
	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C1_INST,
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu1_l1 */
	},
};

/* vpe_7xx_pwrdm:  */
static struct powerdomain vpe_7xx_pwrdm = {
	.name		  = "vpe_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_VPE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* vpe_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_7xx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_MPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[1] = PWRSTS_RET,	/* mpu_ram */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* mpu_l2 */
		[1] = PWRSTS_ON,	/* mpu_ram */
	},
};

/* l3init_7xx_pwrdm: L3 initators pheripherals power domain  */
static struct powerdomain l3init_7xx_pwrdm = {
	.name		  = "l3init_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_L3INIT_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gmac_bank */
		[1] = PWRSTS_ON,	/* l3init_bank1 */
		[2] = PWRSTS_ON,	/* l3init_bank2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve3_7xx_pwrdm:  */
static struct powerdomain eve3_7xx_pwrdm = {
	.name		  = "eve3_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE3_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve3_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* emu_7xx_pwrdm: Emulation power domain */
static struct powerdomain emu_7xx_pwrdm = {
	.name		  = "emu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EMU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* emu_bank */
	},
};

/* dsp2_7xx_pwrdm:  */
static struct powerdomain dsp2_7xx_pwrdm = {
	.name		  = "dsp2_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSP2_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dsp2_edma */
		[1] = PWRSTS_ON,	/* dsp2_l1 */
		[2] = PWRSTS_ON,	/* dsp2_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dsp1_7xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp1_7xx_pwrdm = {
	.name		  = "dsp1_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSP1_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dsp1_edma */
		[1] = PWRSTS_ON,	/* dsp1_l1 */
		[2] = PWRSTS_ON,	/* dsp1_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* cam_7xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_7xx_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CAM_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* vip_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve4_7xx_pwrdm:  */
static struct powerdomain eve4_7xx_pwrdm = {
	.name		  = "eve4_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE4_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve4_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve2_7xx_pwrdm:  */
static struct powerdomain eve2_7xx_pwrdm = {
	.name		  = "eve2_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE2_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve2_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve1_7xx_pwrdm:  */
static struct powerdomain eve1_7xx_pwrdm = {
	.name		  = "eve1_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE1_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve1_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * The following power domains are not under SW control
 *
 * mpuaon
 * mmaon
 */

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_dra7xx[] __initdata = {
	&iva_7xx_pwrdm,
	&rtc_7xx_pwrdm,
	&ipu_7xx_pwrdm,
	&dss_7xx_pwrdm,
	&l4per_7xx_pwrdm,
	&gpu_7xx_pwrdm,
	&wkupaon_7xx_pwrdm,
	&core_7xx_pwrdm,
	&coreaon_7xx_pwrdm,
	&cpu0_7xx_pwrdm,
	&cpu1_7xx_pwrdm,
	&vpe_7xx_pwrdm,
	&mpu_7xx_pwrdm,
	&l3init_7xx_pwrdm,
	&eve3_7xx_pwrdm,
	&emu_7xx_pwrdm,
	&dsp2_7xx_pwrdm,
	&dsp1_7xx_pwrdm,
	&cam_7xx_pwrdm,
	&eve4_7xx_pwrdm,
	&eve2_7xx_pwrdm,
	&eve1_7xx_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_dra76x[] __initdata = {
	&custefuse_aon_7xx_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_dra74x[] __initdata = {
	&custefuse_7xx_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_dra72x[] __initdata = {
	&custefuse_aon_7xx_pwrdm,
	NULL
};

void __init dra7xx_powerdomains_init(void)
{
	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_dra7xx);

	if (soc_is_dra76x())
		pwrdm_register_pwrdms(powerdomains_dra76x);
	else if (soc_is_dra74x())
		pwrdm_register_pwrdms(powerdomains_dra74x);
	else if (soc_is_dra72x())
		pwrdm_register_pwrdms(powerdomains_dra72x);

	pwrdm_complete_init();
}
Commit	Line	Data
97dd16b1 A	1	/*
	2	* DRA7xx Power domains framework
	3	*
	4	* Copyright (C) 2009-2013 Texas Instruments, Inc.
	5	* Copyright (C) 2009-2011 Nokia Corporation
	6	*
	7	* Generated by code originally written by:
	8	* Abhijit Pagare (abhijitpagare@ti.com)
	9	* Benoit Cousson (b-cousson@ti.com)
	10	* Paul Walmsley (paul@pwsan.com)
	11	*
	12	* This file is automatically generated from the OMAP hardware databases.
	13	* We respectfully ask that any modifications to this file be coordinated
	14	* with the public linux-omap@vger.kernel.org mailing list and the
	15	* authors above to ensure that the autogeneration scripts are kept
	16	* up-to-date with the file contents.
	17	*
	18	* This program is free software; you can redistribute it and/or modify
	19	* it under the terms of the GNU General Public License version 2 as
	20	* published by the Free Software Foundation.
	21	*/
	22
	23	#include <linux/kernel.h>
	24	#include <linux/init.h>
	25
	26	#include "powerdomain.h"
	27
	28	#include "prcm-common.h"
	29	#include "prcm44xx.h"
	30	#include "prm7xx.h"
	31	#include "prcm_mpu7xx.h"
3af6ccc3	32	#include "soc.h"
97dd16b1 A	33
	34	/* iva_7xx_pwrdm: IVA-HD power domain */
	35	static struct powerdomain iva_7xx_pwrdm = {
	36	.name = "iva_pwrdm",
	37	.prcm_offs = DRA7XX_PRM_IVA_INST,
	38	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	39	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	40	.banks = 4,
97dd16b1	41	.pwrsts_mem_on = {
41feb8ef NM	42	[0] = PWRSTS_ON, /* hwa_mem */
	43	[1] = PWRSTS_ON, /* sl2_mem */
	44	[2] = PWRSTS_ON, /* tcm1_mem */
	45	[3] = PWRSTS_ON, /* tcm2_mem */
97dd16b1 A	46	},
	47	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	48	};
	49
	50	/* rtc_7xx_pwrdm: */
	51	static struct powerdomain rtc_7xx_pwrdm = {
	52	.name = "rtc_pwrdm",
	53	.prcm_offs = DRA7XX_PRM_RTC_INST,
	54	.prcm_partition = DRA7XX_PRM_PARTITION,
	55	.pwrsts = PWRSTS_ON,
	56	};
	57
	58	/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
	59	static struct powerdomain custefuse_7xx_pwrdm = {
	60	.name = "custefuse_pwrdm",
	61	.prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
	62	.prcm_partition = DRA7XX_PRM_PARTITION,
	63	.pwrsts = PWRSTS_OFF_ON,
	64	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	65	};
	66
3af6ccc3 LV	67	/* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
	68	static struct powerdomain custefuse_aon_7xx_pwrdm = {
	69	.name = "custefuse_pwrdm",
	70	.prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
	71	.prcm_partition = DRA7XX_PRM_PARTITION,
	72	.pwrsts = PWRSTS_ON,
	73	};
	74
97dd16b1 A	75	/* ipu_7xx_pwrdm: Audio back end power domain */
	76	static struct powerdomain ipu_7xx_pwrdm = {
	77	.name = "ipu_pwrdm",
	78	.prcm_offs = DRA7XX_PRM_IPU_INST,
	79	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	80	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	81	.banks = 2,
97dd16b1	82	.pwrsts_mem_on = {
41feb8ef NM	83	[0] = PWRSTS_ON, /* aessmem */
41feb8ef NM	84	[1] = PWRSTS_ON, /* periphmem */
97dd16b1 A	85	},
	86	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	87	};
	88
	89	/* dss_7xx_pwrdm: Display subsystem power domain */
	90	static struct powerdomain dss_7xx_pwrdm = {
	91	.name = "dss_pwrdm",
	92	.prcm_offs = DRA7XX_PRM_DSS_INST,
	93	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	94	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	95	.banks = 1,
97dd16b1	96	.pwrsts_mem_on = {
41feb8ef	97	[0] = PWRSTS_ON, /* dss_mem */
97dd16b1 A	98	},
	99	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	100	};
	101
	102	/* l4per_7xx_pwrdm: Target peripherals power domain */
	103	static struct powerdomain l4per_7xx_pwrdm = {
	104	.name = "l4per_pwrdm",
	105	.prcm_offs = DRA7XX_PRM_L4PER_INST,
	106	.prcm_partition = DRA7XX_PRM_PARTITION,
d16c0d72	107	.pwrsts = PWRSTS_ON,
97dd16b1	108	.banks = 2,
97dd16b1	109	.pwrsts_mem_on = {
41feb8ef NM	110	[0] = PWRSTS_ON, /* nonretained_bank */
41feb8ef NM	111	[1] = PWRSTS_ON, /* retained_bank */
97dd16b1 A	112	},
	113	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	114	};
	115
	116	/* gpu_7xx_pwrdm: 3D accelerator power domain */
	117	static struct powerdomain gpu_7xx_pwrdm = {
	118	.name = "gpu_pwrdm",
	119	.prcm_offs = DRA7XX_PRM_GPU_INST,
	120	.prcm_partition = DRA7XX_PRM_PARTITION,
	121	.pwrsts = PWRSTS_OFF_ON,
	122	.banks = 1,
97dd16b1	123	.pwrsts_mem_on = {
41feb8ef	124	[0] = PWRSTS_ON, /* gpu_mem */
97dd16b1 A	125	},
	126	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	127	};
	128
	129	/* wkupaon_7xx_pwrdm: Wake-up power domain */
	130	static struct powerdomain wkupaon_7xx_pwrdm = {
	131	.name = "wkupaon_pwrdm",
	132	.prcm_offs = DRA7XX_PRM_WKUPAON_INST,
	133	.prcm_partition = DRA7XX_PRM_PARTITION,
	134	.pwrsts = PWRSTS_ON,
	135	.banks = 1,
97dd16b1 A	136	.pwrsts_mem_on = {
	137	[0] = PWRSTS_ON, /* wkup_bank */
	138	},
	139	};
	140
	141	/* core_7xx_pwrdm: CORE power domain */
	142	static struct powerdomain core_7xx_pwrdm = {
	143	.name = "core_pwrdm",
	144	.prcm_offs = DRA7XX_PRM_CORE_INST,
	145	.prcm_partition = DRA7XX_PRM_PARTITION,
f971512c	146	.pwrsts = PWRSTS_ON,
97dd16b1	147	.banks = 5,
97dd16b1	148	.pwrsts_mem_on = {
41feb8ef NM	149	[0] = PWRSTS_ON, /* core_nret_bank */
	150	[1] = PWRSTS_ON, /* core_ocmram */
	151	[2] = PWRSTS_ON, /* core_other_bank */
	152	[3] = PWRSTS_ON, /* ipu_l2ram */
	153	[4] = PWRSTS_ON, /* ipu_unicache */
97dd16b1 A	154	},
	155	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	156	};
	157
	158	/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
	159	static struct powerdomain coreaon_7xx_pwrdm = {
	160	.name = "coreaon_pwrdm",
	161	.prcm_offs = DRA7XX_PRM_COREAON_INST,
	162	.prcm_partition = DRA7XX_PRM_PARTITION,
	163	.pwrsts = PWRSTS_ON,
	164	};
	165
	166	/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
	167	static struct powerdomain cpu0_7xx_pwrdm = {
	168	.name = "cpu0_pwrdm",
	169	.prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
	170	.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
cafc8cb5 NM	171	.pwrsts = PWRSTS_RET_ON,
cafc8cb5 NM	172	.pwrsts_logic_ret = PWRSTS_RET,
97dd16b1 A	173	.banks = 1,
	174	.pwrsts_mem_ret = {
	175	[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
	176	},
	177	.pwrsts_mem_on = {
	178	[0] = PWRSTS_ON, /* cpu0_l1 */
	179	},
	180	};
	181
	182	/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
	183	static struct powerdomain cpu1_7xx_pwrdm = {
	184	.name = "cpu1_pwrdm",
	185	.prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
	186	.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
cafc8cb5 NM	187	.pwrsts = PWRSTS_RET_ON,
cafc8cb5 NM	188	.pwrsts_logic_ret = PWRSTS_RET,
97dd16b1 A	189	.banks = 1,
	190	.pwrsts_mem_ret = {
	191	[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
	192	},
	193	.pwrsts_mem_on = {
	194	[0] = PWRSTS_ON, /* cpu1_l1 */
	195	},
	196	};
	197
	198	/* vpe_7xx_pwrdm: */
	199	static struct powerdomain vpe_7xx_pwrdm = {
	200	.name = "vpe_pwrdm",
	201	.prcm_offs = DRA7XX_PRM_VPE_INST,
	202	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	203	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	204	.banks = 1,
97dd16b1	205	.pwrsts_mem_on = {
41feb8ef	206	[0] = PWRSTS_ON, /* vpe_bank */
97dd16b1 A	207	},
	208	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	209	};
	210
	211	/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
	212	static struct powerdomain mpu_7xx_pwrdm = {
	213	.name = "mpu_pwrdm",
	214	.prcm_offs = DRA7XX_PRM_MPU_INST,
	215	.prcm_partition = DRA7XX_PRM_PARTITION,
	216	.pwrsts = PWRSTS_RET_ON,
cafc8cb5	217	.pwrsts_logic_ret = PWRSTS_RET,
97dd16b1 A	218	.banks = 2,
	219	.pwrsts_mem_ret = {
	220	[0] = PWRSTS_OFF_RET, /* mpu_l2 */
	221	[1] = PWRSTS_RET, /* mpu_ram */
	222	},
	223	.pwrsts_mem_on = {
41feb8ef NM	224	[0] = PWRSTS_ON, /* mpu_l2 */
41feb8ef NM	225	[1] = PWRSTS_ON, /* mpu_ram */
97dd16b1 A	226	},
	227	};
	228
	229	/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
	230	static struct powerdomain l3init_7xx_pwrdm = {
	231	.name = "l3init_pwrdm",
	232	.prcm_offs = DRA7XX_PRM_L3INIT_INST,
	233	.prcm_partition = DRA7XX_PRM_PARTITION,
d16c0d72	234	.pwrsts = PWRSTS_ON,
97dd16b1	235	.banks = 3,
97dd16b1	236	.pwrsts_mem_on = {
41feb8ef NM	237	[0] = PWRSTS_ON, /* gmac_bank */
	238	[1] = PWRSTS_ON, /* l3init_bank1 */
	239	[2] = PWRSTS_ON, /* l3init_bank2 */
97dd16b1 A	240	},
	241	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	242	};
	243
	244	/* eve3_7xx_pwrdm: */
	245	static struct powerdomain eve3_7xx_pwrdm = {
	246	.name = "eve3_pwrdm",
	247	.prcm_offs = DRA7XX_PRM_EVE3_INST,
	248	.prcm_partition = DRA7XX_PRM_PARTITION,
	249	.pwrsts = PWRSTS_OFF_ON,
	250	.banks = 1,
97dd16b1	251	.pwrsts_mem_on = {
41feb8ef	252	[0] = PWRSTS_ON, /* eve3_bank */
97dd16b1 A	253	},
	254	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	255	};
	256
	257	/* emu_7xx_pwrdm: Emulation power domain */
	258	static struct powerdomain emu_7xx_pwrdm = {
	259	.name = "emu_pwrdm",
	260	.prcm_offs = DRA7XX_PRM_EMU_INST,
	261	.prcm_partition = DRA7XX_PRM_PARTITION,
	262	.pwrsts = PWRSTS_OFF_ON,
	263	.banks = 1,
97dd16b1	264	.pwrsts_mem_on = {
41feb8ef	265	[0] = PWRSTS_ON, /* emu_bank */
97dd16b1 A	266	},
	267	};
	268
	269	/* dsp2_7xx_pwrdm: */
	270	static struct powerdomain dsp2_7xx_pwrdm = {
	271	.name = "dsp2_pwrdm",
	272	.prcm_offs = DRA7XX_PRM_DSP2_INST,
	273	.prcm_partition = DRA7XX_PRM_PARTITION,
	274	.pwrsts = PWRSTS_OFF_ON,
	275	.banks = 3,
97dd16b1	276	.pwrsts_mem_on = {
41feb8ef NM	277	[0] = PWRSTS_ON, /* dsp2_edma */
	278	[1] = PWRSTS_ON, /* dsp2_l1 */
	279	[2] = PWRSTS_ON, /* dsp2_l2 */
97dd16b1 A	280	},
	281	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	282	};
	283
	284	/* dsp1_7xx_pwrdm: Tesla processor power domain */
	285	static struct powerdomain dsp1_7xx_pwrdm = {
	286	.name = "dsp1_pwrdm",
	287	.prcm_offs = DRA7XX_PRM_DSP1_INST,
	288	.prcm_partition = DRA7XX_PRM_PARTITION,
	289	.pwrsts = PWRSTS_OFF_ON,
	290	.banks = 3,
97dd16b1	291	.pwrsts_mem_on = {
41feb8ef NM	292	[0] = PWRSTS_ON, /* dsp1_edma */
	293	[1] = PWRSTS_ON, /* dsp1_l1 */
	294	[2] = PWRSTS_ON, /* dsp1_l2 */
97dd16b1 A	295	},
	296	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	297	};
	298
	299	/* cam_7xx_pwrdm: Camera subsystem power domain */
	300	static struct powerdomain cam_7xx_pwrdm = {
	301	.name = "cam_pwrdm",
	302	.prcm_offs = DRA7XX_PRM_CAM_INST,
	303	.prcm_partition = DRA7XX_PRM_PARTITION,
	304	.pwrsts = PWRSTS_OFF_ON,
	305	.banks = 1,
97dd16b1	306	.pwrsts_mem_on = {
41feb8ef	307	[0] = PWRSTS_ON, /* vip_bank */
97dd16b1 A	308	},
	309	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	310	};
	311
	312	/* eve4_7xx_pwrdm: */
	313	static struct powerdomain eve4_7xx_pwrdm = {
	314	.name = "eve4_pwrdm",
	315	.prcm_offs = DRA7XX_PRM_EVE4_INST,
	316	.prcm_partition = DRA7XX_PRM_PARTITION,
	317	.pwrsts = PWRSTS_OFF_ON,
	318	.banks = 1,
97dd16b1	319	.pwrsts_mem_on = {
41feb8ef	320	[0] = PWRSTS_ON, /* eve4_bank */
97dd16b1 A	321	},
	322	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	323	};
	324
	325	/* eve2_7xx_pwrdm: */
	326	static struct powerdomain eve2_7xx_pwrdm = {
	327	.name = "eve2_pwrdm",
	328	.prcm_offs = DRA7XX_PRM_EVE2_INST,
	329	.prcm_partition = DRA7XX_PRM_PARTITION,
	330	.pwrsts = PWRSTS_OFF_ON,
	331	.banks = 1,
97dd16b1	332	.pwrsts_mem_on = {
41feb8ef	333	[0] = PWRSTS_ON, /* eve2_bank */
97dd16b1 A	334	},
	335	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	336	};
	337
	338	/* eve1_7xx_pwrdm: */
	339	static struct powerdomain eve1_7xx_pwrdm = {
	340	.name = "eve1_pwrdm",
	341	.prcm_offs = DRA7XX_PRM_EVE1_INST,
	342	.prcm_partition = DRA7XX_PRM_PARTITION,
	343	.pwrsts = PWRSTS_OFF_ON,
	344	.banks = 1,
97dd16b1	345	.pwrsts_mem_on = {
41feb8ef	346	[0] = PWRSTS_ON, /* eve1_bank */
97dd16b1 A	347	},
	348	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	349	};
	350
	351	/*
	352	* The following power domains are not under SW control
	353	*
	354	* mpuaon
	355	* mmaon
	356	*/
	357
	358	/* As powerdomains are added or removed above, this list must also be changed */
	359	static struct powerdomain *powerdomains_dra7xx[] __initdata = {
	360	&iva_7xx_pwrdm,
	361	&rtc_7xx_pwrdm,
97dd16b1 A	362	&ipu_7xx_pwrdm,
	363	&dss_7xx_pwrdm,
	364	&l4per_7xx_pwrdm,
	365	&gpu_7xx_pwrdm,
	366	&wkupaon_7xx_pwrdm,
	367	&core_7xx_pwrdm,
	368	&coreaon_7xx_pwrdm,
	369	&cpu0_7xx_pwrdm,
	370	&cpu1_7xx_pwrdm,
	371	&vpe_7xx_pwrdm,
	372	&mpu_7xx_pwrdm,
	373	&l3init_7xx_pwrdm,
	374	&eve3_7xx_pwrdm,
	375	&emu_7xx_pwrdm,
	376	&dsp2_7xx_pwrdm,
	377	&dsp1_7xx_pwrdm,
	378	&cam_7xx_pwrdm,
	379	&eve4_7xx_pwrdm,
	380	&eve2_7xx_pwrdm,
	381	&eve1_7xx_pwrdm,
	382	NULL
	383	};
	384
3af6ccc3 LV	385	static struct powerdomain *powerdomains_dra76x[] __initdata = {
	386	&custefuse_aon_7xx_pwrdm,
	387	NULL
	388	};
	389
	390	static struct powerdomain *powerdomains_dra74x[] __initdata = {
	391	&custefuse_7xx_pwrdm,
	392	NULL
	393	};
	394
	395	static struct powerdomain *powerdomains_dra72x[] __initdata = {
	396	&custefuse_aon_7xx_pwrdm,
	397	NULL
	398	};
	399
97dd16b1 A	400	void __init dra7xx_powerdomains_init(void)
	401	{
	402	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	403	pwrdm_register_pwrdms(powerdomains_dra7xx);
3af6ccc3 LV	404
	405	if (soc_is_dra76x())
	406	pwrdm_register_pwrdms(powerdomains_dra76x);
	407	else if (soc_is_dra74x())
	408	pwrdm_register_pwrdms(powerdomains_dra74x);
	409	else if (soc_is_dra72x())
	410	pwrdm_register_pwrdms(powerdomains_dra72x);
	411
97dd16b1 A	412	pwrdm_complete_init();
97dd16b1 A	413	}