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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
97dd16b1 A |
2 | /* |
3 | * DRA7xx Power domains framework | |
4 | * | |
5 | * Copyright (C) 2009-2013 Texas Instruments, Inc. | |
6 | * Copyright (C) 2009-2011 Nokia Corporation | |
7 | * | |
8 | * Generated by code originally written by: | |
9 | * Abhijit Pagare (abhijitpagare@ti.com) | |
10 | * Benoit Cousson (b-cousson@ti.com) | |
11 | * Paul Walmsley (paul@pwsan.com) | |
12 | * | |
13 | * This file is automatically generated from the OMAP hardware databases. | |
14 | * We respectfully ask that any modifications to this file be coordinated | |
15 | * with the public linux-omap@vger.kernel.org mailing list and the | |
16 | * authors above to ensure that the autogeneration scripts are kept | |
17 | * up-to-date with the file contents. | |
97dd16b1 A |
18 | */ |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
22 | ||
23 | #include "powerdomain.h" | |
24 | ||
25 | #include "prcm-common.h" | |
26 | #include "prcm44xx.h" | |
27 | #include "prm7xx.h" | |
28 | #include "prcm_mpu7xx.h" | |
3af6ccc3 | 29 | #include "soc.h" |
97dd16b1 A |
30 | |
31 | /* iva_7xx_pwrdm: IVA-HD power domain */ | |
32 | static struct powerdomain iva_7xx_pwrdm = { | |
33 | .name = "iva_pwrdm", | |
34 | .prcm_offs = DRA7XX_PRM_IVA_INST, | |
35 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
dac4fba2 | 36 | .pwrsts = PWRSTS_OFF_ON, |
97dd16b1 | 37 | .banks = 4, |
97dd16b1 | 38 | .pwrsts_mem_on = { |
41feb8ef NM |
39 | [0] = PWRSTS_ON, /* hwa_mem */ |
40 | [1] = PWRSTS_ON, /* sl2_mem */ | |
41 | [2] = PWRSTS_ON, /* tcm1_mem */ | |
42 | [3] = PWRSTS_ON, /* tcm2_mem */ | |
97dd16b1 A |
43 | }, |
44 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
45 | }; | |
46 | ||
47 | /* rtc_7xx_pwrdm: */ | |
48 | static struct powerdomain rtc_7xx_pwrdm = { | |
49 | .name = "rtc_pwrdm", | |
50 | .prcm_offs = DRA7XX_PRM_RTC_INST, | |
51 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
52 | .pwrsts = PWRSTS_ON, | |
53 | }; | |
54 | ||
55 | /* custefuse_7xx_pwrdm: Customer efuse controller power domain */ | |
56 | static struct powerdomain custefuse_7xx_pwrdm = { | |
57 | .name = "custefuse_pwrdm", | |
58 | .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, | |
59 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
60 | .pwrsts = PWRSTS_OFF_ON, | |
61 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
62 | }; | |
63 | ||
3af6ccc3 LV |
64 | /* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */ |
65 | static struct powerdomain custefuse_aon_7xx_pwrdm = { | |
66 | .name = "custefuse_pwrdm", | |
67 | .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, | |
68 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
69 | .pwrsts = PWRSTS_ON, | |
70 | }; | |
71 | ||
97dd16b1 A |
72 | /* ipu_7xx_pwrdm: Audio back end power domain */ |
73 | static struct powerdomain ipu_7xx_pwrdm = { | |
74 | .name = "ipu_pwrdm", | |
75 | .prcm_offs = DRA7XX_PRM_IPU_INST, | |
76 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
dac4fba2 | 77 | .pwrsts = PWRSTS_OFF_ON, |
97dd16b1 | 78 | .banks = 2, |
97dd16b1 | 79 | .pwrsts_mem_on = { |
41feb8ef NM |
80 | [0] = PWRSTS_ON, /* aessmem */ |
81 | [1] = PWRSTS_ON, /* periphmem */ | |
97dd16b1 A |
82 | }, |
83 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
84 | }; | |
85 | ||
86 | /* dss_7xx_pwrdm: Display subsystem power domain */ | |
87 | static struct powerdomain dss_7xx_pwrdm = { | |
88 | .name = "dss_pwrdm", | |
89 | .prcm_offs = DRA7XX_PRM_DSS_INST, | |
90 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
dac4fba2 | 91 | .pwrsts = PWRSTS_OFF_ON, |
97dd16b1 | 92 | .banks = 1, |
97dd16b1 | 93 | .pwrsts_mem_on = { |
41feb8ef | 94 | [0] = PWRSTS_ON, /* dss_mem */ |
97dd16b1 A |
95 | }, |
96 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
97 | }; | |
98 | ||
99 | /* l4per_7xx_pwrdm: Target peripherals power domain */ | |
100 | static struct powerdomain l4per_7xx_pwrdm = { | |
101 | .name = "l4per_pwrdm", | |
102 | .prcm_offs = DRA7XX_PRM_L4PER_INST, | |
103 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
d16c0d72 | 104 | .pwrsts = PWRSTS_ON, |
97dd16b1 | 105 | .banks = 2, |
97dd16b1 | 106 | .pwrsts_mem_on = { |
41feb8ef NM |
107 | [0] = PWRSTS_ON, /* nonretained_bank */ |
108 | [1] = PWRSTS_ON, /* retained_bank */ | |
97dd16b1 A |
109 | }, |
110 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
111 | }; | |
112 | ||
113 | /* gpu_7xx_pwrdm: 3D accelerator power domain */ | |
114 | static struct powerdomain gpu_7xx_pwrdm = { | |
115 | .name = "gpu_pwrdm", | |
116 | .prcm_offs = DRA7XX_PRM_GPU_INST, | |
117 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
118 | .pwrsts = PWRSTS_OFF_ON, | |
119 | .banks = 1, | |
97dd16b1 | 120 | .pwrsts_mem_on = { |
41feb8ef | 121 | [0] = PWRSTS_ON, /* gpu_mem */ |
97dd16b1 A |
122 | }, |
123 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
124 | }; | |
125 | ||
126 | /* wkupaon_7xx_pwrdm: Wake-up power domain */ | |
127 | static struct powerdomain wkupaon_7xx_pwrdm = { | |
128 | .name = "wkupaon_pwrdm", | |
129 | .prcm_offs = DRA7XX_PRM_WKUPAON_INST, | |
130 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
131 | .pwrsts = PWRSTS_ON, | |
132 | .banks = 1, | |
97dd16b1 A |
133 | .pwrsts_mem_on = { |
134 | [0] = PWRSTS_ON, /* wkup_bank */ | |
135 | }, | |
136 | }; | |
137 | ||
138 | /* core_7xx_pwrdm: CORE power domain */ | |
139 | static struct powerdomain core_7xx_pwrdm = { | |
140 | .name = "core_pwrdm", | |
141 | .prcm_offs = DRA7XX_PRM_CORE_INST, | |
142 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
f971512c | 143 | .pwrsts = PWRSTS_ON, |
97dd16b1 | 144 | .banks = 5, |
97dd16b1 | 145 | .pwrsts_mem_on = { |
41feb8ef NM |
146 | [0] = PWRSTS_ON, /* core_nret_bank */ |
147 | [1] = PWRSTS_ON, /* core_ocmram */ | |
148 | [2] = PWRSTS_ON, /* core_other_bank */ | |
149 | [3] = PWRSTS_ON, /* ipu_l2ram */ | |
150 | [4] = PWRSTS_ON, /* ipu_unicache */ | |
97dd16b1 A |
151 | }, |
152 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
153 | }; | |
154 | ||
155 | /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ | |
156 | static struct powerdomain coreaon_7xx_pwrdm = { | |
157 | .name = "coreaon_pwrdm", | |
158 | .prcm_offs = DRA7XX_PRM_COREAON_INST, | |
159 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
160 | .pwrsts = PWRSTS_ON, | |
161 | }; | |
162 | ||
163 | /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ | |
164 | static struct powerdomain cpu0_7xx_pwrdm = { | |
165 | .name = "cpu0_pwrdm", | |
166 | .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, | |
167 | .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, | |
cafc8cb5 NM |
168 | .pwrsts = PWRSTS_RET_ON, |
169 | .pwrsts_logic_ret = PWRSTS_RET, | |
97dd16b1 A |
170 | .banks = 1, |
171 | .pwrsts_mem_ret = { | |
172 | [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ | |
173 | }, | |
174 | .pwrsts_mem_on = { | |
175 | [0] = PWRSTS_ON, /* cpu0_l1 */ | |
176 | }, | |
177 | }; | |
178 | ||
179 | /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ | |
180 | static struct powerdomain cpu1_7xx_pwrdm = { | |
181 | .name = "cpu1_pwrdm", | |
182 | .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, | |
183 | .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, | |
cafc8cb5 NM |
184 | .pwrsts = PWRSTS_RET_ON, |
185 | .pwrsts_logic_ret = PWRSTS_RET, | |
97dd16b1 A |
186 | .banks = 1, |
187 | .pwrsts_mem_ret = { | |
188 | [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ | |
189 | }, | |
190 | .pwrsts_mem_on = { | |
191 | [0] = PWRSTS_ON, /* cpu1_l1 */ | |
192 | }, | |
193 | }; | |
194 | ||
195 | /* vpe_7xx_pwrdm: */ | |
196 | static struct powerdomain vpe_7xx_pwrdm = { | |
197 | .name = "vpe_pwrdm", | |
198 | .prcm_offs = DRA7XX_PRM_VPE_INST, | |
199 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
dac4fba2 | 200 | .pwrsts = PWRSTS_OFF_ON, |
97dd16b1 | 201 | .banks = 1, |
97dd16b1 | 202 | .pwrsts_mem_on = { |
41feb8ef | 203 | [0] = PWRSTS_ON, /* vpe_bank */ |
97dd16b1 A |
204 | }, |
205 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
206 | }; | |
207 | ||
208 | /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */ | |
209 | static struct powerdomain mpu_7xx_pwrdm = { | |
210 | .name = "mpu_pwrdm", | |
211 | .prcm_offs = DRA7XX_PRM_MPU_INST, | |
212 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
213 | .pwrsts = PWRSTS_RET_ON, | |
cafc8cb5 | 214 | .pwrsts_logic_ret = PWRSTS_RET, |
97dd16b1 A |
215 | .banks = 2, |
216 | .pwrsts_mem_ret = { | |
217 | [0] = PWRSTS_OFF_RET, /* mpu_l2 */ | |
218 | [1] = PWRSTS_RET, /* mpu_ram */ | |
219 | }, | |
220 | .pwrsts_mem_on = { | |
41feb8ef NM |
221 | [0] = PWRSTS_ON, /* mpu_l2 */ |
222 | [1] = PWRSTS_ON, /* mpu_ram */ | |
97dd16b1 A |
223 | }, |
224 | }; | |
225 | ||
226 | /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */ | |
227 | static struct powerdomain l3init_7xx_pwrdm = { | |
228 | .name = "l3init_pwrdm", | |
229 | .prcm_offs = DRA7XX_PRM_L3INIT_INST, | |
230 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
d16c0d72 | 231 | .pwrsts = PWRSTS_ON, |
97dd16b1 | 232 | .banks = 3, |
97dd16b1 | 233 | .pwrsts_mem_on = { |
41feb8ef NM |
234 | [0] = PWRSTS_ON, /* gmac_bank */ |
235 | [1] = PWRSTS_ON, /* l3init_bank1 */ | |
236 | [2] = PWRSTS_ON, /* l3init_bank2 */ | |
97dd16b1 A |
237 | }, |
238 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
239 | }; | |
240 | ||
241 | /* eve3_7xx_pwrdm: */ | |
242 | static struct powerdomain eve3_7xx_pwrdm = { | |
243 | .name = "eve3_pwrdm", | |
244 | .prcm_offs = DRA7XX_PRM_EVE3_INST, | |
245 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
246 | .pwrsts = PWRSTS_OFF_ON, | |
247 | .banks = 1, | |
97dd16b1 | 248 | .pwrsts_mem_on = { |
41feb8ef | 249 | [0] = PWRSTS_ON, /* eve3_bank */ |
97dd16b1 A |
250 | }, |
251 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
252 | }; | |
253 | ||
254 | /* emu_7xx_pwrdm: Emulation power domain */ | |
255 | static struct powerdomain emu_7xx_pwrdm = { | |
256 | .name = "emu_pwrdm", | |
257 | .prcm_offs = DRA7XX_PRM_EMU_INST, | |
258 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
259 | .pwrsts = PWRSTS_OFF_ON, | |
260 | .banks = 1, | |
97dd16b1 | 261 | .pwrsts_mem_on = { |
41feb8ef | 262 | [0] = PWRSTS_ON, /* emu_bank */ |
97dd16b1 A |
263 | }, |
264 | }; | |
265 | ||
266 | /* dsp2_7xx_pwrdm: */ | |
267 | static struct powerdomain dsp2_7xx_pwrdm = { | |
268 | .name = "dsp2_pwrdm", | |
269 | .prcm_offs = DRA7XX_PRM_DSP2_INST, | |
270 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
271 | .pwrsts = PWRSTS_OFF_ON, | |
272 | .banks = 3, | |
97dd16b1 | 273 | .pwrsts_mem_on = { |
41feb8ef NM |
274 | [0] = PWRSTS_ON, /* dsp2_edma */ |
275 | [1] = PWRSTS_ON, /* dsp2_l1 */ | |
276 | [2] = PWRSTS_ON, /* dsp2_l2 */ | |
97dd16b1 A |
277 | }, |
278 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
279 | }; | |
280 | ||
281 | /* dsp1_7xx_pwrdm: Tesla processor power domain */ | |
282 | static struct powerdomain dsp1_7xx_pwrdm = { | |
283 | .name = "dsp1_pwrdm", | |
284 | .prcm_offs = DRA7XX_PRM_DSP1_INST, | |
285 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
286 | .pwrsts = PWRSTS_OFF_ON, | |
287 | .banks = 3, | |
97dd16b1 | 288 | .pwrsts_mem_on = { |
41feb8ef NM |
289 | [0] = PWRSTS_ON, /* dsp1_edma */ |
290 | [1] = PWRSTS_ON, /* dsp1_l1 */ | |
291 | [2] = PWRSTS_ON, /* dsp1_l2 */ | |
97dd16b1 A |
292 | }, |
293 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
294 | }; | |
295 | ||
296 | /* cam_7xx_pwrdm: Camera subsystem power domain */ | |
297 | static struct powerdomain cam_7xx_pwrdm = { | |
298 | .name = "cam_pwrdm", | |
299 | .prcm_offs = DRA7XX_PRM_CAM_INST, | |
300 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
301 | .pwrsts = PWRSTS_OFF_ON, | |
302 | .banks = 1, | |
97dd16b1 | 303 | .pwrsts_mem_on = { |
41feb8ef | 304 | [0] = PWRSTS_ON, /* vip_bank */ |
97dd16b1 A |
305 | }, |
306 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
307 | }; | |
308 | ||
309 | /* eve4_7xx_pwrdm: */ | |
310 | static struct powerdomain eve4_7xx_pwrdm = { | |
311 | .name = "eve4_pwrdm", | |
312 | .prcm_offs = DRA7XX_PRM_EVE4_INST, | |
313 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
314 | .pwrsts = PWRSTS_OFF_ON, | |
315 | .banks = 1, | |
97dd16b1 | 316 | .pwrsts_mem_on = { |
41feb8ef | 317 | [0] = PWRSTS_ON, /* eve4_bank */ |
97dd16b1 A |
318 | }, |
319 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
320 | }; | |
321 | ||
322 | /* eve2_7xx_pwrdm: */ | |
323 | static struct powerdomain eve2_7xx_pwrdm = { | |
324 | .name = "eve2_pwrdm", | |
325 | .prcm_offs = DRA7XX_PRM_EVE2_INST, | |
326 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
327 | .pwrsts = PWRSTS_OFF_ON, | |
328 | .banks = 1, | |
97dd16b1 | 329 | .pwrsts_mem_on = { |
41feb8ef | 330 | [0] = PWRSTS_ON, /* eve2_bank */ |
97dd16b1 A |
331 | }, |
332 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
333 | }; | |
334 | ||
335 | /* eve1_7xx_pwrdm: */ | |
336 | static struct powerdomain eve1_7xx_pwrdm = { | |
337 | .name = "eve1_pwrdm", | |
338 | .prcm_offs = DRA7XX_PRM_EVE1_INST, | |
339 | .prcm_partition = DRA7XX_PRM_PARTITION, | |
340 | .pwrsts = PWRSTS_OFF_ON, | |
341 | .banks = 1, | |
97dd16b1 | 342 | .pwrsts_mem_on = { |
41feb8ef | 343 | [0] = PWRSTS_ON, /* eve1_bank */ |
97dd16b1 A |
344 | }, |
345 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | |
346 | }; | |
347 | ||
348 | /* | |
349 | * The following power domains are not under SW control | |
350 | * | |
351 | * mpuaon | |
352 | * mmaon | |
353 | */ | |
354 | ||
355 | /* As powerdomains are added or removed above, this list must also be changed */ | |
356 | static struct powerdomain *powerdomains_dra7xx[] __initdata = { | |
357 | &iva_7xx_pwrdm, | |
358 | &rtc_7xx_pwrdm, | |
97dd16b1 A |
359 | &ipu_7xx_pwrdm, |
360 | &dss_7xx_pwrdm, | |
361 | &l4per_7xx_pwrdm, | |
362 | &gpu_7xx_pwrdm, | |
363 | &wkupaon_7xx_pwrdm, | |
364 | &core_7xx_pwrdm, | |
365 | &coreaon_7xx_pwrdm, | |
366 | &cpu0_7xx_pwrdm, | |
367 | &cpu1_7xx_pwrdm, | |
368 | &vpe_7xx_pwrdm, | |
369 | &mpu_7xx_pwrdm, | |
370 | &l3init_7xx_pwrdm, | |
371 | &eve3_7xx_pwrdm, | |
372 | &emu_7xx_pwrdm, | |
373 | &dsp2_7xx_pwrdm, | |
374 | &dsp1_7xx_pwrdm, | |
375 | &cam_7xx_pwrdm, | |
376 | &eve4_7xx_pwrdm, | |
377 | &eve2_7xx_pwrdm, | |
378 | &eve1_7xx_pwrdm, | |
379 | NULL | |
380 | }; | |
381 | ||
3af6ccc3 LV |
382 | static struct powerdomain *powerdomains_dra76x[] __initdata = { |
383 | &custefuse_aon_7xx_pwrdm, | |
384 | NULL | |
385 | }; | |
386 | ||
387 | static struct powerdomain *powerdomains_dra74x[] __initdata = { | |
388 | &custefuse_7xx_pwrdm, | |
389 | NULL | |
390 | }; | |
391 | ||
392 | static struct powerdomain *powerdomains_dra72x[] __initdata = { | |
393 | &custefuse_aon_7xx_pwrdm, | |
394 | NULL | |
395 | }; | |
396 | ||
97dd16b1 A |
397 | void __init dra7xx_powerdomains_init(void) |
398 | { | |
399 | pwrdm_register_platform_funcs(&omap4_pwrdm_operations); | |
400 | pwrdm_register_pwrdms(powerdomains_dra7xx); | |
3af6ccc3 LV |
401 | |
402 | if (soc_is_dra76x()) | |
403 | pwrdm_register_pwrdms(powerdomains_dra76x); | |
404 | else if (soc_is_dra74x()) | |
405 | pwrdm_register_pwrdms(powerdomains_dra74x); | |
406 | else if (soc_is_dra72x()) | |
407 | pwrdm_register_pwrdms(powerdomains_dra72x); | |
408 | ||
97dd16b1 A |
409 | pwrdm_complete_init(); |
410 | } |