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1dbae815 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/mach-omap2/prcm-regs.h |
b824efae TL |
3 | * |
4 | * OMAP24XX Power Reset and Clock Management (PRCM) registers | |
1dbae815 TL |
5 | * |
6 | * Copyright (C) 2005 Texas Instruments, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
b824efae TL |
23 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H |
24 | #define __ARCH_ARM_MACH_OMAP2_PRCM_H | |
1dbae815 TL |
25 | |
26 | /* SET_PERFORMANCE_LEVEL PARAMETERS */ | |
27 | #define PRCM_HALF_SPEED 1 | |
28 | #define PRCM_FULL_SPEED 2 | |
29 | ||
30 | #ifndef __ASSEMBLER__ | |
31 | ||
32 | #define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset)) | |
33 | ||
34 | #define PRCM_REVISION PRCM_REG32(0x000) | |
35 | #define PRCM_SYSCONFIG PRCM_REG32(0x010) | |
36 | #define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018) | |
37 | #define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C) | |
38 | #define PRCM_VOLTCTRL PRCM_REG32(0x050) | |
39 | #define PRCM_VOLTST PRCM_REG32(0x054) | |
40 | #define PRCM_CLKSRC_CTRL PRCM_REG32(0x060) | |
41 | #define PRCM_CLKOUT_CTRL PRCM_REG32(0x070) | |
42 | #define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078) | |
43 | #define PRCM_CLKCFG_CTRL PRCM_REG32(0x080) | |
44 | #define PRCM_CLKCFG_STATUS PRCM_REG32(0x084) | |
45 | #define PRCM_VOLTSETUP PRCM_REG32(0x090) | |
46 | #define PRCM_CLKSSETUP PRCM_REG32(0x094) | |
47 | #define PRCM_POLCTRL PRCM_REG32(0x098) | |
48 | ||
49 | /* GENERAL PURPOSE */ | |
50 | #define GENERAL_PURPOSE1 PRCM_REG32(0x0B0) | |
51 | #define GENERAL_PURPOSE2 PRCM_REG32(0x0B4) | |
52 | #define GENERAL_PURPOSE3 PRCM_REG32(0x0B8) | |
53 | #define GENERAL_PURPOSE4 PRCM_REG32(0x0BC) | |
54 | #define GENERAL_PURPOSE5 PRCM_REG32(0x0C0) | |
55 | #define GENERAL_PURPOSE6 PRCM_REG32(0x0C4) | |
56 | #define GENERAL_PURPOSE7 PRCM_REG32(0x0C8) | |
57 | #define GENERAL_PURPOSE8 PRCM_REG32(0x0CC) | |
58 | #define GENERAL_PURPOSE9 PRCM_REG32(0x0D0) | |
59 | #define GENERAL_PURPOSE10 PRCM_REG32(0x0D4) | |
60 | #define GENERAL_PURPOSE11 PRCM_REG32(0x0D8) | |
61 | #define GENERAL_PURPOSE12 PRCM_REG32(0x0DC) | |
62 | #define GENERAL_PURPOSE13 PRCM_REG32(0x0E0) | |
63 | #define GENERAL_PURPOSE14 PRCM_REG32(0x0E4) | |
64 | #define GENERAL_PURPOSE15 PRCM_REG32(0x0E8) | |
65 | #define GENERAL_PURPOSE16 PRCM_REG32(0x0EC) | |
66 | #define GENERAL_PURPOSE17 PRCM_REG32(0x0F0) | |
67 | #define GENERAL_PURPOSE18 PRCM_REG32(0x0F4) | |
68 | #define GENERAL_PURPOSE19 PRCM_REG32(0x0F8) | |
69 | #define GENERAL_PURPOSE20 PRCM_REG32(0x0FC) | |
70 | ||
71 | /* MPU */ | |
72 | #define CM_CLKSEL_MPU PRCM_REG32(0x140) | |
73 | #define CM_CLKSTCTRL_MPU PRCM_REG32(0x148) | |
74 | #define RM_RSTST_MPU PRCM_REG32(0x158) | |
75 | #define PM_WKDEP_MPU PRCM_REG32(0x1C8) | |
76 | #define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4) | |
77 | #define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8) | |
78 | #define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC) | |
79 | #define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0) | |
80 | #define PM_PWSTST_MPU PRCM_REG32(0x1E4) | |
81 | ||
82 | /* CORE */ | |
83 | #define CM_FCLKEN1_CORE PRCM_REG32(0x200) | |
84 | #define CM_FCLKEN2_CORE PRCM_REG32(0x204) | |
85 | #define CM_FCLKEN3_CORE PRCM_REG32(0x208) | |
86 | #define CM_ICLKEN1_CORE PRCM_REG32(0x210) | |
87 | #define CM_ICLKEN2_CORE PRCM_REG32(0x214) | |
88 | #define CM_ICLKEN3_CORE PRCM_REG32(0x218) | |
89 | #define CM_ICLKEN4_CORE PRCM_REG32(0x21C) | |
90 | #define CM_IDLEST1_CORE PRCM_REG32(0x220) | |
91 | #define CM_IDLEST2_CORE PRCM_REG32(0x224) | |
92 | #define CM_IDLEST3_CORE PRCM_REG32(0x228) | |
93 | #define CM_IDLEST4_CORE PRCM_REG32(0x22C) | |
94 | #define CM_AUTOIDLE1_CORE PRCM_REG32(0x230) | |
95 | #define CM_AUTOIDLE2_CORE PRCM_REG32(0x234) | |
96 | #define CM_AUTOIDLE3_CORE PRCM_REG32(0x238) | |
97 | #define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C) | |
98 | #define CM_CLKSEL1_CORE PRCM_REG32(0x240) | |
99 | #define CM_CLKSEL2_CORE PRCM_REG32(0x244) | |
100 | #define CM_CLKSTCTRL_CORE PRCM_REG32(0x248) | |
101 | #define PM_WKEN1_CORE PRCM_REG32(0x2A0) | |
102 | #define PM_WKEN2_CORE PRCM_REG32(0x2A4) | |
103 | #define PM_WKST1_CORE PRCM_REG32(0x2B0) | |
104 | #define PM_WKST2_CORE PRCM_REG32(0x2B4) | |
105 | #define PM_WKDEP_CORE PRCM_REG32(0x2C8) | |
106 | #define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0) | |
107 | #define PM_PWSTST_CORE PRCM_REG32(0x2E4) | |
108 | ||
109 | /* GFX */ | |
110 | #define CM_FCLKEN_GFX PRCM_REG32(0x300) | |
111 | #define CM_ICLKEN_GFX PRCM_REG32(0x310) | |
112 | #define CM_IDLEST_GFX PRCM_REG32(0x320) | |
113 | #define CM_CLKSEL_GFX PRCM_REG32(0x340) | |
114 | #define CM_CLKSTCTRL_GFX PRCM_REG32(0x348) | |
115 | #define RM_RSTCTRL_GFX PRCM_REG32(0x350) | |
116 | #define RM_RSTST_GFX PRCM_REG32(0x358) | |
117 | #define PM_WKDEP_GFX PRCM_REG32(0x3C8) | |
118 | #define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0) | |
119 | #define PM_PWSTST_GFX PRCM_REG32(0x3E4) | |
120 | ||
121 | /* WAKE-UP */ | |
122 | #define CM_FCLKEN_WKUP PRCM_REG32(0x400) | |
123 | #define CM_ICLKEN_WKUP PRCM_REG32(0x410) | |
124 | #define CM_IDLEST_WKUP PRCM_REG32(0x420) | |
125 | #define CM_AUTOIDLE_WKUP PRCM_REG32(0x430) | |
126 | #define CM_CLKSEL_WKUP PRCM_REG32(0x440) | |
127 | #define RM_RSTCTRL_WKUP PRCM_REG32(0x450) | |
128 | #define RM_RSTTIME_WKUP PRCM_REG32(0x454) | |
129 | #define RM_RSTST_WKUP PRCM_REG32(0x458) | |
130 | #define PM_WKEN_WKUP PRCM_REG32(0x4A0) | |
131 | #define PM_WKST_WKUP PRCM_REG32(0x4B0) | |
132 | ||
133 | /* CLOCKS */ | |
134 | #define CM_CLKEN_PLL PRCM_REG32(0x500) | |
135 | #define CM_IDLEST_CKGEN PRCM_REG32(0x520) | |
136 | #define CM_AUTOIDLE_PLL PRCM_REG32(0x530) | |
137 | #define CM_CLKSEL1_PLL PRCM_REG32(0x540) | |
138 | #define CM_CLKSEL2_PLL PRCM_REG32(0x544) | |
139 | ||
140 | /* DSP */ | |
141 | #define CM_FCLKEN_DSP PRCM_REG32(0x800) | |
142 | #define CM_ICLKEN_DSP PRCM_REG32(0x810) | |
143 | #define CM_IDLEST_DSP PRCM_REG32(0x820) | |
144 | #define CM_AUTOIDLE_DSP PRCM_REG32(0x830) | |
145 | #define CM_CLKSEL_DSP PRCM_REG32(0x840) | |
146 | #define CM_CLKSTCTRL_DSP PRCM_REG32(0x848) | |
147 | #define RM_RSTCTRL_DSP PRCM_REG32(0x850) | |
148 | #define RM_RSTST_DSP PRCM_REG32(0x858) | |
149 | #define PM_WKEN_DSP PRCM_REG32(0x8A0) | |
150 | #define PM_WKDEP_DSP PRCM_REG32(0x8C8) | |
151 | #define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0) | |
152 | #define PM_PWSTST_DSP PRCM_REG32(0x8E4) | |
153 | #define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0) | |
154 | #define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4) | |
155 | ||
156 | /* IVA */ | |
157 | #define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8) | |
158 | #define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC) | |
159 | ||
160 | /* Modem on 2430 */ | |
161 | #define CM_FCLKEN_MDM PRCM_REG32(0xC00) | |
162 | #define CM_ICLKEN_MDM PRCM_REG32(0xC10) | |
163 | #define CM_IDLEST_MDM PRCM_REG32(0xC20) | |
b824efae | 164 | #define CM_AUTOIDLE_MDM PRCM_REG32(0xC30) |
1dbae815 | 165 | #define CM_CLKSEL_MDM PRCM_REG32(0xC40) |
b824efae TL |
166 | #define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48) |
167 | #define RM_RSTCTRL_MDM PRCM_REG32(0xC50) | |
168 | #define RM_RSTST_MDM PRCM_REG32(0xC58) | |
169 | #define PM_WKEN_MDM PRCM_REG32(0xCA0) | |
170 | #define PM_WKST_MDM PRCM_REG32(0xCB0) | |
171 | #define PM_WKDEP_MDM PRCM_REG32(0xCC8) | |
172 | #define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0) | |
173 | #define PM_PWSTST_MDM PRCM_REG32(0xCE4) | |
174 | ||
175 | #define OMAP24XX_L4_IO_BASE 0x48000000 | |
176 | ||
177 | #define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000) | |
1dbae815 TL |
178 | #define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) |
179 | ||
b824efae TL |
180 | #define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000) |
181 | #define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset)) | |
1dbae815 | 182 | |
b824efae TL |
183 | /* FIXME: Move these to timer code */ |
184 | #define GPT1_BASE (0x48028000) | |
1dbae815 TL |
185 | #define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) |
186 | ||
187 | /* Misc sysconfig */ | |
188 | #define DISPC_SYSCONFIG DISP_REG32(0x410) | |
b824efae | 189 | #define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000) |
1dbae815 | 190 | #define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) |
b824efae TL |
191 | #define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10) |
192 | #define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010) | |
193 | ||
194 | #define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10) | |
195 | #define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C) | |
196 | #define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C) | |
1dbae815 | 197 | #define GPMC_SYSCONFIG GPMC_REG32(0x010) |
b824efae TL |
198 | #define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010) |
199 | #define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054) | |
200 | #define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054) | |
201 | #define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054) | |
202 | #define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10) | |
203 | #define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000) | |
204 | #define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10) | |
205 | #define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010) | |
1dbae815 TL |
206 | |
207 | /* rkw - good cannidates for PM_ to start what nm was trying */ | |
b824efae TL |
208 | #define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000) |
209 | #define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000) | |
210 | #define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000) | |
211 | #define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000) | |
212 | #define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000) | |
213 | #define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000) | |
214 | #define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000) | |
215 | #define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000) | |
216 | #define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000) | |
217 | #define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000) | |
218 | #define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000) | |
219 | ||
220 | /* FIXME: Move these to timer code */ | |
1dbae815 TL |
221 | #define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) |
222 | #define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) | |
223 | #define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) | |
224 | #define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10) | |
225 | #define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10) | |
226 | #define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10) | |
227 | #define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10) | |
228 | #define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10) | |
229 | #define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10) | |
230 | #define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10) | |
231 | #define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) | |
232 | #define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) | |
233 | ||
b824efae TL |
234 | /* FIXME: Move these to gpio code */ |
235 | #define OMAP24XX_GPIO_BASE 0x48018000 | |
236 | #define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1))) | |
237 | ||
238 | #define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10)) | |
239 | #define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10)) | |
240 | #define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10)) | |
241 | #define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10)) | |
1dbae815 | 242 | |
b824efae TL |
243 | #if defined(CONFIG_ARCH_OMAP243X) |
244 | #define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10)) | |
245 | #endif | |
1dbae815 TL |
246 | |
247 | /* GP TIMER 1 */ | |
248 | #define GPTIMER1_TISTAT GPT1_REG32(0x014) | |
249 | #define GPTIMER1_TISR GPT1_REG32(0x018) | |
250 | #define GPTIMER1_TIER GPT1_REG32(0x01C) | |
251 | #define GPTIMER1_TWER GPT1_REG32(0x020) | |
252 | #define GPTIMER1_TCLR GPT1_REG32(0x024) | |
253 | #define GPTIMER1_TCRR GPT1_REG32(0x028) | |
254 | #define GPTIMER1_TLDR GPT1_REG32(0x02C) | |
255 | #define GPTIMER1_TTGR GPT1_REG32(0x030) | |
256 | #define GPTIMER1_TWPS GPT1_REG32(0x034) | |
257 | #define GPTIMER1_TMAR GPT1_REG32(0x038) | |
258 | #define GPTIMER1_TCAR1 GPT1_REG32(0x03C) | |
259 | #define GPTIMER1_TSICR GPT1_REG32(0x040) | |
260 | #define GPTIMER1_TCAR2 GPT1_REG32(0x044) | |
261 | ||
262 | /* rkw -- base fix up please... */ | |
b824efae | 263 | #define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018) |
1dbae815 TL |
264 | |
265 | /* SDRC */ | |
b824efae TL |
266 | #define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060) |
267 | #define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064) | |
268 | #define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068) | |
269 | #define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C) | |
270 | #define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070) | |
271 | #define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084) | |
1dbae815 TL |
272 | |
273 | /* GPIO 1 */ | |
274 | #define GPIO1_BASE GPIOX_BASE(1) | |
275 | #define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset)) | |
276 | #define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C) | |
277 | #define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018) | |
278 | #define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C) | |
279 | #define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028) | |
280 | #define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020) | |
281 | #define GPIO1_RISINGDETECT GPIO1_REG32(0x048) | |
282 | #define GPIO1_DATAIN GPIO1_REG32(0x038) | |
283 | #define GPIO1_OE GPIO1_REG32(0x034) | |
284 | #define GPIO1_DATAOUT GPIO1_REG32(0x03C) | |
285 | ||
286 | /* GPIO2 */ | |
287 | #define GPIO2_BASE GPIOX_BASE(2) | |
288 | #define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset)) | |
289 | #define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C) | |
290 | #define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018) | |
291 | #define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C) | |
292 | #define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028) | |
293 | #define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020) | |
294 | #define GPIO2_RISINGDETECT GPIO2_REG32(0x048) | |
295 | #define GPIO2_DATAIN GPIO2_REG32(0x038) | |
296 | #define GPIO2_OE GPIO2_REG32(0x034) | |
297 | #define GPIO2_DATAOUT GPIO2_REG32(0x03C) | |
b824efae TL |
298 | #define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050) |
299 | #define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054) | |
1dbae815 TL |
300 | |
301 | /* GPIO 3 */ | |
302 | #define GPIO3_BASE GPIOX_BASE(3) | |
303 | #define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset)) | |
304 | #define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C) | |
305 | #define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018) | |
306 | #define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C) | |
307 | #define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028) | |
308 | #define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020) | |
309 | #define GPIO3_RISINGDETECT GPIO3_REG32(0x048) | |
310 | #define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C) | |
311 | #define GPIO3_DATAIN GPIO3_REG32(0x038) | |
312 | #define GPIO3_OE GPIO3_REG32(0x034) | |
313 | #define GPIO3_DATAOUT GPIO3_REG32(0x03C) | |
314 | #define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) | |
315 | #define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) | |
b824efae TL |
316 | #define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) |
317 | #define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) | |
1dbae815 TL |
318 | |
319 | /* GPIO 4 */ | |
320 | #define GPIO4_BASE GPIOX_BASE(4) | |
321 | #define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset)) | |
322 | #define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C) | |
323 | #define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018) | |
324 | #define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C) | |
325 | #define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028) | |
326 | #define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020) | |
327 | #define GPIO4_RISINGDETECT GPIO4_REG32(0x048) | |
328 | #define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C) | |
329 | #define GPIO4_DATAIN GPIO4_REG32(0x038) | |
330 | #define GPIO4_OE GPIO4_REG32(0x034) | |
331 | #define GPIO4_DATAOUT GPIO4_REG32(0x03C) | |
332 | #define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) | |
333 | #define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) | |
334 | ||
b824efae TL |
335 | #if defined(CONFIG_ARCH_OMAP243X) |
336 | /* GPIO 5 */ | |
337 | #define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset))) | |
338 | #define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C) | |
339 | #define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018) | |
340 | #define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C) | |
341 | #define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028) | |
342 | #define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020) | |
343 | #define GPIO5_RISINGDETECT GPIO5_REG32(0x048) | |
344 | #define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C) | |
345 | #define GPIO5_DATAIN GPIO5_REG32(0x038) | |
346 | #define GPIO5_OE GPIO5_REG32(0x034) | |
347 | #define GPIO5_DATAOUT GPIO5_REG32(0x03C) | |
348 | #define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050) | |
349 | #define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054) | |
350 | #endif | |
1dbae815 TL |
351 | |
352 | /* IO CONFIG */ | |
b824efae TL |
353 | #define OMAP24XX_CTRL_BASE (L4_24XX_BASE) |
354 | #define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset)) | |
1dbae815 TL |
355 | |
356 | #define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) | |
357 | #define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) | |
358 | #define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8) | |
359 | #define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) | |
360 | #define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) | |
361 | #define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) | |
b824efae | 362 | #define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */ |
1dbae815 TL |
363 | #define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) |
364 | #define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) | |
b824efae TL |
365 | #define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */ |
366 | #define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */ | |
1dbae815 TL |
367 | |
368 | /* CONTROL */ | |
369 | #define CONTROL_DEVCONF CONTROL_REG32(0x274) | |
b824efae | 370 | #define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8) |
1dbae815 TL |
371 | |
372 | /* INTERRUPT CONTROLLER */ | |
b824efae | 373 | #define INTC_BASE ((L4_24XX_BASE) + 0xfe000) |
1dbae815 TL |
374 | #define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) |
375 | ||
376 | #define INTC1_U_BASE INTC_REG32(0x000) | |
377 | #define INTC_MIR0 INTC_REG32(0x084) | |
378 | #define INTC_MIR_SET0 INTC_REG32(0x08C) | |
379 | #define INTC_MIR_CLEAR0 INTC_REG32(0x088) | |
380 | #define INTC_ISR_CLEAR0 INTC_REG32(0x094) | |
381 | #define INTC_MIR1 INTC_REG32(0x0A4) | |
382 | #define INTC_MIR_SET1 INTC_REG32(0x0AC) | |
383 | #define INTC_MIR_CLEAR1 INTC_REG32(0x0A8) | |
384 | #define INTC_ISR_CLEAR1 INTC_REG32(0x0B4) | |
385 | #define INTC_MIR2 INTC_REG32(0x0C4) | |
386 | #define INTC_MIR_SET2 INTC_REG32(0x0CC) | |
387 | #define INTC_MIR_CLEAR2 INTC_REG32(0x0C8) | |
388 | #define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) | |
389 | #define INTC_SIR_IRQ INTC_REG32(0x040) | |
390 | #define INTC_CONTROL INTC_REG32(0x048) | |
b824efae TL |
391 | #define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */ |
392 | #define INTC_ILR30 INTC_REG32(0x178) | |
393 | #define INTC_ILR31 INTC_REG32(0x17C) | |
1dbae815 | 394 | #define INTC_ILR32 INTC_REG32(0x180) |
b824efae TL |
395 | #define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */ |
396 | #define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */ | |
1dbae815 TL |
397 | |
398 | /* RAM FIREWALL */ | |
399 | #define RAMFW_BASE (0x68005000) | |
400 | #define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset)) | |
401 | ||
402 | #define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048) | |
403 | #define RAMFW_READPERM0 RAMFW_REG32(0x050) | |
404 | #define RAMFW_WRITEPERM0 RAMFW_REG32(0x058) | |
405 | ||
406 | /* GPMC CS1 FPGA ON USER INTERFACE MODULE */ | |
407 | //#define DEBUG_BOARD_LED_REGISTER 0x04000014 | |
408 | ||
409 | /* GPMC CS0 */ | |
410 | #define GPMC_CONFIG1_0 GPMC_REG32(0x060) | |
411 | #define GPMC_CONFIG2_0 GPMC_REG32(0x064) | |
412 | #define GPMC_CONFIG3_0 GPMC_REG32(0x068) | |
413 | #define GPMC_CONFIG4_0 GPMC_REG32(0x06C) | |
414 | #define GPMC_CONFIG5_0 GPMC_REG32(0x070) | |
415 | #define GPMC_CONFIG6_0 GPMC_REG32(0x074) | |
416 | #define GPMC_CONFIG7_0 GPMC_REG32(0x078) | |
417 | ||
b824efae TL |
418 | /* GPMC CS1 */ |
419 | #define GPMC_CONFIG1_1 GPMC_REG32(0x090) | |
420 | #define GPMC_CONFIG2_1 GPMC_REG32(0x094) | |
421 | #define GPMC_CONFIG3_1 GPMC_REG32(0x098) | |
422 | #define GPMC_CONFIG4_1 GPMC_REG32(0x09C) | |
423 | #define GPMC_CONFIG5_1 GPMC_REG32(0x0a0) | |
424 | #define GPMC_CONFIG6_1 GPMC_REG32(0x0a4) | |
425 | #define GPMC_CONFIG7_1 GPMC_REG32(0x0a8) | |
426 | ||
427 | /* GPMC CS3 */ | |
428 | #define GPMC_CONFIG1_3 GPMC_REG32(0x0F0) | |
429 | #define GPMC_CONFIG2_3 GPMC_REG32(0x0F4) | |
430 | #define GPMC_CONFIG3_3 GPMC_REG32(0x0F8) | |
431 | #define GPMC_CONFIG4_3 GPMC_REG32(0x0FC) | |
432 | #define GPMC_CONFIG5_3 GPMC_REG32(0x100) | |
433 | #define GPMC_CONFIG6_3 GPMC_REG32(0x104) | |
434 | #define GPMC_CONFIG7_3 GPMC_REG32(0x108) | |
435 | ||
1dbae815 TL |
436 | /* DSS */ |
437 | #define DSS_CONTROL DISP_REG32(0x040) | |
438 | #define DISPC_CONTROL DISP_REG32(0x440) | |
439 | #define DISPC_SYSSTATUS DISP_REG32(0x414) | |
440 | #define DISPC_IRQSTATUS DISP_REG32(0x418) | |
441 | #define DISPC_IRQENABLE DISP_REG32(0x41C) | |
442 | #define DISPC_CONFIG DISP_REG32(0x444) | |
443 | #define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C) | |
444 | #define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450) | |
445 | #define DISPC_TRANS_COLOR0 DISP_REG32(0x454) | |
446 | #define DISPC_TRANS_COLOR1 DISP_REG32(0x458) | |
447 | #define DISPC_LINE_NUMBER DISP_REG32(0x460) | |
448 | #define DISPC_TIMING_H DISP_REG32(0x464) | |
449 | #define DISPC_TIMING_V DISP_REG32(0x468) | |
450 | #define DISPC_POL_FREQ DISP_REG32(0x46C) | |
451 | #define DISPC_DIVISOR DISP_REG32(0x470) | |
452 | #define DISPC_SIZE_DIG DISP_REG32(0x478) | |
453 | #define DISPC_SIZE_LCD DISP_REG32(0x47C) | |
454 | #define DISPC_GFX_BA0 DISP_REG32(0x480) | |
455 | #define DISPC_GFX_BA1 DISP_REG32(0x484) | |
456 | #define DISPC_GFX_POSITION DISP_REG32(0x488) | |
457 | #define DISPC_GFX_SIZE DISP_REG32(0x48C) | |
458 | #define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0) | |
459 | #define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4) | |
460 | #define DISPC_GFX_ROW_INC DISP_REG32(0x4AC) | |
461 | #define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0) | |
462 | #define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4) | |
463 | #define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8) | |
464 | #define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4) | |
465 | #define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) | |
466 | #define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) | |
467 | ||
b824efae TL |
468 | /* HSUSB Suspend */ |
469 | #define HSUSB_CTRL __REG8(0x480AC001) | |
470 | #define USBOTG_POWER __REG32(0x480AC000) | |
471 | ||
472 | /* HS MMC */ | |
473 | #define MMCHS1_SYSCONFIG __REG32(0x4809C010) | |
474 | #define MMCHS2_SYSCONFIG __REG32(0x480b4010) | |
1dbae815 | 475 | |
b824efae | 476 | #endif /* __ASSEMBLER__ */ |
1dbae815 TL |
477 | |
478 | #endif | |
479 | ||
480 | ||
481 | ||
482 | ||
483 |