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69d88a00 | 1 | /* |
59fb659b | 2 | * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions |
69d88a00 | 3 | * |
d9a16f9a | 4 | * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. |
0be1621a | 5 | * Copyright (C) 2010 Nokia Corporation |
69d88a00 | 6 | * |
59fb659b | 7 | * Paul Walmsley |
69d88a00 PW |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
59fb659b PW |
13 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H |
14 | #define __ARCH_ARM_MACH_OMAP2_PRM_H | |
69d88a00 PW |
15 | |
16 | #include "prcm-common.h" | |
17 | ||
d9a16f9a PW |
18 | # ifndef __ASSEMBLER__ |
19 | extern void __iomem *prm_base; | |
20 | extern void omap2_set_globals_prm(void __iomem *prm); | |
21 | # endif | |
22 | ||
b13159af PW |
23 | |
24 | /* | |
25 | * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP | |
26 | * module to softreset | |
27 | */ | |
28 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
29 | ||
30 | /* | |
31 | * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP | |
32 | * submodule to exit hardreset | |
33 | */ | |
34 | #define MAX_MODULE_HARDRESET_WAIT 10000 | |
35 | ||
36 | /* | |
37 | * Register bitfields | |
38 | */ | |
39 | ||
69d88a00 PW |
40 | /* |
41 | * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP | |
42 | * | |
43 | * 2430: PM_PWSTST_MDM | |
44 | * | |
45 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | |
46 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | |
47 | * PM_PWSTST_NEON | |
48 | */ | |
2fd0f75c | 49 | #define OMAP_INTRANSITION_MASK (1 << 20) |
69d88a00 PW |
50 | |
51 | ||
52 | /* | |
53 | * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP | |
54 | * | |
55 | * 2430: PM_PWSTST_MDM | |
56 | * | |
57 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | |
58 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | |
59 | * PM_PWSTST_NEON | |
60 | */ | |
61 | #define OMAP_POWERSTATEST_SHIFT 0 | |
62 | #define OMAP_POWERSTATEST_MASK (0x3 << 0) | |
63 | ||
69d88a00 PW |
64 | /* |
65 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | |
66 | * PM_PWSTCTRL_DSP, PM_PWSTST_MPU | |
67 | * | |
68 | * 2430: PM_PWSTCTRL_MDM shared bits | |
69 | * | |
70 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, | |
71 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | |
72 | * PM_PWSTCTRL_NEON shared bits | |
73 | */ | |
74 | #define OMAP_POWERSTATE_SHIFT 0 | |
75 | #define OMAP_POWERSTATE_MASK (0x3 << 0) | |
76 | ||
2bb2a5d3 PW |
77 | /* |
78 | * Standardized OMAP reset source bits | |
79 | * | |
80 | * To the extent these happen to match the hardware register bit | |
81 | * shifts, it's purely coincidental. Used by omap-wdt.c. | |
82 | * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever | |
83 | * there are any bits remaining in the global PRM_RSTST register that | |
84 | * haven't been identified, or when the PRM code for the current SoC | |
85 | * doesn't know how to interpret the register. | |
86 | */ | |
87 | #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 | |
88 | #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 | |
89 | #define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2 | |
90 | #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 | |
91 | #define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4 | |
92 | #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 | |
93 | #define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6 | |
94 | #define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7 | |
95 | #define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8 | |
96 | #define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9 | |
97 | #define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10 | |
98 | #define OMAP_C2C_RST_SRC_ID_SHIFT 11 | |
99 | #define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12 | |
100 | ||
e24c3573 PW |
101 | #ifndef __ASSEMBLER__ |
102 | ||
2bb2a5d3 PW |
103 | /** |
104 | * struct prm_reset_src_map - map register bitshifts to standard bitshifts | |
105 | * @reg_shift: bitshift in the PRM reset source register | |
106 | * @std_shift: bitshift equivalent in the standard reset source list | |
107 | * | |
108 | * The fields are signed because -1 is used as a terminator. | |
109 | */ | |
110 | struct prm_reset_src_map { | |
111 | s8 reg_shift; | |
112 | s8 std_shift; | |
113 | }; | |
114 | ||
e24c3573 PW |
115 | /** |
116 | * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations | |
2bb2a5d3 | 117 | * @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl |
e24c3573 | 118 | */ |
2bb2a5d3 PW |
119 | struct prm_ll_data { |
120 | u32 (*read_reset_sources)(void); | |
121 | }; | |
e24c3573 PW |
122 | |
123 | extern int prm_register(struct prm_ll_data *pld); | |
124 | extern int prm_unregister(struct prm_ll_data *pld); | |
125 | ||
2bb2a5d3 PW |
126 | extern u32 prm_read_reset_sources(void); |
127 | ||
e24c3573 | 128 | #endif |
69d88a00 | 129 | |
2bb2a5d3 | 130 | |
69d88a00 | 131 | #endif |