[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-omap2 / prm44xx.c

/*
 * OMAP4 PRM module functions
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 * Benoît Cousson
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include <plat/common.h>
#include <plat/cpu.h>
#include <plat/prcm.h>

#include "vp.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
#include "prminst44xx.h"

/* PRM low-level functions */

/* Read a register in a CM/PRM instance in the PRM module */
u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
{
	return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
}

/* Write into a register in a CM/PRM instance in the PRM module */
void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
{
	__raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
}

/* Read-modify-write a register in a PRM module. Caller must lock */
u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
{
	u32 v;

	v = omap4_prm_read_inst_reg(inst, reg);
	v &= ~mask;
	v |= bits;
	omap4_prm_write_inst_reg(v, inst, reg);

	return v;
}

/* PRM VP */

/*
 * struct omap4_vp - OMAP4 VP register access description.
 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 */
struct omap4_vp {
	u32 irqstatus_mpu;
	u32 tranxdone_status;
};

static struct omap4_vp omap4_vp[] = {
	[OMAP4_VP_VDD_MPU_ID] = {
		.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
		.tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
	},
	[OMAP4_VP_VDD_IVA_ID] = {
		.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
		.tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
	},
	[OMAP4_VP_VDD_CORE_ID] = {
		.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
		.tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
	},
};

u32 omap4_prm_vp_check_txdone(u8 vp_id)
{
	struct omap4_vp *vp = &omap4_vp[vp_id];
	u32 irqstatus;

	irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
						OMAP4430_PRM_OCP_SOCKET_INST,
						vp->irqstatus_mpu);
	return irqstatus & vp->tranxdone_status;
}

void omap4_prm_vp_clear_txdone(u8 vp_id)
{
	struct omap4_vp *vp = &omap4_vp[vp_id];

	omap4_prminst_write_inst_reg(vp->tranxdone_status,
				     OMAP4430_PRM_PARTITION,
				     OMAP4430_PRM_OCP_SOCKET_INST,
				     vp->irqstatus_mpu);
};

u32 omap4_prm_vcvp_read(u8 offset)
{
	return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
					   OMAP4430_PRM_DEVICE_INST, offset);
}

void omap4_prm_vcvp_write(u32 val, u8 offset)
{
	omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
				     OMAP4430_PRM_DEVICE_INST, offset);
}

u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
{
	return omap4_prminst_rmw_inst_reg_bits(mask, bits,
					       OMAP4430_PRM_PARTITION,
					       OMAP4430_PRM_DEVICE_INST,
					       offset);
}

static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
{
	u32 mask, st;

	/* XXX read mask from RAM? */
	mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
	st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);

	return mask & st;
}

/**
 * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 * @events: ptr to two consecutive u32s, preallocated by caller
 *
 * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
 * MPU IRQs, and store the result into the two u32s pointed to by @events.
 * No return value.
 */
void omap44xx_prm_read_pending_irqs(unsigned long *events)
{
	events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
					  OMAP4_PRM_IRQSTATUS_MPU_OFFSET);

	events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
					  OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
}

/**
 * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 *
 * Force any buffered writes to the PRM IP block to complete.  Needed
 * by the PRM IRQ handler, which reads and writes directly to the IP
 * block, to avoid race conditions after acknowledging or clearing IRQ
 * bits.  No return value.
 */
void omap44xx_prm_ocp_barrier(void)
{
	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
				OMAP4_REVISION_PRM_OFFSET);
}

/**
 * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 *
 * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
 * @saved_mask.  @saved_mask must be allocated by the caller.
 * Intended to be used in the PRM interrupt handler suspend callback.
 * The OCP barrier is needed to ensure the write to disable PRM
 * interrupts reaches the PRM before returning; otherwise, spurious
 * interrupts might occur.  No return value.
 */
void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
{
	saved_mask[0] =
		omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
					OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
	saved_mask[1] =
		omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
					OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);

	omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
				 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
	omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);

	/* OCP barrier */
	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
				OMAP4_REVISION_PRM_OFFSET);
}

/**
 * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 *
 * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
 * @saved_mask.  Intended to be used in the PRM interrupt handler resume
 * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
 * No OCP barrier should be needed here; any pending PRM interrupts will fire
 * once the writes reach the PRM.  No return value.
 */
void omap44xx_prm_restore_irqen(u32 *saved_mask)
{
	omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
				 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
	omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
}
Commit	Line	Data
0be1621a BC	1	/*
	2	* OMAP4 PRM module functions
	3	*
eaac329d	4	* Copyright (C) 2011 Texas Instruments, Inc.
0be1621a BC	5	* Copyright (C) 2010 Nokia Corporation
	6	* Benoît Cousson
	7	* Paul Walmsley
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/delay.h>
	16	#include <linux/errno.h>
	17	#include <linux/err.h>
2ace831f	18	#include <linux/io.h>
0be1621a BC	19
	20	#include <plat/common.h>
	21	#include <plat/cpu.h>
	22	#include <plat/prcm.h>
	23
58aaa599	24	#include "vp.h"
d198b514	25	#include "prm44xx.h"
0be1621a	26	#include "prm-regbits-44xx.h"
4bb73ade KH	27	#include "prcm44xx.h"
4bb73ade KH	28	#include "prminst44xx.h"
0be1621a	29
2ace831f PW	30	/* PRM low-level functions */
	31
	32	/* Read a register in a CM/PRM instance in the PRM module */
	33	u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
	34	{
	35	return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
	36	}
	37
	38	/* Write into a register in a CM/PRM instance in the PRM module */
	39	void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
	40	{
	41	__raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
	42	}
	43
	44	/* Read-modify-write a register in a PRM module. Caller must lock */
	45	u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
	46	{
	47	u32 v;
	48
	49	v = omap4_prm_read_inst_reg(inst, reg);
	50	v &= ~mask;
	51	v \|= bits;
	52	omap4_prm_write_inst_reg(v, inst, reg);
	53
	54	return v;
	55	}
58aaa599 KH	56
	57	/* PRM VP */
	58
	59	/*
	60	* struct omap4_vp - OMAP4 VP register access description.
	61	* @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
	62	* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
	63	*/
	64	struct omap4_vp {
	65	u32 irqstatus_mpu;
	66	u32 tranxdone_status;
	67	};
	68
	69	static struct omap4_vp omap4_vp[] = {
	70	[OMAP4_VP_VDD_MPU_ID] = {
	71	.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
	72	.tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
	73	},
	74	[OMAP4_VP_VDD_IVA_ID] = {
	75	.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
	76	.tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
	77	},
	78	[OMAP4_VP_VDD_CORE_ID] = {
	79	.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
	80	.tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
	81	},
	82	};
	83
	84	u32 omap4_prm_vp_check_txdone(u8 vp_id)
	85	{
	86	struct omap4_vp *vp = &omap4_vp[vp_id];
	87	u32 irqstatus;
	88
	89	irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	90	OMAP4430_PRM_OCP_SOCKET_INST,
	91	vp->irqstatus_mpu);
	92	return irqstatus & vp->tranxdone_status;
	93	}
	94
	95	void omap4_prm_vp_clear_txdone(u8 vp_id)
	96	{
	97	struct omap4_vp *vp = &omap4_vp[vp_id];
	98
	99	omap4_prminst_write_inst_reg(vp->tranxdone_status,
	100	OMAP4430_PRM_PARTITION,
	101	OMAP4430_PRM_OCP_SOCKET_INST,
	102	vp->irqstatus_mpu);
	103	};
4bb73ade KH	104
	105	u32 omap4_prm_vcvp_read(u8 offset)
	106	{
	107	return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	108	OMAP4430_PRM_DEVICE_INST, offset);
	109	}
	110
	111	void omap4_prm_vcvp_write(u32 val, u8 offset)
	112	{
	113	omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
	114	OMAP4430_PRM_DEVICE_INST, offset);
	115	}
	116
	117	u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
	118	{
	119	return omap4_prminst_rmw_inst_reg_bits(mask, bits,
	120	OMAP4430_PRM_PARTITION,
	121	OMAP4430_PRM_DEVICE_INST,
	122	offset);
	123	}
26c98c56 PW	124
	125	static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
	126	{
	127	u32 mask, st;
	128
	129	/* XXX read mask from RAM? */
	130	mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
	131	st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);
	132
	133	return mask & st;
	134	}
	135
	136	/**
	137	* omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
	138	* @events: ptr to two consecutive u32s, preallocated by caller
	139	*
	140	* Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
	141	* MPU IRQs, and store the result into the two u32s pointed to by @events.
	142	* No return value.
	143	*/
	144	void omap44xx_prm_read_pending_irqs(unsigned long *events)
	145	{
	146	events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
	147	OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
	148
	149	events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
	150	OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
	151	}
	152
	153	/**
	154	* omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
	155	*
	156	* Force any buffered writes to the PRM IP block to complete. Needed
	157	* by the PRM IRQ handler, which reads and writes directly to the IP
	158	* block, to avoid race conditions after acknowledging or clearing IRQ
	159	* bits. No return value.
	160	*/
	161	void omap44xx_prm_ocp_barrier(void)
	162	{
	163	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
	164	OMAP4_REVISION_PRM_OFFSET);
	165	}
91285b6f TK	166
	167	/**
	168	* omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
	169	* @saved_mask: ptr to a u32 array to save IRQENABLE bits
	170	*
	171	* Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
	172	* @saved_mask. @saved_mask must be allocated by the caller.
	173	* Intended to be used in the PRM interrupt handler suspend callback.
	174	* The OCP barrier is needed to ensure the write to disable PRM
	175	* interrupts reaches the PRM before returning; otherwise, spurious
	176	* interrupts might occur. No return value.
	177	*/
	178	void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
	179	{
	180	saved_mask[0] =
	181	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
	182	OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
	183	saved_mask[1] =
	184	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
	185	OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
	186
	187	omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
	188	OMAP4_PRM_IRQENABLE_MPU_OFFSET);
	189	omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
	190	OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
	191
	192	/* OCP barrier */
	193	omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
	194	OMAP4_REVISION_PRM_OFFSET);
	195	}
	196
	197	/**
	198	* omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
	199	* @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
	200	*
	201	* Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
	202	* @saved_mask. Intended to be used in the PRM interrupt handler resume
	203	* callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
	204	* No OCP barrier should be needed here; any pending PRM interrupts will fire
	205	* once the writes reach the PRM. No return value.
	206	*/
	207	void omap44xx_prm_restore_irqen(u32 *saved_mask)
	208	{
	209	omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
	210	OMAP4_PRM_IRQENABLE_MPU_OFFSET);
	211	omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
	212	OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
	213	}