[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / prminst44xx.c

/*
 * OMAP4 PRM instance functions
 *
 * Copyright (C) 2009 Nokia Corporation
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include "iomap.h"
#include "common.h"
#include "prcm-common.h"
#include "prm44xx.h"
#include "prm54xx.h"
#include "prm7xx.h"
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
#include "prcm43xx.h"
#include "prcm_mpu44xx.h"
#include "soc.h"

static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];

static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;

/**
 * omap_prm_base_init - Populates the prm partitions
 *
 * Populates the base addresses of the _prm_bases
 * array used for read/write of prm module registers.
 */
void omap_prm_base_init(void)
{
	memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
	       sizeof(prm_base));
	memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
	       sizeof(prcm_mpu_base));
}

s32 omap4_prmst_get_prm_dev_inst(void)
{
	return prm_dev_inst;
}

void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
{
	prm_dev_inst = dev_inst;
}

/* Read a register in a PRM instance */
u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{
	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
	       part == OMAP4430_INVALID_PRCM_PARTITION ||
	       !_prm_bases[part].va);
	return readl_relaxed(_prm_bases[part].va + inst + idx);
}

/* Write into a register in a PRM instance */
void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
{
	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
	       part == OMAP4430_INVALID_PRCM_PARTITION ||
	       !_prm_bases[part].va);
	writel_relaxed(val, _prm_bases[part].va + inst + idx);
}

/* Read-modify-write a register in PRM. Caller must lock */
u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
				    u16 idx)
{
	u32 v;

	v = omap4_prminst_read_inst_reg(part, inst, idx);
	v &= ~mask;
	v |= bits;
	omap4_prminst_write_inst_reg(v, part, inst, idx);

	return v;
}

/**
 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
 * submodules contained in the hwmod module
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @shift: register bit shift corresponding to the reset line to check
 *
 * Returns 1 if the (sub)module hardreset line is currently asserted,
 * 0 if the (sub)module hardreset line is not currently asserted, or
 * -EINVAL upon parameter error.
 */
int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
					u16 rstctrl_offs)
{
	u32 v;

	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
	v &= 1 << shift;
	v >>= shift;

	return v;
}

/**
 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @shift: register bit shift corresponding to the reset line to assert
 *
 * Some IPs like dsp, ipu or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
 * IP.  These modules may have multiple hard-reset lines that reset
 * different 'submodules' inside the IP block.  This function will
 * place the submodule into reset.  Returns 0 upon success or -EINVAL
 * upon an argument error.
 */
int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
				   u16 rstctrl_offs)
{
	u32 mask = 1 << shift;

	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);

	return 0;
}

/**
 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
 * wait
 * @shift: register bit shift corresponding to the reset line to deassert
 * @st_shift: status bit offset corresponding to the reset line
 * @part: PRM partition
 * @inst: PRM instance offset
 * @rstctrl_offs: reset register offset
 * @rstst_offs: reset status register offset
 *
 * Some IPs like dsp, ipu or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
 * IP.  These modules may have multiple hard-reset lines that reset
 * different 'submodules' inside the IP block.  This function will
 * take the submodule out of reset and wait until the PRCM indicates
 * that the reset has completed before returning.  Returns 0 upon success or
 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 * of reset, or -EBUSY if the submodule did not exit reset promptly.
 */
int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
				     u16 rstctrl_offs, u16 rstst_offs)
{
	int c;
	u32 mask = 1 << shift;
	u32 st_mask = 1 << st_shift;

	/* Check the current status to avoid de-asserting the line twice */
	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
						rstctrl_offs) == 0)
		return -EEXIST;

	/* Clear the reset status by writing 1 to the status bit */
	omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
					rstst_offs);
	/* de-assert the reset control line */
	omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
	/* wait the status to be set */
	omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
							      inst, rstst_offs),
			  MAX_MODULE_HARDRESET_WAIT, c);

	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}


void omap4_prminst_global_warm_sw_reset(void)
{
	u32 v;
	s32 inst = omap4_prmst_get_prm_dev_inst();

	if (inst == PRM_INSTANCE_UNKNOWN)
		return;

	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
					OMAP4_PRM_RSTCTRL_OFFSET);
	v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
				 inst, OMAP4_PRM_RSTCTRL_OFFSET);

	/* OCP barrier */
	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
				    inst, OMAP4_PRM_RSTCTRL_OFFSET);
}
Commit	Line	Data
2ace831f PW	1	/*
	2	* OMAP4 PRM instance functions
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
eaac329d	5	* Copyright (C) 2011 Texas Instruments, Inc.
2ace831f PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/errno.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18
ee0839c2	19	#include "iomap.h"
4e65331c	20	#include "common.h"
610eb8c2	21	#include "prcm-common.h"
2ace831f	22	#include "prm44xx.h"
1d597b07 RN	23	#include "prm54xx.h"
1d597b07 RN	24	#include "prm7xx.h"
2ace831f PW	25	#include "prminst44xx.h"
	26	#include "prm-regbits-44xx.h"
	27	#include "prcm44xx.h"
a7daf64a	28	#include "prcm43xx.h"
2ace831f	29	#include "prcm_mpu44xx.h"
1d597b07	30	#include "soc.h"
2ace831f	31
90129336	32	static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
610eb8c2	33
e3002d1a NM	34	static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
e3002d1a NM	35
610eb8c2 S	36	/**
	37	* omap_prm_base_init - Populates the prm partitions
	38	*
	39	* Populates the base addresses of the _prm_bases
	40	* array used for read/write of prm module registers.
	41	*/
	42	void omap_prm_base_init(void)
	43	{
90129336 TK	44	memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
	45	sizeof(prm_base));
	46	memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
	47	sizeof(prcm_mpu_base));
610eb8c2	48	}
2ace831f	49
e3002d1a NM	50	s32 omap4_prmst_get_prm_dev_inst(void)
e3002d1a NM	51	{
e3002d1a NM	52	return prm_dev_inst;
	53	}
	54
48e0c114 TK	55	void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
	56	{
	57	prm_dev_inst = dev_inst;
	58	}
	59
2ace831f PW	60	/* Read a register in a PRM instance */
	61	u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
	62	{
	63	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS \|\|
	64	part == OMAP4430_INVALID_PRCM_PARTITION \|\|
90129336 TK	65	!_prm_bases[part].va);
90129336 TK	66	return readl_relaxed(_prm_bases[part].va + inst + idx);
2ace831f PW	67	}
	68
	69	/* Write into a register in a PRM instance */
	70	void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
	71	{
	72	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS \|\|
	73	part == OMAP4430_INVALID_PRCM_PARTITION \|\|
90129336 TK	74	!_prm_bases[part].va);
90129336 TK	75	writel_relaxed(val, _prm_bases[part].va + inst + idx);
2ace831f PW	76	}
	77
	78	/* Read-modify-write a register in PRM. Caller must lock */
	79	u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
eaac329d	80	u16 idx)
2ace831f PW	81	{
	82	u32 v;
	83
	84	v = omap4_prminst_read_inst_reg(part, inst, idx);
	85	v &= ~mask;
	86	v \|= bits;
	87	omap4_prminst_write_inst_reg(v, part, inst, idx);
	88
	89	return v;
	90	}
eaac329d	91
eaac329d BC	92	/**
	93	* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
	94	* submodules contained in the hwmod module
	95	* @rstctrl_reg: RM_RSTCTRL register address for this module
	96	* @shift: register bit shift corresponding to the reset line to check
	97	*
	98	* Returns 1 if the (sub)module hardreset line is currently asserted,
	99	* 0 if the (sub)module hardreset line is not currently asserted, or
	100	* -EINVAL upon parameter error.
	101	*/
	102	int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
	103	u16 rstctrl_offs)
	104	{
	105	u32 v;
	106
	107	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
	108	v &= 1 << shift;
	109	v >>= shift;
	110
	111	return v;
	112	}
	113
	114	/**
	115	* omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
	116	* @rstctrl_reg: RM_RSTCTRL register address for this module
	117	* @shift: register bit shift corresponding to the reset line to assert
	118	*
	119	* Some IPs like dsp, ipu or iva contain processors that require an HW
	120	* reset line to be asserted / deasserted in order to fully enable the
	121	* IP. These modules may have multiple hard-reset lines that reset
	122	* different 'submodules' inside the IP block. This function will
	123	* place the submodule into reset. Returns 0 upon success or -EINVAL
	124	* upon an argument error.
	125	*/
	126	int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
	127	u16 rstctrl_offs)
	128	{
	129	u32 mask = 1 << shift;
	130
	131	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
	132
	133	return 0;
	134	}
	135
	136	/**
	137	* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
	138	* wait
eaac329d	139	* @shift: register bit shift corresponding to the reset line to deassert
4ebf5b28	140	* @st_shift: status bit offset corresponding to the reset line
37fb59d7 TK	141	* @part: PRM partition
	142	* @inst: PRM instance offset
	143	* @rstctrl_offs: reset register offset
4ebf5b28	144	* @rstst_offs: reset status register offset
eaac329d BC	145	*
	146	* Some IPs like dsp, ipu or iva contain processors that require an HW
	147	* reset line to be asserted / deasserted in order to fully enable the
	148	* IP. These modules may have multiple hard-reset lines that reset
	149	* different 'submodules' inside the IP block. This function will
	150	* take the submodule out of reset and wait until the PRCM indicates
	151	* that the reset has completed before returning. Returns 0 upon success or
	152	* -EINVAL upon an argument error, -EEXIST if the submodule was already out
	153	* of reset, or -EBUSY if the submodule did not exit reset promptly.
	154	*/
37fb59d7	155	int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
4ebf5b28	156	u16 rstctrl_offs, u16 rstst_offs)
eaac329d BC	157	{
	158	int c;
	159	u32 mask = 1 << shift;
4ebf5b28	160	u32 st_mask = 1 << st_shift;
eaac329d BC	161
	162	/* Check the current status to avoid de-asserting the line twice */
	163	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
	164	rstctrl_offs) == 0)
	165	return -EEXIST;
	166
	167	/* Clear the reset status by writing 1 to the status bit */
4ebf5b28	168	omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
eaac329d BC	169	rstst_offs);
	170	/* de-assert the reset control line */
	171	omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
	172	/* wait the status to be set */
4ebf5b28 TK	173	omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
4ebf5b28 TK	174	inst, rstst_offs),
eaac329d BC	175	MAX_MODULE_HARDRESET_WAIT, c);
	176
	177	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
	178	}
e54433f1 BC	179
	180
	181	void omap4_prminst_global_warm_sw_reset(void)
	182	{
	183	u32 v;
e3002d1a	184	s32 inst = omap4_prmst_get_prm_dev_inst();
1d597b07	185
e3002d1a	186	if (inst == PRM_INSTANCE_UNKNOWN)
1d597b07 RN	187	return;
1d597b07 RN	188
e3002d1a	189	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
1d597b07	190	OMAP4_PRM_RSTCTRL_OFFSET);
e54433f1 BC	191	v \|= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
e54433f1 BC	192	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
e3002d1a	193	inst, OMAP4_PRM_RSTCTRL_OFFSET);
e54433f1 BC	194
	195	/* OCP barrier */
	196	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
e3002d1a	197	inst, OMAP4_PRM_RSTCTRL_OFFSET);
e54433f1	198	}