[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-omap2 / serial.c

/*
 * arch/arm/mach-omap2/serial.c
 *
 * OMAP2 serial support.
 *
 * Copyright (C) 2005-2008 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * Major rework for PM support by Kevin Hilman
 *
 * Based off of arch/arm/mach-omap/omap1/serial.c
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <plat/common.h>
#include <plat/board.h>
#include <plat/clock.h>
#include <plat/control.h>

#include "prm.h"
#include "pm.h"
#include "prm-regbits-34xx.h"

#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV	0x52
#define UART_OMAP_WER		0x17	/* Wake-up enable register */

/*
 * NOTE: By default the serial timeout is disabled as it causes lost characters
 * over the serial ports. This means that the UART clocks will stay on until
 * disabled via sysfs. This also causes that any deeper omap sleep states are
 * blocked. 
 */
#define DEFAULT_TIMEOUT 0

struct omap_uart_state {
	int num;
	int can_sleep;
	struct timer_list timer;
	u32 timeout;

	void __iomem *wk_st;
	void __iomem *wk_en;
	u32 wk_mask;
	u32 padconf;

	struct clk *ick;
	struct clk *fck;
	int clocked;

	struct plat_serial8250_port *p;
	struct list_head node;
	struct platform_device pdev;

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
	int context_valid;

	/* Registers to be saved/restored for OFF-mode */
	u16 dll;
	u16 dlh;
	u16 ier;
	u16 sysc;
	u16 scr;
	u16 wer;
#endif
};

static LIST_HEAD(uart_list);

static struct plat_serial8250_port serial_platform_data0[] = {
	{
		.mapbase	= OMAP_UART1_BASE,
		.irq		= 72,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP24XX_BASE_BAUD * 16,
	}, {
		.flags		= 0
	}
};

static struct plat_serial8250_port serial_platform_data1[] = {
	{
		.mapbase	= OMAP_UART2_BASE,
		.irq		= 73,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP24XX_BASE_BAUD * 16,
	}, {
		.flags		= 0
	}
};

static struct plat_serial8250_port serial_platform_data2[] = {
	{
		.mapbase	= OMAP_UART3_BASE,
		.irq		= 74,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP24XX_BASE_BAUD * 16,
	}, {
		.flags		= 0
	}
};

#ifdef CONFIG_ARCH_OMAP4
static struct plat_serial8250_port serial_platform_data3[] = {
	{
		.mapbase	= OMAP_UART4_BASE,
		.irq		= 70,
		.flags		= UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= OMAP24XX_BASE_BAUD * 16,
	}, {
		.flags		= 0
	}
};
#endif
static inline unsigned int __serial_read_reg(struct uart_port *up,
					   int offset)
{
	offset <<= up->regshift;
	return (unsigned int)__raw_readb(up->membase + offset);
}

static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
					   int offset)
{
	offset <<= up->regshift;
	return (unsigned int)__raw_readb(up->membase + offset);
}

static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
				    int value)
{
	offset <<= p->regshift;
	__raw_writeb(value, p->membase + offset);
}

/*
 * Internal UARTs need to be initialized for the 8250 autoconfig to work
 * properly. Note that the TX watermark initialization may not be needed
 * once the 8250.c watermark handling code is merged.
 */
static inline void __init omap_uart_reset(struct omap_uart_state *uart)
{
	struct plat_serial8250_port *p = uart->p;

	serial_write_reg(p, UART_OMAP_MDR1, 0x07);
	serial_write_reg(p, UART_OMAP_SCR, 0x08);
	serial_write_reg(p, UART_OMAP_MDR1, 0x00);
	serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
}

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)

static void omap_uart_save_context(struct omap_uart_state *uart)
{
	u16 lcr = 0;
	struct plat_serial8250_port *p = uart->p;

	if (!enable_off_mode)
		return;

	lcr = serial_read_reg(p, UART_LCR);
	serial_write_reg(p, UART_LCR, 0xBF);
	uart->dll = serial_read_reg(p, UART_DLL);
	uart->dlh = serial_read_reg(p, UART_DLM);
	serial_write_reg(p, UART_LCR, lcr);
	uart->ier = serial_read_reg(p, UART_IER);
	uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
	uart->scr = serial_read_reg(p, UART_OMAP_SCR);
	uart->wer = serial_read_reg(p, UART_OMAP_WER);

	uart->context_valid = 1;
}

static void omap_uart_restore_context(struct omap_uart_state *uart)
{
	u16 efr = 0;
	struct plat_serial8250_port *p = uart->p;

	if (!enable_off_mode)
		return;

	if (!uart->context_valid)
		return;

	uart->context_valid = 0;

	serial_write_reg(p, UART_OMAP_MDR1, 0x7);
	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	efr = serial_read_reg(p, UART_EFR);
	serial_write_reg(p, UART_EFR, UART_EFR_ECB);
	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	serial_write_reg(p, UART_IER, 0x0);
	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	serial_write_reg(p, UART_DLL, uart->dll);
	serial_write_reg(p, UART_DLM, uart->dlh);
	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	serial_write_reg(p, UART_IER, uart->ier);
	serial_write_reg(p, UART_FCR, 0xA1);
	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	serial_write_reg(p, UART_EFR, efr);
	serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
	serial_write_reg(p, UART_OMAP_SCR, uart->scr);
	serial_write_reg(p, UART_OMAP_WER, uart->wer);
	serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
	serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
}
#else
static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */

static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
{
	if (uart->clocked)
		return;

	clk_enable(uart->ick);
	clk_enable(uart->fck);
	uart->clocked = 1;
	omap_uart_restore_context(uart);
}

#ifdef CONFIG_PM

static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
{
	if (!uart->clocked)
		return;

	omap_uart_save_context(uart);
	uart->clocked = 0;
	clk_disable(uart->ick);
	clk_disable(uart->fck);
}

static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
{
	/* Set wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v |= uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}

	/* Ensure IOPAD wake-enables are set */
	if (cpu_is_omap34xx() && uart->padconf) {
		u16 v = omap_ctrl_readw(uart->padconf);
		v |= OMAP3_PADCONF_WAKEUPENABLE0;
		omap_ctrl_writew(v, uart->padconf);
	}
}

static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
{
	/* Clear wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v &= ~uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}

	/* Ensure IOPAD wake-enables are cleared */
	if (cpu_is_omap34xx() && uart->padconf) {
		u16 v = omap_ctrl_readw(uart->padconf);
		v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
		omap_ctrl_writew(v, uart->padconf);
	}
}

static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
					  int enable)
{
	struct plat_serial8250_port *p = uart->p;
	u16 sysc;

	sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
	if (enable)
		sysc |= 0x2 << 3;
	else
		sysc |= 0x1 << 3;

	serial_write_reg(p, UART_OMAP_SYSC, sysc);
}

static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	omap_uart_enable_clocks(uart);

	omap_uart_smart_idle_enable(uart, 0);
	uart->can_sleep = 0;
	if (uart->timeout)
		mod_timer(&uart->timer, jiffies + uart->timeout);
	else
		del_timer(&uart->timer);
}

static void omap_uart_allow_sleep(struct omap_uart_state *uart)
{
	if (device_may_wakeup(&uart->pdev.dev))
		omap_uart_enable_wakeup(uart);
	else
		omap_uart_disable_wakeup(uart);

	if (!uart->clocked)
		return;

	omap_uart_smart_idle_enable(uart, 1);
	uart->can_sleep = 1;
	del_timer(&uart->timer);
}

static void omap_uart_idle_timer(unsigned long data)
{
	struct omap_uart_state *uart = (struct omap_uart_state *)data;

	omap_uart_allow_sleep(uart);
}

void omap_uart_prepare_idle(int num)
{
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		if (num == uart->num && uart->can_sleep) {
			omap_uart_disable_clocks(uart);
			return;
		}
	}
}

void omap_uart_resume_idle(int num)
{
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		if (num == uart->num) {
			omap_uart_enable_clocks(uart);

			/* Check for IO pad wakeup */
			if (cpu_is_omap34xx() && uart->padconf) {
				u16 p = omap_ctrl_readw(uart->padconf);

				if (p & OMAP3_PADCONF_WAKEUPEVENT0)
					omap_uart_block_sleep(uart);
			}

			/* Check for normal UART wakeup */
			if (__raw_readl(uart->wk_st) & uart->wk_mask)
				omap_uart_block_sleep(uart);
			return;
		}
	}
}

void omap_uart_prepare_suspend(void)
{
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		omap_uart_allow_sleep(uart);
	}
}

int omap_uart_can_sleep(void)
{
	struct omap_uart_state *uart;
	int can_sleep = 1;

	list_for_each_entry(uart, &uart_list, node) {
		if (!uart->clocked)
			continue;

		if (!uart->can_sleep) {
			can_sleep = 0;
			continue;
		}

		/* This UART can now safely sleep. */
		omap_uart_allow_sleep(uart);
	}

	return can_sleep;
}

/**
 * omap_uart_interrupt()
 *
 * This handler is used only to detect that *any* UART interrupt has
 * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 * any UART interrupt will trigger the inactivity timer so the
 * UART will not idle or sleep for its timeout period.
 *
 **/
static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
{
	struct omap_uart_state *uart = dev_id;

	omap_uart_block_sleep(uart);

	return IRQ_NONE;
}

static void omap_uart_idle_init(struct omap_uart_state *uart)
{
	struct plat_serial8250_port *p = uart->p;
	int ret;

	uart->can_sleep = 0;
	uart->timeout = DEFAULT_TIMEOUT;
	setup_timer(&uart->timer, omap_uart_idle_timer,
		    (unsigned long) uart);
	if (uart->timeout)
		mod_timer(&uart->timer, jiffies + uart->timeout);
	omap_uart_smart_idle_enable(uart, 0);

	if (cpu_is_omap34xx()) {
		u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
		u32 wk_mask = 0;
		u32 padconf = 0;

		uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
		uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
		switch (uart->num) {
		case 0:
			wk_mask = OMAP3430_ST_UART1_MASK;
			padconf = 0x182;
			break;
		case 1:
			wk_mask = OMAP3430_ST_UART2_MASK;
			padconf = 0x17a;
			break;
		case 2:
			wk_mask = OMAP3430_ST_UART3_MASK;
			padconf = 0x19e;
			break;
		}
		uart->wk_mask = wk_mask;
		uart->padconf = padconf;
	} else if (cpu_is_omap24xx()) {
		u32 wk_mask = 0;

		if (cpu_is_omap2430()) {
			uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
			uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
		} else if (cpu_is_omap2420()) {
			uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
			uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
		}
		switch (uart->num) {
		case 0:
			wk_mask = OMAP24XX_ST_UART1_MASK;
			break;
		case 1:
			wk_mask = OMAP24XX_ST_UART2_MASK;
			break;
		case 2:
			wk_mask = OMAP24XX_ST_UART3_MASK;
			break;
		}
		uart->wk_mask = wk_mask;
	} else {
		uart->wk_en = 0;
		uart->wk_st = 0;
		uart->wk_mask = 0;
		uart->padconf = 0;
	}

	p->irqflags |= IRQF_SHARED;
	ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
			  "serial idle", (void *)uart);
	WARN_ON(ret);
}

void omap_uart_enable_irqs(int enable)
{
	int ret;
	struct omap_uart_state *uart;

	list_for_each_entry(uart, &uart_list, node) {
		if (enable)
			ret = request_irq(uart->p->irq, omap_uart_interrupt,
				IRQF_SHARED, "serial idle", (void *)uart);
		else
			free_irq(uart->p->irq, (void *)uart);
	}
}

static ssize_t sleep_timeout_show(struct device *dev,
				  struct device_attribute *attr,
				  char *buf)
{
	struct platform_device *pdev = container_of(dev,
					struct platform_device, dev);
	struct omap_uart_state *uart = container_of(pdev,
					struct omap_uart_state, pdev);

	return sprintf(buf, "%u\n", uart->timeout / HZ);
}

static ssize_t sleep_timeout_store(struct device *dev,
				   struct device_attribute *attr,
				   const char *buf, size_t n)
{
	struct platform_device *pdev = container_of(dev,
					struct platform_device, dev);
	struct omap_uart_state *uart = container_of(pdev,
					struct omap_uart_state, pdev);
	unsigned int value;

	if (sscanf(buf, "%u", &value) != 1) {
		printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
		return -EINVAL;
	}

	uart->timeout = value * HZ;
	if (uart->timeout)
		mod_timer(&uart->timer, jiffies + uart->timeout);
	else
		/* A zero value means disable timeout feature */
		omap_uart_block_sleep(uart);

	return n;
}

DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
#else
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
#define DEV_CREATE_FILE(dev, attr)
#endif /* CONFIG_PM */

static struct omap_uart_state omap_uart[] = {
	{
		.pdev = {
			.name			= "serial8250",
			.id			= PLAT8250_DEV_PLATFORM,
			.dev			= {
				.platform_data	= serial_platform_data0,
			},
		},
	}, {
		.pdev = {
			.name			= "serial8250",
			.id			= PLAT8250_DEV_PLATFORM1,
			.dev			= {
				.platform_data	= serial_platform_data1,
			},
		},
	}, {
		.pdev = {
			.name			= "serial8250",
			.id			= PLAT8250_DEV_PLATFORM2,
			.dev			= {
				.platform_data	= serial_platform_data2,
			},
		},
	},
#ifdef CONFIG_ARCH_OMAP4
	{
		.pdev = {
			.name			= "serial8250",
			.id			= 3,
			.dev			= {
				.platform_data	= serial_platform_data3,
			},
		},
	},
#endif
};

/*
 * Override the default 8250 read handler: mem_serial_in()
 * Empty RX fifo read causes an abort on omap3630 and omap4
 * This function makes sure that an empty rx fifo is not read on these silicons
 * (OMAP1/2/3430 are not affected)
 */
static unsigned int serial_in_override(struct uart_port *up, int offset)
{
	if (UART_RX == offset) {
		unsigned int lsr;
		lsr = __serial_read_reg(up, UART_LSR);
		if (!(lsr & UART_LSR_DR))
			return -EPERM;
	}

	return __serial_read_reg(up, offset);
}

void __init omap_serial_early_init(void)
{
	int i;
	char name[16];

	/*
	 * Make sure the serial ports are muxed on at this point.
	 * You have to mux them off in device drivers later on
	 * if not needed.
	 */

	for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
		struct omap_uart_state *uart = &omap_uart[i];
		struct platform_device *pdev = &uart->pdev;
		struct device *dev = &pdev->dev;
		struct plat_serial8250_port *p = dev->platform_data;

		/*
		 * Module 4KB + L4 interconnect 4KB
		 * Static mapping, never released
		 */
		p->membase = ioremap(p->mapbase, SZ_8K);
		if (!p->membase) {
			printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
			continue;
		}

		sprintf(name, "uart%d_ick", i+1);
		uart->ick = clk_get(NULL, name);
		if (IS_ERR(uart->ick)) {
			printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
			uart->ick = NULL;
		}

		sprintf(name, "uart%d_fck", i+1);
		uart->fck = clk_get(NULL, name);
		if (IS_ERR(uart->fck)) {
			printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
			uart->fck = NULL;
		}

		/* FIXME: Remove this once the clkdev is ready */
		if (!cpu_is_omap44xx()) {
			if (!uart->ick || !uart->fck)
				continue;
		}

		uart->num = i;
		p->private_data = uart;
		uart->p = p;

		if (cpu_is_omap44xx())
			p->irq += 32;
	}
}

/**
 * omap_serial_init_port() - initialize single serial port
 * @port: serial port number (0-3)
 *
 * This function initialies serial driver for given @port only.
 * Platforms can call this function instead of omap_serial_init()
 * if they don't plan to use all available UARTs as serial ports.
 *
 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 * use only one of the two.
 */
void __init omap_serial_init_port(int port)
{
	struct omap_uart_state *uart;
	struct platform_device *pdev;
	struct device *dev;

	BUG_ON(port < 0);
	BUG_ON(port >= ARRAY_SIZE(omap_uart));

	uart = &omap_uart[port];
	pdev = &uart->pdev;
	dev = &pdev->dev;

	omap_uart_enable_clocks(uart);

	omap_uart_reset(uart);
	omap_uart_idle_init(uart);

	list_add_tail(&uart->node, &uart_list);

	if (WARN_ON(platform_device_register(pdev)))
		return;

	if ((cpu_is_omap34xx() && uart->padconf) ||
	    (uart->wk_en && uart->wk_mask)) {
		device_init_wakeup(dev, true);
		DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
	}

		/* omap44xx: Never read empty UART fifo
		 * omap3xxx: Never read empty UART fifo on UARTs
		 * with IP rev >=0x52
		 */
		if (cpu_is_omap44xx())
			uart->p->serial_in = serial_in_override;
		else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
				>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
			uart->p->serial_in = serial_in_override;
}

/**
 * omap_serial_init() - intialize all supported serial ports
 *
 * Initializes all available UARTs as serial ports. Platforms
 * can call this function when they want to have default behaviour
 * for serial ports (e.g initialize them all as serial ports).
 */
void __init omap_serial_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
		omap_serial_init_port(i);
}
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* arch/arm/mach-omap2/serial.c
1dbae815 TL	3	*
	4	* OMAP2 serial support.
	5	*
6e81176d	6	* Copyright (C) 2005-2008 Nokia Corporation
1dbae815 TL	7	* Author: Paul Mundt <paul.mundt@nokia.com>
1dbae815 TL	8	*
4af4016c KH	9	* Major rework for PM support by Kevin Hilman
4af4016c KH	10	*
1dbae815 TL	11	* Based off of arch/arm/mach-omap/omap1/serial.c
1dbae815 TL	12	*
44169075 SS	13	* Copyright (C) 2009 Texas Instruments
	14	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
	15	*
1dbae815 TL	16	* This file is subject to the terms and conditions of the GNU General Public
	17	* License. See the file "COPYING" in the main directory of this archive
	18	* for more details.
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/serial_8250.h>
	23	#include <linux/serial_reg.h>
f8ce2547	24	#include <linux/clk.h>
fced80c7	25	#include <linux/io.h>
1dbae815	26
ce491cf8 TL	27	#include <plat/common.h>
	28	#include <plat/board.h>
	29	#include <plat/clock.h>
	30	#include <plat/control.h>
4af4016c KH	31
	32	#include "prm.h"
	33	#include "pm.h"
	34	#include "prm-regbits-34xx.h"
	35
ce13d471	36	#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
4af4016c KH	37	#define UART_OMAP_WER 0x17 /* Wake-up enable register */
4af4016c KH	38
301fe8ee TL	39	/*
	40	* NOTE: By default the serial timeout is disabled as it causes lost characters
	41	* over the serial ports. This means that the UART clocks will stay on until
	42	* disabled via sysfs. This also causes that any deeper omap sleep states are
	43	* blocked.
	44	*/
	45	#define DEFAULT_TIMEOUT 0
4af4016c KH	46
	47	struct omap_uart_state {
	48	int num;
	49	int can_sleep;
	50	struct timer_list timer;
	51	u32 timeout;
	52
	53	void __iomem *wk_st;
	54	void __iomem *wk_en;
	55	u32 wk_mask;
	56	u32 padconf;
	57
	58	struct clk *ick;
	59	struct clk *fck;
	60	int clocked;
	61
	62	struct plat_serial8250_port *p;
	63	struct list_head node;
fd455ea8	64	struct platform_device pdev;
1dbae815	65
4af4016c KH	66	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
	67	int context_valid;
	68
	69	/* Registers to be saved/restored for OFF-mode */
	70	u16 dll;
	71	u16 dlh;
	72	u16 ier;
	73	u16 sysc;
	74	u16 scr;
	75	u16 wer;
	76	#endif
	77	};
	78
4af4016c	79	static LIST_HEAD(uart_list);
1dbae815	80
fd455ea8	81	static struct plat_serial8250_port serial_platform_data0[] = {
1dbae815	82	{
e8a91c95	83	.mapbase = OMAP_UART1_BASE,
1dbae815 TL	84	.irq = 72,
	85	.flags = UPF_BOOT_AUTOCONF,
	86	.iotype = UPIO_MEM,
	87	.regshift = 2,
6e81176d	88	.uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815	89	}, {
fd455ea8 KH	90	.flags = 0
	91	}
	92	};
	93
	94	static struct plat_serial8250_port serial_platform_data1[] = {
	95	{
e8a91c95	96	.mapbase = OMAP_UART2_BASE,
1dbae815 TL	97	.irq = 73,
	98	.flags = UPF_BOOT_AUTOCONF,
	99	.iotype = UPIO_MEM,
	100	.regshift = 2,
6e81176d	101	.uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815	102	}, {
fd455ea8 KH	103	.flags = 0
	104	}
	105	};
	106
	107	static struct plat_serial8250_port serial_platform_data2[] = {
	108	{
e8a91c95	109	.mapbase = OMAP_UART3_BASE,
1dbae815 TL	110	.irq = 74,
	111	.flags = UPF_BOOT_AUTOCONF,
	112	.iotype = UPIO_MEM,
	113	.regshift = 2,
6e81176d	114	.uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 TL	115	}, {
	116	.flags = 0
	117	}
	118	};
	119
0e3eaadf SS	120	#ifdef CONFIG_ARCH_OMAP4
	121	static struct plat_serial8250_port serial_platform_data3[] = {
	122	{
0e3eaadf SS	123	.mapbase = OMAP_UART4_BASE,
	124	.irq = 70,
	125	.flags = UPF_BOOT_AUTOCONF,
	126	.iotype = UPIO_MEM,
	127	.regshift = 2,
	128	.uartclk = OMAP24XX_BASE_BAUD * 16,
	129	}, {
	130	.flags = 0
	131	}
	132	};
	133	#endif
9230372a AS	134	static inline unsigned int __serial_read_reg(struct uart_port *up,
	135	int offset)
	136	{
	137	offset <<= up->regshift;
	138	return (unsigned int)__raw_readb(up->membase + offset);
	139	}
	140
1dbae815 TL	141	static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
	142	int offset)
	143	{
	144	offset <<= up->regshift;
	145	return (unsigned int)__raw_readb(up->membase + offset);
	146	}
	147
	148	static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
	149	int value)
	150	{
	151	offset <<= p->regshift;
e8a91c95	152	__raw_writeb(value, p->membase + offset);
1dbae815 TL	153	}
	154
	155	/*
	156	* Internal UARTs need to be initialized for the 8250 autoconfig to work
	157	* properly. Note that the TX watermark initialization may not be needed
	158	* once the 8250.c watermark handling code is merged.
	159	*/
4af4016c	160	static inline void __init omap_uart_reset(struct omap_uart_state *uart)
1dbae815	161	{
4af4016c KH	162	struct plat_serial8250_port *p = uart->p;
4af4016c KH	163
1dbae815 TL	164	serial_write_reg(p, UART_OMAP_MDR1, 0x07);
	165	serial_write_reg(p, UART_OMAP_SCR, 0x08);
	166	serial_write_reg(p, UART_OMAP_MDR1, 0x00);
671c7235	167	serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) \| (1 << 2) \| (1 << 0));
1dbae815 TL	168	}
1dbae815 TL	169
4af4016c KH	170	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
4af4016c KH	171
4af4016c	172	static void omap_uart_save_context(struct omap_uart_state *uart)
6e81176d	173	{
4af4016c KH	174	u16 lcr = 0;
	175	struct plat_serial8250_port *p = uart->p;
	176
	177	if (!enable_off_mode)
	178	return;
	179
	180	lcr = serial_read_reg(p, UART_LCR);
	181	serial_write_reg(p, UART_LCR, 0xBF);
	182	uart->dll = serial_read_reg(p, UART_DLL);
	183	uart->dlh = serial_read_reg(p, UART_DLM);
	184	serial_write_reg(p, UART_LCR, lcr);
	185	uart->ier = serial_read_reg(p, UART_IER);
	186	uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
	187	uart->scr = serial_read_reg(p, UART_OMAP_SCR);
	188	uart->wer = serial_read_reg(p, UART_OMAP_WER);
	189
	190	uart->context_valid = 1;
	191	}
	192
	193	static void omap_uart_restore_context(struct omap_uart_state *uart)
	194	{
	195	u16 efr = 0;
	196	struct plat_serial8250_port *p = uart->p;
	197
	198	if (!enable_off_mode)
	199	return;
	200
	201	if (!uart->context_valid)
	202	return;
	203
	204	uart->context_valid = 0;
	205
	206	serial_write_reg(p, UART_OMAP_MDR1, 0x7);
	207	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	208	efr = serial_read_reg(p, UART_EFR);
	209	serial_write_reg(p, UART_EFR, UART_EFR_ECB);
	210	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	211	serial_write_reg(p, UART_IER, 0x0);
	212	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	213	serial_write_reg(p, UART_DLL, uart->dll);
	214	serial_write_reg(p, UART_DLM, uart->dlh);
	215	serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
	216	serial_write_reg(p, UART_IER, uart->ier);
	217	serial_write_reg(p, UART_FCR, 0xA1);
	218	serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
	219	serial_write_reg(p, UART_EFR, efr);
	220	serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
	221	serial_write_reg(p, UART_OMAP_SCR, uart->scr);
	222	serial_write_reg(p, UART_OMAP_WER, uart->wer);
	223	serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
	224	serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
	225	}
	226	#else
	227	static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
	228	static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
	229	#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
	230
	231	static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
	232	{
	233	if (uart->clocked)
	234	return;
	235
	236	clk_enable(uart->ick);
	237	clk_enable(uart->fck);
238	uart->clocked = 1;
239	omap_uart_restore_context(uart);
240	}
241
242	#ifdef CONFIG_PM
243
244	static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
245	{
246	if (!uart->clocked)
247	return;
248
249	omap_uart_save_context(uart);
250	uart->clocked = 0;
251	clk_disable(uart->ick);
252	clk_disable(uart->fck);
253	}
254
fd455ea8 KH	255	static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
	256	{
	257	/* Set wake-enable bit */
	258	if (uart->wk_en && uart->wk_mask) {
	259	u32 v = __raw_readl(uart->wk_en);
	260	v \|= uart->wk_mask;
	261	__raw_writel(v, uart->wk_en);
	262	}
	263
	264	/* Ensure IOPAD wake-enables are set */
	265	if (cpu_is_omap34xx() && uart->padconf) {
	266	u16 v = omap_ctrl_readw(uart->padconf);
	267	v \|= OMAP3_PADCONF_WAKEUPENABLE0;
	268	omap_ctrl_writew(v, uart->padconf);
	269	}
	270	}
	271
	272	static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
	273	{
	274	/* Clear wake-enable bit */
	275	if (uart->wk_en && uart->wk_mask) {
	276	u32 v = __raw_readl(uart->wk_en);
	277	v &= ~uart->wk_mask;
	278	__raw_writel(v, uart->wk_en);
	279	}
	280
	281	/* Ensure IOPAD wake-enables are cleared */
	282	if (cpu_is_omap34xx() && uart->padconf) {
	283	u16 v = omap_ctrl_readw(uart->padconf);
	284	v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
	285	omap_ctrl_writew(v, uart->padconf);
	286	}
	287	}
	288
4af4016c KH	289	static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
	290	int enable)
	291	{
	292	struct plat_serial8250_port *p = uart->p;
	293	u16 sysc;
	294
	295	sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
	296	if (enable)
	297	sysc \|= 0x2 << 3;
	298	else
	299	sysc \|= 0x1 << 3;
	300
	301	serial_write_reg(p, UART_OMAP_SYSC, sysc);
	302	}
	303
	304	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	305	{
	306	omap_uart_enable_clocks(uart);
	307
	308	omap_uart_smart_idle_enable(uart, 0);
	309	uart->can_sleep = 0;
ba87a9be JH	310	if (uart->timeout)
	311	mod_timer(&uart->timer, jiffies + uart->timeout);
	312	else
	313	del_timer(&uart->timer);
4af4016c KH	314	}
	315
	316	static void omap_uart_allow_sleep(struct omap_uart_state *uart)
	317	{
fd455ea8 KH	318	if (device_may_wakeup(&uart->pdev.dev))
	319	omap_uart_enable_wakeup(uart);
	320	else
	321	omap_uart_disable_wakeup(uart);
	322
4af4016c KH	323	if (!uart->clocked)
	324	return;
	325
	326	omap_uart_smart_idle_enable(uart, 1);
	327	uart->can_sleep = 1;
	328	del_timer(&uart->timer);
	329	}
	330
	331	static void omap_uart_idle_timer(unsigned long data)
	332	{
	333	struct omap_uart_state uart = (struct omap_uart_state )data;
	334
	335	omap_uart_allow_sleep(uart);
	336	}
	337
	338	void omap_uart_prepare_idle(int num)
	339	{
	340	struct omap_uart_state *uart;
	341
	342	list_for_each_entry(uart, &uart_list, node) {
	343	if (num == uart->num && uart->can_sleep) {
	344	omap_uart_disable_clocks(uart);
	345	return;
	346	}
	347	}
	348	}
	349
	350	void omap_uart_resume_idle(int num)
	351	{
	352	struct omap_uart_state *uart;
	353
	354	list_for_each_entry(uart, &uart_list, node) {
	355	if (num == uart->num) {
	356	omap_uart_enable_clocks(uart);
	357
	358	/* Check for IO pad wakeup */
	359	if (cpu_is_omap34xx() && uart->padconf) {
	360	u16 p = omap_ctrl_readw(uart->padconf);
	361
	362	if (p & OMAP3_PADCONF_WAKEUPEVENT0)
	363	omap_uart_block_sleep(uart);
6e81176d	364	}
4af4016c KH	365
	366	/* Check for normal UART wakeup */
	367	if (__raw_readl(uart->wk_st) & uart->wk_mask)
	368	omap_uart_block_sleep(uart);
4af4016c KH	369	return;
	370	}
	371	}
	372	}
	373
	374	void omap_uart_prepare_suspend(void)
	375	{
	376	struct omap_uart_state *uart;
	377
	378	list_for_each_entry(uart, &uart_list, node) {
	379	omap_uart_allow_sleep(uart);
	380	}
	381	}
	382
	383	int omap_uart_can_sleep(void)
	384	{
	385	struct omap_uart_state *uart;
	386	int can_sleep = 1;
	387
	388	list_for_each_entry(uart, &uart_list, node) {
	389	if (!uart->clocked)
	390	continue;
	391
	392	if (!uart->can_sleep) {
	393	can_sleep = 0;
	394	continue;
6e81176d	395	}
4af4016c KH	396
	397	/* This UART can now safely sleep. */
	398	omap_uart_allow_sleep(uart);
6e81176d	399	}
4af4016c KH	400
4af4016c KH	401	return can_sleep;
6e81176d JH	402	}
6e81176d JH	403
4af4016c KH	404	/**
	405	* omap_uart_interrupt()
	406	*
	407	* This handler is used only to detect that any UART interrupt has
	408	* occurred. It does _nothing_ to handle the interrupt. Rather,
	409	* any UART interrupt will trigger the inactivity timer so the
	410	* UART will not idle or sleep for its timeout period.
	411	*
	412	**/
	413	static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
	414	{
	415	struct omap_uart_state *uart = dev_id;
	416
	417	omap_uart_block_sleep(uart);
	418
	419	return IRQ_NONE;
	420	}
	421
	422	static void omap_uart_idle_init(struct omap_uart_state *uart)
	423	{
4af4016c KH	424	struct plat_serial8250_port *p = uart->p;
	425	int ret;
	426
	427	uart->can_sleep = 0;
fd455ea8	428	uart->timeout = DEFAULT_TIMEOUT;
4af4016c KH	429	setup_timer(&uart->timer, omap_uart_idle_timer,
4af4016c KH	430	(unsigned long) uart);
301fe8ee TL	431	if (uart->timeout)
301fe8ee TL	432	mod_timer(&uart->timer, jiffies + uart->timeout);
4af4016c KH	433	omap_uart_smart_idle_enable(uart, 0);
	434
	435	if (cpu_is_omap34xx()) {
	436	u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
	437	u32 wk_mask = 0;
	438	u32 padconf = 0;
	439
	440	uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
	441	uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
	442	switch (uart->num) {
	443	case 0:
	444	wk_mask = OMAP3430_ST_UART1_MASK;
	445	padconf = 0x182;
	446	break;
	447	case 1:
	448	wk_mask = OMAP3430_ST_UART2_MASK;
	449	padconf = 0x17a;
	450	break;
	451	case 2:
	452	wk_mask = OMAP3430_ST_UART3_MASK;
	453	padconf = 0x19e;
	454	break;
	455	}
	456	uart->wk_mask = wk_mask;
	457	uart->padconf = padconf;
	458	} else if (cpu_is_omap24xx()) {
	459	u32 wk_mask = 0;
	460
	461	if (cpu_is_omap2430()) {
	462	uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
	463	uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
	464	} else if (cpu_is_omap2420()) {
	465	uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
	466	uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
	467	}
	468	switch (uart->num) {
	469	case 0:
	470	wk_mask = OMAP24XX_ST_UART1_MASK;
	471	break;
	472	case 1:
	473	wk_mask = OMAP24XX_ST_UART2_MASK;
	474	break;
	475	case 2:
	476	wk_mask = OMAP24XX_ST_UART3_MASK;
	477	break;
	478	}
	479	uart->wk_mask = wk_mask;
	480	} else {
	481	uart->wk_en = 0;
	482	uart->wk_st = 0;
	483	uart->wk_mask = 0;
	484	uart->padconf = 0;
	485	}
	486
c426df87	487	p->irqflags \|= IRQF_SHARED;
4af4016c KH	488	ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
	489	"serial idle", (void *)uart);
	490	WARN_ON(ret);
	491	}
	492
2466211e TK	493	void omap_uart_enable_irqs(int enable)
	494	{
	495	int ret;
	496	struct omap_uart_state *uart;
	497
	498	list_for_each_entry(uart, &uart_list, node) {
	499	if (enable)
	500	ret = request_irq(uart->p->irq, omap_uart_interrupt,
	501	IRQF_SHARED, "serial idle", (void *)uart);
	502	else
	503	free_irq(uart->p->irq, (void *)uart);
	504	}
	505	}
	506
fd455ea8 KH	507	static ssize_t sleep_timeout_show(struct device *dev,
fd455ea8 KH	508	struct device_attribute *attr,
ba87a9be JH	509	char *buf)
ba87a9be JH	510	{
fd455ea8 KH	511	struct platform_device *pdev = container_of(dev,
	512	struct platform_device, dev);
	513	struct omap_uart_state *uart = container_of(pdev,
	514	struct omap_uart_state, pdev);
	515
	516	return sprintf(buf, "%u\n", uart->timeout / HZ);
ba87a9be JH	517	}
ba87a9be JH	518
fd455ea8 KH	519	static ssize_t sleep_timeout_store(struct device *dev,
fd455ea8 KH	520	struct device_attribute *attr,
ba87a9be JH	521	const char *buf, size_t n)
ba87a9be JH	522	{
fd455ea8 KH	523	struct platform_device *pdev = container_of(dev,
	524	struct platform_device, dev);
	525	struct omap_uart_state *uart = container_of(pdev,
	526	struct omap_uart_state, pdev);
ba87a9be JH	527	unsigned int value;
	528
	529	if (sscanf(buf, "%u", &value) != 1) {
	530	printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
	531	return -EINVAL;
	532	}
fd455ea8 KH	533
	534	uart->timeout = value * HZ;
	535	if (uart->timeout)
	536	mod_timer(&uart->timer, jiffies + uart->timeout);
	537	else
	538	/* A zero value means disable timeout feature */
	539	omap_uart_block_sleep(uart);
	540
ba87a9be JH	541	return n;
	542	}
	543
fd455ea8 KH	544	DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
fd455ea8 KH	545	#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
4af4016c KH	546	#else
4af4016c KH	547	static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
fd455ea8	548	#define DEV_CREATE_FILE(dev, attr)
4af4016c KH	549	#endif /* CONFIG_PM */
4af4016c KH	550
9d30b99f	551	static struct omap_uart_state omap_uart[] = {
fd455ea8 KH	552	{
	553	.pdev = {
	554	.name = "serial8250",
	555	.id = PLAT8250_DEV_PLATFORM,
	556	.dev = {
	557	.platform_data = serial_platform_data0,
	558	},
	559	},
	560	}, {
	561	.pdev = {
	562	.name = "serial8250",
	563	.id = PLAT8250_DEV_PLATFORM1,
	564	.dev = {
	565	.platform_data = serial_platform_data1,
	566	},
	567	},
	568	}, {
	569	.pdev = {
	570	.name = "serial8250",
	571	.id = PLAT8250_DEV_PLATFORM2,
	572	.dev = {
	573	.platform_data = serial_platform_data2,
	574	},
	575	},
2aa57be2	576	},
0e3eaadf SS	577	#ifdef CONFIG_ARCH_OMAP4
	578	{
	579	.pdev = {
	580	.name = "serial8250",
61f04ee8	581	.id = 3,
0e3eaadf SS	582	.dev = {
	583	.platform_data = serial_platform_data3,
	584	},
	585	},
	586	},
	587	#endif
2aa57be2 VP	588	};
2aa57be2 VP	589
ce13d471	590	/*
	591	* Override the default 8250 read handler: mem_serial_in()
	592	* Empty RX fifo read causes an abort on omap3630 and omap4
	593	* This function makes sure that an empty rx fifo is not read on these silicons
	594	* (OMAP1/2/3430 are not affected)
	595	*/
	596	static unsigned int serial_in_override(struct uart_port *up, int offset)
	597	{
	598	if (UART_RX == offset) {
	599	unsigned int lsr;
9230372a	600	lsr = __serial_read_reg(up, UART_LSR);
ce13d471	601	if (!(lsr & UART_LSR_DR))
	602	return -EPERM;
	603	}
9230372a AS	604
9230372a AS	605	return __serial_read_reg(up, offset);
ce13d471	606	}
ce13d471	607
b3c6df3a	608	void __init omap_serial_early_init(void)
1dbae815	609	{
fd455ea8	610	int i;
6e81176d	611	char name[16];
1dbae815 TL	612
	613	/*
	614	* Make sure the serial ports are muxed on at this point.
	615	* You have to mux them off in device drivers later on
	616	* if not needed.
	617	*/
	618
9d30b99f	619	for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
4af4016c	620	struct omap_uart_state *uart = &omap_uart[i];
fd455ea8 KH	621	struct platform_device *pdev = &uart->pdev;
	622	struct device *dev = &pdev->dev;
	623	struct plat_serial8250_port *p = dev->platform_data;
1dbae815	624
84f90c9c TL	625	/*
	626	* Module 4KB + L4 interconnect 4KB
	627	* Static mapping, never released
	628	*/
	629	p->membase = ioremap(p->mapbase, SZ_8K);
	630	if (!p->membase) {
	631	printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
	632	continue;
	633	}
	634
6e81176d	635	sprintf(name, "uart%d_ick", i+1);
4af4016c KH	636	uart->ick = clk_get(NULL, name);
4af4016c KH	637	if (IS_ERR(uart->ick)) {
6e81176d	638	printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
4af4016c KH	639	uart->ick = NULL;
4af4016c KH	640	}
6e81176d JH	641
6e81176d JH	642	sprintf(name, "uart%d_fck", i+1);
4af4016c KH	643	uart->fck = clk_get(NULL, name);
4af4016c KH	644	if (IS_ERR(uart->fck)) {
6e81176d	645	printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
4af4016c KH	646	uart->fck = NULL;
	647	}
	648
aae290fb SS	649	/* FIXME: Remove this once the clkdev is ready */
	650	if (!cpu_is_omap44xx()) {
	651	if (!uart->ick \|\| !uart->fck)
	652	continue;
	653	}
4af4016c KH	654
	655	uart->num = i;
	656	p->private_data = uart;
	657	uart->p = p;
1dbae815	658
4789998a KH	659	if (cpu_is_omap44xx())
4789998a KH	660	p->irq += 32;
b3c6df3a PW	661	}
	662	}
	663
f62349ee MW	664	/**
	665	* omap_serial_init_port() - initialize single serial port
	666	* @port: serial port number (0-3)
	667	*
	668	* This function initialies serial driver for given @port only.
	669	* Platforms can call this function instead of omap_serial_init()
	670	* if they don't plan to use all available UARTs as serial ports.
	671	*
	672	* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
	673	* use only one of the two.
	674	*/
	675	void __init omap_serial_init_port(int port)
b3c6df3a	676	{
f62349ee MW	677	struct omap_uart_state *uart;
	678	struct platform_device *pdev;
	679	struct device *dev;
b3c6df3a	680
f62349ee MW	681	BUG_ON(port < 0);
f62349ee MW	682	BUG_ON(port >= ARRAY_SIZE(omap_uart));
b3c6df3a	683
f62349ee MW	684	uart = &omap_uart[port];
	685	pdev = &uart->pdev;
	686	dev = &pdev->dev;
970a724d	687
f2eeeae0 MW	688	omap_uart_enable_clocks(uart);
f2eeeae0 MW	689
f62349ee MW	690	omap_uart_reset(uart);
	691	omap_uart_idle_init(uart);
	692
f2eeeae0 MW	693	list_add_tail(&uart->node, &uart_list);
f2eeeae0 MW	694
f62349ee MW	695	if (WARN_ON(platform_device_register(pdev)))
	696	return;
	697
	698	if ((cpu_is_omap34xx() && uart->padconf) \|\|
	699	(uart->wk_en && uart->wk_mask)) {
	700	device_init_wakeup(dev, true);
	701	DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
fd455ea8	702	}
f62349ee	703
ce13d471	704	/* omap44xx: Never read empty UART fifo
	705	* omap3xxx: Never read empty UART fifo on UARTs
	706	* with IP rev >=0x52
	707	*/
	708	if (cpu_is_omap44xx())
	709	uart->p->serial_in = serial_in_override;
	710	else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
	711	>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
	712	uart->p->serial_in = serial_in_override;
f62349ee MW	713	}
	714
	715	/**
	716	* omap_serial_init() - intialize all supported serial ports
	717	*
	718	* Initializes all available UARTs as serial ports. Platforms
	719	* can call this function when they want to have default behaviour
	720	* for serial ports (e.g initialize them all as serial ports).
	721	*/
	722	void __init omap_serial_init(void)
	723	{
	724	int i;
	725
	726	for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
	727	omap_serial_init_port(i);
1dbae815	728	}