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Commit | Line | Data |
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1dbae815 | 1 | /* |
f30c2269 | 2 | * arch/arm/mach-omap2/serial.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 serial support. | |
5 | * | |
6e81176d | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
1dbae815 TL |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
8 | * | |
4af4016c KH |
9 | * Major rework for PM support by Kevin Hilman |
10 | * | |
1dbae815 TL |
11 | * Based off of arch/arm/mach-omap/omap1/serial.c |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com | |
15 | * | |
1dbae815 TL |
16 | * This file is subject to the terms and conditions of the GNU General Public |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
f8ce2547 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
e03d37d8 | 24 | #include <linux/delay.h> |
6f251e9d KH |
25 | #include <linux/platform_device.h> |
26 | #include <linux/slab.h> | |
3244fcd2 | 27 | #include <linux/pm_runtime.h> |
0d8e2d0d | 28 | #include <linux/console.h> |
6f251e9d | 29 | |
6f251e9d | 30 | #include <plat/omap-serial.h> |
4e65331c | 31 | #include "common.h" |
ce491cf8 | 32 | #include <plat/board.h> |
6f251e9d KH |
33 | #include <plat/dma.h> |
34 | #include <plat/omap_hwmod.h> | |
35 | #include <plat/omap_device.h> | |
4af4016c | 36 | |
59fb659b | 37 | #include "prm2xxx_3xxx.h" |
4af4016c | 38 | #include "pm.h" |
59fb659b | 39 | #include "cm2xxx_3xxx.h" |
4af4016c | 40 | #include "prm-regbits-34xx.h" |
4814ced5 | 41 | #include "control.h" |
40e44399 | 42 | #include "mux.h" |
4af4016c KH |
43 | |
44 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ | |
45 | ||
00034509 | 46 | #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) |
5a927b36 | 47 | |
301fe8ee TL |
48 | /* |
49 | * NOTE: By default the serial timeout is disabled as it causes lost characters | |
50 | * over the serial ports. This means that the UART clocks will stay on until | |
51 | * disabled via sysfs. This also causes that any deeper omap sleep states are | |
52 | * blocked. | |
53 | */ | |
54 | #define DEFAULT_TIMEOUT 0 | |
4af4016c | 55 | |
6f251e9d KH |
56 | #define MAX_UART_HWMOD_NAME_LEN 16 |
57 | ||
4af4016c KH |
58 | struct omap_uart_state { |
59 | int num; | |
60 | int can_sleep; | |
61 | struct timer_list timer; | |
62 | u32 timeout; | |
63 | ||
64 | void __iomem *wk_st; | |
65 | void __iomem *wk_en; | |
66 | u32 wk_mask; | |
67 | u32 padconf; | |
6f251e9d | 68 | u32 dma_enabled; |
4af4016c KH |
69 | |
70 | struct clk *ick; | |
71 | struct clk *fck; | |
72 | int clocked; | |
73 | ||
6f251e9d KH |
74 | int irq; |
75 | int regshift; | |
76 | int irqflags; | |
77 | void __iomem *membase; | |
78 | resource_size_t mapbase; | |
79 | ||
4af4016c | 80 | struct list_head node; |
6f251e9d KH |
81 | struct omap_hwmod *oh; |
82 | struct platform_device *pdev; | |
1dbae815 | 83 | |
5a927b36 | 84 | u32 errata; |
4af4016c KH |
85 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
86 | int context_valid; | |
87 | ||
88 | /* Registers to be saved/restored for OFF-mode */ | |
89 | u16 dll; | |
90 | u16 dlh; | |
91 | u16 ier; | |
92 | u16 sysc; | |
93 | u16 scr; | |
94 | u16 wer; | |
5ade4ff5 | 95 | u16 mcr; |
4af4016c KH |
96 | #endif |
97 | }; | |
98 | ||
4af4016c | 99 | static LIST_HEAD(uart_list); |
6f251e9d | 100 | static u8 num_uarts; |
1dbae815 | 101 | |
9230372a | 102 | static inline unsigned int __serial_read_reg(struct uart_port *up, |
6f251e9d | 103 | int offset) |
9230372a AS |
104 | { |
105 | offset <<= up->regshift; | |
106 | return (unsigned int)__raw_readb(up->membase + offset); | |
107 | } | |
108 | ||
6f251e9d | 109 | static inline unsigned int serial_read_reg(struct omap_uart_state *uart, |
1dbae815 TL |
110 | int offset) |
111 | { | |
6f251e9d KH |
112 | offset <<= uart->regshift; |
113 | return (unsigned int)__raw_readb(uart->membase + offset); | |
1dbae815 TL |
114 | } |
115 | ||
e03d37d8 SS |
116 | static inline void __serial_write_reg(struct uart_port *up, int offset, |
117 | int value) | |
118 | { | |
119 | offset <<= up->regshift; | |
120 | __raw_writeb(value, up->membase + offset); | |
121 | } | |
122 | ||
6f251e9d | 123 | static inline void serial_write_reg(struct omap_uart_state *uart, int offset, |
1dbae815 TL |
124 | int value) |
125 | { | |
6f251e9d KH |
126 | offset <<= uart->regshift; |
127 | __raw_writeb(value, uart->membase + offset); | |
1dbae815 TL |
128 | } |
129 | ||
130 | /* | |
131 | * Internal UARTs need to be initialized for the 8250 autoconfig to work | |
132 | * properly. Note that the TX watermark initialization may not be needed | |
133 | * once the 8250.c watermark handling code is merged. | |
134 | */ | |
6f251e9d | 135 | |
4af4016c | 136 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
1dbae815 | 137 | { |
498cb951 | 138 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
6f251e9d | 139 | serial_write_reg(uart, UART_OMAP_SCR, 0x08); |
498cb951 | 140 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); |
1dbae815 TL |
141 | } |
142 | ||
4af4016c KH |
143 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
144 | ||
00034509 D |
145 | /* |
146 | * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) | |
147 | * The access to uart register after MDR1 Access | |
148 | * causes UART to corrupt data. | |
149 | * | |
150 | * Need a delay = | |
151 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
152 | * give 10 times as much | |
153 | */ | |
154 | static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, | |
155 | u8 fcr_val) | |
156 | { | |
00034509 D |
157 | u8 timeout = 255; |
158 | ||
6f251e9d | 159 | serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); |
00034509 | 160 | udelay(2); |
6f251e9d | 161 | serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | |
00034509 D |
162 | UART_FCR_CLEAR_RCVR); |
163 | /* | |
164 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
165 | * TX_FIFO_E bit is 1. | |
166 | */ | |
6f251e9d | 167 | while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & |
00034509 D |
168 | (UART_LSR_THRE | UART_LSR_DR))) { |
169 | timeout--; | |
170 | if (!timeout) { | |
171 | /* Should *never* happen. we warn and carry on */ | |
6f251e9d KH |
172 | dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", |
173 | serial_read_reg(uart, UART_LSR)); | |
00034509 D |
174 | break; |
175 | } | |
176 | udelay(1); | |
177 | } | |
178 | } | |
179 | ||
4af4016c | 180 | static void omap_uart_save_context(struct omap_uart_state *uart) |
6e81176d | 181 | { |
4af4016c | 182 | u16 lcr = 0; |
4af4016c KH |
183 | |
184 | if (!enable_off_mode) | |
185 | return; | |
186 | ||
6f251e9d | 187 | lcr = serial_read_reg(uart, UART_LCR); |
662b083a | 188 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
189 | uart->dll = serial_read_reg(uart, UART_DLL); |
190 | uart->dlh = serial_read_reg(uart, UART_DLM); | |
191 | serial_write_reg(uart, UART_LCR, lcr); | |
192 | uart->ier = serial_read_reg(uart, UART_IER); | |
193 | uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); | |
194 | uart->scr = serial_read_reg(uart, UART_OMAP_SCR); | |
195 | uart->wer = serial_read_reg(uart, UART_OMAP_WER); | |
662b083a | 196 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
6f251e9d KH |
197 | uart->mcr = serial_read_reg(uart, UART_MCR); |
198 | serial_write_reg(uart, UART_LCR, lcr); | |
4af4016c KH |
199 | |
200 | uart->context_valid = 1; | |
201 | } | |
202 | ||
203 | static void omap_uart_restore_context(struct omap_uart_state *uart) | |
204 | { | |
205 | u16 efr = 0; | |
4af4016c KH |
206 | |
207 | if (!enable_off_mode) | |
208 | return; | |
209 | ||
210 | if (!uart->context_valid) | |
211 | return; | |
212 | ||
213 | uart->context_valid = 0; | |
214 | ||
00034509 | 215 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
498cb951 | 216 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); |
00034509 | 217 | else |
498cb951 AE |
218 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
219 | ||
662b083a | 220 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
221 | efr = serial_read_reg(uart, UART_EFR); |
222 | serial_write_reg(uart, UART_EFR, UART_EFR_ECB); | |
223 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | |
224 | serial_write_reg(uart, UART_IER, 0x0); | |
662b083a | 225 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
226 | serial_write_reg(uart, UART_DLL, uart->dll); |
227 | serial_write_reg(uart, UART_DLM, uart->dlh); | |
228 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | |
229 | serial_write_reg(uart, UART_IER, uart->ier); | |
662b083a | 230 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
6f251e9d | 231 | serial_write_reg(uart, UART_MCR, uart->mcr); |
662b083a | 232 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
233 | serial_write_reg(uart, UART_EFR, efr); |
234 | serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); | |
235 | serial_write_reg(uart, UART_OMAP_SCR, uart->scr); | |
236 | serial_write_reg(uart, UART_OMAP_WER, uart->wer); | |
237 | serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); | |
498cb951 | 238 | |
00034509 | 239 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
498cb951 | 240 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); |
00034509 | 241 | else |
6f251e9d | 242 | /* UART 16x mode */ |
498cb951 AE |
243 | serial_write_reg(uart, UART_OMAP_MDR1, |
244 | UART_OMAP_MDR1_16X_MODE); | |
4af4016c KH |
245 | } |
246 | #else | |
247 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | |
248 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} | |
249 | #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ | |
250 | ||
251 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) | |
252 | { | |
253 | if (uart->clocked) | |
254 | return; | |
255 | ||
6f251e9d | 256 | omap_device_enable(uart->pdev); |
4af4016c KH |
257 | uart->clocked = 1; |
258 | omap_uart_restore_context(uart); | |
259 | } | |
260 | ||
261 | #ifdef CONFIG_PM | |
262 | ||
263 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) | |
264 | { | |
265 | if (!uart->clocked) | |
266 | return; | |
267 | ||
268 | omap_uart_save_context(uart); | |
269 | uart->clocked = 0; | |
6f251e9d | 270 | omap_device_idle(uart->pdev); |
4af4016c KH |
271 | } |
272 | ||
fd455ea8 KH |
273 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) |
274 | { | |
275 | /* Set wake-enable bit */ | |
276 | if (uart->wk_en && uart->wk_mask) { | |
277 | u32 v = __raw_readl(uart->wk_en); | |
278 | v |= uart->wk_mask; | |
279 | __raw_writel(v, uart->wk_en); | |
280 | } | |
281 | ||
282 | /* Ensure IOPAD wake-enables are set */ | |
283 | if (cpu_is_omap34xx() && uart->padconf) { | |
284 | u16 v = omap_ctrl_readw(uart->padconf); | |
285 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | |
286 | omap_ctrl_writew(v, uart->padconf); | |
287 | } | |
288 | } | |
289 | ||
290 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) | |
291 | { | |
292 | /* Clear wake-enable bit */ | |
293 | if (uart->wk_en && uart->wk_mask) { | |
294 | u32 v = __raw_readl(uart->wk_en); | |
295 | v &= ~uart->wk_mask; | |
296 | __raw_writel(v, uart->wk_en); | |
297 | } | |
298 | ||
299 | /* Ensure IOPAD wake-enables are cleared */ | |
300 | if (cpu_is_omap34xx() && uart->padconf) { | |
301 | u16 v = omap_ctrl_readw(uart->padconf); | |
302 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; | |
303 | omap_ctrl_writew(v, uart->padconf); | |
304 | } | |
305 | } | |
306 | ||
4af4016c | 307 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
6f251e9d | 308 | int enable) |
4af4016c | 309 | { |
6f251e9d | 310 | u8 idlemode; |
4af4016c | 311 | |
6f251e9d KH |
312 | if (enable) { |
313 | /** | |
314 | * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests | |
315 | * in Smartidle Mode When Configured for DMA Operations. | |
316 | */ | |
317 | if (uart->dma_enabled) | |
318 | idlemode = HWMOD_IDLEMODE_FORCE; | |
319 | else | |
320 | idlemode = HWMOD_IDLEMODE_SMART; | |
321 | } else { | |
322 | idlemode = HWMOD_IDLEMODE_NO; | |
323 | } | |
4af4016c | 324 | |
6f251e9d | 325 | omap_hwmod_set_slave_idlemode(uart->oh, idlemode); |
4af4016c KH |
326 | } |
327 | ||
328 | static void omap_uart_block_sleep(struct omap_uart_state *uart) | |
329 | { | |
330 | omap_uart_enable_clocks(uart); | |
331 | ||
332 | omap_uart_smart_idle_enable(uart, 0); | |
333 | uart->can_sleep = 0; | |
ba87a9be JH |
334 | if (uart->timeout) |
335 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
336 | else | |
337 | del_timer(&uart->timer); | |
4af4016c KH |
338 | } |
339 | ||
340 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) | |
341 | { | |
6f251e9d | 342 | if (device_may_wakeup(&uart->pdev->dev)) |
fd455ea8 KH |
343 | omap_uart_enable_wakeup(uart); |
344 | else | |
345 | omap_uart_disable_wakeup(uart); | |
346 | ||
4af4016c KH |
347 | if (!uart->clocked) |
348 | return; | |
349 | ||
350 | omap_uart_smart_idle_enable(uart, 1); | |
351 | uart->can_sleep = 1; | |
352 | del_timer(&uart->timer); | |
353 | } | |
354 | ||
355 | static void omap_uart_idle_timer(unsigned long data) | |
356 | { | |
357 | struct omap_uart_state *uart = (struct omap_uart_state *)data; | |
358 | ||
359 | omap_uart_allow_sleep(uart); | |
360 | } | |
361 | ||
4af4016c KH |
362 | int omap_uart_can_sleep(void) |
363 | { | |
364 | struct omap_uart_state *uart; | |
365 | int can_sleep = 1; | |
366 | ||
367 | list_for_each_entry(uart, &uart_list, node) { | |
368 | if (!uart->clocked) | |
369 | continue; | |
370 | ||
371 | if (!uart->can_sleep) { | |
372 | can_sleep = 0; | |
373 | continue; | |
6e81176d | 374 | } |
4af4016c KH |
375 | |
376 | /* This UART can now safely sleep. */ | |
377 | omap_uart_allow_sleep(uart); | |
6e81176d | 378 | } |
4af4016c KH |
379 | |
380 | return can_sleep; | |
6e81176d JH |
381 | } |
382 | ||
4af4016c KH |
383 | /** |
384 | * omap_uart_interrupt() | |
385 | * | |
386 | * This handler is used only to detect that *any* UART interrupt has | |
387 | * occurred. It does _nothing_ to handle the interrupt. Rather, | |
388 | * any UART interrupt will trigger the inactivity timer so the | |
389 | * UART will not idle or sleep for its timeout period. | |
390 | * | |
391 | **/ | |
6f251e9d | 392 | /* static int first_interrupt; */ |
4af4016c KH |
393 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) |
394 | { | |
395 | struct omap_uart_state *uart = dev_id; | |
396 | ||
397 | omap_uart_block_sleep(uart); | |
398 | ||
399 | return IRQ_NONE; | |
400 | } | |
401 | ||
402 | static void omap_uart_idle_init(struct omap_uart_state *uart) | |
403 | { | |
4af4016c KH |
404 | int ret; |
405 | ||
406 | uart->can_sleep = 0; | |
fd455ea8 | 407 | uart->timeout = DEFAULT_TIMEOUT; |
4af4016c KH |
408 | setup_timer(&uart->timer, omap_uart_idle_timer, |
409 | (unsigned long) uart); | |
301fe8ee TL |
410 | if (uart->timeout) |
411 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
4af4016c KH |
412 | omap_uart_smart_idle_enable(uart, 0); |
413 | ||
a920360f | 414 | if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) { |
52663aea | 415 | u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; |
4af4016c KH |
416 | u32 wk_mask = 0; |
417 | u32 padconf = 0; | |
418 | ||
c4d7e58f | 419 | /* XXX These PRM accesses do not belong here */ |
4af4016c KH |
420 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); |
421 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); | |
422 | switch (uart->num) { | |
423 | case 0: | |
424 | wk_mask = OMAP3430_ST_UART1_MASK; | |
425 | padconf = 0x182; | |
426 | break; | |
427 | case 1: | |
428 | wk_mask = OMAP3430_ST_UART2_MASK; | |
429 | padconf = 0x17a; | |
430 | break; | |
431 | case 2: | |
432 | wk_mask = OMAP3430_ST_UART3_MASK; | |
433 | padconf = 0x19e; | |
434 | break; | |
52663aea G |
435 | case 3: |
436 | wk_mask = OMAP3630_ST_UART4_MASK; | |
437 | padconf = 0x0d2; | |
438 | break; | |
4af4016c KH |
439 | } |
440 | uart->wk_mask = wk_mask; | |
441 | uart->padconf = padconf; | |
442 | } else if (cpu_is_omap24xx()) { | |
443 | u32 wk_mask = 0; | |
cb74f022 | 444 | u32 wk_en = PM_WKEN1, wk_st = PM_WKST1; |
4af4016c | 445 | |
4af4016c KH |
446 | switch (uart->num) { |
447 | case 0: | |
448 | wk_mask = OMAP24XX_ST_UART1_MASK; | |
449 | break; | |
450 | case 1: | |
451 | wk_mask = OMAP24XX_ST_UART2_MASK; | |
452 | break; | |
453 | case 2: | |
cb74f022 KH |
454 | wk_en = OMAP24XX_PM_WKEN2; |
455 | wk_st = OMAP24XX_PM_WKST2; | |
4af4016c KH |
456 | wk_mask = OMAP24XX_ST_UART3_MASK; |
457 | break; | |
458 | } | |
459 | uart->wk_mask = wk_mask; | |
cb74f022 KH |
460 | if (cpu_is_omap2430()) { |
461 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); | |
462 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); | |
463 | } else if (cpu_is_omap2420()) { | |
464 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); | |
465 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); | |
466 | } | |
4af4016c | 467 | } else { |
c54bae1f NM |
468 | uart->wk_en = NULL; |
469 | uart->wk_st = NULL; | |
4af4016c KH |
470 | uart->wk_mask = 0; |
471 | uart->padconf = 0; | |
472 | } | |
473 | ||
6f251e9d KH |
474 | uart->irqflags |= IRQF_SHARED; |
475 | ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, | |
476 | IRQF_SHARED, "serial idle", (void *)uart); | |
4af4016c KH |
477 | WARN_ON(ret); |
478 | } | |
479 | ||
fd455ea8 KH |
480 | static ssize_t sleep_timeout_show(struct device *dev, |
481 | struct device_attribute *attr, | |
ba87a9be JH |
482 | char *buf) |
483 | { | |
6f251e9d KH |
484 | struct platform_device *pdev = to_platform_device(dev); |
485 | struct omap_device *odev = to_omap_device(pdev); | |
486 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; | |
fd455ea8 KH |
487 | |
488 | return sprintf(buf, "%u\n", uart->timeout / HZ); | |
ba87a9be JH |
489 | } |
490 | ||
fd455ea8 KH |
491 | static ssize_t sleep_timeout_store(struct device *dev, |
492 | struct device_attribute *attr, | |
ba87a9be JH |
493 | const char *buf, size_t n) |
494 | { | |
6f251e9d KH |
495 | struct platform_device *pdev = to_platform_device(dev); |
496 | struct omap_device *odev = to_omap_device(pdev); | |
497 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; | |
ba87a9be JH |
498 | unsigned int value; |
499 | ||
500 | if (sscanf(buf, "%u", &value) != 1) { | |
10c805eb | 501 | dev_err(dev, "sleep_timeout_store: Invalid value\n"); |
ba87a9be JH |
502 | return -EINVAL; |
503 | } | |
fd455ea8 KH |
504 | |
505 | uart->timeout = value * HZ; | |
506 | if (uart->timeout) | |
507 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
508 | else | |
509 | /* A zero value means disable timeout feature */ | |
510 | omap_uart_block_sleep(uart); | |
511 | ||
ba87a9be JH |
512 | return n; |
513 | } | |
514 | ||
bfe6977a NM |
515 | static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, |
516 | sleep_timeout_store); | |
fd455ea8 | 517 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) |
4af4016c KH |
518 | #else |
519 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | |
a1b04cc1 SS |
520 | static void omap_uart_block_sleep(struct omap_uart_state *uart) |
521 | { | |
522 | /* Needed to enable UART clocks when built without CONFIG_PM */ | |
523 | omap_uart_enable_clocks(uart); | |
524 | } | |
fd455ea8 | 525 | #define DEV_CREATE_FILE(dev, attr) |
4af4016c KH |
526 | #endif /* CONFIG_PM */ |
527 | ||
3e16f925 | 528 | static int __init omap_serial_early_init(void) |
1dbae815 | 529 | { |
6f251e9d | 530 | int i = 0; |
1dbae815 | 531 | |
6f251e9d KH |
532 | do { |
533 | char oh_name[MAX_UART_HWMOD_NAME_LEN]; | |
534 | struct omap_hwmod *oh; | |
535 | struct omap_uart_state *uart; | |
21b90340 | 536 | |
6f251e9d KH |
537 | snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, |
538 | "uart%d", i + 1); | |
539 | oh = omap_hwmod_lookup(oh_name); | |
540 | if (!oh) | |
541 | break; | |
542 | ||
543 | uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); | |
544 | if (WARN_ON(!uart)) | |
3e16f925 | 545 | return -ENODEV; |
1dbae815 | 546 | |
6f251e9d KH |
547 | uart->oh = oh; |
548 | uart->num = i++; | |
549 | list_add_tail(&uart->node, &uart_list); | |
550 | num_uarts++; | |
1dbae815 | 551 | |
84f90c9c | 552 | /* |
550c8092 | 553 | * NOTE: omap_hwmod_setup*() has not yet been called, |
6f251e9d | 554 | * so no hwmod functions will work yet. |
84f90c9c | 555 | */ |
6e81176d | 556 | |
6f251e9d KH |
557 | /* |
558 | * During UART early init, device need to be probed | |
559 | * to determine SoC specific init before omap_device | |
560 | * is ready. Therefore, don't allow idle here | |
561 | */ | |
562 | uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; | |
563 | } while (1); | |
3e16f925 TL |
564 | |
565 | return 0; | |
b3c6df3a | 566 | } |
3e16f925 | 567 | core_initcall(omap_serial_early_init); |
b3c6df3a | 568 | |
f62349ee MW |
569 | /** |
570 | * omap_serial_init_port() - initialize single serial port | |
40e44399 | 571 | * @bdata: port specific board data pointer |
f62349ee | 572 | * |
40e44399 | 573 | * This function initialies serial driver for given port only. |
f62349ee MW |
574 | * Platforms can call this function instead of omap_serial_init() |
575 | * if they don't plan to use all available UARTs as serial ports. | |
576 | * | |
577 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), | |
578 | * use only one of the two. | |
579 | */ | |
40e44399 | 580 | void __init omap_serial_init_port(struct omap_board_data *bdata) |
b3c6df3a | 581 | { |
f62349ee | 582 | struct omap_uart_state *uart; |
6f251e9d | 583 | struct omap_hwmod *oh; |
3528c58e | 584 | struct platform_device *pdev; |
6f251e9d KH |
585 | void *pdata = NULL; |
586 | u32 pdata_size = 0; | |
587 | char *name; | |
6f251e9d | 588 | struct omap_uart_port_info omap_up; |
970a724d | 589 | |
40e44399 | 590 | if (WARN_ON(!bdata)) |
6f251e9d | 591 | return; |
40e44399 TL |
592 | if (WARN_ON(bdata->id < 0)) |
593 | return; | |
594 | if (WARN_ON(bdata->id >= num_uarts)) | |
e88d556d | 595 | return; |
f62349ee | 596 | |
6f251e9d | 597 | list_for_each_entry(uart, &uart_list, node) |
40e44399 | 598 | if (bdata->id == uart->num) |
6f251e9d | 599 | break; |
f2eeeae0 | 600 | |
6f251e9d KH |
601 | oh = uart->oh; |
602 | uart->dma_enabled = 0; | |
6f251e9d KH |
603 | name = DRIVER_NAME; |
604 | ||
605 | omap_up.dma_enabled = uart->dma_enabled; | |
606 | omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; | |
607 | omap_up.mapbase = oh->slaves[0]->addr->pa_start; | |
608 | omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); | |
609 | omap_up.irqflags = IRQF_SHARED; | |
610 | omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | |
611 | ||
612 | pdata = &omap_up; | |
613 | pdata_size = sizeof(struct omap_uart_port_info); | |
6f251e9d KH |
614 | |
615 | if (WARN_ON(!oh)) | |
616 | return; | |
617 | ||
3528c58e | 618 | pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, |
f718e2c0 | 619 | NULL, 0, false); |
3528c58e | 620 | WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", |
6f251e9d KH |
621 | name, oh->name); |
622 | ||
9f8b6949 | 623 | omap_device_disable_idle_on_suspend(pdev); |
40e44399 TL |
624 | oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); |
625 | ||
6f251e9d KH |
626 | uart->irq = oh->mpu_irqs[0].irq; |
627 | uart->regshift = 2; | |
628 | uart->mapbase = oh->slaves[0]->addr->pa_start; | |
629 | uart->membase = omap_hwmod_get_mpu_rt_va(oh); | |
3528c58e | 630 | uart->pdev = pdev; |
6f251e9d KH |
631 | |
632 | oh->dev_attr = uart; | |
633 | ||
ac751efa | 634 | console_lock(); /* in case the earlycon is on the UART */ |
0d8e2d0d | 635 | |
6f251e9d KH |
636 | /* |
637 | * Because of early UART probing, UART did not get idled | |
638 | * on init. Now that omap_device is ready, ensure full idle | |
639 | * before doing omap_device_enable(). | |
640 | */ | |
641 | omap_hwmod_idle(uart->oh); | |
642 | ||
643 | omap_device_enable(uart->pdev); | |
644 | omap_uart_idle_init(uart); | |
645 | omap_uart_reset(uart); | |
646 | omap_hwmod_enable_wakeup(uart->oh); | |
647 | omap_device_idle(uart->pdev); | |
648 | ||
649 | /* | |
650 | * Need to block sleep long enough for interrupt driven | |
651 | * driver to start. Console driver is in polling mode | |
652 | * so device needs to be kept enabled while polling driver | |
653 | * is in use. | |
654 | */ | |
655 | if (uart->timeout) | |
656 | uart->timeout = (30 * HZ); | |
657 | omap_uart_block_sleep(uart); | |
658 | uart->timeout = DEFAULT_TIMEOUT; | |
659 | ||
ac751efa | 660 | console_unlock(); |
0d8e2d0d | 661 | |
6f251e9d KH |
662 | if ((cpu_is_omap34xx() && uart->padconf) || |
663 | (uart->wk_en && uart->wk_mask)) { | |
3528c58e KH |
664 | device_init_wakeup(&pdev->dev, true); |
665 | DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout); | |
e03d37d8 | 666 | } |
00034509 D |
667 | |
668 | /* Enable the MDR1 errata for OMAP3 */ | |
a920360f | 669 | if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) |
00034509 | 670 | uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; |
f62349ee MW |
671 | } |
672 | ||
673 | /** | |
b595076a | 674 | * omap_serial_init() - initialize all supported serial ports |
f62349ee MW |
675 | * |
676 | * Initializes all available UARTs as serial ports. Platforms | |
677 | * can call this function when they want to have default behaviour | |
678 | * for serial ports (e.g initialize them all as serial ports). | |
679 | */ | |
680 | void __init omap_serial_init(void) | |
681 | { | |
6f251e9d | 682 | struct omap_uart_state *uart; |
40e44399 | 683 | struct omap_board_data bdata; |
f62349ee | 684 | |
40e44399 TL |
685 | list_for_each_entry(uart, &uart_list, node) { |
686 | bdata.id = uart->num; | |
687 | bdata.flags = 0; | |
688 | bdata.pads = NULL; | |
689 | bdata.pads_cnt = 0; | |
690 | omap_serial_init_port(&bdata); | |
691 | ||
692 | } | |
1dbae815 | 693 | } |