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Commit | Line | Data |
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1dbae815 | 1 | /* |
f30c2269 | 2 | * arch/arm/mach-omap2/serial.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 serial support. | |
5 | * | |
6e81176d | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
1dbae815 TL |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
8 | * | |
4af4016c KH |
9 | * Major rework for PM support by Kevin Hilman |
10 | * | |
1dbae815 TL |
11 | * Based off of arch/arm/mach-omap/omap1/serial.c |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com | |
15 | * | |
1dbae815 TL |
16 | * This file is subject to the terms and conditions of the GNU General Public |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
1dbae815 | 22 | #include <linux/serial_reg.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
fced80c7 | 24 | #include <linux/io.h> |
e03d37d8 | 25 | #include <linux/delay.h> |
6f251e9d KH |
26 | #include <linux/platform_device.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/serial_8250.h> | |
3244fcd2 | 29 | #include <linux/pm_runtime.h> |
0d8e2d0d | 30 | #include <linux/console.h> |
6f251e9d KH |
31 | |
32 | #ifdef CONFIG_SERIAL_OMAP | |
33 | #include <plat/omap-serial.h> | |
34 | #endif | |
1dbae815 | 35 | |
ce491cf8 TL |
36 | #include <plat/common.h> |
37 | #include <plat/board.h> | |
38 | #include <plat/clock.h> | |
6f251e9d KH |
39 | #include <plat/dma.h> |
40 | #include <plat/omap_hwmod.h> | |
41 | #include <plat/omap_device.h> | |
4af4016c | 42 | |
59fb659b | 43 | #include "prm2xxx_3xxx.h" |
4af4016c | 44 | #include "pm.h" |
59fb659b | 45 | #include "cm2xxx_3xxx.h" |
4af4016c | 46 | #include "prm-regbits-34xx.h" |
4814ced5 | 47 | #include "control.h" |
40e44399 | 48 | #include "mux.h" |
4af4016c | 49 | |
ce13d471 | 50 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
4af4016c KH |
51 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
52 | ||
5a927b36 | 53 | #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) |
00034509 | 54 | #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) |
5a927b36 | 55 | |
301fe8ee TL |
56 | /* |
57 | * NOTE: By default the serial timeout is disabled as it causes lost characters | |
58 | * over the serial ports. This means that the UART clocks will stay on until | |
59 | * disabled via sysfs. This also causes that any deeper omap sleep states are | |
60 | * blocked. | |
61 | */ | |
62 | #define DEFAULT_TIMEOUT 0 | |
4af4016c | 63 | |
6f251e9d KH |
64 | #define MAX_UART_HWMOD_NAME_LEN 16 |
65 | ||
4af4016c KH |
66 | struct omap_uart_state { |
67 | int num; | |
68 | int can_sleep; | |
69 | struct timer_list timer; | |
70 | u32 timeout; | |
71 | ||
72 | void __iomem *wk_st; | |
73 | void __iomem *wk_en; | |
74 | u32 wk_mask; | |
75 | u32 padconf; | |
6f251e9d | 76 | u32 dma_enabled; |
4af4016c KH |
77 | |
78 | struct clk *ick; | |
79 | struct clk *fck; | |
80 | int clocked; | |
81 | ||
6f251e9d KH |
82 | int irq; |
83 | int regshift; | |
84 | int irqflags; | |
85 | void __iomem *membase; | |
86 | resource_size_t mapbase; | |
87 | ||
4af4016c | 88 | struct list_head node; |
6f251e9d KH |
89 | struct omap_hwmod *oh; |
90 | struct platform_device *pdev; | |
1dbae815 | 91 | |
5a927b36 | 92 | u32 errata; |
4af4016c KH |
93 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
94 | int context_valid; | |
95 | ||
96 | /* Registers to be saved/restored for OFF-mode */ | |
97 | u16 dll; | |
98 | u16 dlh; | |
99 | u16 ier; | |
100 | u16 sysc; | |
101 | u16 scr; | |
102 | u16 wer; | |
5ade4ff5 | 103 | u16 mcr; |
4af4016c KH |
104 | #endif |
105 | }; | |
106 | ||
4af4016c | 107 | static LIST_HEAD(uart_list); |
6f251e9d | 108 | static u8 num_uarts; |
1dbae815 | 109 | |
8da37d9d KH |
110 | static int uart_idle_hwmod(struct omap_device *od) |
111 | { | |
dc6d1cda | 112 | omap_hwmod_idle(od->hwmods[0]); |
8da37d9d KH |
113 | |
114 | return 0; | |
115 | } | |
116 | ||
117 | static int uart_enable_hwmod(struct omap_device *od) | |
118 | { | |
dc6d1cda | 119 | omap_hwmod_enable(od->hwmods[0]); |
8da37d9d KH |
120 | |
121 | return 0; | |
122 | } | |
123 | ||
6f251e9d KH |
124 | static struct omap_device_pm_latency omap_uart_latency[] = { |
125 | { | |
8da37d9d KH |
126 | .deactivate_func = uart_idle_hwmod, |
127 | .activate_func = uart_enable_hwmod, | |
6f251e9d KH |
128 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, |
129 | }, | |
130 | }; | |
131 | ||
9230372a | 132 | static inline unsigned int __serial_read_reg(struct uart_port *up, |
6f251e9d | 133 | int offset) |
9230372a AS |
134 | { |
135 | offset <<= up->regshift; | |
136 | return (unsigned int)__raw_readb(up->membase + offset); | |
137 | } | |
138 | ||
6f251e9d | 139 | static inline unsigned int serial_read_reg(struct omap_uart_state *uart, |
1dbae815 TL |
140 | int offset) |
141 | { | |
6f251e9d KH |
142 | offset <<= uart->regshift; |
143 | return (unsigned int)__raw_readb(uart->membase + offset); | |
1dbae815 TL |
144 | } |
145 | ||
e03d37d8 SS |
146 | static inline void __serial_write_reg(struct uart_port *up, int offset, |
147 | int value) | |
148 | { | |
149 | offset <<= up->regshift; | |
150 | __raw_writeb(value, up->membase + offset); | |
151 | } | |
152 | ||
6f251e9d | 153 | static inline void serial_write_reg(struct omap_uart_state *uart, int offset, |
1dbae815 TL |
154 | int value) |
155 | { | |
6f251e9d KH |
156 | offset <<= uart->regshift; |
157 | __raw_writeb(value, uart->membase + offset); | |
1dbae815 TL |
158 | } |
159 | ||
160 | /* | |
161 | * Internal UARTs need to be initialized for the 8250 autoconfig to work | |
162 | * properly. Note that the TX watermark initialization may not be needed | |
163 | * once the 8250.c watermark handling code is merged. | |
164 | */ | |
6f251e9d | 165 | |
4af4016c | 166 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
1dbae815 | 167 | { |
498cb951 | 168 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
6f251e9d | 169 | serial_write_reg(uart, UART_OMAP_SCR, 0x08); |
498cb951 | 170 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); |
1dbae815 TL |
171 | } |
172 | ||
4af4016c KH |
173 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
174 | ||
00034509 D |
175 | /* |
176 | * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) | |
177 | * The access to uart register after MDR1 Access | |
178 | * causes UART to corrupt data. | |
179 | * | |
180 | * Need a delay = | |
181 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
182 | * give 10 times as much | |
183 | */ | |
184 | static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, | |
185 | u8 fcr_val) | |
186 | { | |
00034509 D |
187 | u8 timeout = 255; |
188 | ||
6f251e9d | 189 | serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); |
00034509 | 190 | udelay(2); |
6f251e9d | 191 | serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | |
00034509 D |
192 | UART_FCR_CLEAR_RCVR); |
193 | /* | |
194 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
195 | * TX_FIFO_E bit is 1. | |
196 | */ | |
6f251e9d | 197 | while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & |
00034509 D |
198 | (UART_LSR_THRE | UART_LSR_DR))) { |
199 | timeout--; | |
200 | if (!timeout) { | |
201 | /* Should *never* happen. we warn and carry on */ | |
6f251e9d KH |
202 | dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", |
203 | serial_read_reg(uart, UART_LSR)); | |
00034509 D |
204 | break; |
205 | } | |
206 | udelay(1); | |
207 | } | |
208 | } | |
209 | ||
4af4016c | 210 | static void omap_uart_save_context(struct omap_uart_state *uart) |
6e81176d | 211 | { |
4af4016c | 212 | u16 lcr = 0; |
4af4016c KH |
213 | |
214 | if (!enable_off_mode) | |
215 | return; | |
216 | ||
6f251e9d | 217 | lcr = serial_read_reg(uart, UART_LCR); |
662b083a | 218 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
219 | uart->dll = serial_read_reg(uart, UART_DLL); |
220 | uart->dlh = serial_read_reg(uart, UART_DLM); | |
221 | serial_write_reg(uart, UART_LCR, lcr); | |
222 | uart->ier = serial_read_reg(uart, UART_IER); | |
223 | uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); | |
224 | uart->scr = serial_read_reg(uart, UART_OMAP_SCR); | |
225 | uart->wer = serial_read_reg(uart, UART_OMAP_WER); | |
662b083a | 226 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
6f251e9d KH |
227 | uart->mcr = serial_read_reg(uart, UART_MCR); |
228 | serial_write_reg(uart, UART_LCR, lcr); | |
4af4016c KH |
229 | |
230 | uart->context_valid = 1; | |
231 | } | |
232 | ||
233 | static void omap_uart_restore_context(struct omap_uart_state *uart) | |
234 | { | |
235 | u16 efr = 0; | |
4af4016c KH |
236 | |
237 | if (!enable_off_mode) | |
238 | return; | |
239 | ||
240 | if (!uart->context_valid) | |
241 | return; | |
242 | ||
243 | uart->context_valid = 0; | |
244 | ||
00034509 | 245 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
498cb951 | 246 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); |
00034509 | 247 | else |
498cb951 AE |
248 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
249 | ||
662b083a | 250 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
251 | efr = serial_read_reg(uart, UART_EFR); |
252 | serial_write_reg(uart, UART_EFR, UART_EFR_ECB); | |
253 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | |
254 | serial_write_reg(uart, UART_IER, 0x0); | |
662b083a | 255 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
256 | serial_write_reg(uart, UART_DLL, uart->dll); |
257 | serial_write_reg(uart, UART_DLM, uart->dlh); | |
258 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | |
259 | serial_write_reg(uart, UART_IER, uart->ier); | |
662b083a | 260 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
6f251e9d | 261 | serial_write_reg(uart, UART_MCR, uart->mcr); |
662b083a | 262 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
263 | serial_write_reg(uart, UART_EFR, efr); |
264 | serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); | |
265 | serial_write_reg(uart, UART_OMAP_SCR, uart->scr); | |
266 | serial_write_reg(uart, UART_OMAP_WER, uart->wer); | |
267 | serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); | |
498cb951 | 268 | |
00034509 | 269 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
498cb951 | 270 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); |
00034509 | 271 | else |
6f251e9d | 272 | /* UART 16x mode */ |
498cb951 AE |
273 | serial_write_reg(uart, UART_OMAP_MDR1, |
274 | UART_OMAP_MDR1_16X_MODE); | |
4af4016c KH |
275 | } |
276 | #else | |
277 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | |
278 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} | |
279 | #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ | |
280 | ||
281 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) | |
282 | { | |
283 | if (uart->clocked) | |
284 | return; | |
285 | ||
6f251e9d | 286 | omap_device_enable(uart->pdev); |
4af4016c KH |
287 | uart->clocked = 1; |
288 | omap_uart_restore_context(uart); | |
289 | } | |
290 | ||
291 | #ifdef CONFIG_PM | |
292 | ||
293 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) | |
294 | { | |
295 | if (!uart->clocked) | |
296 | return; | |
297 | ||
298 | omap_uart_save_context(uart); | |
299 | uart->clocked = 0; | |
6f251e9d | 300 | omap_device_idle(uart->pdev); |
4af4016c KH |
301 | } |
302 | ||
fd455ea8 KH |
303 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) |
304 | { | |
305 | /* Set wake-enable bit */ | |
306 | if (uart->wk_en && uart->wk_mask) { | |
307 | u32 v = __raw_readl(uart->wk_en); | |
308 | v |= uart->wk_mask; | |
309 | __raw_writel(v, uart->wk_en); | |
310 | } | |
311 | ||
312 | /* Ensure IOPAD wake-enables are set */ | |
313 | if (cpu_is_omap34xx() && uart->padconf) { | |
314 | u16 v = omap_ctrl_readw(uart->padconf); | |
315 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | |
316 | omap_ctrl_writew(v, uart->padconf); | |
317 | } | |
318 | } | |
319 | ||
320 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) | |
321 | { | |
322 | /* Clear wake-enable bit */ | |
323 | if (uart->wk_en && uart->wk_mask) { | |
324 | u32 v = __raw_readl(uart->wk_en); | |
325 | v &= ~uart->wk_mask; | |
326 | __raw_writel(v, uart->wk_en); | |
327 | } | |
328 | ||
329 | /* Ensure IOPAD wake-enables are cleared */ | |
330 | if (cpu_is_omap34xx() && uart->padconf) { | |
331 | u16 v = omap_ctrl_readw(uart->padconf); | |
332 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; | |
333 | omap_ctrl_writew(v, uart->padconf); | |
334 | } | |
335 | } | |
336 | ||
4af4016c | 337 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
6f251e9d | 338 | int enable) |
4af4016c | 339 | { |
6f251e9d | 340 | u8 idlemode; |
4af4016c | 341 | |
6f251e9d KH |
342 | if (enable) { |
343 | /** | |
344 | * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests | |
345 | * in Smartidle Mode When Configured for DMA Operations. | |
346 | */ | |
347 | if (uart->dma_enabled) | |
348 | idlemode = HWMOD_IDLEMODE_FORCE; | |
349 | else | |
350 | idlemode = HWMOD_IDLEMODE_SMART; | |
351 | } else { | |
352 | idlemode = HWMOD_IDLEMODE_NO; | |
353 | } | |
4af4016c | 354 | |
6f251e9d | 355 | omap_hwmod_set_slave_idlemode(uart->oh, idlemode); |
4af4016c KH |
356 | } |
357 | ||
358 | static void omap_uart_block_sleep(struct omap_uart_state *uart) | |
359 | { | |
360 | omap_uart_enable_clocks(uart); | |
361 | ||
362 | omap_uart_smart_idle_enable(uart, 0); | |
363 | uart->can_sleep = 0; | |
ba87a9be JH |
364 | if (uart->timeout) |
365 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
366 | else | |
367 | del_timer(&uart->timer); | |
4af4016c KH |
368 | } |
369 | ||
370 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) | |
371 | { | |
6f251e9d | 372 | if (device_may_wakeup(&uart->pdev->dev)) |
fd455ea8 KH |
373 | omap_uart_enable_wakeup(uart); |
374 | else | |
375 | omap_uart_disable_wakeup(uart); | |
376 | ||
4af4016c KH |
377 | if (!uart->clocked) |
378 | return; | |
379 | ||
380 | omap_uart_smart_idle_enable(uart, 1); | |
381 | uart->can_sleep = 1; | |
382 | del_timer(&uart->timer); | |
383 | } | |
384 | ||
385 | static void omap_uart_idle_timer(unsigned long data) | |
386 | { | |
387 | struct omap_uart_state *uart = (struct omap_uart_state *)data; | |
388 | ||
389 | omap_uart_allow_sleep(uart); | |
390 | } | |
391 | ||
392 | void omap_uart_prepare_idle(int num) | |
393 | { | |
394 | struct omap_uart_state *uart; | |
395 | ||
396 | list_for_each_entry(uart, &uart_list, node) { | |
397 | if (num == uart->num && uart->can_sleep) { | |
398 | omap_uart_disable_clocks(uart); | |
399 | return; | |
400 | } | |
401 | } | |
402 | } | |
403 | ||
404 | void omap_uart_resume_idle(int num) | |
405 | { | |
406 | struct omap_uart_state *uart; | |
407 | ||
408 | list_for_each_entry(uart, &uart_list, node) { | |
f910043c | 409 | if (num == uart->num && uart->can_sleep) { |
4af4016c KH |
410 | omap_uart_enable_clocks(uart); |
411 | ||
412 | /* Check for IO pad wakeup */ | |
413 | if (cpu_is_omap34xx() && uart->padconf) { | |
414 | u16 p = omap_ctrl_readw(uart->padconf); | |
415 | ||
416 | if (p & OMAP3_PADCONF_WAKEUPEVENT0) | |
417 | omap_uart_block_sleep(uart); | |
6e81176d | 418 | } |
4af4016c KH |
419 | |
420 | /* Check for normal UART wakeup */ | |
421 | if (__raw_readl(uart->wk_st) & uart->wk_mask) | |
422 | omap_uart_block_sleep(uart); | |
4af4016c KH |
423 | return; |
424 | } | |
425 | } | |
426 | } | |
427 | ||
428 | void omap_uart_prepare_suspend(void) | |
429 | { | |
430 | struct omap_uart_state *uart; | |
431 | ||
432 | list_for_each_entry(uart, &uart_list, node) { | |
433 | omap_uart_allow_sleep(uart); | |
434 | } | |
435 | } | |
436 | ||
437 | int omap_uart_can_sleep(void) | |
438 | { | |
439 | struct omap_uart_state *uart; | |
440 | int can_sleep = 1; | |
441 | ||
442 | list_for_each_entry(uart, &uart_list, node) { | |
443 | if (!uart->clocked) | |
444 | continue; | |
445 | ||
446 | if (!uart->can_sleep) { | |
447 | can_sleep = 0; | |
448 | continue; | |
6e81176d | 449 | } |
4af4016c KH |
450 | |
451 | /* This UART can now safely sleep. */ | |
452 | omap_uart_allow_sleep(uart); | |
6e81176d | 453 | } |
4af4016c KH |
454 | |
455 | return can_sleep; | |
6e81176d JH |
456 | } |
457 | ||
4af4016c KH |
458 | /** |
459 | * omap_uart_interrupt() | |
460 | * | |
461 | * This handler is used only to detect that *any* UART interrupt has | |
462 | * occurred. It does _nothing_ to handle the interrupt. Rather, | |
463 | * any UART interrupt will trigger the inactivity timer so the | |
464 | * UART will not idle or sleep for its timeout period. | |
465 | * | |
466 | **/ | |
6f251e9d | 467 | /* static int first_interrupt; */ |
4af4016c KH |
468 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) |
469 | { | |
470 | struct omap_uart_state *uart = dev_id; | |
471 | ||
472 | omap_uart_block_sleep(uart); | |
473 | ||
474 | return IRQ_NONE; | |
475 | } | |
476 | ||
477 | static void omap_uart_idle_init(struct omap_uart_state *uart) | |
478 | { | |
4af4016c KH |
479 | int ret; |
480 | ||
481 | uart->can_sleep = 0; | |
fd455ea8 | 482 | uart->timeout = DEFAULT_TIMEOUT; |
4af4016c KH |
483 | setup_timer(&uart->timer, omap_uart_idle_timer, |
484 | (unsigned long) uart); | |
301fe8ee TL |
485 | if (uart->timeout) |
486 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
4af4016c KH |
487 | omap_uart_smart_idle_enable(uart, 0); |
488 | ||
01001712 | 489 | if (cpu_is_omap34xx() && !cpu_is_ti816x()) { |
52663aea | 490 | u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; |
4af4016c KH |
491 | u32 wk_mask = 0; |
492 | u32 padconf = 0; | |
493 | ||
c4d7e58f | 494 | /* XXX These PRM accesses do not belong here */ |
4af4016c KH |
495 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); |
496 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); | |
497 | switch (uart->num) { | |
498 | case 0: | |
499 | wk_mask = OMAP3430_ST_UART1_MASK; | |
500 | padconf = 0x182; | |
501 | break; | |
502 | case 1: | |
503 | wk_mask = OMAP3430_ST_UART2_MASK; | |
504 | padconf = 0x17a; | |
505 | break; | |
506 | case 2: | |
507 | wk_mask = OMAP3430_ST_UART3_MASK; | |
508 | padconf = 0x19e; | |
509 | break; | |
52663aea G |
510 | case 3: |
511 | wk_mask = OMAP3630_ST_UART4_MASK; | |
512 | padconf = 0x0d2; | |
513 | break; | |
4af4016c KH |
514 | } |
515 | uart->wk_mask = wk_mask; | |
516 | uart->padconf = padconf; | |
517 | } else if (cpu_is_omap24xx()) { | |
518 | u32 wk_mask = 0; | |
cb74f022 | 519 | u32 wk_en = PM_WKEN1, wk_st = PM_WKST1; |
4af4016c | 520 | |
4af4016c KH |
521 | switch (uart->num) { |
522 | case 0: | |
523 | wk_mask = OMAP24XX_ST_UART1_MASK; | |
524 | break; | |
525 | case 1: | |
526 | wk_mask = OMAP24XX_ST_UART2_MASK; | |
527 | break; | |
528 | case 2: | |
cb74f022 KH |
529 | wk_en = OMAP24XX_PM_WKEN2; |
530 | wk_st = OMAP24XX_PM_WKST2; | |
4af4016c KH |
531 | wk_mask = OMAP24XX_ST_UART3_MASK; |
532 | break; | |
533 | } | |
534 | uart->wk_mask = wk_mask; | |
cb74f022 KH |
535 | if (cpu_is_omap2430()) { |
536 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); | |
537 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); | |
538 | } else if (cpu_is_omap2420()) { | |
539 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); | |
540 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); | |
541 | } | |
4af4016c | 542 | } else { |
c54bae1f NM |
543 | uart->wk_en = NULL; |
544 | uart->wk_st = NULL; | |
4af4016c KH |
545 | uart->wk_mask = 0; |
546 | uart->padconf = 0; | |
547 | } | |
548 | ||
6f251e9d KH |
549 | uart->irqflags |= IRQF_SHARED; |
550 | ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, | |
551 | IRQF_SHARED, "serial idle", (void *)uart); | |
4af4016c KH |
552 | WARN_ON(ret); |
553 | } | |
554 | ||
2466211e TK |
555 | void omap_uart_enable_irqs(int enable) |
556 | { | |
557 | int ret; | |
558 | struct omap_uart_state *uart; | |
559 | ||
560 | list_for_each_entry(uart, &uart_list, node) { | |
3244fcd2 KH |
561 | if (enable) { |
562 | pm_runtime_put_sync(&uart->pdev->dev); | |
6f251e9d KH |
563 | ret = request_threaded_irq(uart->irq, NULL, |
564 | omap_uart_interrupt, | |
565 | IRQF_SHARED, | |
566 | "serial idle", | |
567 | (void *)uart); | |
3244fcd2 KH |
568 | } else { |
569 | pm_runtime_get_noresume(&uart->pdev->dev); | |
6f251e9d | 570 | free_irq(uart->irq, (void *)uart); |
3244fcd2 | 571 | } |
2466211e TK |
572 | } |
573 | } | |
574 | ||
fd455ea8 KH |
575 | static ssize_t sleep_timeout_show(struct device *dev, |
576 | struct device_attribute *attr, | |
ba87a9be JH |
577 | char *buf) |
578 | { | |
6f251e9d KH |
579 | struct platform_device *pdev = to_platform_device(dev); |
580 | struct omap_device *odev = to_omap_device(pdev); | |
581 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; | |
fd455ea8 KH |
582 | |
583 | return sprintf(buf, "%u\n", uart->timeout / HZ); | |
ba87a9be JH |
584 | } |
585 | ||
fd455ea8 KH |
586 | static ssize_t sleep_timeout_store(struct device *dev, |
587 | struct device_attribute *attr, | |
ba87a9be JH |
588 | const char *buf, size_t n) |
589 | { | |
6f251e9d KH |
590 | struct platform_device *pdev = to_platform_device(dev); |
591 | struct omap_device *odev = to_omap_device(pdev); | |
592 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; | |
ba87a9be JH |
593 | unsigned int value; |
594 | ||
595 | if (sscanf(buf, "%u", &value) != 1) { | |
10c805eb | 596 | dev_err(dev, "sleep_timeout_store: Invalid value\n"); |
ba87a9be JH |
597 | return -EINVAL; |
598 | } | |
fd455ea8 KH |
599 | |
600 | uart->timeout = value * HZ; | |
601 | if (uart->timeout) | |
602 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
603 | else | |
604 | /* A zero value means disable timeout feature */ | |
605 | omap_uart_block_sleep(uart); | |
606 | ||
ba87a9be JH |
607 | return n; |
608 | } | |
609 | ||
bfe6977a NM |
610 | static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, |
611 | sleep_timeout_store); | |
fd455ea8 | 612 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) |
4af4016c KH |
613 | #else |
614 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | |
a1b04cc1 SS |
615 | static void omap_uart_block_sleep(struct omap_uart_state *uart) |
616 | { | |
617 | /* Needed to enable UART clocks when built without CONFIG_PM */ | |
618 | omap_uart_enable_clocks(uart); | |
619 | } | |
fd455ea8 | 620 | #define DEV_CREATE_FILE(dev, attr) |
4af4016c KH |
621 | #endif /* CONFIG_PM */ |
622 | ||
6f251e9d | 623 | #ifndef CONFIG_SERIAL_OMAP |
ce13d471 | 624 | /* |
625 | * Override the default 8250 read handler: mem_serial_in() | |
626 | * Empty RX fifo read causes an abort on omap3630 and omap4 | |
627 | * This function makes sure that an empty rx fifo is not read on these silicons | |
628 | * (OMAP1/2/3430 are not affected) | |
629 | */ | |
630 | static unsigned int serial_in_override(struct uart_port *up, int offset) | |
631 | { | |
632 | if (UART_RX == offset) { | |
633 | unsigned int lsr; | |
9230372a | 634 | lsr = __serial_read_reg(up, UART_LSR); |
ce13d471 | 635 | if (!(lsr & UART_LSR_DR)) |
636 | return -EPERM; | |
637 | } | |
9230372a AS |
638 | |
639 | return __serial_read_reg(up, offset); | |
ce13d471 | 640 | } |
641 | ||
e03d37d8 SS |
642 | static void serial_out_override(struct uart_port *up, int offset, int value) |
643 | { | |
644 | unsigned int status, tmout = 10000; | |
645 | ||
646 | status = __serial_read_reg(up, UART_LSR); | |
647 | while (!(status & UART_LSR_THRE)) { | |
648 | /* Wait up to 10ms for the character(s) to be sent. */ | |
649 | if (--tmout == 0) | |
650 | break; | |
651 | udelay(1); | |
652 | status = __serial_read_reg(up, UART_LSR); | |
653 | } | |
654 | __serial_write_reg(up, offset, value); | |
655 | } | |
6f251e9d KH |
656 | #endif |
657 | ||
3e16f925 | 658 | static int __init omap_serial_early_init(void) |
1dbae815 | 659 | { |
6f251e9d | 660 | int i = 0; |
1dbae815 | 661 | |
6f251e9d KH |
662 | do { |
663 | char oh_name[MAX_UART_HWMOD_NAME_LEN]; | |
664 | struct omap_hwmod *oh; | |
665 | struct omap_uart_state *uart; | |
21b90340 | 666 | |
6f251e9d KH |
667 | snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, |
668 | "uart%d", i + 1); | |
669 | oh = omap_hwmod_lookup(oh_name); | |
670 | if (!oh) | |
671 | break; | |
672 | ||
673 | uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); | |
674 | if (WARN_ON(!uart)) | |
3e16f925 | 675 | return -ENODEV; |
1dbae815 | 676 | |
6f251e9d KH |
677 | uart->oh = oh; |
678 | uart->num = i++; | |
679 | list_add_tail(&uart->node, &uart_list); | |
680 | num_uarts++; | |
1dbae815 | 681 | |
84f90c9c | 682 | /* |
550c8092 | 683 | * NOTE: omap_hwmod_setup*() has not yet been called, |
6f251e9d | 684 | * so no hwmod functions will work yet. |
84f90c9c | 685 | */ |
6e81176d | 686 | |
6f251e9d KH |
687 | /* |
688 | * During UART early init, device need to be probed | |
689 | * to determine SoC specific init before omap_device | |
690 | * is ready. Therefore, don't allow idle here | |
691 | */ | |
692 | uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; | |
693 | } while (1); | |
3e16f925 TL |
694 | |
695 | return 0; | |
b3c6df3a | 696 | } |
3e16f925 | 697 | core_initcall(omap_serial_early_init); |
b3c6df3a | 698 | |
f62349ee MW |
699 | /** |
700 | * omap_serial_init_port() - initialize single serial port | |
40e44399 | 701 | * @bdata: port specific board data pointer |
f62349ee | 702 | * |
40e44399 | 703 | * This function initialies serial driver for given port only. |
f62349ee MW |
704 | * Platforms can call this function instead of omap_serial_init() |
705 | * if they don't plan to use all available UARTs as serial ports. | |
706 | * | |
707 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), | |
708 | * use only one of the two. | |
709 | */ | |
40e44399 | 710 | void __init omap_serial_init_port(struct omap_board_data *bdata) |
b3c6df3a | 711 | { |
f62349ee | 712 | struct omap_uart_state *uart; |
6f251e9d KH |
713 | struct omap_hwmod *oh; |
714 | struct omap_device *od; | |
715 | void *pdata = NULL; | |
716 | u32 pdata_size = 0; | |
717 | char *name; | |
718 | #ifndef CONFIG_SERIAL_OMAP | |
719 | struct plat_serial8250_port ports[2] = { | |
720 | {}, | |
721 | {.flags = 0}, | |
722 | }; | |
723 | struct plat_serial8250_port *p = &ports[0]; | |
724 | #else | |
725 | struct omap_uart_port_info omap_up; | |
726 | #endif | |
970a724d | 727 | |
40e44399 | 728 | if (WARN_ON(!bdata)) |
6f251e9d | 729 | return; |
40e44399 TL |
730 | if (WARN_ON(bdata->id < 0)) |
731 | return; | |
732 | if (WARN_ON(bdata->id >= num_uarts)) | |
e88d556d | 733 | return; |
f62349ee | 734 | |
6f251e9d | 735 | list_for_each_entry(uart, &uart_list, node) |
40e44399 | 736 | if (bdata->id == uart->num) |
6f251e9d | 737 | break; |
f2eeeae0 | 738 | |
6f251e9d KH |
739 | oh = uart->oh; |
740 | uart->dma_enabled = 0; | |
741 | #ifndef CONFIG_SERIAL_OMAP | |
742 | name = "serial8250"; | |
f62349ee | 743 | |
6f251e9d KH |
744 | /* |
745 | * !! 8250 driver does not use standard IORESOURCE* It | |
746 | * has it's own custom pdata that can be taken from | |
747 | * the hwmod resource data. But, this needs to be | |
748 | * done after the build. | |
749 | * | |
750 | * ?? does it have to be done before the register ?? | |
751 | * YES, because platform_device_data_add() copies | |
752 | * pdata, it does not use a pointer. | |
753 | */ | |
754 | p->flags = UPF_BOOT_AUTOCONF; | |
755 | p->iotype = UPIO_MEM; | |
756 | p->regshift = 2; | |
757 | p->uartclk = OMAP24XX_BASE_BAUD * 16; | |
758 | p->irq = oh->mpu_irqs[0].irq; | |
759 | p->mapbase = oh->slaves[0]->addr->pa_start; | |
760 | p->membase = omap_hwmod_get_mpu_rt_va(oh); | |
761 | p->irqflags = IRQF_SHARED; | |
762 | p->private_data = uart; | |
f62349ee | 763 | |
30e53bcc | 764 | /* |
01001712 | 765 | * omap44xx, ti816x: Never read empty UART fifo |
30e53bcc | 766 | * omap3xxx: Never read empty UART fifo on UARTs |
767 | * with IP rev >=0x52 | |
768 | */ | |
6f251e9d KH |
769 | uart->regshift = p->regshift; |
770 | uart->membase = p->membase; | |
01001712 | 771 | if (cpu_is_omap44xx() || cpu_is_ti816x()) |
5a927b36 | 772 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; |
6f251e9d | 773 | else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) |
5a927b36 NM |
774 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) |
775 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; | |
776 | ||
777 | if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { | |
6f251e9d KH |
778 | p->serial_in = serial_in_override; |
779 | p->serial_out = serial_out_override; | |
780 | } | |
781 | ||
782 | pdata = &ports[0]; | |
783 | pdata_size = 2 * sizeof(struct plat_serial8250_port); | |
784 | #else | |
785 | ||
786 | name = DRIVER_NAME; | |
787 | ||
788 | omap_up.dma_enabled = uart->dma_enabled; | |
789 | omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; | |
790 | omap_up.mapbase = oh->slaves[0]->addr->pa_start; | |
791 | omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); | |
792 | omap_up.irqflags = IRQF_SHARED; | |
793 | omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | |
794 | ||
795 | pdata = &omap_up; | |
796 | pdata_size = sizeof(struct omap_uart_port_info); | |
797 | #endif | |
798 | ||
799 | if (WARN_ON(!oh)) | |
800 | return; | |
801 | ||
802 | od = omap_device_build(name, uart->num, oh, pdata, pdata_size, | |
803 | omap_uart_latency, | |
804 | ARRAY_SIZE(omap_uart_latency), false); | |
805 | WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", | |
806 | name, oh->name); | |
807 | ||
c8c9fda5 | 808 | omap_device_disable_idle_on_suspend(od); |
40e44399 TL |
809 | oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); |
810 | ||
6f251e9d KH |
811 | uart->irq = oh->mpu_irqs[0].irq; |
812 | uart->regshift = 2; | |
813 | uart->mapbase = oh->slaves[0]->addr->pa_start; | |
814 | uart->membase = omap_hwmod_get_mpu_rt_va(oh); | |
815 | uart->pdev = &od->pdev; | |
816 | ||
817 | oh->dev_attr = uart; | |
818 | ||
ac751efa | 819 | console_lock(); /* in case the earlycon is on the UART */ |
0d8e2d0d | 820 | |
6f251e9d KH |
821 | /* |
822 | * Because of early UART probing, UART did not get idled | |
823 | * on init. Now that omap_device is ready, ensure full idle | |
824 | * before doing omap_device_enable(). | |
825 | */ | |
826 | omap_hwmod_idle(uart->oh); | |
827 | ||
828 | omap_device_enable(uart->pdev); | |
829 | omap_uart_idle_init(uart); | |
830 | omap_uart_reset(uart); | |
831 | omap_hwmod_enable_wakeup(uart->oh); | |
832 | omap_device_idle(uart->pdev); | |
833 | ||
834 | /* | |
835 | * Need to block sleep long enough for interrupt driven | |
836 | * driver to start. Console driver is in polling mode | |
837 | * so device needs to be kept enabled while polling driver | |
838 | * is in use. | |
839 | */ | |
840 | if (uart->timeout) | |
841 | uart->timeout = (30 * HZ); | |
842 | omap_uart_block_sleep(uart); | |
843 | uart->timeout = DEFAULT_TIMEOUT; | |
844 | ||
ac751efa | 845 | console_unlock(); |
0d8e2d0d | 846 | |
6f251e9d KH |
847 | if ((cpu_is_omap34xx() && uart->padconf) || |
848 | (uart->wk_en && uart->wk_mask)) { | |
849 | device_init_wakeup(&od->pdev.dev, true); | |
850 | DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout); | |
e03d37d8 | 851 | } |
00034509 D |
852 | |
853 | /* Enable the MDR1 errata for OMAP3 */ | |
01001712 | 854 | if (cpu_is_omap34xx() && !cpu_is_ti816x()) |
00034509 | 855 | uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; |
f62349ee MW |
856 | } |
857 | ||
858 | /** | |
b595076a | 859 | * omap_serial_init() - initialize all supported serial ports |
f62349ee MW |
860 | * |
861 | * Initializes all available UARTs as serial ports. Platforms | |
862 | * can call this function when they want to have default behaviour | |
863 | * for serial ports (e.g initialize them all as serial ports). | |
864 | */ | |
865 | void __init omap_serial_init(void) | |
866 | { | |
6f251e9d | 867 | struct omap_uart_state *uart; |
40e44399 | 868 | struct omap_board_data bdata; |
f62349ee | 869 | |
40e44399 TL |
870 | list_for_each_entry(uart, &uart_list, node) { |
871 | bdata.id = uart->num; | |
872 | bdata.flags = 0; | |
873 | bdata.pads = NULL; | |
874 | bdata.pads_cnt = 0; | |
875 | omap_serial_init_port(&bdata); | |
876 | ||
877 | } | |
1dbae815 | 878 | } |