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Commit | Line | Data |
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1dbae815 | 1 | /* |
f30c2269 | 2 | * arch/arm/mach-omap2/serial.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 serial support. | |
5 | * | |
6e81176d | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
1dbae815 TL |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
8 | * | |
4af4016c KH |
9 | * Major rework for PM support by Kevin Hilman |
10 | * | |
1dbae815 TL |
11 | * Based off of arch/arm/mach-omap/omap1/serial.c |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com | |
15 | * | |
1dbae815 TL |
16 | * This file is subject to the terms and conditions of the GNU General Public |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
1dbae815 | 22 | #include <linux/serial_reg.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
fced80c7 | 24 | #include <linux/io.h> |
e03d37d8 | 25 | #include <linux/delay.h> |
6f251e9d KH |
26 | #include <linux/platform_device.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/serial_8250.h> | |
3244fcd2 | 29 | #include <linux/pm_runtime.h> |
0d8e2d0d | 30 | #include <linux/console.h> |
6f251e9d KH |
31 | |
32 | #ifdef CONFIG_SERIAL_OMAP | |
33 | #include <plat/omap-serial.h> | |
34 | #endif | |
1dbae815 | 35 | |
ce491cf8 TL |
36 | #include <plat/common.h> |
37 | #include <plat/board.h> | |
38 | #include <plat/clock.h> | |
6f251e9d KH |
39 | #include <plat/dma.h> |
40 | #include <plat/omap_hwmod.h> | |
41 | #include <plat/omap_device.h> | |
4af4016c | 42 | |
59fb659b | 43 | #include "prm2xxx_3xxx.h" |
4af4016c | 44 | #include "pm.h" |
59fb659b | 45 | #include "cm2xxx_3xxx.h" |
4af4016c | 46 | #include "prm-regbits-34xx.h" |
4814ced5 | 47 | #include "control.h" |
4af4016c | 48 | |
ce13d471 | 49 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
4af4016c KH |
50 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
51 | ||
5a927b36 | 52 | #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) |
00034509 | 53 | #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) |
5a927b36 | 54 | |
301fe8ee TL |
55 | /* |
56 | * NOTE: By default the serial timeout is disabled as it causes lost characters | |
57 | * over the serial ports. This means that the UART clocks will stay on until | |
58 | * disabled via sysfs. This also causes that any deeper omap sleep states are | |
59 | * blocked. | |
60 | */ | |
61 | #define DEFAULT_TIMEOUT 0 | |
4af4016c | 62 | |
6f251e9d KH |
63 | #define MAX_UART_HWMOD_NAME_LEN 16 |
64 | ||
4af4016c KH |
65 | struct omap_uart_state { |
66 | int num; | |
67 | int can_sleep; | |
68 | struct timer_list timer; | |
69 | u32 timeout; | |
70 | ||
71 | void __iomem *wk_st; | |
72 | void __iomem *wk_en; | |
73 | u32 wk_mask; | |
74 | u32 padconf; | |
6f251e9d | 75 | u32 dma_enabled; |
4af4016c KH |
76 | |
77 | struct clk *ick; | |
78 | struct clk *fck; | |
79 | int clocked; | |
80 | ||
6f251e9d KH |
81 | int irq; |
82 | int regshift; | |
83 | int irqflags; | |
84 | void __iomem *membase; | |
85 | resource_size_t mapbase; | |
86 | ||
4af4016c | 87 | struct list_head node; |
6f251e9d KH |
88 | struct omap_hwmod *oh; |
89 | struct platform_device *pdev; | |
1dbae815 | 90 | |
5a927b36 | 91 | u32 errata; |
4af4016c KH |
92 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
93 | int context_valid; | |
94 | ||
95 | /* Registers to be saved/restored for OFF-mode */ | |
96 | u16 dll; | |
97 | u16 dlh; | |
98 | u16 ier; | |
99 | u16 sysc; | |
100 | u16 scr; | |
101 | u16 wer; | |
5ade4ff5 | 102 | u16 mcr; |
4af4016c KH |
103 | #endif |
104 | }; | |
105 | ||
4af4016c | 106 | static LIST_HEAD(uart_list); |
6f251e9d | 107 | static u8 num_uarts; |
1dbae815 | 108 | |
8da37d9d KH |
109 | static int uart_idle_hwmod(struct omap_device *od) |
110 | { | |
dc6d1cda | 111 | omap_hwmod_idle(od->hwmods[0]); |
8da37d9d KH |
112 | |
113 | return 0; | |
114 | } | |
115 | ||
116 | static int uart_enable_hwmod(struct omap_device *od) | |
117 | { | |
dc6d1cda | 118 | omap_hwmod_enable(od->hwmods[0]); |
8da37d9d KH |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
6f251e9d KH |
123 | static struct omap_device_pm_latency omap_uart_latency[] = { |
124 | { | |
8da37d9d KH |
125 | .deactivate_func = uart_idle_hwmod, |
126 | .activate_func = uart_enable_hwmod, | |
6f251e9d KH |
127 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, |
128 | }, | |
129 | }; | |
130 | ||
9230372a | 131 | static inline unsigned int __serial_read_reg(struct uart_port *up, |
6f251e9d | 132 | int offset) |
9230372a AS |
133 | { |
134 | offset <<= up->regshift; | |
135 | return (unsigned int)__raw_readb(up->membase + offset); | |
136 | } | |
137 | ||
6f251e9d | 138 | static inline unsigned int serial_read_reg(struct omap_uart_state *uart, |
1dbae815 TL |
139 | int offset) |
140 | { | |
6f251e9d KH |
141 | offset <<= uart->regshift; |
142 | return (unsigned int)__raw_readb(uart->membase + offset); | |
1dbae815 TL |
143 | } |
144 | ||
e03d37d8 SS |
145 | static inline void __serial_write_reg(struct uart_port *up, int offset, |
146 | int value) | |
147 | { | |
148 | offset <<= up->regshift; | |
149 | __raw_writeb(value, up->membase + offset); | |
150 | } | |
151 | ||
6f251e9d | 152 | static inline void serial_write_reg(struct omap_uart_state *uart, int offset, |
1dbae815 TL |
153 | int value) |
154 | { | |
6f251e9d KH |
155 | offset <<= uart->regshift; |
156 | __raw_writeb(value, uart->membase + offset); | |
1dbae815 TL |
157 | } |
158 | ||
159 | /* | |
160 | * Internal UARTs need to be initialized for the 8250 autoconfig to work | |
161 | * properly. Note that the TX watermark initialization may not be needed | |
162 | * once the 8250.c watermark handling code is merged. | |
163 | */ | |
6f251e9d | 164 | |
4af4016c | 165 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
1dbae815 | 166 | { |
498cb951 | 167 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
6f251e9d | 168 | serial_write_reg(uart, UART_OMAP_SCR, 0x08); |
498cb951 | 169 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); |
1dbae815 TL |
170 | } |
171 | ||
4af4016c KH |
172 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
173 | ||
00034509 D |
174 | /* |
175 | * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) | |
176 | * The access to uart register after MDR1 Access | |
177 | * causes UART to corrupt data. | |
178 | * | |
179 | * Need a delay = | |
180 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
181 | * give 10 times as much | |
182 | */ | |
183 | static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, | |
184 | u8 fcr_val) | |
185 | { | |
00034509 D |
186 | u8 timeout = 255; |
187 | ||
6f251e9d | 188 | serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); |
00034509 | 189 | udelay(2); |
6f251e9d | 190 | serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | |
00034509 D |
191 | UART_FCR_CLEAR_RCVR); |
192 | /* | |
193 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
194 | * TX_FIFO_E bit is 1. | |
195 | */ | |
6f251e9d | 196 | while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & |
00034509 D |
197 | (UART_LSR_THRE | UART_LSR_DR))) { |
198 | timeout--; | |
199 | if (!timeout) { | |
200 | /* Should *never* happen. we warn and carry on */ | |
6f251e9d KH |
201 | dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", |
202 | serial_read_reg(uart, UART_LSR)); | |
00034509 D |
203 | break; |
204 | } | |
205 | udelay(1); | |
206 | } | |
207 | } | |
208 | ||
4af4016c | 209 | static void omap_uart_save_context(struct omap_uart_state *uart) |
6e81176d | 210 | { |
4af4016c | 211 | u16 lcr = 0; |
4af4016c KH |
212 | |
213 | if (!enable_off_mode) | |
214 | return; | |
215 | ||
6f251e9d | 216 | lcr = serial_read_reg(uart, UART_LCR); |
662b083a | 217 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
218 | uart->dll = serial_read_reg(uart, UART_DLL); |
219 | uart->dlh = serial_read_reg(uart, UART_DLM); | |
220 | serial_write_reg(uart, UART_LCR, lcr); | |
221 | uart->ier = serial_read_reg(uart, UART_IER); | |
222 | uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); | |
223 | uart->scr = serial_read_reg(uart, UART_OMAP_SCR); | |
224 | uart->wer = serial_read_reg(uart, UART_OMAP_WER); | |
662b083a | 225 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
6f251e9d KH |
226 | uart->mcr = serial_read_reg(uart, UART_MCR); |
227 | serial_write_reg(uart, UART_LCR, lcr); | |
4af4016c KH |
228 | |
229 | uart->context_valid = 1; | |
230 | } | |
231 | ||
232 | static void omap_uart_restore_context(struct omap_uart_state *uart) | |
233 | { | |
234 | u16 efr = 0; | |
4af4016c KH |
235 | |
236 | if (!enable_off_mode) | |
237 | return; | |
238 | ||
239 | if (!uart->context_valid) | |
240 | return; | |
241 | ||
242 | uart->context_valid = 0; | |
243 | ||
00034509 | 244 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
498cb951 | 245 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); |
00034509 | 246 | else |
498cb951 AE |
247 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
248 | ||
662b083a | 249 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
250 | efr = serial_read_reg(uart, UART_EFR); |
251 | serial_write_reg(uart, UART_EFR, UART_EFR_ECB); | |
252 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | |
253 | serial_write_reg(uart, UART_IER, 0x0); | |
662b083a | 254 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
255 | serial_write_reg(uart, UART_DLL, uart->dll); |
256 | serial_write_reg(uart, UART_DLM, uart->dlh); | |
257 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | |
258 | serial_write_reg(uart, UART_IER, uart->ier); | |
662b083a | 259 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
6f251e9d | 260 | serial_write_reg(uart, UART_MCR, uart->mcr); |
662b083a | 261 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
6f251e9d KH |
262 | serial_write_reg(uart, UART_EFR, efr); |
263 | serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); | |
264 | serial_write_reg(uart, UART_OMAP_SCR, uart->scr); | |
265 | serial_write_reg(uart, UART_OMAP_WER, uart->wer); | |
266 | serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); | |
498cb951 | 267 | |
00034509 | 268 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
498cb951 | 269 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); |
00034509 | 270 | else |
6f251e9d | 271 | /* UART 16x mode */ |
498cb951 AE |
272 | serial_write_reg(uart, UART_OMAP_MDR1, |
273 | UART_OMAP_MDR1_16X_MODE); | |
4af4016c KH |
274 | } |
275 | #else | |
276 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | |
277 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} | |
278 | #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ | |
279 | ||
280 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) | |
281 | { | |
282 | if (uart->clocked) | |
283 | return; | |
284 | ||
6f251e9d | 285 | omap_device_enable(uart->pdev); |
4af4016c KH |
286 | uart->clocked = 1; |
287 | omap_uart_restore_context(uart); | |
288 | } | |
289 | ||
290 | #ifdef CONFIG_PM | |
291 | ||
292 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) | |
293 | { | |
294 | if (!uart->clocked) | |
295 | return; | |
296 | ||
297 | omap_uart_save_context(uart); | |
298 | uart->clocked = 0; | |
6f251e9d | 299 | omap_device_idle(uart->pdev); |
4af4016c KH |
300 | } |
301 | ||
fd455ea8 KH |
302 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) |
303 | { | |
304 | /* Set wake-enable bit */ | |
305 | if (uart->wk_en && uart->wk_mask) { | |
306 | u32 v = __raw_readl(uart->wk_en); | |
307 | v |= uart->wk_mask; | |
308 | __raw_writel(v, uart->wk_en); | |
309 | } | |
310 | ||
311 | /* Ensure IOPAD wake-enables are set */ | |
312 | if (cpu_is_omap34xx() && uart->padconf) { | |
313 | u16 v = omap_ctrl_readw(uart->padconf); | |
314 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | |
315 | omap_ctrl_writew(v, uart->padconf); | |
316 | } | |
317 | } | |
318 | ||
319 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) | |
320 | { | |
321 | /* Clear wake-enable bit */ | |
322 | if (uart->wk_en && uart->wk_mask) { | |
323 | u32 v = __raw_readl(uart->wk_en); | |
324 | v &= ~uart->wk_mask; | |
325 | __raw_writel(v, uart->wk_en); | |
326 | } | |
327 | ||
328 | /* Ensure IOPAD wake-enables are cleared */ | |
329 | if (cpu_is_omap34xx() && uart->padconf) { | |
330 | u16 v = omap_ctrl_readw(uart->padconf); | |
331 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; | |
332 | omap_ctrl_writew(v, uart->padconf); | |
333 | } | |
334 | } | |
335 | ||
4af4016c | 336 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
6f251e9d | 337 | int enable) |
4af4016c | 338 | { |
6f251e9d | 339 | u8 idlemode; |
4af4016c | 340 | |
6f251e9d KH |
341 | if (enable) { |
342 | /** | |
343 | * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests | |
344 | * in Smartidle Mode When Configured for DMA Operations. | |
345 | */ | |
346 | if (uart->dma_enabled) | |
347 | idlemode = HWMOD_IDLEMODE_FORCE; | |
348 | else | |
349 | idlemode = HWMOD_IDLEMODE_SMART; | |
350 | } else { | |
351 | idlemode = HWMOD_IDLEMODE_NO; | |
352 | } | |
4af4016c | 353 | |
6f251e9d | 354 | omap_hwmod_set_slave_idlemode(uart->oh, idlemode); |
4af4016c KH |
355 | } |
356 | ||
357 | static void omap_uart_block_sleep(struct omap_uart_state *uart) | |
358 | { | |
359 | omap_uart_enable_clocks(uart); | |
360 | ||
361 | omap_uart_smart_idle_enable(uart, 0); | |
362 | uart->can_sleep = 0; | |
ba87a9be JH |
363 | if (uart->timeout) |
364 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
365 | else | |
366 | del_timer(&uart->timer); | |
4af4016c KH |
367 | } |
368 | ||
369 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) | |
370 | { | |
6f251e9d | 371 | if (device_may_wakeup(&uart->pdev->dev)) |
fd455ea8 KH |
372 | omap_uart_enable_wakeup(uart); |
373 | else | |
374 | omap_uart_disable_wakeup(uart); | |
375 | ||
4af4016c KH |
376 | if (!uart->clocked) |
377 | return; | |
378 | ||
379 | omap_uart_smart_idle_enable(uart, 1); | |
380 | uart->can_sleep = 1; | |
381 | del_timer(&uart->timer); | |
382 | } | |
383 | ||
384 | static void omap_uart_idle_timer(unsigned long data) | |
385 | { | |
386 | struct omap_uart_state *uart = (struct omap_uart_state *)data; | |
387 | ||
388 | omap_uart_allow_sleep(uart); | |
389 | } | |
390 | ||
391 | void omap_uart_prepare_idle(int num) | |
392 | { | |
393 | struct omap_uart_state *uart; | |
394 | ||
395 | list_for_each_entry(uart, &uart_list, node) { | |
396 | if (num == uart->num && uart->can_sleep) { | |
397 | omap_uart_disable_clocks(uart); | |
398 | return; | |
399 | } | |
400 | } | |
401 | } | |
402 | ||
403 | void omap_uart_resume_idle(int num) | |
404 | { | |
405 | struct omap_uart_state *uart; | |
406 | ||
407 | list_for_each_entry(uart, &uart_list, node) { | |
f910043c | 408 | if (num == uart->num && uart->can_sleep) { |
4af4016c KH |
409 | omap_uart_enable_clocks(uart); |
410 | ||
411 | /* Check for IO pad wakeup */ | |
412 | if (cpu_is_omap34xx() && uart->padconf) { | |
413 | u16 p = omap_ctrl_readw(uart->padconf); | |
414 | ||
415 | if (p & OMAP3_PADCONF_WAKEUPEVENT0) | |
416 | omap_uart_block_sleep(uart); | |
6e81176d | 417 | } |
4af4016c KH |
418 | |
419 | /* Check for normal UART wakeup */ | |
420 | if (__raw_readl(uart->wk_st) & uart->wk_mask) | |
421 | omap_uart_block_sleep(uart); | |
4af4016c KH |
422 | return; |
423 | } | |
424 | } | |
425 | } | |
426 | ||
427 | void omap_uart_prepare_suspend(void) | |
428 | { | |
429 | struct omap_uart_state *uart; | |
430 | ||
431 | list_for_each_entry(uart, &uart_list, node) { | |
432 | omap_uart_allow_sleep(uart); | |
433 | } | |
434 | } | |
435 | ||
436 | int omap_uart_can_sleep(void) | |
437 | { | |
438 | struct omap_uart_state *uart; | |
439 | int can_sleep = 1; | |
440 | ||
441 | list_for_each_entry(uart, &uart_list, node) { | |
442 | if (!uart->clocked) | |
443 | continue; | |
444 | ||
445 | if (!uart->can_sleep) { | |
446 | can_sleep = 0; | |
447 | continue; | |
6e81176d | 448 | } |
4af4016c KH |
449 | |
450 | /* This UART can now safely sleep. */ | |
451 | omap_uart_allow_sleep(uart); | |
6e81176d | 452 | } |
4af4016c KH |
453 | |
454 | return can_sleep; | |
6e81176d JH |
455 | } |
456 | ||
4af4016c KH |
457 | /** |
458 | * omap_uart_interrupt() | |
459 | * | |
460 | * This handler is used only to detect that *any* UART interrupt has | |
461 | * occurred. It does _nothing_ to handle the interrupt. Rather, | |
462 | * any UART interrupt will trigger the inactivity timer so the | |
463 | * UART will not idle or sleep for its timeout period. | |
464 | * | |
465 | **/ | |
6f251e9d | 466 | /* static int first_interrupt; */ |
4af4016c KH |
467 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) |
468 | { | |
469 | struct omap_uart_state *uart = dev_id; | |
470 | ||
471 | omap_uart_block_sleep(uart); | |
472 | ||
473 | return IRQ_NONE; | |
474 | } | |
475 | ||
476 | static void omap_uart_idle_init(struct omap_uart_state *uart) | |
477 | { | |
4af4016c KH |
478 | int ret; |
479 | ||
480 | uart->can_sleep = 0; | |
fd455ea8 | 481 | uart->timeout = DEFAULT_TIMEOUT; |
4af4016c KH |
482 | setup_timer(&uart->timer, omap_uart_idle_timer, |
483 | (unsigned long) uart); | |
301fe8ee TL |
484 | if (uart->timeout) |
485 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
4af4016c KH |
486 | omap_uart_smart_idle_enable(uart, 0); |
487 | ||
488 | if (cpu_is_omap34xx()) { | |
52663aea | 489 | u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; |
4af4016c KH |
490 | u32 wk_mask = 0; |
491 | u32 padconf = 0; | |
492 | ||
c4d7e58f | 493 | /* XXX These PRM accesses do not belong here */ |
4af4016c KH |
494 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); |
495 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); | |
496 | switch (uart->num) { | |
497 | case 0: | |
498 | wk_mask = OMAP3430_ST_UART1_MASK; | |
499 | padconf = 0x182; | |
500 | break; | |
501 | case 1: | |
502 | wk_mask = OMAP3430_ST_UART2_MASK; | |
503 | padconf = 0x17a; | |
504 | break; | |
505 | case 2: | |
506 | wk_mask = OMAP3430_ST_UART3_MASK; | |
507 | padconf = 0x19e; | |
508 | break; | |
52663aea G |
509 | case 3: |
510 | wk_mask = OMAP3630_ST_UART4_MASK; | |
511 | padconf = 0x0d2; | |
512 | break; | |
4af4016c KH |
513 | } |
514 | uart->wk_mask = wk_mask; | |
515 | uart->padconf = padconf; | |
516 | } else if (cpu_is_omap24xx()) { | |
517 | u32 wk_mask = 0; | |
cb74f022 | 518 | u32 wk_en = PM_WKEN1, wk_st = PM_WKST1; |
4af4016c | 519 | |
4af4016c KH |
520 | switch (uart->num) { |
521 | case 0: | |
522 | wk_mask = OMAP24XX_ST_UART1_MASK; | |
523 | break; | |
524 | case 1: | |
525 | wk_mask = OMAP24XX_ST_UART2_MASK; | |
526 | break; | |
527 | case 2: | |
cb74f022 KH |
528 | wk_en = OMAP24XX_PM_WKEN2; |
529 | wk_st = OMAP24XX_PM_WKST2; | |
4af4016c KH |
530 | wk_mask = OMAP24XX_ST_UART3_MASK; |
531 | break; | |
532 | } | |
533 | uart->wk_mask = wk_mask; | |
cb74f022 KH |
534 | if (cpu_is_omap2430()) { |
535 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); | |
536 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); | |
537 | } else if (cpu_is_omap2420()) { | |
538 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); | |
539 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); | |
540 | } | |
4af4016c | 541 | } else { |
c54bae1f NM |
542 | uart->wk_en = NULL; |
543 | uart->wk_st = NULL; | |
4af4016c KH |
544 | uart->wk_mask = 0; |
545 | uart->padconf = 0; | |
546 | } | |
547 | ||
6f251e9d KH |
548 | uart->irqflags |= IRQF_SHARED; |
549 | ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, | |
550 | IRQF_SHARED, "serial idle", (void *)uart); | |
4af4016c KH |
551 | WARN_ON(ret); |
552 | } | |
553 | ||
2466211e TK |
554 | void omap_uart_enable_irqs(int enable) |
555 | { | |
556 | int ret; | |
557 | struct omap_uart_state *uart; | |
558 | ||
559 | list_for_each_entry(uart, &uart_list, node) { | |
3244fcd2 KH |
560 | if (enable) { |
561 | pm_runtime_put_sync(&uart->pdev->dev); | |
6f251e9d KH |
562 | ret = request_threaded_irq(uart->irq, NULL, |
563 | omap_uart_interrupt, | |
564 | IRQF_SHARED, | |
565 | "serial idle", | |
566 | (void *)uart); | |
3244fcd2 KH |
567 | } else { |
568 | pm_runtime_get_noresume(&uart->pdev->dev); | |
6f251e9d | 569 | free_irq(uart->irq, (void *)uart); |
3244fcd2 | 570 | } |
2466211e TK |
571 | } |
572 | } | |
573 | ||
fd455ea8 KH |
574 | static ssize_t sleep_timeout_show(struct device *dev, |
575 | struct device_attribute *attr, | |
ba87a9be JH |
576 | char *buf) |
577 | { | |
6f251e9d KH |
578 | struct platform_device *pdev = to_platform_device(dev); |
579 | struct omap_device *odev = to_omap_device(pdev); | |
580 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; | |
fd455ea8 KH |
581 | |
582 | return sprintf(buf, "%u\n", uart->timeout / HZ); | |
ba87a9be JH |
583 | } |
584 | ||
fd455ea8 KH |
585 | static ssize_t sleep_timeout_store(struct device *dev, |
586 | struct device_attribute *attr, | |
ba87a9be JH |
587 | const char *buf, size_t n) |
588 | { | |
6f251e9d KH |
589 | struct platform_device *pdev = to_platform_device(dev); |
590 | struct omap_device *odev = to_omap_device(pdev); | |
591 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; | |
ba87a9be JH |
592 | unsigned int value; |
593 | ||
594 | if (sscanf(buf, "%u", &value) != 1) { | |
10c805eb | 595 | dev_err(dev, "sleep_timeout_store: Invalid value\n"); |
ba87a9be JH |
596 | return -EINVAL; |
597 | } | |
fd455ea8 KH |
598 | |
599 | uart->timeout = value * HZ; | |
600 | if (uart->timeout) | |
601 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
602 | else | |
603 | /* A zero value means disable timeout feature */ | |
604 | omap_uart_block_sleep(uart); | |
605 | ||
ba87a9be JH |
606 | return n; |
607 | } | |
608 | ||
bfe6977a NM |
609 | static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, |
610 | sleep_timeout_store); | |
fd455ea8 | 611 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) |
4af4016c KH |
612 | #else |
613 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | |
a1b04cc1 SS |
614 | static void omap_uart_block_sleep(struct omap_uart_state *uart) |
615 | { | |
616 | /* Needed to enable UART clocks when built without CONFIG_PM */ | |
617 | omap_uart_enable_clocks(uart); | |
618 | } | |
fd455ea8 | 619 | #define DEV_CREATE_FILE(dev, attr) |
4af4016c KH |
620 | #endif /* CONFIG_PM */ |
621 | ||
6f251e9d | 622 | #ifndef CONFIG_SERIAL_OMAP |
ce13d471 | 623 | /* |
624 | * Override the default 8250 read handler: mem_serial_in() | |
625 | * Empty RX fifo read causes an abort on omap3630 and omap4 | |
626 | * This function makes sure that an empty rx fifo is not read on these silicons | |
627 | * (OMAP1/2/3430 are not affected) | |
628 | */ | |
629 | static unsigned int serial_in_override(struct uart_port *up, int offset) | |
630 | { | |
631 | if (UART_RX == offset) { | |
632 | unsigned int lsr; | |
9230372a | 633 | lsr = __serial_read_reg(up, UART_LSR); |
ce13d471 | 634 | if (!(lsr & UART_LSR_DR)) |
635 | return -EPERM; | |
636 | } | |
9230372a AS |
637 | |
638 | return __serial_read_reg(up, offset); | |
ce13d471 | 639 | } |
640 | ||
e03d37d8 SS |
641 | static void serial_out_override(struct uart_port *up, int offset, int value) |
642 | { | |
643 | unsigned int status, tmout = 10000; | |
644 | ||
645 | status = __serial_read_reg(up, UART_LSR); | |
646 | while (!(status & UART_LSR_THRE)) { | |
647 | /* Wait up to 10ms for the character(s) to be sent. */ | |
648 | if (--tmout == 0) | |
649 | break; | |
650 | udelay(1); | |
651 | status = __serial_read_reg(up, UART_LSR); | |
652 | } | |
653 | __serial_write_reg(up, offset, value); | |
654 | } | |
6f251e9d KH |
655 | #endif |
656 | ||
b3c6df3a | 657 | void __init omap_serial_early_init(void) |
1dbae815 | 658 | { |
6f251e9d | 659 | int i = 0; |
1dbae815 | 660 | |
6f251e9d KH |
661 | do { |
662 | char oh_name[MAX_UART_HWMOD_NAME_LEN]; | |
663 | struct omap_hwmod *oh; | |
664 | struct omap_uart_state *uart; | |
21b90340 | 665 | |
6f251e9d KH |
666 | snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, |
667 | "uart%d", i + 1); | |
668 | oh = omap_hwmod_lookup(oh_name); | |
669 | if (!oh) | |
670 | break; | |
671 | ||
672 | uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); | |
673 | if (WARN_ON(!uart)) | |
674 | return; | |
1dbae815 | 675 | |
6f251e9d KH |
676 | uart->oh = oh; |
677 | uart->num = i++; | |
678 | list_add_tail(&uart->node, &uart_list); | |
679 | num_uarts++; | |
1dbae815 | 680 | |
84f90c9c | 681 | /* |
6f251e9d KH |
682 | * NOTE: omap_hwmod_init() has not yet been called, |
683 | * so no hwmod functions will work yet. | |
84f90c9c | 684 | */ |
6e81176d | 685 | |
6f251e9d KH |
686 | /* |
687 | * During UART early init, device need to be probed | |
688 | * to determine SoC specific init before omap_device | |
689 | * is ready. Therefore, don't allow idle here | |
690 | */ | |
691 | uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; | |
692 | } while (1); | |
b3c6df3a PW |
693 | } |
694 | ||
f62349ee MW |
695 | /** |
696 | * omap_serial_init_port() - initialize single serial port | |
697 | * @port: serial port number (0-3) | |
698 | * | |
699 | * This function initialies serial driver for given @port only. | |
700 | * Platforms can call this function instead of omap_serial_init() | |
701 | * if they don't plan to use all available UARTs as serial ports. | |
702 | * | |
703 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), | |
704 | * use only one of the two. | |
705 | */ | |
706 | void __init omap_serial_init_port(int port) | |
b3c6df3a | 707 | { |
f62349ee | 708 | struct omap_uart_state *uart; |
6f251e9d KH |
709 | struct omap_hwmod *oh; |
710 | struct omap_device *od; | |
711 | void *pdata = NULL; | |
712 | u32 pdata_size = 0; | |
713 | char *name; | |
714 | #ifndef CONFIG_SERIAL_OMAP | |
715 | struct plat_serial8250_port ports[2] = { | |
716 | {}, | |
717 | {.flags = 0}, | |
718 | }; | |
719 | struct plat_serial8250_port *p = &ports[0]; | |
720 | #else | |
721 | struct omap_uart_port_info omap_up; | |
722 | #endif | |
970a724d | 723 | |
6f251e9d KH |
724 | if (WARN_ON(port < 0)) |
725 | return; | |
726 | if (WARN_ON(port >= num_uarts)) | |
e88d556d | 727 | return; |
f62349ee | 728 | |
6f251e9d KH |
729 | list_for_each_entry(uart, &uart_list, node) |
730 | if (port == uart->num) | |
731 | break; | |
f2eeeae0 | 732 | |
6f251e9d KH |
733 | oh = uart->oh; |
734 | uart->dma_enabled = 0; | |
735 | #ifndef CONFIG_SERIAL_OMAP | |
736 | name = "serial8250"; | |
f62349ee | 737 | |
6f251e9d KH |
738 | /* |
739 | * !! 8250 driver does not use standard IORESOURCE* It | |
740 | * has it's own custom pdata that can be taken from | |
741 | * the hwmod resource data. But, this needs to be | |
742 | * done after the build. | |
743 | * | |
744 | * ?? does it have to be done before the register ?? | |
745 | * YES, because platform_device_data_add() copies | |
746 | * pdata, it does not use a pointer. | |
747 | */ | |
748 | p->flags = UPF_BOOT_AUTOCONF; | |
749 | p->iotype = UPIO_MEM; | |
750 | p->regshift = 2; | |
751 | p->uartclk = OMAP24XX_BASE_BAUD * 16; | |
752 | p->irq = oh->mpu_irqs[0].irq; | |
753 | p->mapbase = oh->slaves[0]->addr->pa_start; | |
754 | p->membase = omap_hwmod_get_mpu_rt_va(oh); | |
755 | p->irqflags = IRQF_SHARED; | |
756 | p->private_data = uart; | |
f62349ee | 757 | |
30e53bcc | 758 | /* |
759 | * omap44xx: Never read empty UART fifo | |
760 | * omap3xxx: Never read empty UART fifo on UARTs | |
761 | * with IP rev >=0x52 | |
762 | */ | |
6f251e9d KH |
763 | uart->regshift = p->regshift; |
764 | uart->membase = p->membase; | |
5a927b36 NM |
765 | if (cpu_is_omap44xx()) |
766 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; | |
6f251e9d | 767 | else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) |
5a927b36 NM |
768 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) |
769 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; | |
770 | ||
771 | if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { | |
6f251e9d KH |
772 | p->serial_in = serial_in_override; |
773 | p->serial_out = serial_out_override; | |
774 | } | |
775 | ||
776 | pdata = &ports[0]; | |
777 | pdata_size = 2 * sizeof(struct plat_serial8250_port); | |
778 | #else | |
779 | ||
780 | name = DRIVER_NAME; | |
781 | ||
782 | omap_up.dma_enabled = uart->dma_enabled; | |
783 | omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; | |
784 | omap_up.mapbase = oh->slaves[0]->addr->pa_start; | |
785 | omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); | |
786 | omap_up.irqflags = IRQF_SHARED; | |
787 | omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | |
788 | ||
789 | pdata = &omap_up; | |
790 | pdata_size = sizeof(struct omap_uart_port_info); | |
791 | #endif | |
792 | ||
793 | if (WARN_ON(!oh)) | |
794 | return; | |
795 | ||
796 | od = omap_device_build(name, uart->num, oh, pdata, pdata_size, | |
797 | omap_uart_latency, | |
798 | ARRAY_SIZE(omap_uart_latency), false); | |
799 | WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", | |
800 | name, oh->name); | |
801 | ||
802 | uart->irq = oh->mpu_irqs[0].irq; | |
803 | uart->regshift = 2; | |
804 | uart->mapbase = oh->slaves[0]->addr->pa_start; | |
805 | uart->membase = omap_hwmod_get_mpu_rt_va(oh); | |
806 | uart->pdev = &od->pdev; | |
807 | ||
808 | oh->dev_attr = uart; | |
809 | ||
0d8e2d0d PW |
810 | acquire_console_sem(); /* in case the earlycon is on the UART */ |
811 | ||
6f251e9d KH |
812 | /* |
813 | * Because of early UART probing, UART did not get idled | |
814 | * on init. Now that omap_device is ready, ensure full idle | |
815 | * before doing omap_device_enable(). | |
816 | */ | |
817 | omap_hwmod_idle(uart->oh); | |
818 | ||
819 | omap_device_enable(uart->pdev); | |
820 | omap_uart_idle_init(uart); | |
821 | omap_uart_reset(uart); | |
822 | omap_hwmod_enable_wakeup(uart->oh); | |
823 | omap_device_idle(uart->pdev); | |
824 | ||
825 | /* | |
826 | * Need to block sleep long enough for interrupt driven | |
827 | * driver to start. Console driver is in polling mode | |
828 | * so device needs to be kept enabled while polling driver | |
829 | * is in use. | |
830 | */ | |
831 | if (uart->timeout) | |
832 | uart->timeout = (30 * HZ); | |
833 | omap_uart_block_sleep(uart); | |
834 | uart->timeout = DEFAULT_TIMEOUT; | |
835 | ||
0d8e2d0d PW |
836 | release_console_sem(); |
837 | ||
6f251e9d KH |
838 | if ((cpu_is_omap34xx() && uart->padconf) || |
839 | (uart->wk_en && uart->wk_mask)) { | |
840 | device_init_wakeup(&od->pdev.dev, true); | |
841 | DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout); | |
e03d37d8 | 842 | } |
00034509 D |
843 | |
844 | /* Enable the MDR1 errata for OMAP3 */ | |
845 | if (cpu_is_omap34xx()) | |
846 | uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; | |
f62349ee MW |
847 | } |
848 | ||
849 | /** | |
850 | * omap_serial_init() - intialize all supported serial ports | |
851 | * | |
852 | * Initializes all available UARTs as serial ports. Platforms | |
853 | * can call this function when they want to have default behaviour | |
854 | * for serial ports (e.g initialize them all as serial ports). | |
855 | */ | |
856 | void __init omap_serial_init(void) | |
857 | { | |
6f251e9d | 858 | struct omap_uart_state *uart; |
f62349ee | 859 | |
6f251e9d KH |
860 | list_for_each_entry(uart, &uart_list, node) |
861 | omap_serial_init_port(uart->num); | |
1dbae815 | 862 | } |