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8bd22949 KH |
1 | /* |
2 | * linux/arch/arm/mach-omap2/sleep.S | |
3 | * | |
4 | * (C) Copyright 2007 | |
5 | * Texas Instruments | |
6 | * Karthik Dasu <karthik-dp@ti.com> | |
7 | * | |
8 | * (C) Copyright 2004 | |
9 | * Texas Instruments, <www.ti.com> | |
10 | * Richard Woodruff <r-woodruff2@ti.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | #include <linux/linkage.h> | |
28 | #include <asm/assembler.h> | |
29 | #include <mach/io.h> | |
8bd22949 | 30 | |
89139dce | 31 | #include "cm.h" |
8bd22949 KH |
32 | #include "prm.h" |
33 | #include "sdrc.h" | |
4814ced5 | 34 | #include "control.h" |
8bd22949 | 35 | |
a89b6f00 RN |
36 | #define SDRC_SCRATCHPAD_SEM_V 0xfa00291c |
37 | ||
8bd22949 KH |
38 | #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ |
39 | OMAP3430_PM_PREPWSTST) | |
0795a75a | 40 | #define PM_PREPWSTST_CORE_P 0x48306AE8 |
8bd22949 KH |
41 | #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ |
42 | OMAP3430_PM_PREPWSTST) | |
37903009 | 43 | #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL |
89139dce | 44 | #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) |
9d93b8a2 | 45 | #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) |
27d59a4a TK |
46 | #define SRAM_BASE_P 0x40200000 |
47 | #define CONTROL_STAT 0x480022F0 | |
458e999e NM |
48 | #define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\ |
49 | + OMAP36XX_CONTROL_MEM_RTA_CTRL) | |
8bd22949 KH |
50 | #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is |
51 | * available */ | |
61255ab9 RN |
52 | #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ |
53 | + SCRATCHPAD_MEM_OFFS) | |
8bd22949 | 54 | #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) |
0795a75a TK |
55 | #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) |
56 | #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) | |
57 | #define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) | |
58 | #define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) | |
59 | #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) | |
60 | #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) | |
61 | #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) | |
89139dce PDS |
62 | #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
63 | #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) | |
8bd22949 | 64 | |
a89b6f00 | 65 | .text |
46cd09a7 | 66 | /* Function to acquire the semaphore in scratchpad */ |
a89b6f00 RN |
67 | ENTRY(lock_scratchpad_sem) |
68 | stmfd sp!, {lr} @ save registers on stack | |
69 | wait_sem: | |
70 | mov r0,#1 | |
71 | ldr r1, sdrc_scratchpad_sem | |
72 | wait_loop: | |
73 | ldr r2, [r1] @ load the lock value | |
74 | cmp r2, r0 @ is the lock free ? | |
75 | beq wait_loop @ not free... | |
76 | swp r2, r0, [r1] @ semaphore free so lock it and proceed | |
77 | cmp r2, r0 @ did we succeed ? | |
78 | beq wait_sem @ no - try again | |
79 | ldmfd sp!, {pc} @ restore regs and return | |
80 | sdrc_scratchpad_sem: | |
81 | .word SDRC_SCRATCHPAD_SEM_V | |
82 | ENTRY(lock_scratchpad_sem_sz) | |
83 | .word . - lock_scratchpad_sem | |
84 | ||
85 | .text | |
86 | /* Function to release the scratchpad semaphore */ | |
87 | ENTRY(unlock_scratchpad_sem) | |
88 | stmfd sp!, {lr} @ save registers on stack | |
89 | ldr r3, sdrc_scratchpad_sem | |
90 | mov r2,#0 | |
91 | str r2,[r3] | |
92 | ldmfd sp!, {pc} @ restore regs and return | |
93 | ENTRY(unlock_scratchpad_sem_sz) | |
94 | .word . - unlock_scratchpad_sem | |
95 | ||
8bd22949 KH |
96 | .text |
97 | /* Function call to get the restore pointer for resume from OFF */ | |
98 | ENTRY(get_restore_pointer) | |
99 | stmfd sp!, {lr} @ save registers on stack | |
100 | adr r0, restore | |
101 | ldmfd sp!, {pc} @ restore regs and return | |
102 | ENTRY(get_restore_pointer_sz) | |
0795a75a | 103 | .word . - get_restore_pointer |
458e999e NM |
104 | .text |
105 | /* Function call to get the restore pointer for 3630 resume from OFF */ | |
106 | ENTRY(get_omap3630_restore_pointer) | |
107 | stmfd sp!, {lr} @ save registers on stack | |
108 | adr r0, restore_3630 | |
109 | ldmfd sp!, {pc} @ restore regs and return | |
110 | ENTRY(get_omap3630_restore_pointer_sz) | |
111 | .word . - get_omap3630_restore_pointer | |
0795a75a TK |
112 | |
113 | .text | |
114 | /* Function call to get the restore pointer for for ES3 to resume from OFF */ | |
115 | ENTRY(get_es3_restore_pointer) | |
116 | stmfd sp!, {lr} @ save registers on stack | |
117 | adr r0, restore_es3 | |
118 | ldmfd sp!, {pc} @ restore regs and return | |
119 | ENTRY(get_es3_restore_pointer_sz) | |
120 | .word . - get_es3_restore_pointer | |
121 | ||
122 | ENTRY(es3_sdrc_fix) | |
123 | ldr r4, sdrc_syscfg @ get config addr | |
124 | ldr r5, [r4] @ get value | |
125 | tst r5, #0x100 @ is part access blocked | |
126 | it eq | |
127 | biceq r5, r5, #0x100 @ clear bit if set | |
128 | str r5, [r4] @ write back change | |
129 | ldr r4, sdrc_mr_0 @ get config addr | |
130 | ldr r5, [r4] @ get value | |
131 | str r5, [r4] @ write back change | |
132 | ldr r4, sdrc_emr2_0 @ get config addr | |
133 | ldr r5, [r4] @ get value | |
134 | str r5, [r4] @ write back change | |
135 | ldr r4, sdrc_manual_0 @ get config addr | |
136 | mov r5, #0x2 @ autorefresh command | |
137 | str r5, [r4] @ kick off refreshes | |
138 | ldr r4, sdrc_mr_1 @ get config addr | |
139 | ldr r5, [r4] @ get value | |
140 | str r5, [r4] @ write back change | |
141 | ldr r4, sdrc_emr2_1 @ get config addr | |
142 | ldr r5, [r4] @ get value | |
143 | str r5, [r4] @ write back change | |
144 | ldr r4, sdrc_manual_1 @ get config addr | |
145 | mov r5, #0x2 @ autorefresh command | |
146 | str r5, [r4] @ kick off refreshes | |
147 | bx lr | |
148 | sdrc_syscfg: | |
149 | .word SDRC_SYSCONFIG_P | |
150 | sdrc_mr_0: | |
151 | .word SDRC_MR_0_P | |
152 | sdrc_emr2_0: | |
153 | .word SDRC_EMR2_0_P | |
154 | sdrc_manual_0: | |
155 | .word SDRC_MANUAL_0_P | |
156 | sdrc_mr_1: | |
157 | .word SDRC_MR_1_P | |
158 | sdrc_emr2_1: | |
159 | .word SDRC_EMR2_1_P | |
160 | sdrc_manual_1: | |
161 | .word SDRC_MANUAL_1_P | |
162 | ENTRY(es3_sdrc_fix_sz) | |
163 | .word . - es3_sdrc_fix | |
27d59a4a TK |
164 | |
165 | /* Function to call rom code to save secure ram context */ | |
166 | ENTRY(save_secure_ram_context) | |
167 | stmfd sp!, {r1-r12, lr} @ save registers on stack | |
168 | save_secure_ram_debug: | |
169 | /* b save_secure_ram_debug */ @ enable to debug save code | |
170 | adr r3, api_params @ r3 points to parameters | |
171 | str r0, [r3,#0x4] @ r0 has sdram address | |
172 | ldr r12, high_mask | |
173 | and r3, r3, r12 | |
174 | ldr r12, sram_phy_addr_mask | |
175 | orr r3, r3, r12 | |
176 | mov r0, #25 @ set service ID for PPA | |
177 | mov r12, r0 @ copy secure service ID in r12 | |
178 | mov r1, #0 @ set task id for ROM code in r1 | |
ba50ea7e | 179 | mov r2, #4 @ set some flags in r2, r6 |
27d59a4a TK |
180 | mov r6, #0xff |
181 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | |
182 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | |
183 | .word 0xE1600071 @ call SMI monitor (smi #1) | |
184 | nop | |
185 | nop | |
186 | nop | |
187 | nop | |
188 | ldmfd sp!, {r1-r12, pc} | |
189 | sram_phy_addr_mask: | |
190 | .word SRAM_BASE_P | |
191 | high_mask: | |
192 | .word 0xffff | |
193 | api_params: | |
194 | .word 0x4, 0x0, 0x0, 0x1, 0x1 | |
195 | ENTRY(save_secure_ram_context_sz) | |
196 | .word . - save_secure_ram_context | |
197 | ||
8bd22949 KH |
198 | /* |
199 | * Forces OMAP into idle state | |
200 | * | |
201 | * omap34xx_suspend() - This bit of code just executes the WFI | |
202 | * for normal idles. | |
203 | * | |
204 | * Note: This code get's copied to internal SRAM at boot. When the OMAP | |
205 | * wakes up it continues execution at the point it went to sleep. | |
206 | */ | |
207 | ENTRY(omap34xx_cpu_suspend) | |
208 | stmfd sp!, {r0-r12, lr} @ save registers on stack | |
209 | loop: | |
210 | /*b loop*/ @Enable to debug by stepping through code | |
211 | /* r0 contains restore pointer in sdram */ | |
212 | /* r1 contains information about saving context */ | |
213 | ldr r4, sdrc_power @ read the SDRC_POWER register | |
214 | ldr r5, [r4] @ read the contents of SDRC_POWER | |
215 | orr r5, r5, #0x40 @ enable self refresh on idle req | |
216 | str r5, [r4] @ write back to SDRC_POWER register | |
217 | ||
218 | cmp r1, #0x0 | |
219 | /* If context save is required, do that and execute wfi */ | |
220 | bne save_context_wfi | |
221 | /* Data memory barrier and Data sync barrier */ | |
222 | mov r1, #0 | |
223 | mcr p15, 0, r1, c7, c10, 4 | |
224 | mcr p15, 0, r1, c7, c10, 5 | |
225 | ||
226 | wfi @ wait for interrupt | |
227 | ||
228 | nop | |
229 | nop | |
230 | nop | |
231 | nop | |
232 | nop | |
233 | nop | |
234 | nop | |
235 | nop | |
236 | nop | |
237 | nop | |
89139dce | 238 | bl wait_sdrc_ok |
8bd22949 KH |
239 | |
240 | ldmfd sp!, {r0-r12, pc} @ restore regs and return | |
0795a75a TK |
241 | restore_es3: |
242 | /*b restore_es3*/ @ Enable to debug restore code | |
243 | ldr r5, pm_prepwstst_core_p | |
244 | ldr r4, [r5] | |
245 | and r4, r4, #0x3 | |
246 | cmp r4, #0x0 @ Check if previous power state of CORE is OFF | |
247 | bne restore | |
248 | adr r0, es3_sdrc_fix | |
249 | ldr r1, sram_base | |
250 | ldr r2, es3_sdrc_fix_sz | |
251 | mov r2, r2, ror #2 | |
252 | copy_to_sram: | |
253 | ldmia r0!, {r3} @ val = *src | |
254 | stmia r1!, {r3} @ *dst = val | |
255 | subs r2, r2, #0x1 @ num_words-- | |
256 | bne copy_to_sram | |
257 | ldr r1, sram_base | |
258 | blx r1 | |
458e999e NM |
259 | b restore |
260 | ||
261 | restore_3630: | |
262 | /*b restore_es3630*/ @ Enable to debug restore code | |
263 | ldr r1, pm_prepwstst_core_p | |
264 | ldr r2, [r1] | |
265 | and r2, r2, #0x3 | |
266 | cmp r2, #0x0 @ Check if previous power state of CORE is OFF | |
267 | bne restore | |
268 | /* Disable RTA before giving control */ | |
269 | ldr r1, control_mem_rta | |
270 | mov r2, #OMAP36XX_RTA_DISABLE | |
271 | str r2, [r1] | |
272 | /* Fall thru for the remaining logic */ | |
8bd22949 | 273 | restore: |
61255ab9 | 274 | /* b restore*/ @ Enable to debug restore code |
8bd22949 KH |
275 | /* Check what was the reason for mpu reset and store the reason in r9*/ |
276 | /* 1 - Only L1 and logic lost */ | |
277 | /* 2 - Only L2 lost - In this case, we wont be here */ | |
278 | /* 3 - Both L1 and L2 lost */ | |
279 | ldr r1, pm_pwstctrl_mpu | |
280 | ldr r2, [r1] | |
281 | and r2, r2, #0x3 | |
282 | cmp r2, #0x0 @ Check if target power state was OFF or RET | |
283 | moveq r9, #0x3 @ MPU OFF => L1 and L2 lost | |
284 | movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation | |
285 | bne logic_l1_restore | |
27d59a4a TK |
286 | ldr r0, control_stat |
287 | ldr r1, [r0] | |
288 | and r1, #0x700 | |
289 | cmp r1, #0x300 | |
290 | beq l2_inv_gp | |
291 | mov r0, #40 @ set service ID for PPA | |
292 | mov r12, r0 @ copy secure Service ID in r12 | |
293 | mov r1, #0 @ set task id for ROM code in r1 | |
294 | mov r2, #4 @ set some flags in r2, r6 | |
295 | mov r6, #0xff | |
296 | adr r3, l2_inv_api_params @ r3 points to dummy parameters | |
297 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | |
298 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | |
299 | .word 0xE1600071 @ call SMI monitor (smi #1) | |
300 | /* Write to Aux control register to set some bits */ | |
301 | mov r0, #42 @ set service ID for PPA | |
302 | mov r12, r0 @ copy secure Service ID in r12 | |
303 | mov r1, #0 @ set task id for ROM code in r1 | |
304 | mov r2, #4 @ set some flags in r2, r6 | |
305 | mov r6, #0xff | |
a087cad9 TK |
306 | ldr r4, scratchpad_base |
307 | ldr r3, [r4, #0xBC] @ r3 points to parameters | |
27d59a4a TK |
308 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
309 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | |
310 | .word 0xE1600071 @ call SMI monitor (smi #1) | |
311 | ||
79dcfdd4 TK |
312 | #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE |
313 | /* Restore L2 aux control register */ | |
314 | @ set service ID for PPA | |
315 | mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID | |
316 | mov r12, r0 @ copy service ID in r12 | |
317 | mov r1, #0 @ set task ID for ROM code in r1 | |
318 | mov r2, #4 @ set some flags in r2, r6 | |
319 | mov r6, #0xff | |
320 | ldr r4, scratchpad_base | |
321 | ldr r3, [r4, #0xBC] | |
322 | adds r3, r3, #8 @ r3 points to parameters | |
323 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | |
324 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | |
325 | .word 0xE1600071 @ call SMI monitor (smi #1) | |
326 | #endif | |
27d59a4a TK |
327 | b logic_l1_restore |
328 | l2_inv_api_params: | |
329 | .word 0x1, 0x00 | |
27d59a4a | 330 | l2_inv_gp: |
8bd22949 KH |
331 | /* Execute smi to invalidate L2 cache */ |
332 | mov r12, #0x1 @ set up to invalide L2 | |
27d59a4a TK |
333 | smi: .word 0xE1600070 @ Call SMI monitor (smieq) |
334 | /* Write to Aux control register to set some bits */ | |
a087cad9 TK |
335 | ldr r4, scratchpad_base |
336 | ldr r3, [r4,#0xBC] | |
337 | ldr r0, [r3,#4] | |
27d59a4a TK |
338 | mov r12, #0x3 |
339 | .word 0xE1600070 @ Call SMI monitor (smieq) | |
79dcfdd4 TK |
340 | ldr r4, scratchpad_base |
341 | ldr r3, [r4,#0xBC] | |
342 | ldr r0, [r3,#12] | |
343 | mov r12, #0x2 | |
344 | .word 0xE1600070 @ Call SMI monitor (smieq) | |
8bd22949 KH |
345 | logic_l1_restore: |
346 | mov r1, #0 | |
347 | /* Invalidate all instruction caches to PoU | |
348 | * and flush branch target cache */ | |
349 | mcr p15, 0, r1, c7, c5, 0 | |
350 | ||
351 | ldr r4, scratchpad_base | |
352 | ldr r3, [r4,#0xBC] | |
79dcfdd4 | 353 | adds r3, r3, #16 |
8bd22949 KH |
354 | ldmia r3!, {r4-r6} |
355 | mov sp, r4 | |
356 | msr spsr_cxsf, r5 | |
357 | mov lr, r6 | |
358 | ||
359 | ldmia r3!, {r4-r9} | |
360 | /* Coprocessor access Control Register */ | |
361 | mcr p15, 0, r4, c1, c0, 2 | |
362 | ||
363 | /* TTBR0 */ | |
364 | MCR p15, 0, r5, c2, c0, 0 | |
365 | /* TTBR1 */ | |
366 | MCR p15, 0, r6, c2, c0, 1 | |
367 | /* Translation table base control register */ | |
368 | MCR p15, 0, r7, c2, c0, 2 | |
369 | /*domain access Control Register */ | |
370 | MCR p15, 0, r8, c3, c0, 0 | |
371 | /* data fault status Register */ | |
372 | MCR p15, 0, r9, c5, c0, 0 | |
373 | ||
374 | ldmia r3!,{r4-r8} | |
375 | /* instruction fault status Register */ | |
376 | MCR p15, 0, r4, c5, c0, 1 | |
377 | /*Data Auxiliary Fault Status Register */ | |
378 | MCR p15, 0, r5, c5, c1, 0 | |
379 | /*Instruction Auxiliary Fault Status Register*/ | |
380 | MCR p15, 0, r6, c5, c1, 1 | |
381 | /*Data Fault Address Register */ | |
382 | MCR p15, 0, r7, c6, c0, 0 | |
383 | /*Instruction Fault Address Register*/ | |
384 | MCR p15, 0, r8, c6, c0, 2 | |
385 | ldmia r3!,{r4-r7} | |
386 | ||
387 | /* user r/w thread and process ID */ | |
388 | MCR p15, 0, r4, c13, c0, 2 | |
389 | /* user ro thread and process ID */ | |
390 | MCR p15, 0, r5, c13, c0, 3 | |
391 | /*Privileged only thread and process ID */ | |
392 | MCR p15, 0, r6, c13, c0, 4 | |
393 | /* cache size selection */ | |
394 | MCR p15, 2, r7, c0, c0, 0 | |
395 | ldmia r3!,{r4-r8} | |
396 | /* Data TLB lockdown registers */ | |
397 | MCR p15, 0, r4, c10, c0, 0 | |
398 | /* Instruction TLB lockdown registers */ | |
399 | MCR p15, 0, r5, c10, c0, 1 | |
400 | /* Secure or Nonsecure Vector Base Address */ | |
401 | MCR p15, 0, r6, c12, c0, 0 | |
402 | /* FCSE PID */ | |
403 | MCR p15, 0, r7, c13, c0, 0 | |
404 | /* Context PID */ | |
405 | MCR p15, 0, r8, c13, c0, 1 | |
406 | ||
407 | ldmia r3!,{r4-r5} | |
408 | /* primary memory remap register */ | |
409 | MCR p15, 0, r4, c10, c2, 0 | |
410 | /*normal memory remap register */ | |
411 | MCR p15, 0, r5, c10, c2, 1 | |
412 | ||
413 | /* Restore cpsr */ | |
414 | ldmia r3!,{r4} /*load CPSR from SDRAM*/ | |
415 | msr cpsr, r4 /*store cpsr */ | |
416 | ||
417 | /* Enabling MMU here */ | |
418 | mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ | |
419 | /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ | |
420 | and r7, #0x7 | |
421 | cmp r7, #0x0 | |
422 | beq usettbr0 | |
423 | ttbr_error: | |
424 | /* More work needs to be done to support N[0:2] value other than 0 | |
425 | * So looping here so that the error can be detected | |
426 | */ | |
427 | b ttbr_error | |
428 | usettbr0: | |
429 | mrc p15, 0, r2, c2, c0, 0 | |
430 | ldr r5, ttbrbit_mask | |
431 | and r2, r5 | |
432 | mov r4, pc | |
433 | ldr r5, table_index_mask | |
434 | and r4, r5 /* r4 = 31 to 20 bits of pc */ | |
435 | /* Extract the value to be written to table entry */ | |
436 | ldr r1, table_entry | |
437 | add r1, r1, r4 /* r1 has value to be written to table entry*/ | |
438 | /* Getting the address of table entry to modify */ | |
439 | lsr r4, #18 | |
440 | add r2, r4 /* r2 has the location which needs to be modified */ | |
441 | /* Storing previous entry of location being modified */ | |
442 | ldr r5, scratchpad_base | |
443 | ldr r4, [r2] | |
444 | str r4, [r5, #0xC0] | |
445 | /* Modify the table entry */ | |
446 | str r1, [r2] | |
447 | /* Storing address of entry being modified | |
448 | * - will be restored after enabling MMU */ | |
449 | ldr r5, scratchpad_base | |
450 | str r2, [r5, #0xC4] | |
451 | ||
452 | mov r0, #0 | |
453 | mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer | |
454 | mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array | |
455 | mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB | |
456 | mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB | |
457 | /* Restore control register but dont enable caches here*/ | |
458 | /* Caches will be enabled after restoring MMU table entry */ | |
459 | ldmia r3!, {r4} | |
460 | /* Store previous value of control register in scratchpad */ | |
461 | str r4, [r5, #0xC8] | |
462 | ldr r2, cache_pred_disable_mask | |
463 | and r4, r2 | |
464 | mcr p15, 0, r4, c1, c0, 0 | |
465 | ||
466 | ldmfd sp!, {r0-r12, pc} @ restore regs and return | |
467 | save_context_wfi: | |
468 | /*b save_context_wfi*/ @ enable to debug save code | |
469 | mov r8, r0 /* Store SDRAM address in r8 */ | |
a087cad9 TK |
470 | mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register |
471 | mov r4, #0x1 @ Number of parameters for restore call | |
79dcfdd4 TK |
472 | stmia r8!, {r4-r5} @ Push parameters for restore call |
473 | mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register | |
474 | stmia r8!, {r4-r5} @ Push parameters for restore call | |
8bd22949 KH |
475 | /* Check what that target sleep state is:stored in r1*/ |
476 | /* 1 - Only L1 and logic lost */ | |
477 | /* 2 - Only L2 lost */ | |
478 | /* 3 - Both L1 and L2 lost */ | |
479 | cmp r1, #0x2 /* Only L2 lost */ | |
480 | beq clean_l2 | |
481 | cmp r1, #0x1 /* L2 retained */ | |
482 | /* r9 stores whether to clean L2 or not*/ | |
483 | moveq r9, #0x0 /* Dont Clean L2 */ | |
484 | movne r9, #0x1 /* Clean L2 */ | |
485 | l1_logic_lost: | |
486 | /* Store sp and spsr to SDRAM */ | |
487 | mov r4, sp | |
488 | mrs r5, spsr | |
489 | mov r6, lr | |
490 | stmia r8!, {r4-r6} | |
491 | /* Save all ARM registers */ | |
492 | /* Coprocessor access control register */ | |
493 | mrc p15, 0, r6, c1, c0, 2 | |
494 | stmia r8!, {r6} | |
495 | /* TTBR0, TTBR1 and Translation table base control */ | |
496 | mrc p15, 0, r4, c2, c0, 0 | |
497 | mrc p15, 0, r5, c2, c0, 1 | |
498 | mrc p15, 0, r6, c2, c0, 2 | |
499 | stmia r8!, {r4-r6} | |
500 | /* Domain access control register, data fault status register, | |
501 | and instruction fault status register */ | |
502 | mrc p15, 0, r4, c3, c0, 0 | |
503 | mrc p15, 0, r5, c5, c0, 0 | |
504 | mrc p15, 0, r6, c5, c0, 1 | |
505 | stmia r8!, {r4-r6} | |
506 | /* Data aux fault status register, instruction aux fault status, | |
507 | datat fault address register and instruction fault address register*/ | |
508 | mrc p15, 0, r4, c5, c1, 0 | |
509 | mrc p15, 0, r5, c5, c1, 1 | |
510 | mrc p15, 0, r6, c6, c0, 0 | |
511 | mrc p15, 0, r7, c6, c0, 2 | |
512 | stmia r8!, {r4-r7} | |
513 | /* user r/w thread and process ID, user r/o thread and process ID, | |
514 | priv only thread and process ID, cache size selection */ | |
515 | mrc p15, 0, r4, c13, c0, 2 | |
516 | mrc p15, 0, r5, c13, c0, 3 | |
517 | mrc p15, 0, r6, c13, c0, 4 | |
518 | mrc p15, 2, r7, c0, c0, 0 | |
519 | stmia r8!, {r4-r7} | |
520 | /* Data TLB lockdown, instruction TLB lockdown registers */ | |
521 | mrc p15, 0, r5, c10, c0, 0 | |
522 | mrc p15, 0, r6, c10, c0, 1 | |
523 | stmia r8!, {r5-r6} | |
524 | /* Secure or non secure vector base address, FCSE PID, Context PID*/ | |
525 | mrc p15, 0, r4, c12, c0, 0 | |
526 | mrc p15, 0, r5, c13, c0, 0 | |
527 | mrc p15, 0, r6, c13, c0, 1 | |
528 | stmia r8!, {r4-r6} | |
529 | /* Primary remap, normal remap registers */ | |
530 | mrc p15, 0, r4, c10, c2, 0 | |
531 | mrc p15, 0, r5, c10, c2, 1 | |
532 | stmia r8!,{r4-r5} | |
533 | ||
534 | /* Store current cpsr*/ | |
535 | mrs r2, cpsr | |
536 | stmia r8!, {r2} | |
537 | ||
538 | mrc p15, 0, r4, c1, c0, 0 | |
539 | /* save control register */ | |
540 | stmia r8!, {r4} | |
541 | clean_caches: | |
542 | /* Clean Data or unified cache to POU*/ | |
543 | /* How to invalidate only L1 cache???? - #FIX_ME# */ | |
544 | /* mcr p15, 0, r11, c7, c11, 1 */ | |
545 | cmp r9, #1 /* Check whether L2 inval is required or not*/ | |
546 | bne skip_l2_inval | |
547 | clean_l2: | |
0bd40535 RW |
548 | /* |
549 | * Jump out to kernel flush routine | |
550 | * - reuse that code is better | |
551 | * - it executes in a cached space so is faster than refetch per-block | |
552 | * - should be faster and will change with kernel | |
553 | * - 'might' have to copy address, load and jump to it | |
554 | * - lr is used since we are running in SRAM currently. | |
555 | */ | |
556 | ldr r1, kernel_flush | |
557 | mov lr, pc | |
558 | bx r1 | |
559 | ||
8bd22949 KH |
560 | skip_l2_inval: |
561 | /* Data memory barrier and Data sync barrier */ | |
562 | mov r1, #0 | |
563 | mcr p15, 0, r1, c7, c10, 4 | |
564 | mcr p15, 0, r1, c7, c10, 5 | |
565 | ||
566 | wfi @ wait for interrupt | |
567 | nop | |
568 | nop | |
569 | nop | |
570 | nop | |
571 | nop | |
572 | nop | |
573 | nop | |
574 | nop | |
575 | nop | |
576 | nop | |
89139dce | 577 | bl wait_sdrc_ok |
8bd22949 KH |
578 | /* restore regs and return */ |
579 | ldmfd sp!, {r0-r12, pc} | |
580 | ||
89139dce PDS |
581 | /* Make sure SDRC accesses are ok */ |
582 | wait_sdrc_ok: | |
9d93b8a2 PDS |
583 | |
584 | /* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ | |
585 | ldr r4, cm_idlest_ckgen | |
586 | wait_dpll3_lock: | |
587 | ldr r5, [r4] | |
588 | tst r5, #1 | |
589 | beq wait_dpll3_lock | |
590 | ||
89139dce | 591 | ldr r4, cm_idlest1_core |
9d93b8a2 | 592 | wait_sdrc_ready: |
89139dce | 593 | ldr r5, [r4] |
9d93b8a2 PDS |
594 | tst r5, #0x2 |
595 | bne wait_sdrc_ready | |
596 | /* allow DLL powerdown upon hw idle req */ | |
89139dce PDS |
597 | ldr r4, sdrc_power |
598 | ldr r5, [r4] | |
599 | bic r5, r5, #0x40 | |
600 | str r5, [r4] | |
9d93b8a2 PDS |
601 | is_dll_in_lock_mode: |
602 | ||
89139dce PDS |
603 | /* Is dll in lock mode? */ |
604 | ldr r4, sdrc_dlla_ctrl | |
605 | ldr r5, [r4] | |
606 | tst r5, #0x4 | |
607 | bxne lr | |
608 | /* wait till dll locks */ | |
9d93b8a2 PDS |
609 | wait_dll_lock_timed: |
610 | ldr r4, wait_dll_lock_counter | |
611 | add r4, r4, #1 | |
612 | str r4, wait_dll_lock_counter | |
613 | ldr r4, sdrc_dlla_status | |
614 | mov r6, #8 /* Wait 20uS for lock */ | |
615 | wait_dll_lock: | |
616 | subs r6, r6, #0x1 | |
617 | beq kick_dll | |
89139dce PDS |
618 | ldr r5, [r4] |
619 | and r5, r5, #0x4 | |
620 | cmp r5, #0x4 | |
621 | bne wait_dll_lock | |
622 | bx lr | |
8bd22949 | 623 | |
9d93b8a2 PDS |
624 | /* disable/reenable DLL if not locked */ |
625 | kick_dll: | |
626 | ldr r4, sdrc_dlla_ctrl | |
627 | ldr r5, [r4] | |
628 | mov r6, r5 | |
629 | bic r6, #(1<<3) /* disable dll */ | |
630 | str r6, [r4] | |
631 | dsb | |
632 | orr r6, r6, #(1<<3) /* enable dll */ | |
633 | str r6, [r4] | |
634 | dsb | |
635 | ldr r4, kick_counter | |
636 | add r4, r4, #1 | |
637 | str r4, kick_counter | |
638 | b wait_dll_lock_timed | |
639 | ||
89139dce PDS |
640 | cm_idlest1_core: |
641 | .word CM_IDLEST1_CORE_V | |
9d93b8a2 PDS |
642 | cm_idlest_ckgen: |
643 | .word CM_IDLEST_CKGEN_V | |
89139dce PDS |
644 | sdrc_dlla_status: |
645 | .word SDRC_DLLA_STATUS_V | |
646 | sdrc_dlla_ctrl: | |
647 | .word SDRC_DLLA_CTRL_V | |
8bd22949 KH |
648 | pm_prepwstst_core: |
649 | .word PM_PREPWSTST_CORE_V | |
0795a75a TK |
650 | pm_prepwstst_core_p: |
651 | .word PM_PREPWSTST_CORE_P | |
8bd22949 KH |
652 | pm_prepwstst_mpu: |
653 | .word PM_PREPWSTST_MPU_V | |
654 | pm_pwstctrl_mpu: | |
655 | .word PM_PWSTCTRL_MPU_P | |
656 | scratchpad_base: | |
657 | .word SCRATCHPAD_BASE_P | |
0795a75a TK |
658 | sram_base: |
659 | .word SRAM_BASE_P + 0x8000 | |
8bd22949 KH |
660 | sdrc_power: |
661 | .word SDRC_POWER_V | |
8bd22949 KH |
662 | clk_stabilize_delay: |
663 | .word 0x000001FF | |
664 | assoc_mask: | |
665 | .word 0x3ff | |
666 | numset_mask: | |
667 | .word 0x7fff | |
668 | ttbrbit_mask: | |
669 | .word 0xFFFFC000 | |
670 | table_index_mask: | |
671 | .word 0xFFF00000 | |
672 | table_entry: | |
673 | .word 0x00000C02 | |
674 | cache_pred_disable_mask: | |
675 | .word 0xFFFFE7FB | |
27d59a4a TK |
676 | control_stat: |
677 | .word CONTROL_STAT | |
458e999e NM |
678 | control_mem_rta: |
679 | .word CONTROL_MEM_RTA_CTRL | |
0bd40535 RW |
680 | kernel_flush: |
681 | .word v7_flush_dcache_all | |
9d93b8a2 PDS |
682 | /* |
683 | * When exporting to userspace while the counters are in SRAM, | |
684 | * these 2 words need to be at the end to facilitate retrival! | |
685 | */ | |
686 | kick_counter: | |
687 | .word 0 | |
688 | wait_dll_lock_counter: | |
689 | .word 0 | |
8bd22949 KH |
690 | ENTRY(omap34xx_cpu_suspend_sz) |
691 | .word . - omap34xx_cpu_suspend |