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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
8bd22949 | 2 | /* |
8bd22949 KH |
3 | * (C) Copyright 2007 |
4 | * Texas Instruments | |
5 | * Karthik Dasu <karthik-dp@ti.com> | |
6 | * | |
7 | * (C) Copyright 2004 | |
8 | * Texas Instruments, <www.ti.com> | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
8bd22949 KH |
10 | */ |
11 | #include <linux/linkage.h> | |
ee0839c2 | 12 | |
8bd22949 | 13 | #include <asm/assembler.h> |
ee0839c2 | 14 | |
c49f34bc | 15 | #include "omap34xx.h" |
ee0839c2 | 16 | #include "iomap.h" |
ff4ae5d9 | 17 | #include "cm3xxx.h" |
139563ad | 18 | #include "prm3xxx.h" |
8bd22949 | 19 | #include "sdrc.h" |
bf027ca1 | 20 | #include "sram.h" |
4814ced5 | 21 | #include "control.h" |
8bd22949 | 22 | |
fe360e1c JP |
23 | /* |
24 | * Registers access definitions | |
25 | */ | |
26 | #define SDRC_SCRATCHPAD_SEM_OFFS 0xc | |
27 | #define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ | |
28 | (SDRC_SCRATCHPAD_SEM_OFFS) | |
29 | #define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ | |
30 | OMAP3430_PM_PREPWSTST | |
37903009 | 31 | #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL |
89139dce | 32 | #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) |
9d93b8a2 | 33 | #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) |
fe360e1c JP |
34 | #define SRAM_BASE_P OMAP3_SRAM_PA |
35 | #define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS | |
36 | #define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ | |
37 | OMAP36XX_CONTROL_MEM_RTA_CTRL) | |
38 | ||
39 | /* Move this as correct place is available */ | |
40 | #define SCRATCHPAD_MEM_OFFS 0x310 | |
41 | #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ | |
42 | OMAP343X_CONTROL_MEM_WKUP +\ | |
43 | SCRATCHPAD_MEM_OFFS) | |
8bd22949 | 44 | #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) |
0795a75a TK |
45 | #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) |
46 | #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) | |
47 | #define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) | |
48 | #define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) | |
49 | #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) | |
50 | #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) | |
51 | #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) | |
89139dce PDS |
52 | #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
53 | #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) | |
8bd22949 | 54 | |
dd313947 DM |
55 | /* |
56 | * This file needs be built unconditionally as ARM to interoperate correctly | |
57 | * with non-Thumb-2-capable firmware. | |
58 | */ | |
59 | .arm | |
d3cdfd2a JP |
60 | |
61 | /* | |
62 | * API functions | |
f7dfe3d8 JP |
63 | */ |
64 | ||
c4236d2e PDS |
65 | .text |
66 | /* | |
67 | * L2 cache needs to be toggled for stable OFF mode functionality on 3630. | |
1e81bc01 | 68 | * This function sets up a flag that will allow for this toggling to take |
f7dfe3d8 | 69 | * place on 3630. Hopefully some version in the future may not need this. |
c4236d2e PDS |
70 | */ |
71 | ENTRY(enable_omap3630_toggle_l2_on_restore) | |
bb1c9034 | 72 | stmfd sp!, {lr} @ save registers on stack |
c4236d2e PDS |
73 | /* Setup so that we will disable and enable l2 */ |
74 | mov r1, #0x1 | |
eeaf9646 TL |
75 | adrl r3, l2dis_3630_offset @ may be too distant for plain adr |
76 | ldr r2, [r3] @ value for offset | |
77 | str r1, [r2, r3] @ write to l2dis_3630 | |
bb1c9034 | 78 | ldmfd sp!, {pc} @ restore regs and return |
dd313947 | 79 | ENDPROC(enable_omap3630_toggle_l2_on_restore) |
c4236d2e | 80 | |
a5311d4d | 81 | /* |
d09220a8 TL |
82 | * Function to call rom code to save secure ram context. |
83 | * | |
84 | * r0 = physical address of the parameters | |
a5311d4d | 85 | */ |
27d59a4a | 86 | ENTRY(save_secure_ram_context) |
857c1b81 | 87 | stmfd sp!, {r4 - r11, lr} @ save registers on stack |
d09220a8 | 88 | mov r3, r0 @ physical address of parameters |
27d59a4a TK |
89 | mov r0, #25 @ set service ID for PPA |
90 | mov r12, r0 @ copy secure service ID in r12 | |
91 | mov r1, #0 @ set task id for ROM code in r1 | |
ba50ea7e | 92 | mov r2, #4 @ set some flags in r2, r6 |
27d59a4a | 93 | mov r6, #0xff |
4444d712 SS |
94 | dsb @ data write barrier |
95 | dmb @ data memory barrier | |
76d50018 | 96 | smc #1 @ call SMI monitor (smi #1) |
27d59a4a TK |
97 | nop |
98 | nop | |
99 | nop | |
100 | nop | |
857c1b81 | 101 | ldmfd sp!, {r4 - r11, pc} |
dd313947 | 102 | ENDPROC(save_secure_ram_context) |
a5311d4d | 103 | |
f7dfe3d8 JP |
104 | /* |
105 | * ====================== | |
106 | * == Idle entry point == | |
107 | * ====================== | |
108 | */ | |
109 | ||
8bd22949 KH |
110 | /* |
111 | * Forces OMAP into idle state | |
112 | * | |
f7dfe3d8 JP |
113 | * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed |
114 | * and executes the WFI instruction. Calling WFI effectively changes the | |
115 | * power domains states to the desired target power states. | |
116 | * | |
8bd22949 | 117 | * |
f7dfe3d8 | 118 | * Notes: |
46e130d2 JP |
119 | * - only the minimum set of functions gets copied to internal SRAM at boot |
120 | * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function | |
121 | * pointers in SDRAM or SRAM are called depending on the desired low power | |
122 | * target state. | |
f7dfe3d8 JP |
123 | * - when the OMAP wakes up it continues at different execution points |
124 | * depending on the low power mode (non-OFF vs OFF modes), | |
125 | * cf. 'Resume path for xxx mode' comments. | |
8bd22949 | 126 | */ |
b6338bdc | 127 | .align 3 |
8bd22949 | 128 | ENTRY(omap34xx_cpu_suspend) |
857c1b81 | 129 | stmfd sp!, {r4 - r11, lr} @ save registers on stack |
d3cdfd2a | 130 | |
f7dfe3d8 | 131 | /* |
cbe26349 | 132 | * r0 contains information about saving context: |
f7dfe3d8 JP |
133 | * 0 - No context lost |
134 | * 1 - Only L1 and logic lost | |
c9749a35 SS |
135 | * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) |
136 | * 3 - Both L1 and L2 lost and logic lost | |
f7dfe3d8 | 137 | */ |
8bd22949 | 138 | |
46e130d2 JP |
139 | /* |
140 | * For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi) | |
141 | * For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram) | |
142 | */ | |
143 | ldr r4, omap3_do_wfi_sram_addr | |
144 | ldr r5, [r4] | |
cbe26349 | 145 | cmp r0, #0x0 @ If no context save required, |
46e130d2 JP |
146 | bxeq r5 @ jump to the WFI code in SRAM |
147 | ||
f7dfe3d8 JP |
148 | |
149 | /* Otherwise fall through to the save context code */ | |
150 | save_context_wfi: | |
f7dfe3d8 JP |
151 | /* |
152 | * jump out to kernel flush routine | |
153 | * - reuse that code is better | |
154 | * - it executes in a cached space so is faster than refetch per-block | |
155 | * - should be faster and will change with kernel | |
156 | * - 'might' have to copy address, load and jump to it | |
90625110 SS |
157 | * Flush all data from the L1 data cache before disabling |
158 | * SCTLR.C bit. | |
f7dfe3d8 | 159 | */ |
bb1c9034 JP |
160 | ldr r1, kernel_flush |
161 | mov lr, pc | |
162 | bx r1 | |
f7dfe3d8 | 163 | |
90625110 SS |
164 | /* |
165 | * Clear the SCTLR.C bit to prevent further data cache | |
166 | * allocation. Clearing SCTLR.C would make all the data accesses | |
167 | * strongly ordered and would not hit the cache. | |
168 | */ | |
169 | mrc p15, 0, r0, c1, c0, 0 | |
170 | bic r0, r0, #(1 << 2) @ Disable the C bit | |
171 | mcr p15, 0, r0, c1, c0, 0 | |
172 | isb | |
173 | ||
174 | /* | |
175 | * Invalidate L1 data cache. Even though only invalidate is | |
176 | * necessary exported flush API is used here. Doing clean | |
177 | * on already clean cache would be almost NOP. | |
f7dfe3d8 | 178 | */ |
bb1c9034 | 179 | ldr r1, kernel_flush |
dd313947 | 180 | blx r1 |
46e130d2 | 181 | b omap3_do_wfi |
d8a50941 | 182 | ENDPROC(omap34xx_cpu_suspend) |
46e130d2 JP |
183 | omap3_do_wfi_sram_addr: |
184 | .word omap3_do_wfi_sram | |
185 | kernel_flush: | |
186 | .word v7_flush_dcache_all | |
187 | ||
188 | /* =================================== | |
189 | * == WFI instruction => Enter idle == | |
190 | * =================================== | |
191 | */ | |
192 | ||
193 | /* | |
194 | * Do WFI instruction | |
195 | * Includes the resume path for non-OFF modes | |
196 | * | |
197 | * This code gets copied to internal SRAM and is accessible | |
198 | * from both SDRAM and SRAM: | |
199 | * - executed from SRAM for non-off modes (omap3_do_wfi_sram), | |
200 | * - executed from SDRAM for OFF mode (omap3_do_wfi). | |
201 | */ | |
202 | .align 3 | |
203 | ENTRY(omap3_do_wfi) | |
f7dfe3d8 JP |
204 | ldr r4, sdrc_power @ read the SDRC_POWER register |
205 | ldr r5, [r4] @ read the contents of SDRC_POWER | |
206 | orr r5, r5, #0x40 @ enable self refresh on idle req | |
207 | str r5, [r4] @ write back to SDRC_POWER register | |
208 | ||
8bd22949 | 209 | /* Data memory barrier and Data sync barrier */ |
4444d712 SS |
210 | dsb |
211 | dmb | |
8bd22949 | 212 | |
f7dfe3d8 JP |
213 | /* |
214 | * =================================== | |
215 | * == WFI instruction => Enter idle == | |
216 | * =================================== | |
217 | */ | |
8bd22949 KH |
218 | wfi @ wait for interrupt |
219 | ||
f7dfe3d8 JP |
220 | /* |
221 | * =================================== | |
222 | * == Resume path for non-OFF modes == | |
223 | * =================================== | |
224 | */ | |
8bd22949 KH |
225 | nop |
226 | nop | |
227 | nop | |
228 | nop | |
229 | nop | |
230 | nop | |
231 | nop | |
232 | nop | |
233 | nop | |
234 | nop | |
8bd22949 | 235 | |
46e130d2 JP |
236 | /* |
237 | * This function implements the erratum ID i581 WA: | |
238 | * SDRC state restore before accessing the SDRAM | |
239 | * | |
240 | * Only used at return from non-OFF mode. For OFF | |
241 | * mode the ROM code configures the SDRC and | |
242 | * the DPLL before calling the restore code directly | |
243 | * from DDR. | |
244 | */ | |
245 | ||
246 | /* Make sure SDRC accesses are ok */ | |
247 | wait_sdrc_ok: | |
248 | ||
249 | /* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ | |
250 | ldr r4, cm_idlest_ckgen | |
251 | wait_dpll3_lock: | |
252 | ldr r5, [r4] | |
253 | tst r5, #1 | |
254 | beq wait_dpll3_lock | |
255 | ||
256 | ldr r4, cm_idlest1_core | |
257 | wait_sdrc_ready: | |
258 | ldr r5, [r4] | |
259 | tst r5, #0x2 | |
260 | bne wait_sdrc_ready | |
261 | /* allow DLL powerdown upon hw idle req */ | |
262 | ldr r4, sdrc_power | |
263 | ldr r5, [r4] | |
264 | bic r5, r5, #0x40 | |
265 | str r5, [r4] | |
266 | ||
46e130d2 JP |
267 | is_dll_in_lock_mode: |
268 | /* Is dll in lock mode? */ | |
269 | ldr r4, sdrc_dlla_ctrl | |
270 | ldr r5, [r4] | |
271 | tst r5, #0x4 | |
272 | bne exit_nonoff_modes @ Return if locked | |
273 | /* wait till dll locks */ | |
46e130d2 | 274 | wait_dll_lock_timed: |
46e130d2 JP |
275 | ldr r4, sdrc_dlla_status |
276 | /* Wait 20uS for lock */ | |
277 | mov r6, #8 | |
278 | wait_dll_lock: | |
279 | subs r6, r6, #0x1 | |
280 | beq kick_dll | |
281 | ldr r5, [r4] | |
282 | and r5, r5, #0x4 | |
283 | cmp r5, #0x4 | |
284 | bne wait_dll_lock | |
285 | b exit_nonoff_modes @ Return when locked | |
286 | ||
287 | /* disable/reenable DLL if not locked */ | |
288 | kick_dll: | |
289 | ldr r4, sdrc_dlla_ctrl | |
290 | ldr r5, [r4] | |
291 | mov r6, r5 | |
292 | bic r6, #(1<<3) @ disable dll | |
293 | str r6, [r4] | |
294 | dsb | |
295 | orr r6, r6, #(1<<3) @ enable dll | |
296 | str r6, [r4] | |
297 | dsb | |
46e130d2 JP |
298 | b wait_dll_lock_timed |
299 | ||
300 | exit_nonoff_modes: | |
301 | /* Re-enable C-bit if needed */ | |
90625110 SS |
302 | mrc p15, 0, r0, c1, c0, 0 |
303 | tst r0, #(1 << 2) @ Check C bit enabled? | |
304 | orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared | |
305 | mcreq p15, 0, r0, c1, c0, 0 | |
306 | isb | |
307 | ||
f7dfe3d8 JP |
308 | /* |
309 | * =================================== | |
310 | * == Exit point from non-OFF modes == | |
311 | * =================================== | |
312 | */ | |
857c1b81 | 313 | ldmfd sp!, {r4 - r11, pc} @ restore regs and return |
d8a50941 | 314 | ENDPROC(omap3_do_wfi) |
46e130d2 JP |
315 | sdrc_power: |
316 | .word SDRC_POWER_V | |
317 | cm_idlest1_core: | |
318 | .word CM_IDLEST1_CORE_V | |
319 | cm_idlest_ckgen: | |
320 | .word CM_IDLEST_CKGEN_V | |
321 | sdrc_dlla_status: | |
322 | .word SDRC_DLLA_STATUS_V | |
323 | sdrc_dlla_ctrl: | |
324 | .word SDRC_DLLA_CTRL_V | |
46e130d2 JP |
325 | ENTRY(omap3_do_wfi_sz) |
326 | .word . - omap3_do_wfi | |
327 | ||
f7dfe3d8 JP |
328 | |
329 | /* | |
330 | * ============================== | |
331 | * == Resume path for OFF mode == | |
332 | * ============================== | |
333 | */ | |
334 | ||
335 | /* | |
336 | * The restore_* functions are called by the ROM code | |
337 | * when back from WFI in OFF mode. | |
338 | * Cf. the get_*restore_pointer functions. | |
339 | * | |
340 | * restore_es3: applies to 34xx >= ES3.0 | |
341 | * restore_3630: applies to 36xx | |
342 | * restore: common code for 3xxx | |
46e130d2 JP |
343 | * |
344 | * Note: when back from CORE and MPU OFF mode we are running | |
345 | * from SDRAM, without MMU, without the caches and prediction. | |
346 | * Also the SRAM content has been cleared. | |
f7dfe3d8 | 347 | */ |
14c79bbe | 348 | ENTRY(omap3_restore_es3) |
0795a75a TK |
349 | ldr r5, pm_prepwstst_core_p |
350 | ldr r4, [r5] | |
351 | and r4, r4, #0x3 | |
352 | cmp r4, #0x0 @ Check if previous power state of CORE is OFF | |
46e130d2 | 353 | bne omap3_restore @ Fall through to OMAP3 common code |
0795a75a TK |
354 | adr r0, es3_sdrc_fix |
355 | ldr r1, sram_base | |
356 | ldr r2, es3_sdrc_fix_sz | |
357 | mov r2, r2, ror #2 | |
358 | copy_to_sram: | |
359 | ldmia r0!, {r3} @ val = *src | |
360 | stmia r1!, {r3} @ *dst = val | |
361 | subs r2, r2, #0x1 @ num_words-- | |
362 | bne copy_to_sram | |
363 | ldr r1, sram_base | |
364 | blx r1 | |
46e130d2 | 365 | b omap3_restore @ Fall through to OMAP3 common code |
14c79bbe | 366 | ENDPROC(omap3_restore_es3) |
458e999e | 367 | |
14c79bbe | 368 | ENTRY(omap3_restore_3630) |
458e999e NM |
369 | ldr r1, pm_prepwstst_core_p |
370 | ldr r2, [r1] | |
371 | and r2, r2, #0x3 | |
372 | cmp r2, #0x0 @ Check if previous power state of CORE is OFF | |
46e130d2 | 373 | bne omap3_restore @ Fall through to OMAP3 common code |
458e999e NM |
374 | /* Disable RTA before giving control */ |
375 | ldr r1, control_mem_rta | |
376 | mov r2, #OMAP36XX_RTA_DISABLE | |
377 | str r2, [r1] | |
14c79bbe | 378 | ENDPROC(omap3_restore_3630) |
f7dfe3d8 JP |
379 | |
380 | /* Fall through to common code for the remaining logic */ | |
381 | ||
14c79bbe | 382 | ENTRY(omap3_restore) |
bb1c9034 | 383 | /* |
2637ce30 RK |
384 | * Read the pwstctrl register to check the reason for mpu reset. |
385 | * This tells us what was lost. | |
f7dfe3d8 | 386 | */ |
bb1c9034 | 387 | ldr r1, pm_pwstctrl_mpu |
8bd22949 | 388 | ldr r2, [r1] |
bb1c9034 JP |
389 | and r2, r2, #0x3 |
390 | cmp r2, #0x0 @ Check if target power state was OFF or RET | |
8bd22949 | 391 | bne logic_l1_restore |
c4236d2e | 392 | |
eeaf9646 TL |
393 | adr r1, l2dis_3630_offset @ address for offset |
394 | ldr r0, [r1] @ value for offset | |
395 | ldr r0, [r1, r0] @ value at l2dis_3630 | |
c4236d2e PDS |
396 | cmp r0, #0x1 @ should we disable L2 on 3630? |
397 | bne skipl2dis | |
398 | mrc p15, 0, r0, c1, c0, 1 | |
399 | bic r0, r0, #2 @ disable L2 cache | |
400 | mcr p15, 0, r0, c1, c0, 1 | |
401 | skipl2dis: | |
27d59a4a TK |
402 | ldr r0, control_stat |
403 | ldr r1, [r0] | |
404 | and r1, #0x700 | |
405 | cmp r1, #0x300 | |
406 | beq l2_inv_gp | |
0a0b1327 TL |
407 | adr r0, l2_inv_api_params_offset |
408 | ldr r3, [r0] | |
409 | add r3, r3, r0 @ r3 points to dummy parameters | |
bb1c9034 JP |
410 | mov r0, #40 @ set service ID for PPA |
411 | mov r12, r0 @ copy secure Service ID in r12 | |
412 | mov r1, #0 @ set task id for ROM code in r1 | |
413 | mov r2, #4 @ set some flags in r2, r6 | |
27d59a4a | 414 | mov r6, #0xff |
4444d712 SS |
415 | dsb @ data write barrier |
416 | dmb @ data memory barrier | |
76d50018 | 417 | smc #1 @ call SMI monitor (smi #1) |
27d59a4a | 418 | /* Write to Aux control register to set some bits */ |
bb1c9034 JP |
419 | mov r0, #42 @ set service ID for PPA |
420 | mov r12, r0 @ copy secure Service ID in r12 | |
421 | mov r1, #0 @ set task id for ROM code in r1 | |
422 | mov r2, #4 @ set some flags in r2, r6 | |
27d59a4a | 423 | mov r6, #0xff |
a087cad9 | 424 | ldr r4, scratchpad_base |
bb1c9034 | 425 | ldr r3, [r4, #0xBC] @ r3 points to parameters |
4444d712 SS |
426 | dsb @ data write barrier |
427 | dmb @ data memory barrier | |
76d50018 | 428 | smc #1 @ call SMI monitor (smi #1) |
27d59a4a | 429 | |
79dcfdd4 TK |
430 | #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE |
431 | /* Restore L2 aux control register */ | |
bb1c9034 | 432 | @ set service ID for PPA |
79dcfdd4 | 433 | mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID |
bb1c9034 JP |
434 | mov r12, r0 @ copy service ID in r12 |
435 | mov r1, #0 @ set task ID for ROM code in r1 | |
436 | mov r2, #4 @ set some flags in r2, r6 | |
79dcfdd4 TK |
437 | mov r6, #0xff |
438 | ldr r4, scratchpad_base | |
439 | ldr r3, [r4, #0xBC] | |
bb1c9034 | 440 | adds r3, r3, #8 @ r3 points to parameters |
4444d712 SS |
441 | dsb @ data write barrier |
442 | dmb @ data memory barrier | |
76d50018 | 443 | smc #1 @ call SMI monitor (smi #1) |
79dcfdd4 | 444 | #endif |
27d59a4a | 445 | b logic_l1_restore |
bb1c9034 | 446 | |
dd313947 | 447 | .align |
0a0b1327 TL |
448 | l2_inv_api_params_offset: |
449 | .long l2_inv_api_params - . | |
27d59a4a | 450 | l2_inv_gp: |
8bd22949 | 451 | /* Execute smi to invalidate L2 cache */ |
bb1c9034 | 452 | mov r12, #0x1 @ set up to invalidate L2 |
76d50018 | 453 | smc #0 @ Call SMI monitor (smieq) |
27d59a4a | 454 | /* Write to Aux control register to set some bits */ |
a087cad9 TK |
455 | ldr r4, scratchpad_base |
456 | ldr r3, [r4,#0xBC] | |
457 | ldr r0, [r3,#4] | |
27d59a4a | 458 | mov r12, #0x3 |
76d50018 | 459 | smc #0 @ Call SMI monitor (smieq) |
79dcfdd4 TK |
460 | ldr r4, scratchpad_base |
461 | ldr r3, [r4,#0xBC] | |
462 | ldr r0, [r3,#12] | |
463 | mov r12, #0x2 | |
76d50018 | 464 | smc #0 @ Call SMI monitor (smieq) |
8bd22949 | 465 | logic_l1_restore: |
eeaf9646 TL |
466 | adr r0, l2dis_3630_offset @ adress for offset |
467 | ldr r1, [r0] @ value for offset | |
468 | ldr r1, [r0, r1] @ value at l2dis_3630 | |
bb1c9034 | 469 | cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 |
c4236d2e PDS |
470 | bne skipl2reen |
471 | mrc p15, 0, r1, c1, c0, 1 | |
bb1c9034 | 472 | orr r1, r1, #2 @ re-enable L2 cache |
c4236d2e PDS |
473 | mcr p15, 0, r1, c1, c0, 1 |
474 | skipl2reen: | |
8bd22949 | 475 | |
076f2cc4 RK |
476 | /* Now branch to the common CPU resume function */ |
477 | b cpu_resume | |
14c79bbe | 478 | ENDPROC(omap3_restore) |
8bd22949 | 479 | |
076f2cc4 | 480 | .ltorg |
1e81bc01 | 481 | |
46e130d2 JP |
482 | /* |
483 | * Local variables | |
484 | */ | |
485 | pm_prepwstst_core_p: | |
486 | .word PM_PREPWSTST_CORE_P | |
487 | pm_pwstctrl_mpu: | |
488 | .word PM_PWSTCTRL_MPU_P | |
489 | scratchpad_base: | |
490 | .word SCRATCHPAD_BASE_P | |
491 | sram_base: | |
492 | .word SRAM_BASE_P + 0x8000 | |
493 | control_stat: | |
494 | .word CONTROL_STAT | |
495 | control_mem_rta: | |
496 | .word CONTROL_MEM_RTA_CTRL | |
eeaf9646 TL |
497 | l2dis_3630_offset: |
498 | .long l2dis_3630 - . | |
499 | ||
500 | .data | |
1abd3502 | 501 | .align 2 |
46e130d2 JP |
502 | l2dis_3630: |
503 | .word 0 | |
504 | ||
0a0b1327 | 505 | .data |
1abd3502 | 506 | .align 2 |
0a0b1327 TL |
507 | l2_inv_api_params: |
508 | .word 0x1, 0x00 | |
509 | ||
1e81bc01 JP |
510 | /* |
511 | * Internal functions | |
512 | */ | |
513 | ||
46e130d2 JP |
514 | /* |
515 | * This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 | |
516 | * Copied to and run from SRAM in order to reconfigure the SDRC parameters. | |
517 | */ | |
1e81bc01 | 518 | .text |
dd313947 | 519 | .align 3 |
1e81bc01 JP |
520 | ENTRY(es3_sdrc_fix) |
521 | ldr r4, sdrc_syscfg @ get config addr | |
522 | ldr r5, [r4] @ get value | |
523 | tst r5, #0x100 @ is part access blocked | |
524 | it eq | |
525 | biceq r5, r5, #0x100 @ clear bit if set | |
526 | str r5, [r4] @ write back change | |
527 | ldr r4, sdrc_mr_0 @ get config addr | |
528 | ldr r5, [r4] @ get value | |
529 | str r5, [r4] @ write back change | |
530 | ldr r4, sdrc_emr2_0 @ get config addr | |
531 | ldr r5, [r4] @ get value | |
532 | str r5, [r4] @ write back change | |
533 | ldr r4, sdrc_manual_0 @ get config addr | |
534 | mov r5, #0x2 @ autorefresh command | |
535 | str r5, [r4] @ kick off refreshes | |
536 | ldr r4, sdrc_mr_1 @ get config addr | |
537 | ldr r5, [r4] @ get value | |
538 | str r5, [r4] @ write back change | |
539 | ldr r4, sdrc_emr2_1 @ get config addr | |
540 | ldr r5, [r4] @ get value | |
541 | str r5, [r4] @ write back change | |
542 | ldr r4, sdrc_manual_1 @ get config addr | |
543 | mov r5, #0x2 @ autorefresh command | |
544 | str r5, [r4] @ kick off refreshes | |
545 | bx lr | |
546 | ||
46e130d2 JP |
547 | /* |
548 | * Local variables | |
549 | */ | |
dd313947 | 550 | .align |
1e81bc01 JP |
551 | sdrc_syscfg: |
552 | .word SDRC_SYSCONFIG_P | |
553 | sdrc_mr_0: | |
554 | .word SDRC_MR_0_P | |
555 | sdrc_emr2_0: | |
556 | .word SDRC_EMR2_0_P | |
557 | sdrc_manual_0: | |
558 | .word SDRC_MANUAL_0_P | |
559 | sdrc_mr_1: | |
560 | .word SDRC_MR_1_P | |
561 | sdrc_emr2_1: | |
562 | .word SDRC_EMR2_1_P | |
563 | sdrc_manual_1: | |
564 | .word SDRC_MANUAL_1_P | |
dd313947 | 565 | ENDPROC(es3_sdrc_fix) |
1e81bc01 JP |
566 | ENTRY(es3_sdrc_fix_sz) |
567 | .word . - es3_sdrc_fix |