]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/mach-omap2/sr_device.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / sr_device.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
0c0a5d61
TG
2/*
3 * OMAP3/OMAP4 smartreflex device file
4 *
5 * Author: Thara Gopinath <thara@ti.com>
6 *
7 * Based originally on code from smartreflex.c
8 * Copyright (C) 2010 Texas Instruments, Inc.
9 * Thara Gopinath <thara@ti.com>
10 *
11 * Copyright (C) 2008 Nokia Corporation
12 * Kalle Jokiniemi
13 *
14 * Copyright (C) 2007 Texas Instruments, Inc.
15 * Lesly A M <x0080970@ti.com>
0c0a5d61 16 */
b86aeafc 17#include <linux/power/smartreflex.h>
0c0a5d61
TG
18
19#include <linux/err.h>
20#include <linux/slab.h>
b35cecf9 21#include <linux/io.h>
0c0a5d61 22
e4c060db 23#include "soc.h"
25c7d49e 24#include "omap_device.h"
e1d6f472 25#include "voltage.h"
0c0a5d61 26#include "control.h"
d0eadf6d 27#include "pm.h"
0c0a5d61
TG
28
29static bool sr_enable_on_init;
30
0c0a5d61
TG
31/* Read EFUSE values from control registers for OMAP3430 */
32static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
33 struct omap_sr_data *sr_data)
34{
35 struct omap_sr_nvalue_table *nvalue_table;
5e7f2e12
JP
36 int i, j, count = 0;
37
38 sr_data->nvalue_count = 0;
39 sr_data->nvalue_table = NULL;
0c0a5d61
TG
40
41 while (volt_data[count].volt_nominal)
42 count++;
43
6b72de4d 44 nvalue_table = kcalloc(count, sizeof(*nvalue_table), GFP_KERNEL);
c76e4d2e 45 if (!nvalue_table)
5e7f2e12 46 return;
5e7f2e12
JP
47
48 for (i = 0, j = 0; i < count; i++) {
b35cecf9 49 u32 v;
5e7f2e12 50
b35cecf9
TG
51 /*
52 * In OMAP4 the efuse registers are 24 bit aligned.
edfaf05c 53 * A readl_relaxed will fail for non-32 bit aligned address
b35cecf9
TG
54 * and hence the 8-bit read and shift.
55 */
56 if (cpu_is_omap44xx()) {
57 u16 offset = volt_data[i].sr_efuse_offs;
58
59 v = omap_ctrl_readb(offset) |
60 omap_ctrl_readb(offset + 1) << 8 |
61 omap_ctrl_readb(offset + 2) << 16;
62 } else {
5e7f2e12 63 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
b35cecf9 64 }
0c0a5d61 65
5e7f2e12
JP
66 /*
67 * Many OMAP SoCs don't have the eFuse values set.
68 * For example, pretty much all OMAP3xxx before
69 * ES3.something.
70 *
71 * XXX There needs to be some way for board files or
72 * userspace to add these in.
73 */
74 if (v == 0)
75 continue;
76
77 nvalue_table[j].nvalue = v;
78 nvalue_table[j].efuse_offs = volt_data[i].sr_efuse_offs;
79 nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
80 nvalue_table[j].volt_nominal = volt_data[i].volt_nominal;
81
82 j++;
0c0a5d61
TG
83 }
84
85 sr_data->nvalue_table = nvalue_table;
5e7f2e12 86 sr_data->nvalue_count = j;
0c0a5d61
TG
87}
88
d060b405
TL
89extern struct omap_sr_data omap_sr_pdata[];
90
9cf793f9 91static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
0c0a5d61 92{
695eea3d 93 struct omap_sr_data *sr_data = NULL;
0c0a5d61 94 struct omap_volt_data *volt_data;
cea6b942 95 struct omap_smartreflex_dev_attr *sr_dev_attr;
0c0a5d61
TG
96 static int i;
97
695eea3d
TL
98 if (!strncmp(oh->name, "smartreflex_mpu_iva", 20) ||
99 !strncmp(oh->name, "smartreflex_mpu", 16))
100 sr_data = &omap_sr_pdata[OMAP_SR_MPU];
101 else if (!strncmp(oh->name, "smartreflex_core", 17))
102 sr_data = &omap_sr_pdata[OMAP_SR_CORE];
103 else if (!strncmp(oh->name, "smartreflex_iva", 16))
104 sr_data = &omap_sr_pdata[OMAP_SR_IVA];
105
106 if (!sr_data) {
107 pr_err("%s: Unknown instance %s\n", __func__, oh->name);
108 return -EINVAL;
109 }
0c0a5d61 110
cea6b942
SG
111 sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
112 if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
7852ec05
PW
113 pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
114 __func__, oh->name);
0c0a5d61
TG
115 goto exit;
116 }
117
8b765d72 118 sr_data->name = oh->name;
70451127
TL
119 if (cpu_is_omap343x())
120 sr_data->ip_type = 1;
121 else
122 sr_data->ip_type = 2;
0c0a5d61
TG
123 sr_data->senn_mod = 0x1;
124 sr_data->senp_mod = 0x1;
125
98aed08e
JP
126 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
127 sr_data->err_weight = OMAP3430_SR_ERRWEIGHT;
128 sr_data->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
129 sr_data->accum_data = OMAP3430_SR_ACCUMDATA;
130 if (!(strcmp(sr_data->name, "smartreflex_mpu"))) {
131 sr_data->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
132 sr_data->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
133 } else {
134 sr_data->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
135 sr_data->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
136 }
137 }
138
cea6b942 139 sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
07684c1b 140 if (!sr_data->voltdm) {
0c0a5d61 141 pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
cea6b942 142 __func__, sr_dev_attr->sensor_voltdm_name);
0c0a5d61
TG
143 goto exit;
144 }
145
146 omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
147 if (!volt_data) {
7852ec05
PW
148 pr_err("%s: No Voltage table registered for VDD%d\n",
149 __func__, i + 1);
0c0a5d61
TG
150 goto exit;
151 }
152
153 sr_set_nvalues(volt_data, sr_data);
154
155 sr_data->enable_on_init = sr_enable_on_init;
156
0c0a5d61
TG
157exit:
158 i++;
695eea3d 159
0c0a5d61
TG
160 return 0;
161}
162
163/*
164 * API to be called from board files to enable smartreflex
165 * autocompensation at init.
166 */
167void __init omap_enable_smartreflex_on_init(void)
168{
169 sr_enable_on_init = true;
170}
171
172int __init omap_devinit_smartreflex(void)
173{
174 return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
175}