[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / timer-gp.c

/*
 * linux/arch/arm/mach-omap2/timer-gp.c
 *
 * OMAP2 GP timer support.
 *
 * Copyright (C) 2009 Nokia Corporation
 *
 * Update to use new clocksource/clockevent layers
 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
 * Copyright (C) 2007 MontaVista Software, Inc.
 *
 * Original driver:
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *         Juha Yrjölä <juha.yrjola@nokia.com>
 * OMAP Dual-mode timer framework support by Timo Teras
 *
 * Some parts based off of TI's 24xx code:
 *
 * Copyright (C) 2004-2009 Texas Instruments, Inc.
 *
 * Roughly modelled after the OMAP1 MPU timer code.
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>

#include <asm/mach/time.h>
#include <plat/dmtimer.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>
#include <plat/common.h>
#include <plat/omap_hwmod.h>

/* Parent clocks, eventually these will come from the clock framework */

#define OMAP2_MPU_SOURCE	"sys_ck"
#define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
#define OMAP4_MPU_SOURCE	"sys_clkin_ck"
#define OMAP2_32K_SOURCE	"func_32k_ck"
#define OMAP3_32K_SOURCE	"omap_32k_fck"
#define OMAP4_32K_SOURCE	"sys_32k_ck"

#ifdef CONFIG_OMAP_32K_TIMER
#define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
#define OMAP3_SECURE_TIMER	12
#else
#define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
#define OMAP3_SECURE_TIMER	1
#endif

/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
#define MAX_GPTIMER_ID		12

u32 sys_timer_reserved;

/* Clockevent code */

static struct omap_dm_timer clkev;
static struct clock_event_device clockevent_gpt;

static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_gpt;

	__omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction omap2_gp_timer_irq = {
	.name		= "gp timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= omap2_gp_timer_interrupt,
};

static int omap2_gp_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	__omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
						0xffffffff - cycles, 1);

	return 0;
}

static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 period;

	__omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		period = clkev.rate / HZ;
		period -= 1;
		/* Looks like we need to first set the load value separately */
		__omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
					0xffffffff - period, 1);
		__omap_dm_timer_load_start(clkev.io_base,
					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
						0xffffffff - period, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device clockevent_gpt = {
	.name		= "gp timer",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.set_next_event	= omap2_gp_timer_set_next_event,
	.set_mode	= omap2_gp_timer_set_mode,
};

static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
						int gptimer_id,
						const char *fck_source)
{
	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
	struct omap_hwmod *oh;
	size_t size;
	int res = 0;

	sprintf(name, "timer%d", gptimer_id);
	omap_hwmod_setup_one(name);
	oh = omap_hwmod_lookup(name);
	if (!oh)
		return -ENODEV;

	timer->irq = oh->mpu_irqs[0].irq;
	timer->phys_base = oh->slaves[0]->addr->pa_start;
	size = oh->slaves[0]->addr->pa_end - timer->phys_base;

	/* Static mapping, never released */
	timer->io_base = ioremap(timer->phys_base, size);
	if (!timer->io_base)
		return -ENXIO;

	/* After the dmtimer is using hwmod these clocks won't be needed */
	sprintf(name, "gpt%d_fck", gptimer_id);
	timer->fclk = clk_get(NULL, name);
	if (IS_ERR(timer->fclk))
		return -ENODEV;

	sprintf(name, "gpt%d_ick", gptimer_id);
	timer->iclk = clk_get(NULL, name);
	if (IS_ERR(timer->iclk)) {
		clk_put(timer->fclk);
		return -ENODEV;
	}

	omap_hwmod_enable(oh);

	sys_timer_reserved |= (1 << (gptimer_id - 1));

	if (gptimer_id != 12) {
		struct clk *src;

		src = clk_get(NULL, fck_source);
		if (IS_ERR(src)) {
			res = -EINVAL;
		} else {
			res = __omap_dm_timer_set_source(timer->fclk, src);
			if (IS_ERR_VALUE(res))
				pr_warning("%s: timer%i cannot set source\n",
						__func__, gptimer_id);
			clk_put(src);
		}
	}
	__omap_dm_timer_reset(timer->io_base, 1, 1);
	timer->posted = 1;

	timer->rate = clk_get_rate(timer->fclk);

	timer->reserved = 1;

	return res;
}

static void __init omap2_gp_clockevent_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
	BUG_ON(res);

	omap2_gp_timer_irq.dev_id = (void *)&clkev;
	setup_irq(clkev.irq, &omap2_gp_timer_irq);

	__omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);

	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
				     clockevent_gpt.shift);
	clockevent_gpt.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	clockevent_gpt.min_delta_ns =
		clockevent_delta2ns(3, &clockevent_gpt);
		/* Timer internal resynch latency. */

	clockevent_gpt.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_gpt);

	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
		gptimer_id, clkev.rate);
}

/* Clocksource code */

#ifdef CONFIG_OMAP_32K_TIMER
/* 
 * When 32k-timer is enabled, don't use GPTimer for clocksource
 * instead, just leave default clocksource which uses the 32k
 * sync counter.  See clocksource setup in plat-omap/counter_32k.c
 */

static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
{
	omap_init_clocksource_32k();
}

#else

static struct omap_dm_timer clksrc;

/*
 * clocksource
 */
static DEFINE_CLOCK_DATA(cd);
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
	return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
}

static struct clocksource clocksource_gpt = {
	.name		= "gp timer",
	.rating		= 300,
	.read		= clocksource_read_cycles,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void notrace dmtimer_update_sched_clock(void)
{
	u32 cyc;

	cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);

	update_sched_clock(&cd, cyc, (u32)~0);
}

unsigned long long notrace sched_clock(void)
{
	u32 cyc = 0;

	if (clksrc.reserved)
		cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);

	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}

/* Setup free-running counter for clocksource */
static void __init omap2_gp_clocksource_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	BUG_ON(res);

	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
		gptimer_id, clksrc.rate);

	__omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
	init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);

	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
		pr_err("Could not register clocksource %s\n",
			clocksource_gpt.name);
}
#endif

#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
				clksrc_nr, clksrc_src)			\
static void __init omap##name##_timer_init(void)			\
{									\
	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
	omap2_gp_clocksource_init((clksrc_nr), clksrc_src);		\
}

#define OMAP_SYS_TIMER(name)						\
struct sys_timer omap##name##_timer = {					\
	.init	= omap##name##_timer_init,				\
};

#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
OMAP_SYS_TIMER(2)
#endif

#ifdef CONFIG_ARCH_OMAP3
OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3)
OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
			2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3_secure)
#endif

#ifdef CONFIG_ARCH_OMAP4
static void __init omap4_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
	BUG_ON(!twd_base);
#endif
	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
	omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
}
OMAP_SYS_TIMER(4)
#endif
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/timer-gp.c
	3	*
	4	* OMAP2 GP timer support.
	5	*
f248076c PW	6	* Copyright (C) 2009 Nokia Corporation
f248076c PW	7	*
5a3a388f KH	8	* Update to use new clocksource/clockevent layers
	9	* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
	10	* Copyright (C) 2007 MontaVista Software, Inc.
	11	*
	12	* Original driver:
1dbae815 TL	13	* Copyright (C) 2005 Nokia Corporation
1dbae815 TL	14	* Author: Paul Mundt <paul.mundt@nokia.com>
96de0e25	15	* Juha Yrjölä <juha.yrjola@nokia.com>
77900a2f	16	* OMAP Dual-mode timer framework support by Timo Teras
1dbae815 TL	17	*
	18	* Some parts based off of TI's 24xx code:
	19	*
44169075	20	* Copyright (C) 2004-2009 Texas Instruments, Inc.
1dbae815 TL	21	*
1dbae815 TL	22	* Roughly modelled after the OMAP1 MPU timer code.
44169075	23	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1dbae815 TL	24	*
	25	* This file is subject to the terms and conditions of the GNU General Public
	26	* License. See the file "COPYING" in the main directory of this archive
	27	* for more details.
	28	*/
	29	#include <linux/init.h>
	30	#include <linux/time.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/err.h>
f8ce2547	33	#include <linux/clk.h>
77900a2f	34	#include <linux/delay.h>
e6687290	35	#include <linux/irq.h>
5a3a388f KH	36	#include <linux/clocksource.h>
5a3a388f KH	37	#include <linux/clockchips.h>
f8ce2547	38
1dbae815	39	#include <asm/mach/time.h>
ce491cf8	40	#include <plat/dmtimer.h>
39e1d4c1	41	#include <asm/localtimer.h>
cbc94380	42	#include <asm/sched_clock.h>
38698bef PW	43	#include <plat/common.h>
38698bef PW	44	#include <plat/omap_hwmod.h>
1dbae815	45
aa561889 TL	46	/* Parent clocks, eventually these will come from the clock framework */
	47
	48	#define OMAP2_MPU_SOURCE "sys_ck"
	49	#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
	50	#define OMAP4_MPU_SOURCE "sys_clkin_ck"
	51	#define OMAP2_32K_SOURCE "func_32k_ck"
	52	#define OMAP3_32K_SOURCE "omap_32k_fck"
	53	#define OMAP4_32K_SOURCE "sys_32k_ck"
	54
	55	#ifdef CONFIG_OMAP_32K_TIMER
	56	#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
	57	#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
	58	#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
	59	#define OMAP3_SECURE_TIMER 12
	60	#else
	61	#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
	62	#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
	63	#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
	64	#define OMAP3_SECURE_TIMER 1
	65	#endif
d8328f3b	66
f248076c PW	67	/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
	68	#define MAX_GPTIMER_ID 12
	69
11a0186f TL	70	u32 sys_timer_reserved;
11a0186f TL	71
aa561889 TL	72	/* Clockevent code */
	73
	74	static struct omap_dm_timer clkev;
5a3a388f	75	static struct clock_event_device clockevent_gpt;
1dbae815	76
0cd61b68	77	static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
1dbae815	78	{
5a3a388f KH	79	struct clock_event_device *evt = &clockevent_gpt;
5a3a388f KH	80
aa561889	81	__omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
1dbae815	82
5a3a388f	83	evt->event_handler(evt);
1dbae815 TL	84	return IRQ_HANDLED;
	85	}
	86
	87	static struct irqaction omap2_gp_timer_irq = {
	88	.name = "gp timer",
b30fabad	89	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
1dbae815 TL	90	.handler = omap2_gp_timer_interrupt,
	91	};
	92
5a3a388f KH	93	static int omap2_gp_timer_set_next_event(unsigned long cycles,
5a3a388f KH	94	struct clock_event_device *evt)
1dbae815	95	{
aa561889 TL	96	__omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
aa561889 TL	97	0xffffffff - cycles, 1);
5a3a388f KH	98
	99	return 0;
	100	}
	101
	102	static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
	103	struct clock_event_device *evt)
	104	{
	105	u32 period;
	106
aa561889	107	__omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
5a3a388f KH	108
	109	switch (mode) {
	110	case CLOCK_EVT_MODE_PERIODIC:
aa561889	111	period = clkev.rate / HZ;
5a3a388f	112	period -= 1;
aa561889 TL	113	/* Looks like we need to first set the load value separately */
	114	__omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
	115	0xffffffff - period, 1);
	116	__omap_dm_timer_load_start(clkev.io_base,
	117	OMAP_TIMER_CTRL_AR \| OMAP_TIMER_CTRL_ST,
	118	0xffffffff - period, 1);
5a3a388f KH	119	break;
	120	case CLOCK_EVT_MODE_ONESHOT:
	121	break;
	122	case CLOCK_EVT_MODE_UNUSED:
	123	case CLOCK_EVT_MODE_SHUTDOWN:
	124	case CLOCK_EVT_MODE_RESUME:
	125	break;
	126	}
	127	}
	128
	129	static struct clock_event_device clockevent_gpt = {
	130	.name = "gp timer",
	131	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	132	.shift = 32,
	133	.set_next_event = omap2_gp_timer_set_next_event,
	134	.set_mode = omap2_gp_timer_set_mode,
	135	};
	136
aa561889 TL	137	static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
	138	int gptimer_id,
	139	const char *fck_source)
5a3a388f	140	{
aa561889 TL	141	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
	142	struct omap_hwmod *oh;
	143	size_t size;
	144	int res = 0;
	145
	146	sprintf(name, "timer%d", gptimer_id);
	147	omap_hwmod_setup_one(name);
	148	oh = omap_hwmod_lookup(name);
	149	if (!oh)
	150	return -ENODEV;
	151
	152	timer->irq = oh->mpu_irqs[0].irq;
	153	timer->phys_base = oh->slaves[0]->addr->pa_start;
	154	size = oh->slaves[0]->addr->pa_end - timer->phys_base;
	155
	156	/* Static mapping, never released */
	157	timer->io_base = ioremap(timer->phys_base, size);
	158	if (!timer->io_base)
	159	return -ENXIO;
	160
	161	/* After the dmtimer is using hwmod these clocks won't be needed */
	162	sprintf(name, "gpt%d_fck", gptimer_id);
	163	timer->fclk = clk_get(NULL, name);
	164	if (IS_ERR(timer->fclk))
	165	return -ENODEV;
	166
	167	sprintf(name, "gpt%d_ick", gptimer_id);
	168	timer->iclk = clk_get(NULL, name);
	169	if (IS_ERR(timer->iclk)) {
	170	clk_put(timer->fclk);
	171	return -ENODEV;
	172	}
f248076c	173
aa561889 TL	174	omap_hwmod_enable(oh);
aa561889 TL	175
11a0186f TL	176	sys_timer_reserved \|= (1 << (gptimer_id - 1));
11a0186f TL	177
aa561889 TL	178	if (gptimer_id != 12) {
	179	struct clk *src;
	180
	181	src = clk_get(NULL, fck_source);
	182	if (IS_ERR(src)) {
	183	res = -EINVAL;
	184	} else {
	185	res = __omap_dm_timer_set_source(timer->fclk, src);
	186	if (IS_ERR_VALUE(res))
	187	pr_warning("%s: timer%i cannot set source\n",
	188	__func__, gptimer_id);
	189	clk_put(src);
	190	}
	191	}
	192	__omap_dm_timer_reset(timer->io_base, 1, 1);
	193	timer->posted = 1;
	194
	195	timer->rate = clk_get_rate(timer->fclk);
1dbae815	196
aa561889	197	timer->reserved = 1;
38698bef	198
aa561889 TL	199	return res;
aa561889 TL	200	}
f248076c	201
aa561889 TL	202	static void __init omap2_gp_clockevent_init(int gptimer_id,
	203	const char *fck_source)
	204	{
	205	int res;
f248076c	206
aa561889 TL	207	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
aa561889 TL	208	BUG_ON(res);
f248076c	209
98e182a2	210	omap2_gp_timer_irq.dev_id = (void *)&clkev;
aa561889	211	setup_irq(clkev.irq, &omap2_gp_timer_irq);
5a3a388f	212
aa561889 TL	213	__omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
	214
	215	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
5a3a388f KH	216	clockevent_gpt.shift);
	217	clockevent_gpt.max_delta_ns =
	218	clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	219	clockevent_gpt.min_delta_ns =
df88acbb AK	220	clockevent_delta2ns(3, &clockevent_gpt);
df88acbb AK	221	/* Timer internal resynch latency. */
5a3a388f	222
320ab2b0	223	clockevent_gpt.cpumask = cpumask_of(0);
5a3a388f	224	clockevents_register_device(&clockevent_gpt);
aa561889 TL	225
	226	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
	227	gptimer_id, clkev.rate);
5a3a388f KH	228	}
5a3a388f KH	229
f248076c PW	230	/* Clocksource code */
f248076c PW	231
5a3a388f KH	232	#ifdef CONFIG_OMAP_32K_TIMER
	233	/*
	234	* When 32k-timer is enabled, don't use GPTimer for clocksource
	235	* instead, just leave default clocksource which uses the 32k
d8328f3b	236	* sync counter. See clocksource setup in plat-omap/counter_32k.c
5a3a388f KH	237	*/
5a3a388f KH	238
3d05a3e8	239	static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
d8328f3b PW	240	{
	241	omap_init_clocksource_32k();
	242	}
	243
5a3a388f	244	#else
3d05a3e8 TL	245
	246	static struct omap_dm_timer clksrc;
	247
5a3a388f KH	248	/*
	249	* clocksource
	250	*/
cbc94380	251	static DEFINE_CLOCK_DATA(cd);
8e19608e	252	static cycle_t clocksource_read_cycles(struct clocksource *cs)
5a3a388f	253	{
3d05a3e8	254	return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
5a3a388f KH	255	}
	256
	257	static struct clocksource clocksource_gpt = {
	258	.name = "gp timer",
	259	.rating = 300,
	260	.read = clocksource_read_cycles,
	261	.mask = CLOCKSOURCE_MASK(32),
5a3a388f KH	262	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	263	};
	264
cbc94380 PW	265	static void notrace dmtimer_update_sched_clock(void)
	266	{
	267	u32 cyc;
	268
3d05a3e8	269	cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
cbc94380 PW	270
	271	update_sched_clock(&cd, cyc, (u32)~0);
	272	}
	273
3d05a3e8	274	unsigned long long notrace sched_clock(void)
5a3a388f	275	{
3d05a3e8	276	u32 cyc = 0;
5a3a388f	277
3d05a3e8 TL	278	if (clksrc.reserved)
3d05a3e8 TL	279	cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
5a3a388f	280
3d05a3e8 TL	281	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
	282	}
	283
	284	/* Setup free-running counter for clocksource */
	285	static void __init omap2_gp_clocksource_init(int gptimer_id,
	286	const char *fck_source)
	287	{
	288	int res;
	289
	290	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	291	BUG_ON(res);
5a3a388f	292
3d05a3e8 TL	293	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
3d05a3e8 TL	294	gptimer_id, clksrc.rate);
5a3a388f	295
3d05a3e8 TL	296	__omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
3d05a3e8 TL	297	init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
cbc94380	298
3d05a3e8 TL	299	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
	300	pr_err("Could not register clocksource %s\n",
	301	clocksource_gpt.name);
5a3a388f KH	302	}
	303	#endif
	304
3d05a3e8 TL	305	#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
3d05a3e8 TL	306	clksrc_nr, clksrc_src) \
e74984e4 TL	307	static void __init omap##name##_timer_init(void) \
e74984e4 TL	308	{ \
aa561889	309	omap2_gp_clockevent_init((clkev_nr), clkev_src); \
3d05a3e8	310	omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
e74984e4 TL	311	}
	312
	313	#define OMAP_SYS_TIMER(name) \
	314	struct sys_timer omap##name##_timer = { \
	315	.init = omap##name##_timer_init, \
	316	};
	317
	318	#ifdef CONFIG_ARCH_OMAP2
3d05a3e8	319	OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
e74984e4 TL	320	OMAP_SYS_TIMER(2)
	321	#endif
	322
	323	#ifdef CONFIG_ARCH_OMAP3
3d05a3e8	324	OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
e74984e4	325	OMAP_SYS_TIMER(3)
3d05a3e8 TL	326	OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
3d05a3e8 TL	327	2, OMAP3_MPU_SOURCE)
e74984e4 TL	328	OMAP_SYS_TIMER(3_secure)
	329	#endif
	330
	331	#ifdef CONFIG_ARCH_OMAP4
	332	static void __init omap4_timer_init(void)
5a3a388f	333	{
39e1d4c1	334	#ifdef CONFIG_LOCAL_TIMERS
e74984e4 TL	335	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
e74984e4 TL	336	BUG_ON(!twd_base);
39e1d4c1	337	#endif
aa561889	338	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
3d05a3e8	339	omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
1dbae815	340	}
e74984e4 TL	341	OMAP_SYS_TIMER(4)
e74984e4 TL	342	#endif