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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
40fc3bb5 JH |
42 | #include <linux/platform_device.h> |
43 | #include <linux/platform_data/dmtimer-omap.h> | |
38ff87f7 | 44 | #include <linux/sched_clock.h> |
f8ce2547 | 45 | |
1dbae815 | 46 | #include <asm/mach/time.h> |
a45c983f | 47 | #include <asm/smp_twd.h> |
7d7e1eba | 48 | |
2a296c8f | 49 | #include "omap_hwmod.h" |
25c7d49e | 50 | #include "omap_device.h" |
5c2e8852 | 51 | #include <plat/counter-32k.h> |
7d7e1eba | 52 | #include <plat/dmtimer.h> |
1d5aef49 | 53 | #include "omap-pm.h" |
b481113a | 54 | |
dbc04161 | 55 | #include "soc.h" |
7d7e1eba | 56 | #include "common.h" |
afc9d590 | 57 | #include "control.h" |
b481113a | 58 | #include "powerdomain.h" |
5523e409 | 59 | #include "omap-secure.h" |
1dbae815 | 60 | |
fa6d79d2 SS |
61 | #define REALTIME_COUNTER_BASE 0x48243200 |
62 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
63 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
64 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
65 | ||
aa561889 TL |
66 | /* Clockevent code */ |
67 | ||
68 | static struct omap_dm_timer clkev; | |
5a3a388f | 69 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 70 | |
12b28ba6 DG |
71 | /* Clockevent hwmod for am335x and am437x suspend */ |
72 | static struct omap_hwmod *clockevent_gpt_hwmod; | |
73 | ||
d5da94b8 | 74 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
5523e409 S |
75 | static unsigned long arch_timer_freq; |
76 | ||
77 | void set_cntfreq(void) | |
78 | { | |
79 | omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); | |
80 | } | |
d5da94b8 | 81 | #endif |
1dbae815 | 82 | |
0cd61b68 | 83 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 84 | { |
5a3a388f KH |
85 | struct clock_event_device *evt = &clockevent_gpt; |
86 | ||
ee17f114 | 87 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 88 | |
5a3a388f | 89 | evt->event_handler(evt); |
1dbae815 TL |
90 | return IRQ_HANDLED; |
91 | } | |
92 | ||
93 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 94 | .name = "gp_timer", |
fe806d04 | 95 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
96 | .handler = omap2_gp_timer_interrupt, |
97 | }; | |
98 | ||
5a3a388f KH |
99 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
100 | struct clock_event_device *evt) | |
1dbae815 | 101 | { |
ee17f114 | 102 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 103 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
104 | |
105 | return 0; | |
106 | } | |
107 | ||
74364615 VK |
108 | static int omap2_gp_timer_shutdown(struct clock_event_device *evt) |
109 | { | |
110 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) | |
5a3a388f KH |
115 | { |
116 | u32 period; | |
117 | ||
971d0254 | 118 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f | 119 | |
74364615 VK |
120 | period = clkev.rate / HZ; |
121 | period -= 1; | |
122 | /* Looks like we need to first set the load value separately */ | |
123 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, | |
124 | OMAP_TIMER_POSTED); | |
125 | __omap_dm_timer_load_start(&clkev, | |
126 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, | |
127 | 0xffffffff - period, OMAP_TIMER_POSTED); | |
128 | return 0; | |
5a3a388f KH |
129 | } |
130 | ||
12b28ba6 DG |
131 | static void omap_clkevt_idle(struct clock_event_device *unused) |
132 | { | |
133 | if (!clockevent_gpt_hwmod) | |
134 | return; | |
135 | ||
136 | omap_hwmod_idle(clockevent_gpt_hwmod); | |
137 | } | |
138 | ||
139 | static void omap_clkevt_unidle(struct clock_event_device *unused) | |
140 | { | |
141 | if (!clockevent_gpt_hwmod) | |
142 | return; | |
143 | ||
144 | omap_hwmod_enable(clockevent_gpt_hwmod); | |
145 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); | |
146 | } | |
147 | ||
5a3a388f | 148 | static struct clock_event_device clockevent_gpt = { |
74364615 VK |
149 | .features = CLOCK_EVT_FEAT_PERIODIC | |
150 | CLOCK_EVT_FEAT_ONESHOT, | |
151 | .rating = 300, | |
152 | .set_next_event = omap2_gp_timer_set_next_event, | |
153 | .set_state_shutdown = omap2_gp_timer_shutdown, | |
154 | .set_state_periodic = omap2_gp_timer_set_periodic, | |
155 | .set_state_oneshot = omap2_gp_timer_shutdown, | |
156 | .tick_resume = omap2_gp_timer_shutdown, | |
5a3a388f KH |
157 | }; |
158 | ||
ad24bde8 JH |
159 | static struct property device_disabled = { |
160 | .name = "status", | |
161 | .length = sizeof("disabled"), | |
162 | .value = "disabled", | |
163 | }; | |
164 | ||
31957609 | 165 | static const struct of_device_id omap_timer_match[] __initconst = { |
002e1ec5 JH |
166 | { .compatible = "ti,omap2420-timer", }, |
167 | { .compatible = "ti,omap3430-timer", }, | |
168 | { .compatible = "ti,omap4430-timer", }, | |
169 | { .compatible = "ti,omap5430-timer", }, | |
132754e4 TL |
170 | { .compatible = "ti,dm814-timer", }, |
171 | { .compatible = "ti,dm816-timer", }, | |
002e1ec5 JH |
172 | { .compatible = "ti,am335x-timer", }, |
173 | { .compatible = "ti,am335x-timer-1ms", }, | |
ad24bde8 JH |
174 | { } |
175 | }; | |
176 | ||
9725f445 JH |
177 | /** |
178 | * omap_get_timer_dt - get a timer using device-tree | |
179 | * @match - device-tree match structure for matching a device type | |
180 | * @property - optional timer property to match | |
181 | * | |
182 | * Helper function to get a timer during early boot using device-tree for use | |
183 | * as kernel system timer. Optionally, the property argument can be used to | |
184 | * select a timer with a specific property. Once a timer is found then mark | |
185 | * the timer node in device-tree as disabled, to prevent the kernel from | |
186 | * registering this timer as a platform device and so no one else can use it. | |
187 | */ | |
31957609 | 188 | static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, |
9725f445 JH |
189 | const char *property) |
190 | { | |
191 | struct device_node *np; | |
192 | ||
193 | for_each_matching_node(np, match) { | |
034bf091 | 194 | if (!of_device_is_available(np)) |
9725f445 | 195 | continue; |
9725f445 | 196 | |
034bf091 | 197 | if (property && !of_get_property(np, property, NULL)) |
9725f445 | 198 | continue; |
9725f445 | 199 | |
2eb03937 JH |
200 | if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || |
201 | of_get_property(np, "ti,timer-dsp", NULL) || | |
202 | of_get_property(np, "ti,timer-pwm", NULL) || | |
203 | of_get_property(np, "ti,timer-secure", NULL))) | |
204 | continue; | |
205 | ||
bf4c9449 FB |
206 | if (!of_device_is_compatible(np, "ti,omap-counter32k")) |
207 | of_add_property(np, &device_disabled); | |
9725f445 JH |
208 | return np; |
209 | } | |
210 | ||
211 | return NULL; | |
212 | } | |
213 | ||
ad24bde8 JH |
214 | /** |
215 | * omap_dmtimer_init - initialisation function when device tree is used | |
216 | * | |
ed5a4c62 SA |
217 | * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" |
218 | * cannot be used by the kernel as they are reserved. Therefore, to prevent the | |
ad24bde8 JH |
219 | * kernel registering these devices remove them dynamically from the device |
220 | * tree on boot. | |
221 | */ | |
bf85f205 | 222 | static void __init omap_dmtimer_init(void) |
ad24bde8 JH |
223 | { |
224 | struct device_node *np; | |
225 | ||
ed5a4c62 | 226 | if (!cpu_is_omap34xx() && !soc_is_dra7xx()) |
ad24bde8 JH |
227 | return; |
228 | ||
229 | /* If we are a secure device, remove any secure timer nodes */ | |
230 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 | 231 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
9a0cb985 | 232 | of_node_put(np); |
ad24bde8 JH |
233 | } |
234 | } | |
235 | ||
bfd6d021 JH |
236 | /** |
237 | * omap_dm_timer_get_errata - get errata flags for a timer | |
238 | * | |
239 | * Get the timer errata flags that are specific to the OMAP device being used. | |
240 | */ | |
bf85f205 | 241 | static u32 __init omap_dm_timer_get_errata(void) |
bfd6d021 JH |
242 | { |
243 | if (cpu_is_omap24xx()) | |
244 | return 0; | |
245 | ||
246 | return OMAP_TIMER_ERRATA_I103_I767; | |
247 | } | |
248 | ||
aa561889 | 249 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
e95ea43a JH |
250 | const char *fck_source, |
251 | const char *property, | |
252 | const char **timer_name, | |
253 | int posted) | |
5a3a388f | 254 | { |
37bd6ca8 | 255 | const char *oh_name = NULL; |
9725f445 | 256 | struct device_node *np; |
aa561889 | 257 | struct omap_hwmod *oh; |
a7990a19 | 258 | struct clk *src; |
f88095ba | 259 | int r = 0; |
aa561889 | 260 | |
8d39ff3d TL |
261 | np = omap_get_timer_dt(omap_timer_match, property); |
262 | if (!np) | |
263 | return -ENODEV; | |
9725f445 | 264 | |
8d39ff3d TL |
265 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); |
266 | if (!oh_name) | |
267 | return -ENODEV; | |
9725f445 | 268 | |
8d39ff3d TL |
269 | timer->irq = irq_of_parse_and_map(np, 0); |
270 | if (!timer->irq) | |
271 | return -ENXIO; | |
9725f445 | 272 | |
8d39ff3d | 273 | timer->io_base = of_iomap(np, 0); |
9725f445 | 274 | |
67d00470 | 275 | timer->fclk = of_clk_get_by_name(np, "fck"); |
138f7ca7 | 276 | |
8d39ff3d | 277 | of_node_put(np); |
9725f445 | 278 | |
9725f445 | 279 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
280 | if (!oh) |
281 | return -ENODEV; | |
282 | ||
e95ea43a JH |
283 | *timer_name = oh->name; |
284 | ||
aa561889 TL |
285 | if (!timer->io_base) |
286 | return -ENXIO; | |
287 | ||
e98580e8 TK |
288 | omap_hwmod_setup_one(oh_name); |
289 | ||
aa561889 | 290 | /* After the dmtimer is using hwmod these clocks won't be needed */ |
138f7ca7 TK |
291 | if (IS_ERR_OR_NULL(timer->fclk)) |
292 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); | |
aa561889 | 293 | if (IS_ERR(timer->fclk)) |
a7990a19 | 294 | return PTR_ERR(timer->fclk); |
aa561889 | 295 | |
a7990a19 JH |
296 | src = clk_get(NULL, fck_source); |
297 | if (IS_ERR(src)) | |
298 | return PTR_ERR(src); | |
aa561889 | 299 | |
874b300a TL |
300 | WARN(clk_set_parent(timer->fclk, src) < 0, |
301 | "Cannot set timer parent clock, no PLL clock driver?"); | |
b1538832 | 302 | |
a7990a19 JH |
303 | clk_put(src); |
304 | ||
b1538832 | 305 | omap_hwmod_enable(oh); |
ee17f114 | 306 | __omap_dm_timer_init_regs(timer); |
aa561889 | 307 | |
bfd6d021 JH |
308 | if (posted) |
309 | __omap_dm_timer_enable_posted(timer); | |
310 | ||
311 | /* Check that the intended posted configuration matches the actual */ | |
312 | if (posted != timer->posted) | |
313 | return -EINVAL; | |
1dbae815 | 314 | |
bfd6d021 | 315 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 316 | timer->reserved = 1; |
38698bef | 317 | |
f88095ba | 318 | return r; |
aa561889 | 319 | } |
f248076c | 320 | |
0b3e6fca GS |
321 | #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) |
322 | void tick_broadcast(const struct cpumask *mask) | |
323 | { | |
324 | } | |
325 | #endif | |
326 | ||
aa561889 | 327 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
328 | const char *fck_source, |
329 | const char *property) | |
aa561889 TL |
330 | { |
331 | int res; | |
f248076c | 332 | |
8f6924dc | 333 | clkev.id = gptimer_id; |
bfd6d021 JH |
334 | clkev.errata = omap_dm_timer_get_errata(); |
335 | ||
336 | /* | |
337 | * For clock-event timers we never read the timer counter and | |
338 | * so we are not impacted by errata i103 and i767. Therefore, | |
339 | * we can safely ignore this errata for clock-event timers. | |
340 | */ | |
341 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
342 | ||
8f6924dc | 343 | res = omap_dm_timer_init_one(&clkev, fck_source, property, |
e95ea43a | 344 | &clockevent_gpt.name, OMAP_TIMER_POSTED); |
aa561889 | 345 | BUG_ON(res); |
f248076c | 346 | |
a032d33b | 347 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 348 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 349 | |
ee17f114 | 350 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 | 351 | |
11d6ec2e SS |
352 | clockevent_gpt.cpumask = cpu_possible_mask; |
353 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
838a2ae8 SG |
354 | clockevents_config_and_register(&clockevent_gpt, clkev.rate, |
355 | 3, /* Timer internal resynch latency */ | |
356 | 0xffffffff); | |
aa561889 | 357 | |
12b28ba6 DG |
358 | if (soc_is_am33xx() || soc_is_am43xx()) { |
359 | clockevent_gpt.suspend = omap_clkevt_idle; | |
360 | clockevent_gpt.resume = omap_clkevt_unidle; | |
361 | ||
362 | clockevent_gpt_hwmod = | |
363 | omap_hwmod_lookup(clockevent_gpt.name); | |
364 | } | |
365 | ||
e95ea43a JH |
366 | pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, |
367 | clkev.rate); | |
5a3a388f KH |
368 | } |
369 | ||
f248076c | 370 | /* Clocksource code */ |
3d05a3e8 | 371 | static struct omap_dm_timer clksrc; |
332f1931 | 372 | static bool use_gptimer_clksrc __initdata; |
3d05a3e8 | 373 | |
5a3a388f KH |
374 | /* |
375 | * clocksource | |
376 | */ | |
a5a1d1c2 | 377 | static u64 clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 378 | { |
a5a1d1c2 | 379 | return (u64)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 380 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
381 | } |
382 | ||
383 | static struct clocksource clocksource_gpt = { | |
5a3a388f KH |
384 | .rating = 300, |
385 | .read = clocksource_read_cycles, | |
386 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
387 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
388 | }; | |
389 | ||
f99ba47c | 390 | static u64 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 391 | { |
3d05a3e8 | 392 | if (clksrc.reserved) |
971d0254 | 393 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 394 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 395 | |
2f0778af | 396 | return 0; |
3d05a3e8 TL |
397 | } |
398 | ||
31957609 | 399 | static const struct of_device_id omap_counter_match[] __initconst = { |
258e84af JH |
400 | { .compatible = "ti,omap-counter32k", }, |
401 | { } | |
402 | }; | |
403 | ||
3d05a3e8 | 404 | /* Setup free-running counter for clocksource */ |
e0c3e27c | 405 | static int __init __maybe_unused omap2_sync32k_clocksource_init(void) |
1fe97c8f VH |
406 | { |
407 | int ret; | |
9883f7c8 | 408 | struct device_node *np = NULL; |
1fe97c8f | 409 | struct omap_hwmod *oh; |
1fe97c8f VH |
410 | const char *oh_name = "counter_32k"; |
411 | ||
9883f7c8 | 412 | /* |
8d39ff3d | 413 | * See if the 32kHz counter is supported. |
9883f7c8 | 414 | */ |
8d39ff3d TL |
415 | np = omap_get_timer_dt(omap_counter_match, NULL); |
416 | if (!np) | |
417 | return -ENODEV; | |
418 | ||
419 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
420 | if (!oh_name) | |
421 | return -ENODEV; | |
9883f7c8 | 422 | |
1fe97c8f VH |
423 | /* |
424 | * First check hwmod data is available for sync32k counter | |
425 | */ | |
426 | oh = omap_hwmod_lookup(oh_name); | |
427 | if (!oh || oh->slaves_cnt == 0) | |
428 | return -ENODEV; | |
429 | ||
430 | omap_hwmod_setup_one(oh_name); | |
431 | ||
1fe97c8f VH |
432 | ret = omap_hwmod_enable(oh); |
433 | if (ret) { | |
434 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
435 | __func__, ret); | |
436 | return ret; | |
437 | } | |
438 | ||
1fe97c8f VH |
439 | return ret; |
440 | } | |
441 | ||
442 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
2eb03937 JH |
443 | const char *fck_source, |
444 | const char *property) | |
3d05a3e8 TL |
445 | { |
446 | int res; | |
447 | ||
8f6924dc | 448 | clksrc.id = gptimer_id; |
bfd6d021 JH |
449 | clksrc.errata = omap_dm_timer_get_errata(); |
450 | ||
8f6924dc | 451 | res = omap_dm_timer_init_one(&clksrc, fck_source, property, |
e95ea43a | 452 | &clocksource_gpt.name, |
bfd6d021 | 453 | OMAP_TIMER_NONPOSTED); |
3d05a3e8 | 454 | BUG_ON(res); |
5a3a388f | 455 | |
ee17f114 | 456 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 457 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 458 | OMAP_TIMER_NONPOSTED); |
f99ba47c | 459 | sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 460 | |
3d05a3e8 TL |
461 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
462 | pr_err("Could not register clocksource %s\n", | |
463 | clocksource_gpt.name); | |
1fe97c8f | 464 | else |
e95ea43a JH |
465 | pr_info("OMAP clocksource: %s at %lu Hz\n", |
466 | clocksource_gpt.name, clksrc.rate); | |
1fe97c8f VH |
467 | } |
468 | ||
3afbb9af FB |
469 | static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src, |
470 | const char *clkev_prop, int clksrc_nr, const char *clksrc_src, | |
471 | const char *clksrc_prop, bool gptimer) | |
472 | { | |
473 | omap_clk_init(); | |
474 | omap_dmtimer_init(); | |
475 | omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop); | |
476 | ||
477 | /* Enable the use of clocksource="gp_timer" kernel parameter */ | |
478 | if (use_gptimer_clksrc || gptimer) | |
479 | omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src, | |
480 | clksrc_prop); | |
481 | else | |
482 | omap2_sync32k_clocksource_init(); | |
483 | } | |
484 | ||
6f82e25d | 485 | void __init omap_init_time(void) |
3afbb9af FB |
486 | { |
487 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", | |
488 | 2, "timer_sys_ck", NULL, false); | |
9c46ffcd | 489 | |
970f9091 | 490 | clocksource_probe(); |
3afbb9af FB |
491 | } |
492 | ||
493 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) | |
494 | void __init omap3_secure_sync32k_timer_init(void) | |
495 | { | |
496 | __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", | |
497 | 2, "timer_sys_ck", NULL, false); | |
970f9091 TK |
498 | |
499 | clocksource_probe(); | |
3afbb9af FB |
500 | } |
501 | #endif /* CONFIG_ARCH_OMAP3 */ | |
502 | ||
f86a2c87 GS |
503 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ |
504 | defined(CONFIG_SOC_AM43XX) | |
3afbb9af FB |
505 | void __init omap3_gptimer_timer_init(void) |
506 | { | |
507 | __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, | |
508 | 1, "timer_sys_ck", "ti,timer-alwon", true); | |
f86a2c87 GS |
509 | if (of_have_populated_dt()) |
510 | clocksource_probe(); | |
3afbb9af FB |
511 | } |
512 | #endif | |
513 | ||
514 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ | |
f86a2c87 | 515 | defined(CONFIG_SOC_DRA7XX) |
3afbb9af FB |
516 | static void __init omap4_sync32k_timer_init(void) |
517 | { | |
518 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", | |
519 | 2, "sys_clkin_ck", NULL, false); | |
520 | } | |
521 | ||
522 | void __init omap4_local_timer_init(void) | |
523 | { | |
524 | omap4_sync32k_timer_init(); | |
a5e1d715 | 525 | clocksource_probe(); |
3afbb9af FB |
526 | } |
527 | #endif | |
528 | ||
529 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) | |
530 | ||
fa6d79d2 SS |
531 | /* |
532 | * The realtime counter also called master counter, is a free-running | |
533 | * counter, which is related to real time. It produces the count used | |
534 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
535 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
536 | * in different power modes, the master counter shifts operation between | |
537 | * clocks, adjusting the increment per clock in hardware accordingly to | |
538 | * maintain a constant count rate. | |
539 | */ | |
540 | static void __init realtime_counter_init(void) | |
541 | { | |
3afbb9af | 542 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
fa6d79d2 SS |
543 | void __iomem *base; |
544 | static struct clk *sys_clk; | |
545 | unsigned long rate; | |
afc9d590 LS |
546 | unsigned int reg; |
547 | unsigned long long num, den; | |
fa6d79d2 SS |
548 | |
549 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
550 | if (!base) { | |
551 | pr_err("%s: ioremap failed\n", __func__); | |
552 | return; | |
553 | } | |
7f585bbf | 554 | sys_clk = clk_get(NULL, "sys_clkin"); |
533b2981 | 555 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
556 | pr_err("%s: failed to get system clock handle\n", __func__); |
557 | iounmap(base); | |
558 | return; | |
559 | } | |
560 | ||
561 | rate = clk_get_rate(sys_clk); | |
afc9d590 LS |
562 | |
563 | if (soc_is_dra7xx()) { | |
564 | /* | |
565 | * Errata i856 says the 32.768KHz crystal does not start at | |
566 | * power on, so the CPU falls back to an emulated 32KHz clock | |
567 | * based on sysclk / 610 instead. This causes the master counter | |
568 | * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 | |
569 | * (OR sysclk * 75 / 244) | |
570 | * | |
571 | * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. | |
572 | * Of course any board built without a populated 32.768KHz | |
573 | * crystal would also need this fix even if the CPU is fixed | |
574 | * later. | |
575 | * | |
576 | * Either case can be detected by using the two speedselect bits | |
577 | * If they are not 0, then the 32.768KHz clock driving the | |
578 | * coarse counter that corrects the fine counter every time it | |
579 | * ticks is actually rate/610 rather than 32.768KHz and we | |
580 | * should compensate to avoid the 570ppm (at 20MHz, much worse | |
581 | * at other rates) too fast system time. | |
582 | */ | |
583 | reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); | |
584 | if (reg & DRA7_SPEEDSELECT_MASK) { | |
585 | num = 75; | |
586 | den = 244; | |
587 | goto sysclk1_based; | |
588 | } | |
589 | } | |
590 | ||
fa6d79d2 SS |
591 | /* Numerator/denumerator values refer TRM Realtime Counter section */ |
592 | switch (rate) { | |
572b24e6 | 593 | case 12000000: |
fa6d79d2 SS |
594 | num = 64; |
595 | den = 125; | |
596 | break; | |
572b24e6 | 597 | case 13000000: |
fa6d79d2 SS |
598 | num = 768; |
599 | den = 1625; | |
600 | break; | |
601 | case 19200000: | |
602 | num = 8; | |
603 | den = 25; | |
604 | break; | |
38a1981c S |
605 | case 20000000: |
606 | num = 192; | |
607 | den = 625; | |
608 | break; | |
572b24e6 | 609 | case 26000000: |
fa6d79d2 SS |
610 | num = 384; |
611 | den = 1625; | |
612 | break; | |
572b24e6 | 613 | case 27000000: |
fa6d79d2 SS |
614 | num = 256; |
615 | den = 1125; | |
616 | break; | |
617 | case 38400000: | |
618 | default: | |
619 | /* Program it for 38.4 MHz */ | |
620 | num = 4; | |
621 | den = 25; | |
622 | break; | |
623 | } | |
624 | ||
afc9d590 | 625 | sysclk1_based: |
fa6d79d2 | 626 | /* Program numerator and denumerator registers */ |
edfaf05c | 627 | reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & |
fa6d79d2 SS |
628 | NUMERATOR_DENUMERATOR_MASK; |
629 | reg |= num; | |
edfaf05c | 630 | writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); |
fa6d79d2 | 631 | |
edfaf05c | 632 | reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & |
fa6d79d2 SS |
633 | NUMERATOR_DENUMERATOR_MASK; |
634 | reg |= den; | |
edfaf05c | 635 | writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); |
fa6d79d2 | 636 | |
afc9d590 | 637 | arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); |
5523e409 S |
638 | set_cntfreq(); |
639 | ||
fa6d79d2 | 640 | iounmap(base); |
fa6d79d2 | 641 | #endif |
6f80b3bb IG |
642 | } |
643 | ||
6bb27d73 | 644 | void __init omap5_realtime_timer_init(void) |
fa6d79d2 | 645 | { |
00ea4d56 | 646 | omap4_sync32k_timer_init(); |
fa6d79d2 | 647 | realtime_counter_init(); |
3c7c5dab | 648 | |
3722ed23 | 649 | clocksource_probe(); |
fa6d79d2 | 650 | } |
0b8214fe | 651 | #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ |
37b3280d | 652 | |
1fe97c8f VH |
653 | /** |
654 | * omap2_override_clocksource - clocksource override with user configuration | |
655 | * | |
656 | * Allows user to override default clocksource, using kernel parameter | |
657 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
658 | * | |
659 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
660 | * and not introducing any OMAP specific interface. | |
661 | */ | |
662 | static int __init omap2_override_clocksource(char *str) | |
663 | { | |
664 | if (!str) | |
665 | return 0; | |
666 | /* | |
667 | * For OMAP architecture, we only have two options | |
668 | * - sync_32k (default) | |
669 | * - gp_timer (sys_clk based) | |
670 | */ | |
671 | if (!strcmp(str, "gp_timer")) | |
672 | use_gptimer_clksrc = true; | |
673 | ||
674 | return 0; | |
675 | } | |
676 | early_param("clocksource", omap2_override_clocksource); |