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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
f8ce2547 | 42 | |
1dbae815 | 43 | #include <asm/mach/time.h> |
a45c983f | 44 | #include <asm/smp_twd.h> |
cbc94380 | 45 | #include <asm/sched_clock.h> |
7d7e1eba | 46 | |
3c7c5dab | 47 | #include <asm/arch_timer.h> |
2a296c8f | 48 | #include "omap_hwmod.h" |
25c7d49e | 49 | #include "omap_device.h" |
5c2e8852 | 50 | #include <plat/counter-32k.h> |
7d7e1eba | 51 | #include <plat/dmtimer.h> |
1d5aef49 | 52 | #include "omap-pm.h" |
b481113a | 53 | |
dbc04161 | 54 | #include "soc.h" |
7d7e1eba | 55 | #include "common.h" |
b481113a | 56 | #include "powerdomain.h" |
1dbae815 | 57 | |
aa561889 TL |
58 | /* Parent clocks, eventually these will come from the clock framework */ |
59 | ||
60 | #define OMAP2_MPU_SOURCE "sys_ck" | |
61 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | |
62 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | |
63 | #define OMAP2_32K_SOURCE "func_32k_ck" | |
64 | #define OMAP3_32K_SOURCE "omap_32k_fck" | |
65 | #define OMAP4_32K_SOURCE "sys_32k_ck" | |
66 | ||
67 | #ifdef CONFIG_OMAP_32K_TIMER | |
68 | #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE | |
69 | #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE | |
70 | #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE | |
71 | #define OMAP3_SECURE_TIMER 12 | |
9725f445 | 72 | #define TIMER_PROP_SECURE "ti,timer-secure" |
aa561889 TL |
73 | #else |
74 | #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE | |
75 | #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE | |
76 | #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE | |
77 | #define OMAP3_SECURE_TIMER 1 | |
9725f445 | 78 | #define TIMER_PROP_SECURE "ti,timer-alwon" |
aa561889 | 79 | #endif |
d8328f3b | 80 | |
fa6d79d2 SS |
81 | #define REALTIME_COUNTER_BASE 0x48243200 |
82 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
83 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
84 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
85 | ||
aa561889 TL |
86 | /* Clockevent code */ |
87 | ||
88 | static struct omap_dm_timer clkev; | |
5a3a388f | 89 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 90 | |
0cd61b68 | 91 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 92 | { |
5a3a388f KH |
93 | struct clock_event_device *evt = &clockevent_gpt; |
94 | ||
ee17f114 | 95 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 96 | |
5a3a388f | 97 | evt->event_handler(evt); |
1dbae815 TL |
98 | return IRQ_HANDLED; |
99 | } | |
100 | ||
101 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 102 | .name = "gp_timer", |
b30fabad | 103 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
104 | .handler = omap2_gp_timer_interrupt, |
105 | }; | |
106 | ||
5a3a388f KH |
107 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
108 | struct clock_event_device *evt) | |
1dbae815 | 109 | { |
ee17f114 | 110 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
aa561889 | 111 | 0xffffffff - cycles, 1); |
5a3a388f KH |
112 | |
113 | return 0; | |
114 | } | |
115 | ||
116 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
117 | struct clock_event_device *evt) | |
118 | { | |
119 | u32 period; | |
120 | ||
ee17f114 | 121 | __omap_dm_timer_stop(&clkev, 1, clkev.rate); |
5a3a388f KH |
122 | |
123 | switch (mode) { | |
124 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 125 | period = clkev.rate / HZ; |
5a3a388f | 126 | period -= 1; |
aa561889 | 127 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 128 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
aa561889 | 129 | 0xffffffff - period, 1); |
ee17f114 | 130 | __omap_dm_timer_load_start(&clkev, |
aa561889 TL |
131 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
132 | 0xffffffff - period, 1); | |
5a3a388f KH |
133 | break; |
134 | case CLOCK_EVT_MODE_ONESHOT: | |
135 | break; | |
136 | case CLOCK_EVT_MODE_UNUSED: | |
137 | case CLOCK_EVT_MODE_SHUTDOWN: | |
138 | case CLOCK_EVT_MODE_RESUME: | |
139 | break; | |
140 | } | |
141 | } | |
142 | ||
143 | static struct clock_event_device clockevent_gpt = { | |
f36921be | 144 | .name = "gp_timer", |
5a3a388f KH |
145 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
146 | .shift = 32, | |
11d6ec2e | 147 | .rating = 300, |
5a3a388f KH |
148 | .set_next_event = omap2_gp_timer_set_next_event, |
149 | .set_mode = omap2_gp_timer_set_mode, | |
150 | }; | |
151 | ||
ad24bde8 JH |
152 | static struct property device_disabled = { |
153 | .name = "status", | |
154 | .length = sizeof("disabled"), | |
155 | .value = "disabled", | |
156 | }; | |
157 | ||
158 | static struct of_device_id omap_timer_match[] __initdata = { | |
159 | { .compatible = "ti,omap2-timer", }, | |
160 | { } | |
161 | }; | |
162 | ||
9883f7c8 JH |
163 | static struct of_device_id omap_counter_match[] __initdata = { |
164 | { .compatible = "ti,omap-counter32k", }, | |
165 | { } | |
166 | }; | |
167 | ||
9725f445 JH |
168 | /** |
169 | * omap_get_timer_dt - get a timer using device-tree | |
170 | * @match - device-tree match structure for matching a device type | |
171 | * @property - optional timer property to match | |
172 | * | |
173 | * Helper function to get a timer during early boot using device-tree for use | |
174 | * as kernel system timer. Optionally, the property argument can be used to | |
175 | * select a timer with a specific property. Once a timer is found then mark | |
176 | * the timer node in device-tree as disabled, to prevent the kernel from | |
177 | * registering this timer as a platform device and so no one else can use it. | |
178 | */ | |
179 | static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |
180 | const char *property) | |
181 | { | |
182 | struct device_node *np; | |
183 | ||
184 | for_each_matching_node(np, match) { | |
185 | if (!of_device_is_available(np)) { | |
186 | of_node_put(np); | |
187 | continue; | |
188 | } | |
189 | ||
190 | if (property && !of_get_property(np, property, NULL)) { | |
191 | of_node_put(np); | |
192 | continue; | |
193 | } | |
194 | ||
195 | prom_add_property(np, &device_disabled); | |
196 | return np; | |
197 | } | |
198 | ||
199 | return NULL; | |
200 | } | |
201 | ||
ad24bde8 JH |
202 | /** |
203 | * omap_dmtimer_init - initialisation function when device tree is used | |
204 | * | |
205 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
206 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
207 | * kernel registering these devices remove them dynamically from the device | |
208 | * tree on boot. | |
209 | */ | |
210 | void __init omap_dmtimer_init(void) | |
211 | { | |
212 | struct device_node *np; | |
213 | ||
214 | if (!cpu_is_omap34xx()) | |
215 | return; | |
216 | ||
217 | /* If we are a secure device, remove any secure timer nodes */ | |
218 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 JH |
219 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
220 | if (np) | |
221 | of_node_put(np); | |
ad24bde8 JH |
222 | } |
223 | } | |
224 | ||
aa561889 TL |
225 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
226 | int gptimer_id, | |
9725f445 JH |
227 | const char *fck_source, |
228 | const char *property) | |
5a3a388f | 229 | { |
aa561889 | 230 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
9725f445 JH |
231 | const char *oh_name; |
232 | struct device_node *np; | |
aa561889 | 233 | struct omap_hwmod *oh; |
6c0c27fd | 234 | struct resource irq_rsrc, mem_rsrc; |
aa561889 TL |
235 | size_t size; |
236 | int res = 0; | |
6c0c27fd | 237 | int r; |
aa561889 | 238 | |
9725f445 JH |
239 | if (of_have_populated_dt()) { |
240 | np = omap_get_timer_dt(omap_timer_match, NULL); | |
241 | if (!np) | |
242 | return -ENODEV; | |
243 | ||
244 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
245 | if (!oh_name) | |
246 | return -ENODEV; | |
247 | ||
248 | timer->irq = irq_of_parse_and_map(np, 0); | |
249 | if (!timer->irq) | |
250 | return -ENXIO; | |
251 | ||
252 | timer->io_base = of_iomap(np, 0); | |
253 | ||
254 | of_node_put(np); | |
255 | } else { | |
256 | if (omap_dm_timer_reserve_systimer(gptimer_id)) | |
257 | return -ENODEV; | |
258 | ||
259 | sprintf(name, "timer%d", gptimer_id); | |
260 | oh_name = name; | |
261 | } | |
262 | ||
263 | omap_hwmod_setup_one(oh_name); | |
264 | oh = omap_hwmod_lookup(oh_name); | |
265 | ||
aa561889 TL |
266 | if (!oh) |
267 | return -ENODEV; | |
268 | ||
9725f445 JH |
269 | if (!of_have_populated_dt()) { |
270 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
271 | &irq_rsrc); | |
272 | if (r) | |
273 | return -ENXIO; | |
274 | timer->irq = irq_rsrc.start; | |
275 | ||
276 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
277 | &mem_rsrc); | |
278 | if (r) | |
279 | return -ENXIO; | |
280 | timer->phys_base = mem_rsrc.start; | |
281 | size = mem_rsrc.end - mem_rsrc.start; | |
282 | ||
283 | /* Static mapping, never released */ | |
284 | timer->io_base = ioremap(timer->phys_base, size); | |
285 | } | |
aa561889 | 286 | |
aa561889 TL |
287 | if (!timer->io_base) |
288 | return -ENXIO; | |
289 | ||
290 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 291 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 TL |
292 | if (IS_ERR(timer->fclk)) |
293 | return -ENODEV; | |
294 | ||
aa561889 TL |
295 | omap_hwmod_enable(oh); |
296 | ||
9725f445 | 297 | /* FIXME: Need to remove hard-coded test on timer ID */ |
aa561889 TL |
298 | if (gptimer_id != 12) { |
299 | struct clk *src; | |
300 | ||
301 | src = clk_get(NULL, fck_source); | |
302 | if (IS_ERR(src)) { | |
303 | res = -EINVAL; | |
304 | } else { | |
305 | res = __omap_dm_timer_set_source(timer->fclk, src); | |
306 | if (IS_ERR_VALUE(res)) | |
9725f445 JH |
307 | pr_warn("%s: %s cannot set source\n", |
308 | __func__, oh->name); | |
aa561889 TL |
309 | clk_put(src); |
310 | } | |
311 | } | |
ee17f114 TL |
312 | __omap_dm_timer_init_regs(timer); |
313 | __omap_dm_timer_reset(timer, 1, 1); | |
aa561889 TL |
314 | timer->posted = 1; |
315 | ||
316 | timer->rate = clk_get_rate(timer->fclk); | |
1dbae815 | 317 | |
aa561889 | 318 | timer->reserved = 1; |
38698bef | 319 | |
aa561889 TL |
320 | return res; |
321 | } | |
f248076c | 322 | |
aa561889 | 323 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
324 | const char *fck_source, |
325 | const char *property) | |
aa561889 TL |
326 | { |
327 | int res; | |
f248076c | 328 | |
9725f445 | 329 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property); |
aa561889 | 330 | BUG_ON(res); |
f248076c | 331 | |
a032d33b | 332 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 333 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 334 | |
ee17f114 | 335 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 TL |
336 | |
337 | clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, | |
5a3a388f KH |
338 | clockevent_gpt.shift); |
339 | clockevent_gpt.max_delta_ns = | |
340 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | |
341 | clockevent_gpt.min_delta_ns = | |
df88acbb AK |
342 | clockevent_delta2ns(3, &clockevent_gpt); |
343 | /* Timer internal resynch latency. */ | |
5a3a388f | 344 | |
11d6ec2e SS |
345 | clockevent_gpt.cpumask = cpu_possible_mask; |
346 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
5a3a388f | 347 | clockevents_register_device(&clockevent_gpt); |
aa561889 TL |
348 | |
349 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | |
350 | gptimer_id, clkev.rate); | |
5a3a388f KH |
351 | } |
352 | ||
f248076c | 353 | /* Clocksource code */ |
3d05a3e8 | 354 | static struct omap_dm_timer clksrc; |
1fe97c8f | 355 | static bool use_gptimer_clksrc; |
3d05a3e8 | 356 | |
5a3a388f KH |
357 | /* |
358 | * clocksource | |
359 | */ | |
8e19608e | 360 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 361 | { |
ee17f114 | 362 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f KH |
363 | } |
364 | ||
365 | static struct clocksource clocksource_gpt = { | |
f36921be | 366 | .name = "gp_timer", |
5a3a388f KH |
367 | .rating = 300, |
368 | .read = clocksource_read_cycles, | |
369 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
370 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
371 | }; | |
372 | ||
2f0778af | 373 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 374 | { |
3d05a3e8 | 375 | if (clksrc.reserved) |
dbc3982a | 376 | return __omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f | 377 | |
2f0778af | 378 | return 0; |
3d05a3e8 TL |
379 | } |
380 | ||
45caae74 | 381 | #ifdef CONFIG_OMAP_32K_TIMER |
3d05a3e8 | 382 | /* Setup free-running counter for clocksource */ |
1fe97c8f VH |
383 | static int __init omap2_sync32k_clocksource_init(void) |
384 | { | |
385 | int ret; | |
9883f7c8 | 386 | struct device_node *np = NULL; |
1fe97c8f VH |
387 | struct omap_hwmod *oh; |
388 | void __iomem *vbase; | |
389 | const char *oh_name = "counter_32k"; | |
390 | ||
9883f7c8 JH |
391 | /* |
392 | * If device-tree is present, then search the DT blob | |
393 | * to see if the 32kHz counter is supported. | |
394 | */ | |
395 | if (of_have_populated_dt()) { | |
396 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
397 | if (!np) | |
398 | return -ENODEV; | |
399 | ||
400 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
401 | if (!oh_name) | |
402 | return -ENODEV; | |
403 | } | |
404 | ||
1fe97c8f VH |
405 | /* |
406 | * First check hwmod data is available for sync32k counter | |
407 | */ | |
408 | oh = omap_hwmod_lookup(oh_name); | |
409 | if (!oh || oh->slaves_cnt == 0) | |
410 | return -ENODEV; | |
411 | ||
412 | omap_hwmod_setup_one(oh_name); | |
413 | ||
9883f7c8 JH |
414 | if (np) { |
415 | vbase = of_iomap(np, 0); | |
416 | of_node_put(np); | |
417 | } else { | |
418 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
419 | } | |
420 | ||
1fe97c8f VH |
421 | if (!vbase) { |
422 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
423 | return -ENXIO; | |
424 | } | |
425 | ||
426 | ret = omap_hwmod_enable(oh); | |
427 | if (ret) { | |
428 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
429 | __func__, ret); | |
430 | return ret; | |
431 | } | |
432 | ||
433 | ret = omap_init_clocksource_32k(vbase); | |
434 | if (ret) { | |
435 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
436 | __func__, ret); | |
437 | omap_hwmod_idle(oh); | |
438 | } | |
439 | ||
440 | return ret; | |
441 | } | |
45caae74 IG |
442 | #else |
443 | static inline int omap2_sync32k_clocksource_init(void) | |
444 | { | |
445 | return -ENODEV; | |
446 | } | |
447 | #endif | |
1fe97c8f VH |
448 | |
449 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
3d05a3e8 TL |
450 | const char *fck_source) |
451 | { | |
452 | int res; | |
453 | ||
9725f445 | 454 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL); |
3d05a3e8 | 455 | BUG_ON(res); |
5a3a388f | 456 | |
ee17f114 | 457 | __omap_dm_timer_load_start(&clksrc, |
e9d0b97e | 458 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); |
2f0778af | 459 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 460 | |
3d05a3e8 TL |
461 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
462 | pr_err("Could not register clocksource %s\n", | |
463 | clocksource_gpt.name); | |
1fe97c8f VH |
464 | else |
465 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", | |
466 | gptimer_id, clksrc.rate); | |
467 | } | |
468 | ||
469 | static void __init omap2_clocksource_init(int gptimer_id, | |
470 | const char *fck_source) | |
471 | { | |
472 | /* | |
473 | * First give preference to kernel parameter configuration | |
474 | * by user (clocksource="gp_timer"). | |
475 | * | |
476 | * In case of missing kernel parameter for clocksource, | |
477 | * first check for availability for 32k-sync timer, in case | |
478 | * of failure in finding 32k_counter module or registering | |
479 | * it as clocksource, execution will fallback to gp-timer. | |
480 | */ | |
481 | if (use_gptimer_clksrc == true) | |
482 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
483 | else if (omap2_sync32k_clocksource_init()) | |
484 | /* Fall back to gp-timer code */ | |
485 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
5a3a388f | 486 | } |
5a3a388f | 487 | |
fa6d79d2 SS |
488 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
489 | /* | |
490 | * The realtime counter also called master counter, is a free-running | |
491 | * counter, which is related to real time. It produces the count used | |
492 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
493 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
494 | * in different power modes, the master counter shifts operation between | |
495 | * clocks, adjusting the increment per clock in hardware accordingly to | |
496 | * maintain a constant count rate. | |
497 | */ | |
498 | static void __init realtime_counter_init(void) | |
499 | { | |
500 | void __iomem *base; | |
501 | static struct clk *sys_clk; | |
502 | unsigned long rate; | |
503 | unsigned int reg, num, den; | |
504 | ||
505 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
506 | if (!base) { | |
507 | pr_err("%s: ioremap failed\n", __func__); | |
508 | return; | |
509 | } | |
510 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | |
533b2981 | 511 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
512 | pr_err("%s: failed to get system clock handle\n", __func__); |
513 | iounmap(base); | |
514 | return; | |
515 | } | |
516 | ||
517 | rate = clk_get_rate(sys_clk); | |
518 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
519 | switch (rate) { | |
520 | case 1200000: | |
521 | num = 64; | |
522 | den = 125; | |
523 | break; | |
524 | case 1300000: | |
525 | num = 768; | |
526 | den = 1625; | |
527 | break; | |
528 | case 19200000: | |
529 | num = 8; | |
530 | den = 25; | |
531 | break; | |
532 | case 2600000: | |
533 | num = 384; | |
534 | den = 1625; | |
535 | break; | |
536 | case 2700000: | |
537 | num = 256; | |
538 | den = 1125; | |
539 | break; | |
540 | case 38400000: | |
541 | default: | |
542 | /* Program it for 38.4 MHz */ | |
543 | num = 4; | |
544 | den = 25; | |
545 | break; | |
546 | } | |
547 | ||
548 | /* Program numerator and denumerator registers */ | |
549 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
550 | NUMERATOR_DENUMERATOR_MASK; | |
551 | reg |= num; | |
552 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
553 | ||
554 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
555 | NUMERATOR_DENUMERATOR_MASK; | |
556 | reg |= den; | |
557 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
558 | ||
559 | iounmap(base); | |
560 | } | |
561 | #else | |
562 | static inline void __init realtime_counter_init(void) | |
563 | {} | |
564 | #endif | |
565 | ||
9725f445 | 566 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
3d05a3e8 | 567 | clksrc_nr, clksrc_src) \ |
e74984e4 TL |
568 | static void __init omap##name##_timer_init(void) \ |
569 | { \ | |
ad24bde8 | 570 | omap_dmtimer_init(); \ |
9725f445 | 571 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
1fe97c8f | 572 | omap2_clocksource_init((clksrc_nr), clksrc_src); \ |
e74984e4 TL |
573 | } |
574 | ||
575 | #define OMAP_SYS_TIMER(name) \ | |
576 | struct sys_timer omap##name##_timer = { \ | |
577 | .init = omap##name##_timer_init, \ | |
578 | }; | |
579 | ||
580 | #ifdef CONFIG_ARCH_OMAP2 | |
9725f445 JH |
581 | OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon", |
582 | 2, OMAP2_MPU_SOURCE) | |
e74984e4 TL |
583 | OMAP_SYS_TIMER(2) |
584 | #endif | |
585 | ||
586 | #ifdef CONFIG_ARCH_OMAP3 | |
9725f445 JH |
587 | OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon", |
588 | 2, OMAP3_MPU_SOURCE) | |
e74984e4 | 589 | OMAP_SYS_TIMER(3) |
3d05a3e8 | 590 | OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, |
9725f445 | 591 | TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE) |
e74984e4 TL |
592 | OMAP_SYS_TIMER(3_secure) |
593 | #endif | |
594 | ||
08f30989 | 595 | #ifdef CONFIG_SOC_AM33XX |
9725f445 JH |
596 | OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", |
597 | 2, OMAP4_MPU_SOURCE) | |
08f30989 AM |
598 | OMAP_SYS_TIMER(3_am33xx) |
599 | #endif | |
600 | ||
e74984e4 | 601 | #ifdef CONFIG_ARCH_OMAP4 |
39e1d4c1 | 602 | #ifdef CONFIG_LOCAL_TIMERS |
a45c983f | 603 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
3f216ef3 | 604 | OMAP44XX_LOCAL_TWD_BASE, 29); |
39e1d4c1 | 605 | #endif |
a45c983f MZ |
606 | |
607 | static void __init omap4_timer_init(void) | |
608 | { | |
9725f445 | 609 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); |
1fe97c8f | 610 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
a45c983f MZ |
611 | #ifdef CONFIG_LOCAL_TIMERS |
612 | /* Local timers are not supprted on OMAP4430 ES1.0 */ | |
613 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
614 | int err; | |
615 | ||
eed0de27 SS |
616 | if (of_have_populated_dt()) { |
617 | twd_local_timer_of_register(); | |
618 | return; | |
619 | } | |
620 | ||
a45c983f MZ |
621 | err = twd_local_timer_register(&twd_local_timer); |
622 | if (err) | |
623 | pr_err("twd_local_timer_register failed %d\n", err); | |
624 | } | |
625 | #endif | |
1dbae815 | 626 | } |
e74984e4 TL |
627 | OMAP_SYS_TIMER(4) |
628 | #endif | |
c345c8b0 | 629 | |
37b3280d | 630 | #ifdef CONFIG_SOC_OMAP5 |
fa6d79d2 SS |
631 | static void __init omap5_timer_init(void) |
632 | { | |
3c7c5dab SS |
633 | int err; |
634 | ||
9725f445 | 635 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); |
fa6d79d2 SS |
636 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
637 | realtime_counter_init(); | |
3c7c5dab SS |
638 | |
639 | err = arch_timer_of_register(); | |
640 | if (err) | |
641 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | |
fa6d79d2 | 642 | } |
37b3280d S |
643 | OMAP_SYS_TIMER(5) |
644 | #endif | |
645 | ||
c345c8b0 TKD |
646 | /** |
647 | * omap_timer_init - build and register timer device with an | |
648 | * associated timer hwmod | |
649 | * @oh: timer hwmod pointer to be used to build timer device | |
650 | * @user: parameter that can be passed from calling hwmod API | |
651 | * | |
652 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
653 | * devices present in the system. The number of timer devices is known | |
654 | * by parsing through the hwmod database for a given class name. At the | |
655 | * end of function call memory is allocated for timer device and it is | |
656 | * registered to the framework ready to be proved by the driver. | |
657 | */ | |
658 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
659 | { | |
660 | int id; | |
661 | int ret = 0; | |
662 | char *name = "omap_timer"; | |
663 | struct dmtimer_platform_data *pdata; | |
c541c15f | 664 | struct platform_device *pdev; |
c345c8b0 TKD |
665 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
666 | ||
667 | pr_debug("%s: %s\n", __func__, oh->name); | |
668 | ||
669 | /* on secure device, do not register secure timer */ | |
670 | timer_dev_attr = oh->dev_attr; | |
671 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
672 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
673 | return ret; | |
674 | ||
675 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
676 | if (!pdata) { | |
677 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
678 | return -ENOMEM; | |
679 | } | |
680 | ||
681 | /* | |
682 | * Extract the IDs from name field in hwmod database | |
683 | * and use the same for constructing ids' for the | |
684 | * timer devices. In a way, we are avoiding usage of | |
685 | * static variable witin the function to do the same. | |
686 | * CAUTION: We have to be careful and make sure the | |
687 | * name in hwmod database does not change in which case | |
688 | * we might either make corresponding change here or | |
689 | * switch back static variable mechanism. | |
690 | */ | |
691 | sscanf(oh->name, "timer%2d", &id); | |
692 | ||
d1c1691b JH |
693 | if (timer_dev_attr) |
694 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 695 | |
6e740f9a TL |
696 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
697 | ||
c541c15f | 698 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), |
c16ae1e6 | 699 | NULL, 0, 0); |
c345c8b0 | 700 | |
c541c15f | 701 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
702 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
703 | __func__, name, oh->name); | |
704 | ret = -EINVAL; | |
705 | } | |
706 | ||
707 | kfree(pdata); | |
708 | ||
709 | return ret; | |
710 | } | |
3392cdd3 TKD |
711 | |
712 | /** | |
713 | * omap2_dm_timer_init - top level regular device initialization | |
714 | * | |
715 | * Uses dedicated hwmod api to parse through hwmod database for | |
716 | * given class name and then build and register the timer device. | |
717 | */ | |
718 | static int __init omap2_dm_timer_init(void) | |
719 | { | |
720 | int ret; | |
721 | ||
9725f445 JH |
722 | /* If dtb is there, the devices will be created dynamically */ |
723 | if (of_have_populated_dt()) | |
724 | return -ENODEV; | |
725 | ||
3392cdd3 TKD |
726 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
727 | if (unlikely(ret)) { | |
728 | pr_err("%s: device registration failed.\n", __func__); | |
729 | return -EINVAL; | |
730 | } | |
731 | ||
732 | return 0; | |
733 | } | |
734 | arch_initcall(omap2_dm_timer_init); | |
1fe97c8f VH |
735 | |
736 | /** | |
737 | * omap2_override_clocksource - clocksource override with user configuration | |
738 | * | |
739 | * Allows user to override default clocksource, using kernel parameter | |
740 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
741 | * | |
742 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
743 | * and not introducing any OMAP specific interface. | |
744 | */ | |
745 | static int __init omap2_override_clocksource(char *str) | |
746 | { | |
747 | if (!str) | |
748 | return 0; | |
749 | /* | |
750 | * For OMAP architecture, we only have two options | |
751 | * - sync_32k (default) | |
752 | * - gp_timer (sys_clk based) | |
753 | */ | |
754 | if (!strcmp(str, "gp_timer")) | |
755 | use_gptimer_clksrc = true; | |
756 | ||
757 | return 0; | |
758 | } | |
759 | early_param("clocksource", omap2_override_clocksource); |