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c0718df4 PW |
1 | /* |
2 | * OMAP4 Voltage Controller (VC) data | |
3 | * | |
4 | * Copyright (C) 2007, 2010 Texas Instruments, Inc. | |
5 | * Rajendra Nayak <rnayak@ti.com> | |
6 | * Lesly A M <x0080970@ti.com> | |
7 | * Thara Gopinath <thara@ti.com> | |
8 | * | |
9 | * Copyright (C) 2008, 2011 Nokia Corporation | |
10 | * Kalle Jokiniemi | |
11 | * Paul Walmsley | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | #include <linux/io.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | ||
4e65331c | 21 | #include "common.h" |
c0718df4 PW |
22 | |
23 | #include "prm44xx.h" | |
24 | #include "prm-regbits-44xx.h" | |
25 | #include "voltage.h" | |
26 | ||
27 | #include "vc.h" | |
28 | ||
29 | /* | |
30 | * VC data common to 44xx chips | |
31 | * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file. | |
32 | */ | |
d84adcf4 | 33 | static const struct omap_vc_common omap4_vc_common = { |
c0718df4 PW |
34 | .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET, |
35 | .data_shift = OMAP4430_DATA_SHIFT, | |
36 | .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT, | |
37 | .regaddr_shift = OMAP4430_REGADDR_SHIFT, | |
38 | .valid = OMAP4430_VALID_MASK, | |
39 | .cmd_on_shift = OMAP4430_ON_SHIFT, | |
40 | .cmd_on_mask = OMAP4430_ON_MASK, | |
41 | .cmd_onlp_shift = OMAP4430_ONLP_SHIFT, | |
42 | .cmd_ret_shift = OMAP4430_RET_SHIFT, | |
43 | .cmd_off_shift = OMAP4430_OFF_SHIFT, | |
f5395480 KH |
44 | .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET, |
45 | .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK, | |
46 | .i2c_mcode_mask = OMAP4430_HSMCODE_MASK, | |
c0718df4 PW |
47 | }; |
48 | ||
49 | /* VC instance data for each controllable voltage line */ | |
d84adcf4 | 50 | struct omap_vc_channel omap4_vc_mpu = { |
8abc0b58 | 51 | .flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT, |
d84adcf4 | 52 | .common = &omap4_vc_common, |
5876c940 KH |
53 | .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET, |
54 | .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET, | |
55 | .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET, | |
56 | .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET, | |
c0718df4 | 57 | .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET, |
c0718df4 | 58 | .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK, |
c0718df4 | 59 | .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK, |
e4e021c5 | 60 | .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK, |
24d3194a | 61 | .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT, |
c0718df4 PW |
62 | }; |
63 | ||
d84adcf4 KH |
64 | struct omap_vc_channel omap4_vc_iva = { |
65 | .common = &omap4_vc_common, | |
5876c940 KH |
66 | .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET, |
67 | .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET, | |
68 | .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET, | |
69 | .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET, | |
c0718df4 | 70 | .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET, |
c0718df4 | 71 | .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK, |
c0718df4 | 72 | .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK, |
e4e021c5 | 73 | .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK, |
24d3194a | 74 | .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT, |
c0718df4 PW |
75 | }; |
76 | ||
d84adcf4 KH |
77 | struct omap_vc_channel omap4_vc_core = { |
78 | .common = &omap4_vc_common, | |
5876c940 KH |
79 | .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET, |
80 | .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET, | |
81 | .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET, | |
82 | .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET, | |
c0718df4 | 83 | .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET, |
c0718df4 | 84 | .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK, |
c0718df4 | 85 | .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK, |
e4e021c5 | 86 | .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK, |
24d3194a | 87 | .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT, |
c0718df4 PW |
88 | }; |
89 | ||
8b5d8c0d TK |
90 | /* |
91 | * Voltage levels for different operating modes: on, sleep, retention and off | |
92 | */ | |
93 | #define OMAP4_ON_VOLTAGE_UV 1375000 | |
94 | #define OMAP4_ONLP_VOLTAGE_UV 1375000 | |
95 | #define OMAP4_RET_VOLTAGE_UV 837500 | |
96 | #define OMAP4_OFF_VOLTAGE_UV 0 | |
97 | ||
98 | struct omap_vc_param omap4_mpu_vc_data = { | |
99 | .on = OMAP4_ON_VOLTAGE_UV, | |
100 | .onlp = OMAP4_ONLP_VOLTAGE_UV, | |
101 | .ret = OMAP4_RET_VOLTAGE_UV, | |
102 | .off = OMAP4_OFF_VOLTAGE_UV, | |
103 | }; | |
104 | ||
105 | struct omap_vc_param omap4_iva_vc_data = { | |
106 | .on = OMAP4_ON_VOLTAGE_UV, | |
107 | .onlp = OMAP4_ONLP_VOLTAGE_UV, | |
108 | .ret = OMAP4_RET_VOLTAGE_UV, | |
109 | .off = OMAP4_OFF_VOLTAGE_UV, | |
110 | }; | |
111 | ||
112 | struct omap_vc_param omap4_core_vc_data = { | |
113 | .on = OMAP4_ON_VOLTAGE_UV, | |
114 | .onlp = OMAP4_ONLP_VOLTAGE_UV, | |
115 | .ret = OMAP4_RET_VOLTAGE_UV, | |
116 | .off = OMAP4_OFF_VOLTAGE_UV, | |
117 | }; |