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c67de5b3 TP |
1 | /* |
2 | * arch/arm/mach-orion/addr-map.c | |
3 | * | |
4 | * Address map functions for Marvell Orion System On Chip | |
5 | * | |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <asm/hardware.h> | |
16 | #include "common.h" | |
17 | ||
18 | /* | |
19 | * The Orion has fully programable address map. There's a separate address | |
20 | * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, | |
21 | * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own | |
22 | * address decode windows that allow it to access any of the Orion resources. | |
23 | * | |
24 | * CPU address decoding -- | |
25 | * Linux assumes that it is the boot loader that already setup the access to | |
26 | * DDR and internal registers. | |
27 | * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. | |
28 | * Setup access to various devices located on the device bus interface (e.g. | |
29 | * flashes, RTC, etc) should be issued by machine-setup.c according to | |
30 | * specific board population (by using orion_setup_cpu_win()). | |
31 | * | |
32 | * Non-CPU Masters address decoding -- | |
33 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | |
34 | * banks only (the typical use case). | |
35 | * Setup access for each master to DDR is issued by common.c. | |
36 | * | |
37 | * Note: although orion_setbits() and orion_clrbits() are not atomic | |
38 | * no locking is necessary here since code in this file is only called | |
39 | * at boot time when there is no concurrency issues. | |
40 | */ | |
41 | ||
42 | /* | |
43 | * Generic Address Decode Windows bit settings | |
44 | */ | |
45 | #define TARGET_DDR 0 | |
46 | #define TARGET_PCI 3 | |
47 | #define TARGET_PCIE 4 | |
48 | #define TARGET_DEV_BUS 1 | |
49 | #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ | |
50 | ((n) == 1) ? 0xd : \ | |
51 | ((n) == 2) ? 0xb : \ | |
52 | ((n) == 3) ? 0x7 : 0xf) | |
53 | #define ATTR_PCIE_MEM 0x59 | |
54 | #define ATTR_PCIE_IO 0x51 | |
55 | #define ATTR_PCI_MEM 0x59 | |
56 | #define ATTR_PCI_IO 0x51 | |
57 | #define ATTR_DEV_CS0 0x1e | |
58 | #define ATTR_DEV_CS1 0x1d | |
59 | #define ATTR_DEV_CS2 0x1b | |
60 | #define ATTR_DEV_BOOT 0xf | |
61 | #define WIN_EN 1 | |
62 | ||
63 | /* | |
64 | * Helpers to get DDR banks info | |
65 | */ | |
66 | #define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) | |
67 | #define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) | |
68 | #define DDR_MAX_CS 4 | |
69 | #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) | |
70 | #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) | |
71 | #define DDR_BANK_EN 1 | |
72 | ||
73 | /* | |
74 | * CPU Address Decode Windows registers | |
75 | */ | |
76 | #define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) | |
77 | #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) | |
78 | #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) | |
79 | #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) | |
80 | #define CPU_MAX_WIN 8 | |
81 | ||
82 | /* | |
83 | * Use this CPU address decode windows allocation | |
84 | */ | |
85 | #define CPU_WIN_PCIE_IO 0 | |
86 | #define CPU_WIN_PCI_IO 1 | |
87 | #define CPU_WIN_PCIE_MEM 2 | |
88 | #define CPU_WIN_PCI_MEM 3 | |
89 | #define CPU_WIN_DEV_BOOT 4 | |
90 | #define CPU_WIN_DEV_CS0 5 | |
91 | #define CPU_WIN_DEV_CS1 6 | |
92 | #define CPU_WIN_DEV_CS2 7 | |
93 | ||
94 | /* | |
95 | * PCIE Address Decode Windows registers | |
96 | */ | |
97 | #define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) | |
98 | #define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) | |
99 | #define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) | |
4c91363d LB |
100 | #define PCIE_WIN_CTRL(n) (((n) < 5) ? \ |
101 | ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ | |
102 | ORION_PCIE_REG(0x1880)) | |
103 | #define PCIE_WIN_BASE(n) (((n) < 5) ? \ | |
104 | ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ | |
105 | ORION_PCIE_REG(0x1884)) | |
106 | #define PCIE_WIN_REMAP(n) (((n) < 5) ? \ | |
107 | ORION_PCIE_REG(0x182c + ((n) << 4)) : \ | |
108 | ORION_PCIE_REG(0x188c)) | |
c67de5b3 TP |
109 | #define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) |
110 | #define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) | |
111 | #define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) | |
112 | #define PCIE_MAX_BARS 3 | |
4c91363d | 113 | #define PCIE_MAX_WINS 6 |
c67de5b3 TP |
114 | |
115 | /* | |
116 | * Use PCIE BAR '1' for all DDR banks | |
117 | */ | |
118 | #define PCIE_DRAM_BAR 1 | |
119 | ||
120 | /* | |
121 | * PCI Address Decode Windows registers | |
122 | */ | |
123 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ | |
124 | ((n) == 1) ? ORION_PCI_REG(0xd08) : \ | |
125 | ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ | |
126 | ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) | |
127 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ | |
128 | ((n) == 1) ? ORION_PCI_REG(0xd48) : \ | |
129 | ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ | |
130 | ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) | |
131 | #define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) | |
132 | #define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4)) | |
133 | #define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4)) | |
134 | #define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4)) | |
135 | #define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) | |
136 | ||
137 | /* | |
138 | * PCI configuration heleprs for BAR settings | |
139 | */ | |
140 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | |
141 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | |
142 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | |
143 | ||
144 | /* | |
145 | * Gigabit Ethernet Address Decode Windows registers | |
146 | */ | |
147 | #define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) | |
148 | #define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) | |
149 | #define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) | |
150 | #define ETH_WIN_EN ORION_ETH_REG(0x290) | |
151 | #define ETH_WIN_PROT ORION_ETH_REG(0x294) | |
152 | #define ETH_MAX_WIN 6 | |
153 | #define ETH_MAX_REMAP_WIN 4 | |
154 | ||
155 | /* | |
156 | * USB Address Decode Windows registers | |
157 | */ | |
158 | #define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \ | |
159 | : ORION_USB1_REG(0x320 + ((w) << 4))) | |
160 | #define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \ | |
161 | : ORION_USB1_REG(0x324 + ((w) << 4))) | |
162 | #define USB_MAX_WIN 4 | |
163 | ||
164 | /* | |
165 | * SATA Address Decode Windows registers | |
166 | */ | |
167 | #define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) | |
168 | #define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) | |
169 | #define SATA_MAX_WIN 4 | |
170 | ||
171 | static int __init orion_cpu_win_can_remap(u32 win) | |
172 | { | |
173 | u32 dev, rev; | |
174 | ||
175 | orion_pcie_id(&dev, &rev); | |
c9e3de94 HVR |
176 | if ((dev == MV88F5281_DEV_ID && win < 4) |
177 | || (dev == MV88F5182_DEV_ID && win < 2) | |
178 | || (dev == MV88F5181_DEV_ID && win < 2)) | |
c67de5b3 TP |
179 | return 1; |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) | |
185 | { | |
186 | u32 win, attr, ctrl; | |
187 | ||
188 | switch (target) { | |
189 | case ORION_PCIE_IO: | |
190 | target = TARGET_PCIE; | |
191 | attr = ATTR_PCIE_IO; | |
192 | win = CPU_WIN_PCIE_IO; | |
193 | break; | |
194 | case ORION_PCI_IO: | |
195 | target = TARGET_PCI; | |
196 | attr = ATTR_PCI_IO; | |
197 | win = CPU_WIN_PCI_IO; | |
198 | break; | |
199 | case ORION_PCIE_MEM: | |
200 | target = TARGET_PCIE; | |
201 | attr = ATTR_PCIE_MEM; | |
202 | win = CPU_WIN_PCIE_MEM; | |
203 | break; | |
204 | case ORION_PCI_MEM: | |
205 | target = TARGET_PCI; | |
206 | attr = ATTR_PCI_MEM; | |
207 | win = CPU_WIN_PCI_MEM; | |
208 | break; | |
209 | case ORION_DEV_BOOT: | |
210 | target = TARGET_DEV_BUS; | |
211 | attr = ATTR_DEV_BOOT; | |
212 | win = CPU_WIN_DEV_BOOT; | |
213 | break; | |
214 | case ORION_DEV0: | |
215 | target = TARGET_DEV_BUS; | |
216 | attr = ATTR_DEV_CS0; | |
217 | win = CPU_WIN_DEV_CS0; | |
218 | break; | |
219 | case ORION_DEV1: | |
220 | target = TARGET_DEV_BUS; | |
221 | attr = ATTR_DEV_CS1; | |
222 | win = CPU_WIN_DEV_CS1; | |
223 | break; | |
224 | case ORION_DEV2: | |
225 | target = TARGET_DEV_BUS; | |
226 | attr = ATTR_DEV_CS2; | |
227 | win = CPU_WIN_DEV_CS2; | |
228 | break; | |
229 | case ORION_DDR: | |
230 | case ORION_REGS: | |
231 | /* | |
232 | * Must be mapped by bootloader. | |
233 | */ | |
234 | default: | |
235 | target = attr = win = -1; | |
236 | BUG(); | |
237 | } | |
238 | ||
239 | base &= 0xffff0000; | |
240 | ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | | |
241 | (target << 4) | WIN_EN); | |
242 | ||
243 | orion_write(CPU_WIN_BASE(win), base); | |
244 | orion_write(CPU_WIN_CTRL(win), ctrl); | |
245 | ||
246 | if (orion_cpu_win_can_remap(win)) { | |
247 | if (remap >= 0) { | |
248 | orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); | |
249 | orion_write(CPU_WIN_REMAP_HI(win), 0); | |
250 | } else { | |
251 | orion_write(CPU_WIN_REMAP_LO(win), base); | |
252 | orion_write(CPU_WIN_REMAP_HI(win), 0); | |
253 | } | |
254 | } | |
255 | } | |
256 | ||
257 | void __init orion_setup_cpu_wins(void) | |
258 | { | |
259 | int i; | |
260 | ||
261 | /* | |
262 | * First, disable and clear windows | |
263 | */ | |
264 | for (i = 0; i < CPU_MAX_WIN; i++) { | |
265 | orion_write(CPU_WIN_BASE(i), 0); | |
266 | orion_write(CPU_WIN_CTRL(i), 0); | |
267 | if (orion_cpu_win_can_remap(i)) { | |
268 | orion_write(CPU_WIN_REMAP_LO(i), 0); | |
269 | orion_write(CPU_WIN_REMAP_HI(i), 0); | |
270 | } | |
271 | } | |
272 | ||
273 | /* | |
7f74c2c7 | 274 | * Setup windows for PCI+PCIe IO+MEM space. |
c67de5b3 | 275 | */ |
7f74c2c7 LB |
276 | orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, |
277 | ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); | |
278 | orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, | |
279 | ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); | |
280 | orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, | |
c67de5b3 | 281 | ORION_PCIE_MEM_SIZE, -1); |
7f74c2c7 | 282 | orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, |
c67de5b3 TP |
283 | ORION_PCI_MEM_SIZE, -1); |
284 | } | |
285 | ||
286 | /* | |
287 | * Setup PCIE BARs and Address Decode Wins: | |
288 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | |
289 | * WIN[0-3] -> DRAM bank[0-3] | |
290 | */ | |
291 | void __init orion_setup_pcie_wins(void) | |
292 | { | |
293 | u32 base, size, i; | |
294 | ||
295 | /* | |
296 | * First, disable and clear BARs and windows | |
297 | */ | |
298 | for (i = 1; i < PCIE_MAX_BARS; i++) { | |
299 | orion_write(PCIE_BAR_CTRL(i), 0); | |
300 | orion_write(PCIE_BAR_LO(i), 0); | |
301 | orion_write(PCIE_BAR_HI(i), 0); | |
302 | } | |
303 | ||
304 | for (i = 0; i < PCIE_MAX_WINS; i++) { | |
305 | orion_write(PCIE_WIN_CTRL(i), 0); | |
306 | orion_write(PCIE_WIN_BASE(i), 0); | |
307 | orion_write(PCIE_WIN_REMAP(i), 0); | |
308 | } | |
309 | ||
310 | /* | |
311 | * Setup windows for DDR banks. Count total DDR size on the fly. | |
312 | */ | |
313 | base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0))); | |
314 | size = 0; | |
315 | for (i = 0; i < DDR_MAX_CS; i++) { | |
316 | u32 bank_base, bank_size; | |
317 | bank_size = orion_read(DDR_SIZE_CS(i)); | |
318 | bank_base = orion_read(DDR_BASE_CS(i)); | |
319 | if (bank_size & DDR_BANK_EN) { | |
320 | bank_size = DDR_REG_TO_SIZE(bank_size); | |
321 | bank_base = DDR_REG_TO_BASE(bank_base); | |
322 | orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000); | |
323 | orion_write(PCIE_WIN_REMAP(i), 0); | |
324 | orion_write(PCIE_WIN_CTRL(i), | |
325 | ((bank_size-1) & 0xffff0000) | | |
326 | (ATTR_DDR_CS(i) << 8) | | |
327 | (TARGET_DDR << 4) | | |
328 | (PCIE_DRAM_BAR << 1) | WIN_EN); | |
329 | size += bank_size; | |
330 | } | |
331 | } | |
332 | ||
333 | /* | |
334 | * Setup BAR[1] to all DRAM banks | |
335 | */ | |
336 | orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000); | |
337 | orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0); | |
338 | orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR), | |
339 | ((size - 1) & 0xffff0000) | WIN_EN); | |
340 | } | |
341 | ||
342 | void __init orion_setup_pci_wins(void) | |
343 | { | |
344 | u32 base, size, i; | |
345 | ||
346 | /* | |
347 | * First, disable windows | |
348 | */ | |
349 | orion_write(PCI_BAR_ENABLE, 0xffffffff); | |
350 | ||
351 | /* | |
352 | * Setup windows for DDR banks. | |
353 | */ | |
354 | for (i = 0; i < DDR_MAX_CS; i++) { | |
355 | base = orion_read(DDR_BASE_CS(i)); | |
356 | size = orion_read(DDR_SIZE_CS(i)); | |
357 | if (size & DDR_BANK_EN) { | |
358 | u32 bus, dev, func, reg, val; | |
359 | size = DDR_REG_TO_SIZE(size); | |
360 | base = DDR_REG_TO_BASE(base); | |
361 | bus = orion_pci_local_bus_nr(); | |
362 | dev = orion_pci_local_dev_nr(); | |
363 | func = PCI_CONF_FUNC_BAR_CS(i); | |
364 | reg = PCI_CONF_REG_BAR_LO_CS(i); | |
365 | orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); | |
366 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, | |
367 | (base & 0xfffff000) | (val & 0xfff)); | |
368 | reg = PCI_CONF_REG_BAR_HI_CS(i); | |
369 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); | |
370 | orion_write(PCI_BAR_SIZE_DDR_CS(i), | |
371 | (size - 1) & 0xfffff000); | |
372 | orion_write(PCI_BAR_REMAP_DDR_CS(i), | |
373 | base & 0xfffff000); | |
374 | orion_clrbits(PCI_BAR_ENABLE, (1 << i)); | |
375 | } | |
376 | } | |
377 | ||
378 | /* | |
379 | * Disable automatic update of address remaping when writing to BARs | |
380 | */ | |
381 | orion_setbits(PCI_ADDR_DECODE_CTRL, 1); | |
382 | } | |
383 | ||
384 | void __init orion_setup_usb_wins(void) | |
385 | { | |
386 | int i; | |
387 | u32 usb_if, dev, rev; | |
388 | u32 max_usb_if = 1; | |
389 | ||
390 | orion_pcie_id(&dev, &rev); | |
391 | if (dev == MV88F5182_DEV_ID) | |
392 | max_usb_if = 2; | |
393 | ||
394 | for (usb_if = 0; usb_if < max_usb_if; usb_if++) { | |
395 | /* | |
396 | * First, disable and clear windows | |
397 | */ | |
398 | for (i = 0; i < USB_MAX_WIN; i++) { | |
399 | orion_write(USB_WIN_BASE(usb_if, i), 0); | |
400 | orion_write(USB_WIN_CTRL(usb_if, i), 0); | |
401 | } | |
402 | ||
403 | /* | |
404 | * Setup windows for DDR banks. | |
405 | */ | |
406 | for (i = 0; i < DDR_MAX_CS; i++) { | |
407 | u32 base, size; | |
408 | size = orion_read(DDR_SIZE_CS(i)); | |
409 | base = orion_read(DDR_BASE_CS(i)); | |
410 | if (size & DDR_BANK_EN) { | |
411 | base = DDR_REG_TO_BASE(base); | |
412 | size = DDR_REG_TO_SIZE(size); | |
413 | orion_write(USB_WIN_CTRL(usb_if, i), | |
414 | ((size-1) & 0xffff0000) | | |
415 | (ATTR_DDR_CS(i) << 8) | | |
416 | (TARGET_DDR << 4) | WIN_EN); | |
417 | orion_write(USB_WIN_BASE(usb_if, i), | |
418 | base & 0xffff0000); | |
419 | } | |
420 | } | |
421 | } | |
422 | } | |
423 | ||
424 | void __init orion_setup_eth_wins(void) | |
425 | { | |
426 | int i; | |
427 | ||
428 | /* | |
429 | * First, disable and clear windows | |
430 | */ | |
431 | for (i = 0; i < ETH_MAX_WIN; i++) { | |
432 | orion_write(ETH_WIN_BASE(i), 0); | |
433 | orion_write(ETH_WIN_SIZE(i), 0); | |
434 | orion_setbits(ETH_WIN_EN, 1 << i); | |
435 | orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); | |
436 | if (i < ETH_MAX_REMAP_WIN) | |
437 | orion_write(ETH_WIN_REMAP(i), 0); | |
438 | } | |
439 | ||
440 | /* | |
441 | * Setup windows for DDR banks. | |
442 | */ | |
443 | for (i = 0; i < DDR_MAX_CS; i++) { | |
444 | u32 base, size; | |
445 | size = orion_read(DDR_SIZE_CS(i)); | |
446 | base = orion_read(DDR_BASE_CS(i)); | |
447 | if (size & DDR_BANK_EN) { | |
448 | base = DDR_REG_TO_BASE(base); | |
449 | size = DDR_REG_TO_SIZE(size); | |
450 | orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); | |
451 | orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | | |
452 | (ATTR_DDR_CS(i) << 8) | | |
453 | TARGET_DDR); | |
454 | orion_clrbits(ETH_WIN_EN, 1 << i); | |
455 | orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); | |
456 | } | |
457 | } | |
458 | } | |
459 | ||
460 | void __init orion_setup_sata_wins(void) | |
461 | { | |
462 | int i; | |
463 | ||
464 | /* | |
465 | * First, disable and clear windows | |
466 | */ | |
467 | for (i = 0; i < SATA_MAX_WIN; i++) { | |
468 | orion_write(SATA_WIN_BASE(i), 0); | |
469 | orion_write(SATA_WIN_CTRL(i), 0); | |
470 | } | |
471 | ||
472 | /* | |
473 | * Setup windows for DDR banks. | |
474 | */ | |
475 | for (i = 0; i < DDR_MAX_CS; i++) { | |
476 | u32 base, size; | |
477 | size = orion_read(DDR_SIZE_CS(i)); | |
478 | base = orion_read(DDR_BASE_CS(i)); | |
479 | if (size & DDR_BANK_EN) { | |
480 | base = DDR_REG_TO_BASE(base); | |
481 | size = DDR_REG_TO_SIZE(size); | |
482 | orion_write(SATA_WIN_CTRL(i), | |
483 | ((size-1) & 0xffff0000) | | |
484 | (ATTR_DDR_CS(i) << 8) | | |
485 | (TARGET_DDR << 4) | WIN_EN); | |
486 | orion_write(SATA_WIN_BASE(i), | |
487 | base & 0xffff0000); | |
488 | } | |
489 | } | |
490 | } |