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Commit | Line | Data |
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585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 | 15 | #include <linux/platform_device.h> |
ee962723 | 16 | #include <linux/dma-mapping.h> |
ca26f7d3 | 17 | #include <linux/serial_8250.h> |
144aa3db | 18 | #include <linux/mv643xx_i2c.h> |
15a32632 | 19 | #include <linux/ata_platform.h> |
764cbcc2 | 20 | #include <linux/delay.h> |
2f129bf4 | 21 | #include <linux/clk-provider.h> |
dcf1cece | 22 | #include <net/dsa.h> |
585cf175 | 23 | #include <asm/page.h> |
be73a347 | 24 | #include <asm/setup.h> |
9f97da78 | 25 | #include <asm/system_misc.h> |
c67de5b3 | 26 | #include <asm/timex.h> |
be73a347 | 27 | #include <asm/mach/arch.h> |
585cf175 | 28 | #include <asm/mach/map.h> |
2bac1de2 | 29 | #include <asm/mach/time.h> |
4ee1f6b5 | 30 | #include <mach/bridge-regs.h> |
a09e64fb RK |
31 | #include <mach/hardware.h> |
32 | #include <mach/orion5x.h> | |
c02cecb9 AB |
33 | #include <linux/platform_data/mtd-orion_nand.h> |
34 | #include <linux/platform_data/usb-ehci-orion.h> | |
6f088f1d | 35 | #include <plat/time.h> |
28a2b450 | 36 | #include <plat/common.h> |
45173d5e | 37 | #include <plat/addr-map.h> |
585cf175 TP |
38 | #include "common.h" |
39 | ||
40 | /***************************************************************************** | |
41 | * I/O Address Mapping | |
42 | ****************************************************************************/ | |
9dd0b194 | 43 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 44 | { |
3904a393 | 45 | .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, |
9dd0b194 LB |
46 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), |
47 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 | 48 | .type = MT_DEVICE, |
e7068ad3 | 49 | }, { |
3904a393 | 50 | .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, |
9dd0b194 LB |
51 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), |
52 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 53 | .type = MT_DEVICE, |
585cf175 TP |
54 | }, |
55 | }; | |
56 | ||
9dd0b194 | 57 | void __init orion5x_map_io(void) |
585cf175 | 58 | { |
9dd0b194 | 59 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 60 | } |
c67de5b3 | 61 | |
044f6c7c | 62 | |
2f129bf4 AL |
63 | /***************************************************************************** |
64 | * CLK tree | |
65 | ****************************************************************************/ | |
66 | static struct clk *tclk; | |
67 | ||
1bffb4a8 | 68 | void __init clk_init(void) |
2f129bf4 AL |
69 | { |
70 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, | |
71 | orion5x_tclk); | |
4574b886 AL |
72 | |
73 | orion_clkdev_init(tclk); | |
2f129bf4 AL |
74 | } |
75 | ||
044f6c7c LB |
76 | /***************************************************************************** |
77 | * EHCI0 | |
78 | ****************************************************************************/ | |
044f6c7c LB |
79 | void __init orion5x_ehci0_init(void) |
80 | { | |
72053353 AL |
81 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, |
82 | EHCI_PHY_ORION); | |
044f6c7c LB |
83 | } |
84 | ||
85 | ||
86 | /***************************************************************************** | |
87 | * EHCI1 | |
88 | ****************************************************************************/ | |
044f6c7c LB |
89 | void __init orion5x_ehci1_init(void) |
90 | { | |
db33f4de | 91 | orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); |
044f6c7c LB |
92 | } |
93 | ||
94 | ||
e07c9d85 | 95 | /***************************************************************************** |
5c602551 | 96 | * GE00 |
e07c9d85 | 97 | ****************************************************************************/ |
9dd0b194 | 98 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 99 | { |
db33f4de | 100 | orion_ge00_init(eth_data, |
7e3819d8 | 101 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, |
58569aee AP |
102 | IRQ_ORION5X_ETH_ERR, |
103 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | |
e07c9d85 TP |
104 | } |
105 | ||
044f6c7c | 106 | |
dcf1cece LB |
107 | /***************************************************************************** |
108 | * Ethernet switch | |
109 | ****************************************************************************/ | |
dcf1cece LB |
110 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) |
111 | { | |
7e3819d8 | 112 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
113 | } |
114 | ||
115 | ||
144aa3db | 116 | /***************************************************************************** |
044f6c7c | 117 | * I2C |
144aa3db | 118 | ****************************************************************************/ |
044f6c7c LB |
119 | void __init orion5x_i2c_init(void) |
120 | { | |
aac7ffa3 AL |
121 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
122 | ||
044f6c7c LB |
123 | } |
124 | ||
125 | ||
f244baa3 | 126 | /***************************************************************************** |
044f6c7c | 127 | * SATA |
f244baa3 | 128 | ****************************************************************************/ |
9dd0b194 | 129 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 130 | { |
db33f4de | 131 | orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); |
f244baa3 SB |
132 | } |
133 | ||
044f6c7c | 134 | |
d323ade1 LB |
135 | /***************************************************************************** |
136 | * SPI | |
137 | ****************************************************************************/ | |
d323ade1 LB |
138 | void __init orion5x_spi_init() |
139 | { | |
4574b886 | 140 | orion_spi_init(SPI_PHYS_BASE); |
d323ade1 LB |
141 | } |
142 | ||
143 | ||
2bac1de2 | 144 | /***************************************************************************** |
044f6c7c LB |
145 | * UART0 |
146 | ****************************************************************************/ | |
044f6c7c LB |
147 | void __init orion5x_uart0_init(void) |
148 | { | |
28a2b450 | 149 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
74c33576 | 150 | IRQ_ORION5X_UART0, tclk); |
044f6c7c LB |
151 | } |
152 | ||
044f6c7c LB |
153 | /***************************************************************************** |
154 | * UART1 | |
2bac1de2 | 155 | ****************************************************************************/ |
044f6c7c LB |
156 | void __init orion5x_uart1_init(void) |
157 | { | |
28a2b450 | 158 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
74c33576 | 159 | IRQ_ORION5X_UART1, tclk); |
044f6c7c | 160 | } |
2bac1de2 | 161 | |
1d5a1a6e SB |
162 | /***************************************************************************** |
163 | * XOR engine | |
164 | ****************************************************************************/ | |
1d5a1a6e SB |
165 | void __init orion5x_xor_init(void) |
166 | { | |
db33f4de | 167 | orion_xor0_init(ORION5X_XOR_PHYS_BASE, |
ee962723 AL |
168 | ORION5X_XOR_PHYS_BASE + 0x200, |
169 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); | |
1d5a1a6e SB |
170 | } |
171 | ||
44350061 AL |
172 | /***************************************************************************** |
173 | * Cryptographic Engines and Security Accelerator (CESA) | |
174 | ****************************************************************************/ | |
175 | static void __init orion5x_crypto_init(void) | |
3a8f7441 | 176 | { |
b6d1c33a | 177 | orion5x_setup_sram_win(); |
44350061 AL |
178 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
179 | SZ_8K, IRQ_ORION5X_CESA); | |
3a8f7441 | 180 | } |
1d5a1a6e | 181 | |
9e058d4f TR |
182 | /***************************************************************************** |
183 | * Watchdog | |
184 | ****************************************************************************/ | |
9e058d4f TR |
185 | void __init orion5x_wdt_init(void) |
186 | { | |
4f04be62 | 187 | orion_wdt_init(); |
9e058d4f TR |
188 | } |
189 | ||
190 | ||
044f6c7c LB |
191 | /***************************************************************************** |
192 | * Time handling | |
193 | ****************************************************************************/ | |
4ee1f6b5 LB |
194 | void __init orion5x_init_early(void) |
195 | { | |
196 | orion_time_set_base(TIMER_VIRT_BASE); | |
84d5dfbf AL |
197 | |
198 | /* | |
199 | * Some Orion5x devices allocate their coherent buffers from atomic | |
200 | * context. Increase size of atomic coherent pool to make sure such | |
201 | * the allocations won't fail. | |
202 | */ | |
203 | init_dma_coherent_pool_size(SZ_1M); | |
4ee1f6b5 LB |
204 | } |
205 | ||
ebe35aff LB |
206 | int orion5x_tclk; |
207 | ||
208 | int __init orion5x_find_tclk(void) | |
209 | { | |
d323ade1 LB |
210 | u32 dev, rev; |
211 | ||
212 | orion5x_pcie_id(&dev, &rev); | |
213 | if (dev == MV88F6183_DEV_ID && | |
214 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
215 | return 133333333; | |
216 | ||
ebe35aff LB |
217 | return 166666667; |
218 | } | |
219 | ||
6bb27d73 | 220 | void __init orion5x_timer_init(void) |
2bac1de2 | 221 | { |
ebe35aff | 222 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
223 | |
224 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
225 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
226 | } |
227 | ||
044f6c7c | 228 | |
c67de5b3 TP |
229 | /***************************************************************************** |
230 | * General | |
231 | ****************************************************************************/ | |
c67de5b3 | 232 | /* |
b46926bb | 233 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 234 | */ |
1bffb4a8 | 235 | void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 236 | { |
9dd0b194 | 237 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
238 | |
239 | if (*dev == MV88F5281_DEV_ID) { | |
240 | if (*rev == MV88F5281_REV_D2) { | |
241 | *dev_name = "MV88F5281-D2"; | |
242 | } else if (*rev == MV88F5281_REV_D1) { | |
243 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
244 | } else if (*rev == MV88F5281_REV_D0) { |
245 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
246 | } else { |
247 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
248 | } | |
249 | } else if (*dev == MV88F5182_DEV_ID) { | |
250 | if (*rev == MV88F5182_REV_A2) { | |
251 | *dev_name = "MV88F5182-A2"; | |
252 | } else { | |
253 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
254 | } | |
c9e3de94 HVR |
255 | } else if (*dev == MV88F5181_DEV_ID) { |
256 | if (*rev == MV88F5181_REV_B1) { | |
257 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
258 | } else if (*rev == MV88F5181L_REV_A1) { |
259 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 260 | } else { |
d2b2a6bb | 261 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 262 | } |
d323ade1 LB |
263 | } else if (*dev == MV88F6183_DEV_ID) { |
264 | if (*rev == MV88F6183_REV_B0) { | |
265 | *dev_name = "MV88F6183-Rev-B0"; | |
266 | } else { | |
267 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
268 | } | |
c67de5b3 TP |
269 | } else { |
270 | *dev_name = "Device-Unknown"; | |
271 | } | |
272 | } | |
273 | ||
9dd0b194 | 274 | void __init orion5x_init(void) |
c67de5b3 TP |
275 | { |
276 | char *dev_name; | |
277 | u32 dev, rev; | |
278 | ||
9dd0b194 | 279 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
280 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
281 | ||
c67de5b3 TP |
282 | /* |
283 | * Setup Orion address map | |
284 | */ | |
9dd0b194 | 285 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e | 286 | |
2f129bf4 AL |
287 | /* Setup root of clk tree */ |
288 | clk_init(); | |
289 | ||
ce72e36e LB |
290 | /* |
291 | * Don't issue "Wait for Interrupt" instruction if we are | |
292 | * running on D0 5281 silicon. | |
293 | */ | |
294 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
295 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
296 | disable_hlt(); | |
297 | } | |
9e058d4f | 298 | |
3fade49b NP |
299 | /* |
300 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
301 | * while 5180n/5181/5281 don't have crypto. | |
302 | */ | |
303 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
304 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
305 | orion5x_crypto_init(); | |
306 | ||
9e058d4f TR |
307 | /* |
308 | * Register watchdog driver | |
309 | */ | |
310 | orion5x_wdt_init(); | |
c67de5b3 | 311 | } |
be73a347 | 312 | |
764cbcc2 RK |
313 | void orion5x_restart(char mode, const char *cmd) |
314 | { | |
315 | /* | |
316 | * Enable and issue soft reset | |
317 | */ | |
318 | orion5x_setbits(RSTOUTn_MASK, (1 << 2)); | |
319 | orion5x_setbits(CPU_SOFT_RESET, 1); | |
320 | mdelay(200); | |
321 | orion5x_clrbits(CPU_SOFT_RESET, 1); | |
322 | } | |
323 | ||
be73a347 GL |
324 | /* |
325 | * Many orion-based systems have buggy bootloader implementations. | |
326 | * This is a common fixup for bogus memory tags. | |
327 | */ | |
0744a3ee RK |
328 | void __init tag_fixup_mem32(struct tag *t, char **from, |
329 | struct meminfo *meminfo) | |
be73a347 GL |
330 | { |
331 | for (; t->hdr.size; t = tag_next(t)) | |
332 | if (t->hdr.tag == ATAG_MEM && | |
333 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
334 | t->u.mem.start & ~PAGE_MASK)) { | |
335 | printk(KERN_WARNING | |
336 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
337 | t->u.mem.size / 1024, t->u.mem.start); | |
338 | t->hdr.tag = 0; | |
339 | } | |
340 | } |